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bnx2: stop using net_device.{base_addr, irq}.
[linux-2.6.git] / drivers / net / ethernet / fealnx.c
blob6f939a1e15682fe9a093a12e127cfdbf5197c234
1 /*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25 */
26
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.52"
29 #define DRV_RELDATE "Sep-11-2006"
30
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/init.h>
83 #include <linux/mii.h>
84 #include <linux/ethtool.h>
85 #include <linux/crc32.h>
86 #include <linux/delay.h>
87 #include <linux/bitops.h>
88
89 #include <asm/processor.h> /* Processor type for cache alignment. */
90 #include <asm/io.h>
91 #include <asm/uaccess.h>
92 #include <asm/byteorder.h>
93
94 /* These identify the driver base version and may not be removed. */
95 static const char version[] __devinitconst =
96 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97
98
99 /* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
101 #ifndef __alpha__
102 #define USE_IO_OPS
103 #endif
104
105 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
106 /* This is only in the support-all-kernels source code. */
107
108 #define RUN_AT(x) (jiffies + (x))
109
110 MODULE_AUTHOR("Myson or whoever");
111 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
112 MODULE_LICENSE("GPL");
113 module_param(max_interrupt_work, int, 0);
114 module_param(debug, int, 0);
115 module_param(rx_copybreak, int, 0);
116 module_param(multicast_filter_limit, int, 0);
117 module_param_array(options, int, NULL, 0);
118 module_param_array(full_duplex, int, NULL, 0);
119 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
120 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
121 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
122 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
123 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
124 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
125
126 enum {
127 MIN_REGION_SIZE = 136,
128 };
129
130 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
131 enum chip_capability_flags {
132 HAS_MII_XCVR,
133 HAS_CHIP_XCVR,
134 };
135
136 /* 89/6/13 add, */
137 /* for different PHY */
138 enum phy_type_flags {
139 MysonPHY = 1,
140 AhdocPHY = 2,
141 SeeqPHY = 3,
142 MarvellPHY = 4,
143 Myson981 = 5,
144 LevelOnePHY = 6,
145 OtherPHY = 10,
146 };
147
148 struct chip_info {
149 char *chip_name;
150 int flags;
151 };
152
153 static const struct chip_info skel_netdrv_tbl[] __devinitdata = {
154 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
155 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
156 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
157 };
158
159 /* Offsets to the Command and Status Registers. */
160 enum fealnx_offsets {
161 PAR0 = 0x0, /* physical address 0-3 */
162 PAR1 = 0x04, /* physical address 4-5 */
163 MAR0 = 0x08, /* multicast address 0-3 */
164 MAR1 = 0x0C, /* multicast address 4-7 */
165 FAR0 = 0x10, /* flow-control address 0-3 */
166 FAR1 = 0x14, /* flow-control address 4-5 */
167 TCRRCR = 0x18, /* receive & transmit configuration */
168 BCR = 0x1C, /* bus command */
169 TXPDR = 0x20, /* transmit polling demand */
170 RXPDR = 0x24, /* receive polling demand */
171 RXCWP = 0x28, /* receive current word pointer */
172 TXLBA = 0x2C, /* transmit list base address */
173 RXLBA = 0x30, /* receive list base address */
174 ISR = 0x34, /* interrupt status */
175 IMR = 0x38, /* interrupt mask */
176 FTH = 0x3C, /* flow control high/low threshold */
177 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
178 TALLY = 0x44, /* tally counters for crc and mpa */
179 TSR = 0x48, /* tally counter for transmit status */
180 BMCRSR = 0x4c, /* basic mode control and status */
181 PHYIDENTIFIER = 0x50, /* phy identifier */
182 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
183 partner ability */
184 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
185 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
186 };
187
188 /* Bits in the interrupt status/enable registers. */
189 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
190 enum intr_status_bits {
191 RFCON = 0x00020000, /* receive flow control xon packet */
192 RFCOFF = 0x00010000, /* receive flow control xoff packet */
193 LSCStatus = 0x00008000, /* link status change */
194 ANCStatus = 0x00004000, /* autonegotiation completed */
195 FBE = 0x00002000, /* fatal bus error */
196 FBEMask = 0x00001800, /* mask bit12-11 */
197 ParityErr = 0x00000000, /* parity error */
198 TargetErr = 0x00001000, /* target abort */
199 MasterErr = 0x00000800, /* master error */
200 TUNF = 0x00000400, /* transmit underflow */
201 ROVF = 0x00000200, /* receive overflow */
202 ETI = 0x00000100, /* transmit early int */
203 ERI = 0x00000080, /* receive early int */
204 CNTOVF = 0x00000040, /* counter overflow */
205 RBU = 0x00000020, /* receive buffer unavailable */
206 TBU = 0x00000010, /* transmit buffer unavilable */
207 TI = 0x00000008, /* transmit interrupt */
208 RI = 0x00000004, /* receive interrupt */
209 RxErr = 0x00000002, /* receive error */
210 };
211
212 /* Bits in the NetworkConfig register, W for writing, R for reading */
213 /* FIXME: some names are invented by me. Marked with (name?) */
214 /* If you have docs and know bit names, please fix 'em */
215 enum rx_mode_bits {
216 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
217 CR_W_FD = 0x00100000, /* full duplex */
218 CR_W_PS10 = 0x00080000, /* 10 mbit */
219 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
220 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
221 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
222 CR_W_RXMODEMASK = 0x000000e0,
223 CR_W_PROM = 0x00000080, /* promiscuous mode */
224 CR_W_AB = 0x00000040, /* accept broadcast */
225 CR_W_AM = 0x00000020, /* accept mutlicast */
226 CR_W_ARP = 0x00000008, /* receive runt pkt */
227 CR_W_ALP = 0x00000004, /* receive long pkt */
228 CR_W_SEP = 0x00000002, /* receive error pkt */
229 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
230
231 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
232 CR_R_FD = 0x00100000, /* full duplex detected */
233 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
234 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
235 };
236
237 /* The Tulip Rx and Tx buffer descriptors. */
238 struct fealnx_desc {
239 s32 status;
240 s32 control;
241 u32 buffer;
242 u32 next_desc;
243 struct fealnx_desc *next_desc_logical;
244 struct sk_buff *skbuff;
245 u32 reserved1;
246 u32 reserved2;
247 };
248
249 /* Bits in network_desc.status */
250 enum rx_desc_status_bits {
251 RXOWN = 0x80000000, /* own bit */
252 FLNGMASK = 0x0fff0000, /* frame length */
253 FLNGShift = 16,
254 MARSTATUS = 0x00004000, /* multicast address received */
255 BARSTATUS = 0x00002000, /* broadcast address received */
256 PHYSTATUS = 0x00001000, /* physical address received */
257 RXFSD = 0x00000800, /* first descriptor */
258 RXLSD = 0x00000400, /* last descriptor */
259 ErrorSummary = 0x80, /* error summary */
260 RUNT = 0x40, /* runt packet received */
261 LONG = 0x20, /* long packet received */
262 FAE = 0x10, /* frame align error */
263 CRC = 0x08, /* crc error */
264 RXER = 0x04, /* receive error */
265 };
266
267 enum rx_desc_control_bits {
268 RXIC = 0x00800000, /* interrupt control */
269 RBSShift = 0,
270 };
271
272 enum tx_desc_status_bits {
273 TXOWN = 0x80000000, /* own bit */
274 JABTO = 0x00004000, /* jabber timeout */
275 CSL = 0x00002000, /* carrier sense lost */
276 LC = 0x00001000, /* late collision */
277 EC = 0x00000800, /* excessive collision */
278 UDF = 0x00000400, /* fifo underflow */
279 DFR = 0x00000200, /* deferred */
280 HF = 0x00000100, /* heartbeat fail */
281 NCRMask = 0x000000ff, /* collision retry count */
282 NCRShift = 0,
283 };
284
285 enum tx_desc_control_bits {
286 TXIC = 0x80000000, /* interrupt control */
287 ETIControl = 0x40000000, /* early transmit interrupt */
288 TXLD = 0x20000000, /* last descriptor */
289 TXFD = 0x10000000, /* first descriptor */
290 CRCEnable = 0x08000000, /* crc control */
291 PADEnable = 0x04000000, /* padding control */
292 RetryTxLC = 0x02000000, /* retry late collision */
293 PKTSMask = 0x3ff800, /* packet size bit21-11 */
294 PKTSShift = 11,
295 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
296 TBSShift = 0,
297 };
298
299 /* BootROM/EEPROM/MII Management Register */
300 #define MASK_MIIR_MII_READ 0x00000000
301 #define MASK_MIIR_MII_WRITE 0x00000008
302 #define MASK_MIIR_MII_MDO 0x00000004
303 #define MASK_MIIR_MII_MDI 0x00000002
304 #define MASK_MIIR_MII_MDC 0x00000001
305
306 /* ST+OP+PHYAD+REGAD+TA */
307 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
308 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
309
310 /* ------------------------------------------------------------------------- */
311 /* Constants for Myson PHY */
312 /* ------------------------------------------------------------------------- */
313 #define MysonPHYID 0xd0000302
314 /* 89-7-27 add, (begin) */
315 #define MysonPHYID0 0x0302
316 #define StatusRegister 18
317 #define SPEED100 0x0400 // bit10
318 #define FULLMODE 0x0800 // bit11
319 /* 89-7-27 add, (end) */
320
321 /* ------------------------------------------------------------------------- */
322 /* Constants for Seeq 80225 PHY */
323 /* ------------------------------------------------------------------------- */
324 #define SeeqPHYID0 0x0016
325
326 #define MIIRegister18 18
327 #define SPD_DET_100 0x80
328 #define DPLX_DET_FULL 0x40
329
330 /* ------------------------------------------------------------------------- */
331 /* Constants for Ahdoc 101 PHY */
332 /* ------------------------------------------------------------------------- */
333 #define AhdocPHYID0 0x0022
334
335 #define DiagnosticReg 18
336 #define DPLX_FULL 0x0800
337 #define Speed_100 0x0400
338
339 /* 89/6/13 add, */
340 /* -------------------------------------------------------------------------- */
341 /* Constants */
342 /* -------------------------------------------------------------------------- */
343 #define MarvellPHYID0 0x0141
344 #define LevelOnePHYID0 0x0013
345
346 #define MII1000BaseTControlReg 9
347 #define MII1000BaseTStatusReg 10
348 #define SpecificReg 17
349
350 /* for 1000BaseT Control Register */
351 #define PHYAbletoPerform1000FullDuplex 0x0200
352 #define PHYAbletoPerform1000HalfDuplex 0x0100
353 #define PHY1000AbilityMask 0x300
354
355 // for phy specific status register, marvell phy.
356 #define SpeedMask 0x0c000
357 #define Speed_1000M 0x08000
358 #define Speed_100M 0x4000
359 #define Speed_10M 0
360 #define Full_Duplex 0x2000
361
362 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
363 #define LXT1000_100M 0x08000
364 #define LXT1000_1000M 0x0c000
365 #define LXT1000_Full 0x200
366 // 89/12/29 add, for phy specific status register, levelone phy, (end)
367
368 /* for 3-in-1 case, BMCRSR register */
369 #define LinkIsUp2 0x00040000
370
371 /* for PHY */
372 #define LinkIsUp 0x0004
373
374
375 struct netdev_private {
376 /* Descriptor rings first for alignment. */
377 struct fealnx_desc *rx_ring;
378 struct fealnx_desc *tx_ring;
379
380 dma_addr_t rx_ring_dma;
381 dma_addr_t tx_ring_dma;
382
383 spinlock_t lock;
384
385 /* Media monitoring timer. */
386 struct timer_list timer;
387
388 /* Reset timer */
389 struct timer_list reset_timer;
390 int reset_timer_armed;
391 unsigned long crvalue_sv;
392 unsigned long imrvalue_sv;
393
394 /* Frequently used values: keep some adjacent for cache effect. */
395 int flags;
396 struct pci_dev *pci_dev;
397 unsigned long crvalue;
398 unsigned long bcrvalue;
399 unsigned long imrvalue;
400 struct fealnx_desc *cur_rx;
401 struct fealnx_desc *lack_rxbuf;
402 int really_rx_count;
403 struct fealnx_desc *cur_tx;
404 struct fealnx_desc *cur_tx_copy;
405 int really_tx_count;
406 int free_tx_count;
407 unsigned int rx_buf_sz; /* Based on MTU+slack. */
408
409 /* These values are keep track of the transceiver/media in use. */
410 unsigned int linkok;
411 unsigned int line_speed;
412 unsigned int duplexmode;
413 unsigned int default_port:4; /* Last dev->if_port value. */
414 unsigned int PHYType;
415
416 /* MII transceiver section. */
417 int mii_cnt; /* MII device addresses. */
418 unsigned char phys[2]; /* MII device addresses. */
419 struct mii_if_info mii;
420 void __iomem *mem;
421 };
422
423
424 static int mdio_read(struct net_device *dev, int phy_id, int location);
425 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
426 static int netdev_open(struct net_device *dev);
427 static void getlinktype(struct net_device *dev);
428 static void getlinkstatus(struct net_device *dev);
429 static void netdev_timer(unsigned long data);
430 static void reset_timer(unsigned long data);
431 static void fealnx_tx_timeout(struct net_device *dev);
432 static void init_ring(struct net_device *dev);
433 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
434 static irqreturn_t intr_handler(int irq, void *dev_instance);
435 static int netdev_rx(struct net_device *dev);
436 static void set_rx_mode(struct net_device *dev);
437 static void __set_rx_mode(struct net_device *dev);
438 static struct net_device_stats *get_stats(struct net_device *dev);
439 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
440 static const struct ethtool_ops netdev_ethtool_ops;
441 static int netdev_close(struct net_device *dev);
442 static void reset_rx_descriptors(struct net_device *dev);
443 static void reset_tx_descriptors(struct net_device *dev);
444
445 static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
446 {
447 int delay = 0x1000;
448 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
449 while (--delay) {
450 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
451 break;
452 }
453 }
454
455
456 static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
457 {
458 int delay = 0x1000;
459 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
460 while (--delay) {
461 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
462 == (CR_R_RXSTOP+CR_R_TXSTOP) )
463 break;
464 }
465 }
466
467 static const struct net_device_ops netdev_ops = {
468 .ndo_open = netdev_open,
469 .ndo_stop = netdev_close,
470 .ndo_start_xmit = start_tx,
471 .ndo_get_stats = get_stats,
472 .ndo_set_rx_mode = set_rx_mode,
473 .ndo_do_ioctl = mii_ioctl,
474 .ndo_tx_timeout = fealnx_tx_timeout,
475 .ndo_change_mtu = eth_change_mtu,
476 .ndo_set_mac_address = eth_mac_addr,
477 .ndo_validate_addr = eth_validate_addr,
478 };
479
480 static int __devinit fealnx_init_one(struct pci_dev *pdev,
481 const struct pci_device_id *ent)
482 {
483 struct netdev_private *np;
484 int i, option, err, irq;
485 static int card_idx = -1;
486 char boardname[12];
487 void __iomem *ioaddr;
488 unsigned long len;
489 unsigned int chip_id = ent->driver_data;
490 struct net_device *dev;
491 void *ring_space;
492 dma_addr_t ring_dma;
493 #ifdef USE_IO_OPS
494 int bar = 0;
495 #else
496 int bar = 1;
497 #endif
498
499 /* when built into the kernel, we only print version if device is found */
500 #ifndef MODULE
501 static int printed_version;
502 if (!printed_version++)
503 printk(version);
504 #endif
505
506 card_idx++;
507 sprintf(boardname, "fealnx%d", card_idx);
508
509 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
510
511 i = pci_enable_device(pdev);
512 if (i) return i;
513 pci_set_master(pdev);
514
515 len = pci_resource_len(pdev, bar);
516 if (len < MIN_REGION_SIZE) {
517 dev_err(&pdev->dev,
518 "region size %ld too small, aborting\n", len);
519 return -ENODEV;
520 }
521
522 i = pci_request_regions(pdev, boardname);
523 if (i)
524 return i;
525
526 irq = pdev->irq;
527
528 ioaddr = pci_iomap(pdev, bar, len);
529 if (!ioaddr) {
530 err = -ENOMEM;
531 goto err_out_res;
532 }
533
534 dev = alloc_etherdev(sizeof(struct netdev_private));
535 if (!dev) {
536 err = -ENOMEM;
537 goto err_out_unmap;
538 }
539 SET_NETDEV_DEV(dev, &pdev->dev);
540
541 /* read ethernet id */
542 for (i = 0; i < 6; ++i)
543 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
544
545 /* Reset the chip to erase previous misconfiguration. */
546 iowrite32(0x00000001, ioaddr + BCR);
547
548 /* Make certain the descriptor lists are aligned. */
549 np = netdev_priv(dev);
550 np->mem = ioaddr;
551 spin_lock_init(&np->lock);
552 np->pci_dev = pdev;
553 np->flags = skel_netdrv_tbl[chip_id].flags;
554 pci_set_drvdata(pdev, dev);
555 np->mii.dev = dev;
556 np->mii.mdio_read = mdio_read;
557 np->mii.mdio_write = mdio_write;
558 np->mii.phy_id_mask = 0x1f;
559 np->mii.reg_num_mask = 0x1f;
560
561 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
562 if (!ring_space) {
563 err = -ENOMEM;
564 goto err_out_free_dev;
565 }
566 np->rx_ring = ring_space;
567 np->rx_ring_dma = ring_dma;
568
569 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
570 if (!ring_space) {
571 err = -ENOMEM;
572 goto err_out_free_rx;
573 }
574 np->tx_ring = ring_space;
575 np->tx_ring_dma = ring_dma;
576
577 /* find the connected MII xcvrs */
578 if (np->flags == HAS_MII_XCVR) {
579 int phy, phy_idx = 0;
580
581 for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys);
582 phy++) {
583 int mii_status = mdio_read(dev, phy, 1);
584
585 if (mii_status != 0xffff && mii_status != 0x0000) {
586 np->phys[phy_idx++] = phy;
587 dev_info(&pdev->dev,
588 "MII PHY found at address %d, status "
589 "0x%4.4x.\n", phy, mii_status);
590 /* get phy type */
591 {
592 unsigned int data;
593
594 data = mdio_read(dev, np->phys[0], 2);
595 if (data == SeeqPHYID0)
596 np->PHYType = SeeqPHY;
597 else if (data == AhdocPHYID0)
598 np->PHYType = AhdocPHY;
599 else if (data == MarvellPHYID0)
600 np->PHYType = MarvellPHY;
601 else if (data == MysonPHYID0)
602 np->PHYType = Myson981;
603 else if (data == LevelOnePHYID0)
604 np->PHYType = LevelOnePHY;
605 else
606 np->PHYType = OtherPHY;
607 }
608 }
609 }
610
611 np->mii_cnt = phy_idx;
612 if (phy_idx == 0)
613 dev_warn(&pdev->dev,
614 "MII PHY not found -- this device may "
615 "not operate correctly.\n");
616 } else {
617 np->phys[0] = 32;
618 /* 89/6/23 add, (begin) */
619 /* get phy type */
620 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
621 np->PHYType = MysonPHY;
622 else
623 np->PHYType = OtherPHY;
624 }
625 np->mii.phy_id = np->phys[0];
626
627 if (dev->mem_start)
628 option = dev->mem_start;
629
630 /* The lower four bits are the media type. */
631 if (option > 0) {
632 if (option & 0x200)
633 np->mii.full_duplex = 1;
634 np->default_port = option & 15;
635 }
636
637 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
638 np->mii.full_duplex = full_duplex[card_idx];
639
640 if (np->mii.full_duplex) {
641 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
642 /* 89/6/13 add, (begin) */
643 // if (np->PHYType==MarvellPHY)
644 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
645 unsigned int data;
646
647 data = mdio_read(dev, np->phys[0], 9);
648 data = (data & 0xfcff) | 0x0200;
649 mdio_write(dev, np->phys[0], 9, data);
650 }
651 /* 89/6/13 add, (end) */
652 if (np->flags == HAS_MII_XCVR)
653 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
654 else
655 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
656 np->mii.force_media = 1;
657 }
658
659 dev->netdev_ops = &netdev_ops;
660 dev->ethtool_ops = &netdev_ethtool_ops;
661 dev->watchdog_timeo = TX_TIMEOUT;
662
663 err = register_netdev(dev);
664 if (err)
665 goto err_out_free_tx;
666
667 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
668 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
669 dev->dev_addr, irq);
670
671 return 0;
672
673 err_out_free_tx:
674 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
675 err_out_free_rx:
676 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
677 err_out_free_dev:
678 free_netdev(dev);
679 err_out_unmap:
680 pci_iounmap(pdev, ioaddr);
681 err_out_res:
682 pci_release_regions(pdev);
683 return err;
684 }
685
686
687 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
688 {
689 struct net_device *dev = pci_get_drvdata(pdev);
690
691 if (dev) {
692 struct netdev_private *np = netdev_priv(dev);
693
694 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
695 np->tx_ring_dma);
696 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
697 np->rx_ring_dma);
698 unregister_netdev(dev);
699 pci_iounmap(pdev, np->mem);
700 free_netdev(dev);
701 pci_release_regions(pdev);
702 pci_set_drvdata(pdev, NULL);
703 } else
704 printk(KERN_ERR "fealnx: remove for unknown device\n");
705 }
706
707
708 static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
709 {
710 ulong miir;
711 int i;
712 unsigned int mask, data;
713
714 /* enable MII output */
715 miir = (ulong) ioread32(miiport);
716 miir &= 0xfffffff0;
717
718 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
719
720 /* send 32 1's preamble */
721 for (i = 0; i < 32; i++) {
722 /* low MDC; MDO is already high (miir) */
723 miir &= ~MASK_MIIR_MII_MDC;
724 iowrite32(miir, miiport);
725
726 /* high MDC */
727 miir |= MASK_MIIR_MII_MDC;
728 iowrite32(miir, miiport);
729 }
730
731 /* calculate ST+OP+PHYAD+REGAD+TA */
732 data = opcode | (phyad << 7) | (regad << 2);
733
734 /* sent out */
735 mask = 0x8000;
736 while (mask) {
737 /* low MDC, prepare MDO */
738 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
739 if (mask & data)
740 miir |= MASK_MIIR_MII_MDO;
741
742 iowrite32(miir, miiport);
743 /* high MDC */
744 miir |= MASK_MIIR_MII_MDC;
745 iowrite32(miir, miiport);
746 udelay(30);
747
748 /* next */
749 mask >>= 1;
750 if (mask == 0x2 && opcode == OP_READ)
751 miir &= ~MASK_MIIR_MII_WRITE;
752 }
753 return miir;
754 }
755
756
757 static int mdio_read(struct net_device *dev, int phyad, int regad)
758 {
759 struct netdev_private *np = netdev_priv(dev);
760 void __iomem *miiport = np->mem + MANAGEMENT;
761 ulong miir;
762 unsigned int mask, data;
763
764 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
765
766 /* read data */
767 mask = 0x8000;
768 data = 0;
769 while (mask) {
770 /* low MDC */
771 miir &= ~MASK_MIIR_MII_MDC;
772 iowrite32(miir, miiport);
773
774 /* read MDI */
775 miir = ioread32(miiport);
776 if (miir & MASK_MIIR_MII_MDI)
777 data |= mask;
778
779 /* high MDC, and wait */
780 miir |= MASK_MIIR_MII_MDC;
781 iowrite32(miir, miiport);
782 udelay(30);
783
784 /* next */
785 mask >>= 1;
786 }
787
788 /* low MDC */
789 miir &= ~MASK_MIIR_MII_MDC;
790 iowrite32(miir, miiport);
791
792 return data & 0xffff;
793 }
794
795
796 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
797 {
798 struct netdev_private *np = netdev_priv(dev);
799 void __iomem *miiport = np->mem + MANAGEMENT;
800 ulong miir;
801 unsigned int mask;
802
803 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
804
805 /* write data */
806 mask = 0x8000;
807 while (mask) {
808 /* low MDC, prepare MDO */
809 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
810 if (mask & data)
811 miir |= MASK_MIIR_MII_MDO;
812 iowrite32(miir, miiport);
813
814 /* high MDC */
815 miir |= MASK_MIIR_MII_MDC;
816 iowrite32(miir, miiport);
817
818 /* next */
819 mask >>= 1;
820 }
821
822 /* low MDC */
823 miir &= ~MASK_MIIR_MII_MDC;
824 iowrite32(miir, miiport);
825 }
826
827
828 static int netdev_open(struct net_device *dev)
829 {
830 struct netdev_private *np = netdev_priv(dev);
831 void __iomem *ioaddr = np->mem;
832 const int irq = np->pci_dev->irq;
833 int rc, i;
834
835 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
836
837 rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
838 if (rc)
839 return -EAGAIN;
840
841 for (i = 0; i < 3; i++)
842 iowrite16(((unsigned short*)dev->dev_addr)[i],
843 ioaddr + PAR0 + i*2);
844
845 init_ring(dev);
846
847 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
848 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
849
850 /* Initialize other registers. */
851 /* Configure the PCI bus bursts and FIFO thresholds.
852 486: Set 8 longword burst.
853 586: no burst limit.
854 Burst length 5:3
855 0 0 0 1
856 0 0 1 4
857 0 1 0 8
858 0 1 1 16
859 1 0 0 32
860 1 0 1 64
861 1 1 0 128
862 1 1 1 256
863 Wait the specified 50 PCI cycles after a reset by initializing
864 Tx and Rx queues and the address filter list.
865 FIXME (Ueimor): optimistic for alpha + posted writes ? */
866
867 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
868 #ifdef __BIG_ENDIAN
869 np->bcrvalue |= 0x04; /* big-endian */
870 #endif
871
872 #if defined(__i386__) && !defined(MODULE)
873 if (boot_cpu_data.x86 <= 4)
874 np->crvalue = 0xa00;
875 else
876 #endif
877 np->crvalue = 0xe00; /* rx 128 burst length */
878
879
880 // 89/12/29 add,
881 // 90/1/16 modify,
882 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
883 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
884 if (np->pci_dev->device == 0x891) {
885 np->bcrvalue |= 0x200; /* set PROG bit */
886 np->crvalue |= CR_W_ENH; /* set enhanced bit */
887 np->imrvalue |= ETI;
888 }
889 iowrite32(np->bcrvalue, ioaddr + BCR);
890
891 if (dev->if_port == 0)
892 dev->if_port = np->default_port;
893
894 iowrite32(0, ioaddr + RXPDR);
895 // 89/9/1 modify,
896 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
897 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
898 np->mii.full_duplex = np->mii.force_media;
899 getlinkstatus(dev);
900 if (np->linkok)
901 getlinktype(dev);
902 __set_rx_mode(dev);
903
904 netif_start_queue(dev);
905
906 /* Clear and Enable interrupts by setting the interrupt mask. */
907 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
908 iowrite32(np->imrvalue, ioaddr + IMR);
909
910 if (debug)
911 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
912
913 /* Set the timer to check for link beat. */
914 init_timer(&np->timer);
915 np->timer.expires = RUN_AT(3 * HZ);
916 np->timer.data = (unsigned long) dev;
917 np->timer.function = netdev_timer;
918
919 /* timer handler */
920 add_timer(&np->timer);
921
922 init_timer(&np->reset_timer);
923 np->reset_timer.data = (unsigned long) dev;
924 np->reset_timer.function = reset_timer;
925 np->reset_timer_armed = 0;
926 out:
927 return rc;
928 }
929
930
931 static void getlinkstatus(struct net_device *dev)
932 /* function: Routine will read MII Status Register to get link status. */
933 /* input : dev... pointer to the adapter block. */
934 /* output : none. */
935 {
936 struct netdev_private *np = netdev_priv(dev);
937 unsigned int i, DelayTime = 0x1000;
938
939 np->linkok = 0;
940
941 if (np->PHYType == MysonPHY) {
942 for (i = 0; i < DelayTime; ++i) {
943 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
944 np->linkok = 1;
945 return;
946 }
947 udelay(100);
948 }
949 } else {
950 for (i = 0; i < DelayTime; ++i) {
951 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
952 np->linkok = 1;
953 return;
954 }
955 udelay(100);
956 }
957 }
958 }
959
960
961 static void getlinktype(struct net_device *dev)
962 {
963 struct netdev_private *np = netdev_priv(dev);
964
965 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
966 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
967 np->duplexmode = 2; /* full duplex */
968 else
969 np->duplexmode = 1; /* half duplex */
970 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
971 np->line_speed = 1; /* 10M */
972 else
973 np->line_speed = 2; /* 100M */
974 } else {
975 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
976 unsigned int data;
977
978 data = mdio_read(dev, np->phys[0], MIIRegister18);
979 if (data & SPD_DET_100)
980 np->line_speed = 2; /* 100M */
981 else
982 np->line_speed = 1; /* 10M */
983 if (data & DPLX_DET_FULL)
984 np->duplexmode = 2; /* full duplex mode */
985 else
986 np->duplexmode = 1; /* half duplex mode */
987 } else if (np->PHYType == AhdocPHY) {
988 unsigned int data;
989
990 data = mdio_read(dev, np->phys[0], DiagnosticReg);
991 if (data & Speed_100)
992 np->line_speed = 2; /* 100M */
993 else
994 np->line_speed = 1; /* 10M */
995 if (data & DPLX_FULL)
996 np->duplexmode = 2; /* full duplex mode */
997 else
998 np->duplexmode = 1; /* half duplex mode */
999 }
1000 /* 89/6/13 add, (begin) */
1001 else if (np->PHYType == MarvellPHY) {
1002 unsigned int data;
1003
1004 data = mdio_read(dev, np->phys[0], SpecificReg);
1005 if (data & Full_Duplex)
1006 np->duplexmode = 2; /* full duplex mode */
1007 else
1008 np->duplexmode = 1; /* half duplex mode */
1009 data &= SpeedMask;
1010 if (data == Speed_1000M)
1011 np->line_speed = 3; /* 1000M */
1012 else if (data == Speed_100M)
1013 np->line_speed = 2; /* 100M */
1014 else
1015 np->line_speed = 1; /* 10M */
1016 }
1017 /* 89/6/13 add, (end) */
1018 /* 89/7/27 add, (begin) */
1019 else if (np->PHYType == Myson981) {
1020 unsigned int data;
1021
1022 data = mdio_read(dev, np->phys[0], StatusRegister);
1023
1024 if (data & SPEED100)
1025 np->line_speed = 2;
1026 else
1027 np->line_speed = 1;
1028
1029 if (data & FULLMODE)
1030 np->duplexmode = 2;
1031 else
1032 np->duplexmode = 1;
1033 }
1034 /* 89/7/27 add, (end) */
1035 /* 89/12/29 add */
1036 else if (np->PHYType == LevelOnePHY) {
1037 unsigned int data;
1038
1039 data = mdio_read(dev, np->phys[0], SpecificReg);
1040 if (data & LXT1000_Full)
1041 np->duplexmode = 2; /* full duplex mode */
1042 else
1043 np->duplexmode = 1; /* half duplex mode */
1044 data &= SpeedMask;
1045 if (data == LXT1000_1000M)
1046 np->line_speed = 3; /* 1000M */
1047 else if (data == LXT1000_100M)
1048 np->line_speed = 2; /* 100M */
1049 else
1050 np->line_speed = 1; /* 10M */
1051 }
1052 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1053 if (np->line_speed == 1)
1054 np->crvalue |= CR_W_PS10;
1055 else if (np->line_speed == 3)
1056 np->crvalue |= CR_W_PS1000;
1057 if (np->duplexmode == 2)
1058 np->crvalue |= CR_W_FD;
1059 }
1060 }
1061
1062
1063 /* Take lock before calling this */
1064 static void allocate_rx_buffers(struct net_device *dev)
1065 {
1066 struct netdev_private *np = netdev_priv(dev);
1067
1068 /* allocate skb for rx buffers */
1069 while (np->really_rx_count != RX_RING_SIZE) {
1070 struct sk_buff *skb;
1071
1072 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1073 if (skb == NULL)
1074 break; /* Better luck next round. */
1075
1076 while (np->lack_rxbuf->skbuff)
1077 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1078
1079 np->lack_rxbuf->skbuff = skb;
1080 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1081 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1082 np->lack_rxbuf->status = RXOWN;
1083 ++np->really_rx_count;
1084 }
1085 }
1086
1087
1088 static void netdev_timer(unsigned long data)
1089 {
1090 struct net_device *dev = (struct net_device *) data;
1091 struct netdev_private *np = netdev_priv(dev);
1092 void __iomem *ioaddr = np->mem;
1093 int old_crvalue = np->crvalue;
1094 unsigned int old_linkok = np->linkok;
1095 unsigned long flags;
1096
1097 if (debug)
1098 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1099 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1100 ioread32(ioaddr + TCRRCR));
1101
1102 spin_lock_irqsave(&np->lock, flags);
1103
1104 if (np->flags == HAS_MII_XCVR) {
1105 getlinkstatus(dev);
1106 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1107 getlinktype(dev);
1108 if (np->crvalue != old_crvalue) {
1109 stop_nic_rxtx(ioaddr, np->crvalue);
1110 iowrite32(np->crvalue, ioaddr + TCRRCR);
1111 }
1112 }
1113 }
1114
1115 allocate_rx_buffers(dev);
1116
1117 spin_unlock_irqrestore(&np->lock, flags);
1118
1119 np->timer.expires = RUN_AT(10 * HZ);
1120 add_timer(&np->timer);
1121 }
1122
1123
1124 /* Take lock before calling */
1125 /* Reset chip and disable rx, tx and interrupts */
1126 static void reset_and_disable_rxtx(struct net_device *dev)
1127 {
1128 struct netdev_private *np = netdev_priv(dev);
1129 void __iomem *ioaddr = np->mem;
1130 int delay=51;
1131
1132 /* Reset the chip's Tx and Rx processes. */
1133 stop_nic_rxtx(ioaddr, 0);
1134
1135 /* Disable interrupts by clearing the interrupt mask. */
1136 iowrite32(0, ioaddr + IMR);
1137
1138 /* Reset the chip to erase previous misconfiguration. */
1139 iowrite32(0x00000001, ioaddr + BCR);
1140
1141 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1142 We surely wait too long (address+data phase). Who cares? */
1143 while (--delay) {
1144 ioread32(ioaddr + BCR);
1145 rmb();
1146 }
1147 }
1148
1149
1150 /* Take lock before calling */
1151 /* Restore chip after reset */
1152 static void enable_rxtx(struct net_device *dev)
1153 {
1154 struct netdev_private *np = netdev_priv(dev);
1155 void __iomem *ioaddr = np->mem;
1156
1157 reset_rx_descriptors(dev);
1158
1159 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1160 ioaddr + TXLBA);
1161 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1162 ioaddr + RXLBA);
1163
1164 iowrite32(np->bcrvalue, ioaddr + BCR);
1165
1166 iowrite32(0, ioaddr + RXPDR);
1167 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1168
1169 /* Clear and Enable interrupts by setting the interrupt mask. */
1170 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1171 iowrite32(np->imrvalue, ioaddr + IMR);
1172
1173 iowrite32(0, ioaddr + TXPDR);
1174 }
1175
1176
1177 static void reset_timer(unsigned long data)
1178 {
1179 struct net_device *dev = (struct net_device *) data;
1180 struct netdev_private *np = netdev_priv(dev);
1181 unsigned long flags;
1182
1183 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1184
1185 spin_lock_irqsave(&np->lock, flags);
1186 np->crvalue = np->crvalue_sv;
1187 np->imrvalue = np->imrvalue_sv;
1188
1189 reset_and_disable_rxtx(dev);
1190 /* works for me without this:
1191 reset_tx_descriptors(dev); */
1192 enable_rxtx(dev);
1193 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1194
1195 np->reset_timer_armed = 0;
1196
1197 spin_unlock_irqrestore(&np->lock, flags);
1198 }
1199
1200
1201 static void fealnx_tx_timeout(struct net_device *dev)
1202 {
1203 struct netdev_private *np = netdev_priv(dev);
1204 void __iomem *ioaddr = np->mem;
1205 unsigned long flags;
1206 int i;
1207
1208 printk(KERN_WARNING
1209 "%s: Transmit timed out, status %8.8x, resetting...\n",
1210 dev->name, ioread32(ioaddr + ISR));
1211
1212 {
1213 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1214 for (i = 0; i < RX_RING_SIZE; i++)
1215 printk(KERN_CONT " %8.8x",
1216 (unsigned int) np->rx_ring[i].status);
1217 printk(KERN_CONT "\n");
1218 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1219 for (i = 0; i < TX_RING_SIZE; i++)
1220 printk(KERN_CONT " %4.4x", np->tx_ring[i].status);
1221 printk(KERN_CONT "\n");
1222 }
1223
1224 spin_lock_irqsave(&np->lock, flags);
1225
1226 reset_and_disable_rxtx(dev);
1227 reset_tx_descriptors(dev);
1228 enable_rxtx(dev);
1229
1230 spin_unlock_irqrestore(&np->lock, flags);
1231
1232 dev->trans_start = jiffies; /* prevent tx timeout */
1233 dev->stats.tx_errors++;
1234 netif_wake_queue(dev); /* or .._start_.. ?? */
1235 }
1236
1237
1238 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1239 static void init_ring(struct net_device *dev)
1240 {
1241 struct netdev_private *np = netdev_priv(dev);
1242 int i;
1243
1244 /* initialize rx variables */
1245 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1246 np->cur_rx = &np->rx_ring[0];
1247 np->lack_rxbuf = np->rx_ring;
1248 np->really_rx_count = 0;
1249
1250 /* initial rx descriptors. */
1251 for (i = 0; i < RX_RING_SIZE; i++) {
1252 np->rx_ring[i].status = 0;
1253 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1254 np->rx_ring[i].next_desc = np->rx_ring_dma +
1255 (i + 1)*sizeof(struct fealnx_desc);
1256 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1257 np->rx_ring[i].skbuff = NULL;
1258 }
1259
1260 /* for the last rx descriptor */
1261 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1262 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1263
1264 /* allocate skb for rx buffers */
1265 for (i = 0; i < RX_RING_SIZE; i++) {
1266 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1267
1268 if (skb == NULL) {
1269 np->lack_rxbuf = &np->rx_ring[i];
1270 break;
1271 }
1272
1273 ++np->really_rx_count;
1274 np->rx_ring[i].skbuff = skb;
1275 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1276 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1277 np->rx_ring[i].status = RXOWN;
1278 np->rx_ring[i].control |= RXIC;
1279 }
1280
1281 /* initialize tx variables */
1282 np->cur_tx = &np->tx_ring[0];
1283 np->cur_tx_copy = &np->tx_ring[0];
1284 np->really_tx_count = 0;
1285 np->free_tx_count = TX_RING_SIZE;
1286
1287 for (i = 0; i < TX_RING_SIZE; i++) {
1288 np->tx_ring[i].status = 0;
1289 /* do we need np->tx_ring[i].control = XXX; ?? */
1290 np->tx_ring[i].next_desc = np->tx_ring_dma +
1291 (i + 1)*sizeof(struct fealnx_desc);
1292 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1293 np->tx_ring[i].skbuff = NULL;
1294 }
1295
1296 /* for the last tx descriptor */
1297 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1298 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1299 }
1300
1301
1302 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1303 {
1304 struct netdev_private *np = netdev_priv(dev);
1305 unsigned long flags;
1306
1307 spin_lock_irqsave(&np->lock, flags);
1308
1309 np->cur_tx_copy->skbuff = skb;
1310
1311 #define one_buffer
1312 #define BPT 1022
1313 #if defined(one_buffer)
1314 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1315 skb->len, PCI_DMA_TODEVICE);
1316 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1317 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1318 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1319 // 89/12/29 add,
1320 if (np->pci_dev->device == 0x891)
1321 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1322 np->cur_tx_copy->status = TXOWN;
1323 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1324 --np->free_tx_count;
1325 #elif defined(two_buffer)
1326 if (skb->len > BPT) {
1327 struct fealnx_desc *next;
1328
1329 /* for the first descriptor */
1330 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1331 BPT, PCI_DMA_TODEVICE);
1332 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1333 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1334 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1335
1336 /* for the last descriptor */
1337 next = np->cur_tx_copy->next_desc_logical;
1338 next->skbuff = skb;
1339 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1340 next->control |= (skb->len << PKTSShift); /* pkt size */
1341 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1342 // 89/12/29 add,
1343 if (np->pci_dev->device == 0x891)
1344 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1345 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1346 skb->len - BPT, PCI_DMA_TODEVICE);
1347
1348 next->status = TXOWN;
1349 np->cur_tx_copy->status = TXOWN;
1350
1351 np->cur_tx_copy = next->next_desc_logical;
1352 np->free_tx_count -= 2;
1353 } else {
1354 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1355 skb->len, PCI_DMA_TODEVICE);
1356 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1357 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1358 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1359 // 89/12/29 add,
1360 if (np->pci_dev->device == 0x891)
1361 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1362 np->cur_tx_copy->status = TXOWN;
1363 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1364 --np->free_tx_count;
1365 }
1366 #endif
1367
1368 if (np->free_tx_count < 2)
1369 netif_stop_queue(dev);
1370 ++np->really_tx_count;
1371 iowrite32(0, np->mem + TXPDR);
1372
1373 spin_unlock_irqrestore(&np->lock, flags);
1374 return NETDEV_TX_OK;
1375 }
1376
1377
1378 /* Take lock before calling */
1379 /* Chip probably hosed tx ring. Clean up. */
1380 static void reset_tx_descriptors(struct net_device *dev)
1381 {
1382 struct netdev_private *np = netdev_priv(dev);
1383 struct fealnx_desc *cur;
1384 int i;
1385
1386 /* initialize tx variables */
1387 np->cur_tx = &np->tx_ring[0];
1388 np->cur_tx_copy = &np->tx_ring[0];
1389 np->really_tx_count = 0;
1390 np->free_tx_count = TX_RING_SIZE;
1391
1392 for (i = 0; i < TX_RING_SIZE; i++) {
1393 cur = &np->tx_ring[i];
1394 if (cur->skbuff) {
1395 pci_unmap_single(np->pci_dev, cur->buffer,
1396 cur->skbuff->len, PCI_DMA_TODEVICE);
1397 dev_kfree_skb_any(cur->skbuff);
1398 cur->skbuff = NULL;
1399 }
1400 cur->status = 0;
1401 cur->control = 0; /* needed? */
1402 /* probably not needed. We do it for purely paranoid reasons */
1403 cur->next_desc = np->tx_ring_dma +
1404 (i + 1)*sizeof(struct fealnx_desc);
1405 cur->next_desc_logical = &np->tx_ring[i + 1];
1406 }
1407 /* for the last tx descriptor */
1408 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1409 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1410 }
1411
1412
1413 /* Take lock and stop rx before calling this */
1414 static void reset_rx_descriptors(struct net_device *dev)
1415 {
1416 struct netdev_private *np = netdev_priv(dev);
1417 struct fealnx_desc *cur = np->cur_rx;
1418 int i;
1419
1420 allocate_rx_buffers(dev);
1421
1422 for (i = 0; i < RX_RING_SIZE; i++) {
1423 if (cur->skbuff)
1424 cur->status = RXOWN;
1425 cur = cur->next_desc_logical;
1426 }
1427
1428 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1429 np->mem + RXLBA);
1430 }
1431
1432
1433 /* The interrupt handler does all of the Rx thread work and cleans up
1434 after the Tx thread. */
1435 static irqreturn_t intr_handler(int irq, void *dev_instance)
1436 {
1437 struct net_device *dev = (struct net_device *) dev_instance;
1438 struct netdev_private *np = netdev_priv(dev);
1439 void __iomem *ioaddr = np->mem;
1440 long boguscnt = max_interrupt_work;
1441 unsigned int num_tx = 0;
1442 int handled = 0;
1443
1444 spin_lock(&np->lock);
1445
1446 iowrite32(0, ioaddr + IMR);
1447
1448 do {
1449 u32 intr_status = ioread32(ioaddr + ISR);
1450
1451 /* Acknowledge all of the current interrupt sources ASAP. */
1452 iowrite32(intr_status, ioaddr + ISR);
1453
1454 if (debug)
1455 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1456 intr_status);
1457
1458 if (!(intr_status & np->imrvalue))
1459 break;
1460
1461 handled = 1;
1462
1463 // 90/1/16 delete,
1464 //
1465 // if (intr_status & FBE)
1466 // { /* fatal error */
1467 // stop_nic_tx(ioaddr, 0);
1468 // stop_nic_rx(ioaddr, 0);
1469 // break;
1470 // };
1471
1472 if (intr_status & TUNF)
1473 iowrite32(0, ioaddr + TXPDR);
1474
1475 if (intr_status & CNTOVF) {
1476 /* missed pkts */
1477 dev->stats.rx_missed_errors +=
1478 ioread32(ioaddr + TALLY) & 0x7fff;
1479
1480 /* crc error */
1481 dev->stats.rx_crc_errors +=
1482 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1483 }
1484
1485 if (intr_status & (RI | RBU)) {
1486 if (intr_status & RI)
1487 netdev_rx(dev);
1488 else {
1489 stop_nic_rx(ioaddr, np->crvalue);
1490 reset_rx_descriptors(dev);
1491 iowrite32(np->crvalue, ioaddr + TCRRCR);
1492 }
1493 }
1494
1495 while (np->really_tx_count) {
1496 long tx_status = np->cur_tx->status;
1497 long tx_control = np->cur_tx->control;
1498
1499 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1500 struct fealnx_desc *next;
1501
1502 next = np->cur_tx->next_desc_logical;
1503 tx_status = next->status;
1504 tx_control = next->control;
1505 }
1506
1507 if (tx_status & TXOWN)
1508 break;
1509
1510 if (!(np->crvalue & CR_W_ENH)) {
1511 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1512 dev->stats.tx_errors++;
1513 if (tx_status & EC)
1514 dev->stats.tx_aborted_errors++;
1515 if (tx_status & CSL)
1516 dev->stats.tx_carrier_errors++;
1517 if (tx_status & LC)
1518 dev->stats.tx_window_errors++;
1519 if (tx_status & UDF)
1520 dev->stats.tx_fifo_errors++;
1521 if ((tx_status & HF) && np->mii.full_duplex == 0)
1522 dev->stats.tx_heartbeat_errors++;
1523
1524 } else {
1525 dev->stats.tx_bytes +=
1526 ((tx_control & PKTSMask) >> PKTSShift);
1527
1528 dev->stats.collisions +=
1529 ((tx_status & NCRMask) >> NCRShift);
1530 dev->stats.tx_packets++;
1531 }
1532 } else {
1533 dev->stats.tx_bytes +=
1534 ((tx_control & PKTSMask) >> PKTSShift);
1535 dev->stats.tx_packets++;
1536 }
1537
1538 /* Free the original skb. */
1539 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1540 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1541 dev_kfree_skb_irq(np->cur_tx->skbuff);
1542 np->cur_tx->skbuff = NULL;
1543 --np->really_tx_count;
1544 if (np->cur_tx->control & TXLD) {
1545 np->cur_tx = np->cur_tx->next_desc_logical;
1546 ++np->free_tx_count;
1547 } else {
1548 np->cur_tx = np->cur_tx->next_desc_logical;
1549 np->cur_tx = np->cur_tx->next_desc_logical;
1550 np->free_tx_count += 2;
1551 }
1552 num_tx++;
1553 } /* end of for loop */
1554
1555 if (num_tx && np->free_tx_count >= 2)
1556 netif_wake_queue(dev);
1557
1558 /* read transmit status for enhanced mode only */
1559 if (np->crvalue & CR_W_ENH) {
1560 long data;
1561
1562 data = ioread32(ioaddr + TSR);
1563 dev->stats.tx_errors += (data & 0xff000000) >> 24;
1564 dev->stats.tx_aborted_errors +=
1565 (data & 0xff000000) >> 24;
1566 dev->stats.tx_window_errors +=
1567 (data & 0x00ff0000) >> 16;
1568 dev->stats.collisions += (data & 0x0000ffff);
1569 }
1570
1571 if (--boguscnt < 0) {
1572 printk(KERN_WARNING "%s: Too much work at interrupt, "
1573 "status=0x%4.4x.\n", dev->name, intr_status);
1574 if (!np->reset_timer_armed) {
1575 np->reset_timer_armed = 1;
1576 np->reset_timer.expires = RUN_AT(HZ/2);
1577 add_timer(&np->reset_timer);
1578 stop_nic_rxtx(ioaddr, 0);
1579 netif_stop_queue(dev);
1580 /* or netif_tx_disable(dev); ?? */
1581 /* Prevent other paths from enabling tx,rx,intrs */
1582 np->crvalue_sv = np->crvalue;
1583 np->imrvalue_sv = np->imrvalue;
1584 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1585 np->imrvalue = 0;
1586 }
1587
1588 break;
1589 }
1590 } while (1);
1591
1592 /* read the tally counters */
1593 /* missed pkts */
1594 dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1595
1596 /* crc error */
1597 dev->stats.rx_crc_errors +=
1598 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1599
1600 if (debug)
1601 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1602 dev->name, ioread32(ioaddr + ISR));
1603
1604 iowrite32(np->imrvalue, ioaddr + IMR);
1605
1606 spin_unlock(&np->lock);
1607
1608 return IRQ_RETVAL(handled);
1609 }
1610
1611
1612 /* This routine is logically part of the interrupt handler, but separated
1613 for clarity and better register allocation. */
1614 static int netdev_rx(struct net_device *dev)
1615 {
1616 struct netdev_private *np = netdev_priv(dev);
1617 void __iomem *ioaddr = np->mem;
1618
1619 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1620 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1621 s32 rx_status = np->cur_rx->status;
1622
1623 if (np->really_rx_count == 0)
1624 break;
1625
1626 if (debug)
1627 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1628
1629 if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) ||
1630 (rx_status & ErrorSummary)) {
1631 if (rx_status & ErrorSummary) { /* there was a fatal error */
1632 if (debug)
1633 printk(KERN_DEBUG
1634 "%s: Receive error, Rx status %8.8x.\n",
1635 dev->name, rx_status);
1636
1637 dev->stats.rx_errors++; /* end of a packet. */
1638 if (rx_status & (LONG | RUNT))
1639 dev->stats.rx_length_errors++;
1640 if (rx_status & RXER)
1641 dev->stats.rx_frame_errors++;
1642 if (rx_status & CRC)
1643 dev->stats.rx_crc_errors++;
1644 } else {
1645 int need_to_reset = 0;
1646 int desno = 0;
1647
1648 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1649 struct fealnx_desc *cur;
1650
1651 /* check this packet is received completely? */
1652 cur = np->cur_rx;
1653 while (desno <= np->really_rx_count) {
1654 ++desno;
1655 if ((!(cur->status & RXOWN)) &&
1656 (cur->status & RXLSD))
1657 break;
1658 /* goto next rx descriptor */
1659 cur = cur->next_desc_logical;
1660 }
1661 if (desno > np->really_rx_count)
1662 need_to_reset = 1;
1663 } else /* RXLSD did not find, something error */
1664 need_to_reset = 1;
1665
1666 if (need_to_reset == 0) {
1667 int i;
1668
1669 dev->stats.rx_length_errors++;
1670
1671 /* free all rx descriptors related this long pkt */
1672 for (i = 0; i < desno; ++i) {
1673 if (!np->cur_rx->skbuff) {
1674 printk(KERN_DEBUG
1675 "%s: I'm scared\n", dev->name);
1676 break;
1677 }
1678 np->cur_rx->status = RXOWN;
1679 np->cur_rx = np->cur_rx->next_desc_logical;
1680 }
1681 continue;
1682 } else { /* rx error, need to reset this chip */
1683 stop_nic_rx(ioaddr, np->crvalue);
1684 reset_rx_descriptors(dev);
1685 iowrite32(np->crvalue, ioaddr + TCRRCR);
1686 }
1687 break; /* exit the while loop */
1688 }
1689 } else { /* this received pkt is ok */
1690
1691 struct sk_buff *skb;
1692 /* Omit the four octet CRC from the length. */
1693 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1694
1695 #ifndef final_version
1696 if (debug)
1697 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1698 " status %x.\n", pkt_len, rx_status);
1699 #endif
1700
1701 /* Check if the packet is long enough to accept without copying
1702 to a minimally-sized skbuff. */
1703 if (pkt_len < rx_copybreak &&
1704 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1705 skb_reserve(skb, 2); /* 16 byte align the IP header */
1706 pci_dma_sync_single_for_cpu(np->pci_dev,
1707 np->cur_rx->buffer,
1708 np->rx_buf_sz,
1709 PCI_DMA_FROMDEVICE);
1710 /* Call copy + cksum if available. */
1711
1712 #if ! defined(__alpha__)
1713 skb_copy_to_linear_data(skb,
1714 np->cur_rx->skbuff->data, pkt_len);
1715 skb_put(skb, pkt_len);
1716 #else
1717 memcpy(skb_put(skb, pkt_len),
1718 np->cur_rx->skbuff->data, pkt_len);
1719 #endif
1720 pci_dma_sync_single_for_device(np->pci_dev,
1721 np->cur_rx->buffer,
1722 np->rx_buf_sz,
1723 PCI_DMA_FROMDEVICE);
1724 } else {
1725 pci_unmap_single(np->pci_dev,
1726 np->cur_rx->buffer,
1727 np->rx_buf_sz,
1728 PCI_DMA_FROMDEVICE);
1729 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1730 np->cur_rx->skbuff = NULL;
1731 --np->really_rx_count;
1732 }
1733 skb->protocol = eth_type_trans(skb, dev);
1734 netif_rx(skb);
1735 dev->stats.rx_packets++;
1736 dev->stats.rx_bytes += pkt_len;
1737 }
1738
1739 np->cur_rx = np->cur_rx->next_desc_logical;
1740 } /* end of while loop */
1741
1742 /* allocate skb for rx buffers */
1743 allocate_rx_buffers(dev);
1744
1745 return 0;
1746 }
1747
1748
1749 static struct net_device_stats *get_stats(struct net_device *dev)
1750 {
1751 struct netdev_private *np = netdev_priv(dev);
1752 void __iomem *ioaddr = np->mem;
1753
1754 /* The chip only need report frame silently dropped. */
1755 if (netif_running(dev)) {
1756 dev->stats.rx_missed_errors +=
1757 ioread32(ioaddr + TALLY) & 0x7fff;
1758 dev->stats.rx_crc_errors +=
1759 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1760 }
1761
1762 return &dev->stats;
1763 }
1764
1765
1766 /* for dev->set_multicast_list */
1767 static void set_rx_mode(struct net_device *dev)
1768 {
1769 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1770 unsigned long flags;
1771 spin_lock_irqsave(lp, flags);
1772 __set_rx_mode(dev);
1773 spin_unlock_irqrestore(lp, flags);
1774 }
1775
1776
1777 /* Take lock before calling */
1778 static void __set_rx_mode(struct net_device *dev)
1779 {
1780 struct netdev_private *np = netdev_priv(dev);
1781 void __iomem *ioaddr = np->mem;
1782 u32 mc_filter[2]; /* Multicast hash filter */
1783 u32 rx_mode;
1784
1785 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1786 memset(mc_filter, 0xff, sizeof(mc_filter));
1787 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1788 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1789 (dev->flags & IFF_ALLMULTI)) {
1790 /* Too many to match, or accept all multicasts. */
1791 memset(mc_filter, 0xff, sizeof(mc_filter));
1792 rx_mode = CR_W_AB | CR_W_AM;
1793 } else {
1794 struct netdev_hw_addr *ha;
1795
1796 memset(mc_filter, 0, sizeof(mc_filter));
1797 netdev_for_each_mc_addr(ha, dev) {
1798 unsigned int bit;
1799 bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1800 mc_filter[bit >> 5] |= (1 << bit);
1801 }
1802 rx_mode = CR_W_AB | CR_W_AM;
1803 }
1804
1805 stop_nic_rxtx(ioaddr, np->crvalue);
1806
1807 iowrite32(mc_filter[0], ioaddr + MAR0);
1808 iowrite32(mc_filter[1], ioaddr + MAR1);
1809 np->crvalue &= ~CR_W_RXMODEMASK;
1810 np->crvalue |= rx_mode;
1811 iowrite32(np->crvalue, ioaddr + TCRRCR);
1812 }
1813
1814 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1815 {
1816 struct netdev_private *np = netdev_priv(dev);
1817
1818 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1819 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1820 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1821 }
1822
1823 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1824 {
1825 struct netdev_private *np = netdev_priv(dev);
1826 int rc;
1827
1828 spin_lock_irq(&np->lock);
1829 rc = mii_ethtool_gset(&np->mii, cmd);
1830 spin_unlock_irq(&np->lock);
1831
1832 return rc;
1833 }
1834
1835 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1836 {
1837 struct netdev_private *np = netdev_priv(dev);
1838 int rc;
1839
1840 spin_lock_irq(&np->lock);
1841 rc = mii_ethtool_sset(&np->mii, cmd);
1842 spin_unlock_irq(&np->lock);
1843
1844 return rc;
1845 }
1846
1847 static int netdev_nway_reset(struct net_device *dev)
1848 {
1849 struct netdev_private *np = netdev_priv(dev);
1850 return mii_nway_restart(&np->mii);
1851 }
1852
1853 static u32 netdev_get_link(struct net_device *dev)
1854 {
1855 struct netdev_private *np = netdev_priv(dev);
1856 return mii_link_ok(&np->mii);
1857 }
1858
1859 static u32 netdev_get_msglevel(struct net_device *dev)
1860 {
1861 return debug;
1862 }
1863
1864 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1865 {
1866 debug = value;
1867 }
1868
1869 static const struct ethtool_ops netdev_ethtool_ops = {
1870 .get_drvinfo = netdev_get_drvinfo,
1871 .get_settings = netdev_get_settings,
1872 .set_settings = netdev_set_settings,
1873 .nway_reset = netdev_nway_reset,
1874 .get_link = netdev_get_link,
1875 .get_msglevel = netdev_get_msglevel,
1876 .set_msglevel = netdev_set_msglevel,
1877 };
1878
1879 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1880 {
1881 struct netdev_private *np = netdev_priv(dev);
1882 int rc;
1883
1884 if (!netif_running(dev))
1885 return -EINVAL;
1886
1887 spin_lock_irq(&np->lock);
1888 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1889 spin_unlock_irq(&np->lock);
1890
1891 return rc;
1892 }
1893
1894
1895 static int netdev_close(struct net_device *dev)
1896 {
1897 struct netdev_private *np = netdev_priv(dev);
1898 void __iomem *ioaddr = np->mem;
1899 int i;
1900
1901 netif_stop_queue(dev);
1902
1903 /* Disable interrupts by clearing the interrupt mask. */
1904 iowrite32(0x0000, ioaddr + IMR);
1905
1906 /* Stop the chip's Tx and Rx processes. */
1907 stop_nic_rxtx(ioaddr, 0);
1908
1909 del_timer_sync(&np->timer);
1910 del_timer_sync(&np->reset_timer);
1911
1912 free_irq(np->pci_dev->irq, dev);
1913
1914 /* Free all the skbuffs in the Rx queue. */
1915 for (i = 0; i < RX_RING_SIZE; i++) {
1916 struct sk_buff *skb = np->rx_ring[i].skbuff;
1917
1918 np->rx_ring[i].status = 0;
1919 if (skb) {
1920 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1921 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1922 dev_kfree_skb(skb);
1923 np->rx_ring[i].skbuff = NULL;
1924 }
1925 }
1926
1927 for (i = 0; i < TX_RING_SIZE; i++) {
1928 struct sk_buff *skb = np->tx_ring[i].skbuff;
1929
1930 if (skb) {
1931 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1932 skb->len, PCI_DMA_TODEVICE);
1933 dev_kfree_skb(skb);
1934 np->tx_ring[i].skbuff = NULL;
1935 }
1936 }
1937
1938 return 0;
1939 }
1940
1941 static DEFINE_PCI_DEVICE_TABLE(fealnx_pci_tbl) = {
1942 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1943 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1944 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1945 {} /* terminate list */
1946 };
1947 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1948
1949
1950 static struct pci_driver fealnx_driver = {
1951 .name = "fealnx",
1952 .id_table = fealnx_pci_tbl,
1953 .probe = fealnx_init_one,
1954 .remove = __devexit_p(fealnx_remove_one),
1955 };
1956
1957 static int __init fealnx_init(void)
1958 {
1959 /* when a module, this is printed whether or not devices are found in probe */
1960 #ifdef MODULE
1961 printk(version);
1962 #endif
1963
1964 return pci_register_driver(&fealnx_driver);
1965 }
1966
1967 static void __exit fealnx_exit(void)
1968 {
1969 pci_unregister_driver(&fealnx_driver);
1970 }
1971
1972 module_init(fealnx_init);
1973 module_exit(fealnx_exit);
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