1 /* sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
3 * Copyright (C) 1997, 1998, 1999, 2003, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/fcntl.h>
11 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
14 #include <linux/string.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/crc32.h>
18 #include <linux/errno.h>
19 #include <linux/ethtool.h>
20 #include <linux/mii.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/bitops.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/of_device.h>
28 #include <linux/gfp.h>
30 #include <asm/auxio.h>
31 #include <asm/byteorder.h>
33 #include <asm/idprom.h>
35 #include <asm/openprom.h>
36 #include <asm/oplib.h>
37 #include <asm/pgtable.h>
41 #define DRV_NAME "sunbmac"
42 #define DRV_VERSION "2.1"
43 #define DRV_RELDATE "August 26, 2008"
44 #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
46 static char version
[] =
47 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" " DRV_AUTHOR
"\n";
49 MODULE_VERSION(DRV_VERSION
);
50 MODULE_AUTHOR(DRV_AUTHOR
);
51 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
52 MODULE_LICENSE("GPL");
59 #define DP(x) printk x
65 #define DTX(x) printk x
71 #define DIRQ(x) printk x
76 #define DEFAULT_JAMSIZE 4 /* Toe jam */
78 #define QEC_RESET_TRIES 200
80 static int qec_global_reset(void __iomem
*gregs
)
82 int tries
= QEC_RESET_TRIES
;
84 sbus_writel(GLOB_CTRL_RESET
, gregs
+ GLOB_CTRL
);
86 if (sbus_readl(gregs
+ GLOB_CTRL
) & GLOB_CTRL_RESET
) {
94 printk(KERN_ERR
"BigMAC: Cannot reset the QEC.\n");
98 static void qec_init(struct bigmac
*bp
)
100 struct platform_device
*qec_op
= bp
->qec_op
;
101 void __iomem
*gregs
= bp
->gregs
;
102 u8 bsizes
= bp
->bigmac_bursts
;
105 /* 64byte bursts do not work at the moment, do
106 * not even try to enable them. -DaveM
108 if (bsizes
& DMA_BURST32
)
109 regval
= GLOB_CTRL_B32
;
111 regval
= GLOB_CTRL_B16
;
112 sbus_writel(regval
| GLOB_CTRL_BMODE
, gregs
+ GLOB_CTRL
);
113 sbus_writel(GLOB_PSIZE_2048
, gregs
+ GLOB_PSIZE
);
115 /* All of memsize is given to bigmac. */
116 sbus_writel(resource_size(&qec_op
->resource
[1]),
119 /* Half to the transmitter, half to the receiver. */
120 sbus_writel(resource_size(&qec_op
->resource
[1]) >> 1,
122 sbus_writel(resource_size(&qec_op
->resource
[1]) >> 1,
126 #define TX_RESET_TRIES 32
127 #define RX_RESET_TRIES 32
129 static void bigmac_tx_reset(void __iomem
*bregs
)
131 int tries
= TX_RESET_TRIES
;
133 sbus_writel(0, bregs
+ BMAC_TXCFG
);
135 /* The fifo threshold bit is read-only and does
138 while ((sbus_readl(bregs
+ BMAC_TXCFG
) & ~(BIGMAC_TXCFG_FIFO
)) != 0 &&
143 printk(KERN_ERR
"BIGMAC: Transmitter will not reset.\n");
144 printk(KERN_ERR
"BIGMAC: tx_cfg is %08x\n",
145 sbus_readl(bregs
+ BMAC_TXCFG
));
149 static void bigmac_rx_reset(void __iomem
*bregs
)
151 int tries
= RX_RESET_TRIES
;
153 sbus_writel(0, bregs
+ BMAC_RXCFG
);
154 while (sbus_readl(bregs
+ BMAC_RXCFG
) && --tries
)
158 printk(KERN_ERR
"BIGMAC: Receiver will not reset.\n");
159 printk(KERN_ERR
"BIGMAC: rx_cfg is %08x\n",
160 sbus_readl(bregs
+ BMAC_RXCFG
));
164 /* Reset the transmitter and receiver. */
165 static void bigmac_stop(struct bigmac
*bp
)
167 bigmac_tx_reset(bp
->bregs
);
168 bigmac_rx_reset(bp
->bregs
);
171 static void bigmac_get_counters(struct bigmac
*bp
, void __iomem
*bregs
)
173 struct net_device_stats
*stats
= &bp
->enet_stats
;
175 stats
->rx_crc_errors
+= sbus_readl(bregs
+ BMAC_RCRCECTR
);
176 sbus_writel(0, bregs
+ BMAC_RCRCECTR
);
178 stats
->rx_frame_errors
+= sbus_readl(bregs
+ BMAC_UNALECTR
);
179 sbus_writel(0, bregs
+ BMAC_UNALECTR
);
181 stats
->rx_length_errors
+= sbus_readl(bregs
+ BMAC_GLECTR
);
182 sbus_writel(0, bregs
+ BMAC_GLECTR
);
184 stats
->tx_aborted_errors
+= sbus_readl(bregs
+ BMAC_EXCTR
);
187 (sbus_readl(bregs
+ BMAC_EXCTR
) +
188 sbus_readl(bregs
+ BMAC_LTCTR
));
189 sbus_writel(0, bregs
+ BMAC_EXCTR
);
190 sbus_writel(0, bregs
+ BMAC_LTCTR
);
193 static void bigmac_clean_rings(struct bigmac
*bp
)
197 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
198 if (bp
->rx_skbs
[i
] != NULL
) {
199 dev_kfree_skb_any(bp
->rx_skbs
[i
]);
200 bp
->rx_skbs
[i
] = NULL
;
204 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
205 if (bp
->tx_skbs
[i
] != NULL
) {
206 dev_kfree_skb_any(bp
->tx_skbs
[i
]);
207 bp
->tx_skbs
[i
] = NULL
;
212 static void bigmac_init_rings(struct bigmac
*bp
, int from_irq
)
214 struct bmac_init_block
*bb
= bp
->bmac_block
;
216 gfp_t gfp_flags
= GFP_KERNEL
;
218 if (from_irq
|| in_interrupt())
219 gfp_flags
= GFP_ATOMIC
;
221 bp
->rx_new
= bp
->rx_old
= bp
->tx_new
= bp
->tx_old
= 0;
223 /* Free any skippy bufs left around in the rings. */
224 bigmac_clean_rings(bp
);
226 /* Now get new skbufs for the receive ring. */
227 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
230 skb
= big_mac_alloc_skb(RX_BUF_ALLOC_SIZE
, gfp_flags
);
234 bp
->rx_skbs
[i
] = skb
;
236 /* Because we reserve afterwards. */
237 skb_put(skb
, ETH_FRAME_LEN
);
238 skb_reserve(skb
, 34);
240 bb
->be_rxd
[i
].rx_addr
=
241 dma_map_single(&bp
->bigmac_op
->dev
,
243 RX_BUF_ALLOC_SIZE
- 34,
245 bb
->be_rxd
[i
].rx_flags
=
246 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
249 for (i
= 0; i
< TX_RING_SIZE
; i
++)
250 bb
->be_txd
[i
].tx_flags
= bb
->be_txd
[i
].tx_addr
= 0;
253 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
254 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
256 static void idle_transceiver(void __iomem
*tregs
)
261 sbus_writel(MGMT_CLKOFF
, tregs
+ TCVR_MPAL
);
262 sbus_readl(tregs
+ TCVR_MPAL
);
263 sbus_writel(MGMT_CLKON
, tregs
+ TCVR_MPAL
);
264 sbus_readl(tregs
+ TCVR_MPAL
);
268 static void write_tcvr_bit(struct bigmac
*bp
, void __iomem
*tregs
, int bit
)
270 if (bp
->tcvr_type
== internal
) {
271 bit
= (bit
& 1) << 3;
272 sbus_writel(bit
| (MGMT_PAL_OENAB
| MGMT_PAL_EXT_MDIO
),
274 sbus_readl(tregs
+ TCVR_MPAL
);
275 sbus_writel(bit
| MGMT_PAL_OENAB
| MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
,
277 sbus_readl(tregs
+ TCVR_MPAL
);
278 } else if (bp
->tcvr_type
== external
) {
279 bit
= (bit
& 1) << 2;
280 sbus_writel(bit
| MGMT_PAL_INT_MDIO
| MGMT_PAL_OENAB
,
282 sbus_readl(tregs
+ TCVR_MPAL
);
283 sbus_writel(bit
| MGMT_PAL_INT_MDIO
| MGMT_PAL_OENAB
| MGMT_PAL_DCLOCK
,
285 sbus_readl(tregs
+ TCVR_MPAL
);
287 printk(KERN_ERR
"write_tcvr_bit: No transceiver type known!\n");
291 static int read_tcvr_bit(struct bigmac
*bp
, void __iomem
*tregs
)
295 if (bp
->tcvr_type
== internal
) {
296 sbus_writel(MGMT_PAL_EXT_MDIO
, tregs
+ TCVR_MPAL
);
297 sbus_readl(tregs
+ TCVR_MPAL
);
298 sbus_writel(MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
,
300 sbus_readl(tregs
+ TCVR_MPAL
);
301 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_INT_MDIO
) >> 3;
302 } else if (bp
->tcvr_type
== external
) {
303 sbus_writel(MGMT_PAL_INT_MDIO
, tregs
+ TCVR_MPAL
);
304 sbus_readl(tregs
+ TCVR_MPAL
);
305 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_DCLOCK
, tregs
+ TCVR_MPAL
);
306 sbus_readl(tregs
+ TCVR_MPAL
);
307 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_EXT_MDIO
) >> 2;
309 printk(KERN_ERR
"read_tcvr_bit: No transceiver type known!\n");
314 static int read_tcvr_bit2(struct bigmac
*bp
, void __iomem
*tregs
)
318 if (bp
->tcvr_type
== internal
) {
319 sbus_writel(MGMT_PAL_EXT_MDIO
, tregs
+ TCVR_MPAL
);
320 sbus_readl(tregs
+ TCVR_MPAL
);
321 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_INT_MDIO
) >> 3;
322 sbus_writel(MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
, tregs
+ TCVR_MPAL
);
323 sbus_readl(tregs
+ TCVR_MPAL
);
324 } else if (bp
->tcvr_type
== external
) {
325 sbus_writel(MGMT_PAL_INT_MDIO
, tregs
+ TCVR_MPAL
);
326 sbus_readl(tregs
+ TCVR_MPAL
);
327 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_EXT_MDIO
) >> 2;
328 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_DCLOCK
, tregs
+ TCVR_MPAL
);
329 sbus_readl(tregs
+ TCVR_MPAL
);
331 printk(KERN_ERR
"read_tcvr_bit2: No transceiver type known!\n");
336 static void put_tcvr_byte(struct bigmac
*bp
,
343 write_tcvr_bit(bp
, tregs
, ((byte
>> shift
) & 1));
345 } while (shift
>= 0);
348 static void bigmac_tcvr_write(struct bigmac
*bp
, void __iomem
*tregs
,
349 int reg
, unsigned short val
)
355 switch(bp
->tcvr_type
) {
361 printk(KERN_ERR
"bigmac_tcvr_read: Whoops, no known transceiver type.\n");
365 idle_transceiver(tregs
);
366 write_tcvr_bit(bp
, tregs
, 0);
367 write_tcvr_bit(bp
, tregs
, 1);
368 write_tcvr_bit(bp
, tregs
, 0);
369 write_tcvr_bit(bp
, tregs
, 1);
371 put_tcvr_byte(bp
, tregs
,
372 ((bp
->tcvr_type
== internal
) ?
373 BIGMAC_PHY_INTERNAL
: BIGMAC_PHY_EXTERNAL
));
375 put_tcvr_byte(bp
, tregs
, reg
);
377 write_tcvr_bit(bp
, tregs
, 1);
378 write_tcvr_bit(bp
, tregs
, 0);
382 write_tcvr_bit(bp
, tregs
, (val
>> shift
) & 1);
384 } while (shift
>= 0);
387 static unsigned short bigmac_tcvr_read(struct bigmac
*bp
,
391 unsigned short retval
= 0;
394 switch(bp
->tcvr_type
) {
400 printk(KERN_ERR
"bigmac_tcvr_read: Whoops, no known transceiver type.\n");
404 idle_transceiver(tregs
);
405 write_tcvr_bit(bp
, tregs
, 0);
406 write_tcvr_bit(bp
, tregs
, 1);
407 write_tcvr_bit(bp
, tregs
, 1);
408 write_tcvr_bit(bp
, tregs
, 0);
410 put_tcvr_byte(bp
, tregs
,
411 ((bp
->tcvr_type
== internal
) ?
412 BIGMAC_PHY_INTERNAL
: BIGMAC_PHY_EXTERNAL
));
414 put_tcvr_byte(bp
, tregs
, reg
);
416 if (bp
->tcvr_type
== external
) {
419 (void) read_tcvr_bit2(bp
, tregs
);
420 (void) read_tcvr_bit2(bp
, tregs
);
425 tmp
= read_tcvr_bit2(bp
, tregs
);
426 retval
|= ((tmp
& 1) << shift
);
428 } while (shift
>= 0);
430 (void) read_tcvr_bit2(bp
, tregs
);
431 (void) read_tcvr_bit2(bp
, tregs
);
432 (void) read_tcvr_bit2(bp
, tregs
);
436 (void) read_tcvr_bit(bp
, tregs
);
437 (void) read_tcvr_bit(bp
, tregs
);
442 tmp
= read_tcvr_bit(bp
, tregs
);
443 retval
|= ((tmp
& 1) << shift
);
445 } while (shift
>= 0);
447 (void) read_tcvr_bit(bp
, tregs
);
448 (void) read_tcvr_bit(bp
, tregs
);
449 (void) read_tcvr_bit(bp
, tregs
);
454 static void bigmac_tcvr_init(struct bigmac
*bp
)
456 void __iomem
*tregs
= bp
->tregs
;
459 idle_transceiver(tregs
);
460 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
,
462 sbus_readl(tregs
+ TCVR_MPAL
);
464 /* Only the bit for the present transceiver (internal or
465 * external) will stick, set them both and see what stays.
467 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_EXT_MDIO
, tregs
+ TCVR_MPAL
);
468 sbus_readl(tregs
+ TCVR_MPAL
);
471 mpal
= sbus_readl(tregs
+ TCVR_MPAL
);
472 if (mpal
& MGMT_PAL_EXT_MDIO
) {
473 bp
->tcvr_type
= external
;
474 sbus_writel(~(TCVR_PAL_EXTLBACK
| TCVR_PAL_MSENSE
| TCVR_PAL_LTENABLE
),
476 sbus_readl(tregs
+ TCVR_TPAL
);
477 } else if (mpal
& MGMT_PAL_INT_MDIO
) {
478 bp
->tcvr_type
= internal
;
479 sbus_writel(~(TCVR_PAL_SERIAL
| TCVR_PAL_EXTLBACK
|
480 TCVR_PAL_MSENSE
| TCVR_PAL_LTENABLE
),
482 sbus_readl(tregs
+ TCVR_TPAL
);
484 printk(KERN_ERR
"BIGMAC: AIEEE, neither internal nor "
485 "external MDIO available!\n");
486 printk(KERN_ERR
"BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
487 sbus_readl(tregs
+ TCVR_MPAL
),
488 sbus_readl(tregs
+ TCVR_TPAL
));
492 static int bigmac_init_hw(struct bigmac
*, int);
494 static int try_next_permutation(struct bigmac
*bp
, void __iomem
*tregs
)
496 if (bp
->sw_bmcr
& BMCR_SPEED100
) {
500 bp
->sw_bmcr
= (BMCR_ISOLATE
| BMCR_PDOWN
| BMCR_LOOPBACK
);
501 bigmac_tcvr_write(bp
, tregs
, MII_BMCR
, bp
->sw_bmcr
);
502 bp
->sw_bmcr
= (BMCR_RESET
);
503 bigmac_tcvr_write(bp
, tregs
, MII_BMCR
, bp
->sw_bmcr
);
507 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, MII_BMCR
);
508 if ((bp
->sw_bmcr
& BMCR_RESET
) == 0)
513 printk(KERN_ERR
"%s: PHY reset failed.\n", bp
->dev
->name
);
515 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, MII_BMCR
);
517 /* Now we try 10baseT. */
518 bp
->sw_bmcr
&= ~(BMCR_SPEED100
);
519 bigmac_tcvr_write(bp
, tregs
, MII_BMCR
, bp
->sw_bmcr
);
523 /* We've tried them all. */
527 static void bigmac_timer(unsigned long data
)
529 struct bigmac
*bp
= (struct bigmac
*) data
;
530 void __iomem
*tregs
= bp
->tregs
;
531 int restart_timer
= 0;
534 if (bp
->timer_state
== ltrywait
) {
535 bp
->sw_bmsr
= bigmac_tcvr_read(bp
, tregs
, MII_BMSR
);
536 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, MII_BMCR
);
537 if (bp
->sw_bmsr
& BMSR_LSTATUS
) {
538 printk(KERN_INFO
"%s: Link is now up at %s.\n",
540 (bp
->sw_bmcr
& BMCR_SPEED100
) ?
541 "100baseT" : "10baseT");
542 bp
->timer_state
= asleep
;
545 if (bp
->timer_ticks
>= 4) {
548 ret
= try_next_permutation(bp
, tregs
);
550 printk(KERN_ERR
"%s: Link down, cable problem?\n",
552 ret
= bigmac_init_hw(bp
, 0);
554 printk(KERN_ERR
"%s: Error, cannot re-init the "
555 "BigMAC.\n", bp
->dev
->name
);
566 /* Can't happens.... */
567 printk(KERN_ERR
"%s: Aieee, link timer is asleep but we got one anyways!\n",
571 bp
->timer_state
= asleep
; /* foo on you */
574 if (restart_timer
!= 0) {
575 bp
->bigmac_timer
.expires
= jiffies
+ ((12 * HZ
)/10); /* 1.2 sec. */
576 add_timer(&bp
->bigmac_timer
);
580 /* Well, really we just force the chip into 100baseT then
581 * 10baseT, each time checking for a link status.
583 static void bigmac_begin_auto_negotiation(struct bigmac
*bp
)
585 void __iomem
*tregs
= bp
->tregs
;
588 /* Grab new software copies of PHY registers. */
589 bp
->sw_bmsr
= bigmac_tcvr_read(bp
, tregs
, MII_BMSR
);
590 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, MII_BMCR
);
593 bp
->sw_bmcr
= (BMCR_ISOLATE
| BMCR_PDOWN
| BMCR_LOOPBACK
);
594 bigmac_tcvr_write(bp
, tregs
, MII_BMCR
, bp
->sw_bmcr
);
595 bp
->sw_bmcr
= (BMCR_RESET
);
596 bigmac_tcvr_write(bp
, tregs
, MII_BMCR
, bp
->sw_bmcr
);
600 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, MII_BMCR
);
601 if ((bp
->sw_bmcr
& BMCR_RESET
) == 0)
606 printk(KERN_ERR
"%s: PHY reset failed.\n", bp
->dev
->name
);
608 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, MII_BMCR
);
610 /* First we try 100baseT. */
611 bp
->sw_bmcr
|= BMCR_SPEED100
;
612 bigmac_tcvr_write(bp
, tregs
, MII_BMCR
, bp
->sw_bmcr
);
614 bp
->timer_state
= ltrywait
;
616 bp
->bigmac_timer
.expires
= jiffies
+ (12 * HZ
) / 10;
617 bp
->bigmac_timer
.data
= (unsigned long) bp
;
618 bp
->bigmac_timer
.function
= bigmac_timer
;
619 add_timer(&bp
->bigmac_timer
);
622 static int bigmac_init_hw(struct bigmac
*bp
, int from_irq
)
624 void __iomem
*gregs
= bp
->gregs
;
625 void __iomem
*cregs
= bp
->creg
;
626 void __iomem
*bregs
= bp
->bregs
;
627 unsigned char *e
= &bp
->dev
->dev_addr
[0];
629 /* Latch current counters into statistics. */
630 bigmac_get_counters(bp
, bregs
);
633 qec_global_reset(gregs
);
638 /* Alloc and reset the tx/rx descriptor chains. */
639 bigmac_init_rings(bp
, from_irq
);
641 /* Initialize the PHY. */
642 bigmac_tcvr_init(bp
);
644 /* Stop transmitter and receiver. */
647 /* Set hardware ethernet address. */
648 sbus_writel(((e
[4] << 8) | e
[5]), bregs
+ BMAC_MACADDR2
);
649 sbus_writel(((e
[2] << 8) | e
[3]), bregs
+ BMAC_MACADDR1
);
650 sbus_writel(((e
[0] << 8) | e
[1]), bregs
+ BMAC_MACADDR0
);
652 /* Clear the hash table until mc upload occurs. */
653 sbus_writel(0, bregs
+ BMAC_HTABLE3
);
654 sbus_writel(0, bregs
+ BMAC_HTABLE2
);
655 sbus_writel(0, bregs
+ BMAC_HTABLE1
);
656 sbus_writel(0, bregs
+ BMAC_HTABLE0
);
658 /* Enable Big Mac hash table filter. */
659 sbus_writel(BIGMAC_RXCFG_HENABLE
| BIGMAC_RXCFG_FIFO
,
663 /* Ok, configure the Big Mac transmitter. */
664 sbus_writel(BIGMAC_TXCFG_FIFO
, bregs
+ BMAC_TXCFG
);
666 /* The HME docs recommend to use the 10LSB of our MAC here. */
667 sbus_writel(((e
[5] | e
[4] << 8) & 0x3ff),
670 /* Enable the output drivers no matter what. */
671 sbus_writel(BIGMAC_XCFG_ODENABLE
| BIGMAC_XCFG_RESV
,
672 bregs
+ BMAC_XIFCFG
);
674 /* Tell the QEC where the ring descriptors are. */
675 sbus_writel(bp
->bblock_dvma
+ bib_offset(be_rxd
, 0),
677 sbus_writel(bp
->bblock_dvma
+ bib_offset(be_txd
, 0),
680 /* Setup the FIFO pointers into QEC local memory. */
681 sbus_writel(0, cregs
+ CREG_RXRBUFPTR
);
682 sbus_writel(0, cregs
+ CREG_RXWBUFPTR
);
683 sbus_writel(sbus_readl(gregs
+ GLOB_RSIZE
),
684 cregs
+ CREG_TXRBUFPTR
);
685 sbus_writel(sbus_readl(gregs
+ GLOB_RSIZE
),
686 cregs
+ CREG_TXWBUFPTR
);
688 /* Tell bigmac what interrupts we don't want to hear about. */
689 sbus_writel(BIGMAC_IMASK_GOTFRAME
| BIGMAC_IMASK_SENTFRAME
,
692 /* Enable the various other irq's. */
693 sbus_writel(0, cregs
+ CREG_RIMASK
);
694 sbus_writel(0, cregs
+ CREG_TIMASK
);
695 sbus_writel(0, cregs
+ CREG_QMASK
);
696 sbus_writel(0, cregs
+ CREG_BMASK
);
698 /* Set jam size to a reasonable default. */
699 sbus_writel(DEFAULT_JAMSIZE
, bregs
+ BMAC_JSIZE
);
701 /* Clear collision counter. */
702 sbus_writel(0, cregs
+ CREG_CCNT
);
704 /* Enable transmitter and receiver. */
705 sbus_writel(sbus_readl(bregs
+ BMAC_TXCFG
) | BIGMAC_TXCFG_ENABLE
,
707 sbus_writel(sbus_readl(bregs
+ BMAC_RXCFG
) | BIGMAC_RXCFG_ENABLE
,
710 /* Ok, start detecting link speed/duplex. */
711 bigmac_begin_auto_negotiation(bp
);
717 /* Error interrupts get sent here. */
718 static void bigmac_is_medium_rare(struct bigmac
*bp
, u32 qec_status
, u32 bmac_status
)
720 printk(KERN_ERR
"bigmac_is_medium_rare: ");
721 if (qec_status
& (GLOB_STAT_ER
| GLOB_STAT_BM
)) {
722 if (qec_status
& GLOB_STAT_ER
)
723 printk("QEC_ERROR, ");
724 if (qec_status
& GLOB_STAT_BM
)
725 printk("QEC_BMAC_ERROR, ");
727 if (bmac_status
& CREG_STAT_ERRORS
) {
728 if (bmac_status
& CREG_STAT_BERROR
)
729 printk("BMAC_ERROR, ");
730 if (bmac_status
& CREG_STAT_TXDERROR
)
731 printk("TXD_ERROR, ");
732 if (bmac_status
& CREG_STAT_TXLERR
)
733 printk("TX_LATE_ERROR, ");
734 if (bmac_status
& CREG_STAT_TXPERR
)
735 printk("TX_PARITY_ERROR, ");
736 if (bmac_status
& CREG_STAT_TXSERR
)
737 printk("TX_SBUS_ERROR, ");
739 if (bmac_status
& CREG_STAT_RXDROP
)
740 printk("RX_DROP_ERROR, ");
742 if (bmac_status
& CREG_STAT_RXSMALL
)
743 printk("RX_SMALL_ERROR, ");
744 if (bmac_status
& CREG_STAT_RXLERR
)
745 printk("RX_LATE_ERROR, ");
746 if (bmac_status
& CREG_STAT_RXPERR
)
747 printk("RX_PARITY_ERROR, ");
748 if (bmac_status
& CREG_STAT_RXSERR
)
749 printk("RX_SBUS_ERROR, ");
753 bigmac_init_hw(bp
, 1);
756 /* BigMAC transmit complete service routines. */
757 static void bigmac_tx(struct bigmac
*bp
)
759 struct be_txd
*txbase
= &bp
->bmac_block
->be_txd
[0];
760 struct net_device
*dev
= bp
->dev
;
763 spin_lock(&bp
->lock
);
766 DTX(("bigmac_tx: tx_old[%d] ", elem
));
767 while (elem
!= bp
->tx_new
) {
769 struct be_txd
*this = &txbase
[elem
];
771 DTX(("this(%p) [flags(%08x)addr(%08x)]",
772 this, this->tx_flags
, this->tx_addr
));
774 if (this->tx_flags
& TXD_OWN
)
776 skb
= bp
->tx_skbs
[elem
];
777 bp
->enet_stats
.tx_packets
++;
778 bp
->enet_stats
.tx_bytes
+= skb
->len
;
779 dma_unmap_single(&bp
->bigmac_op
->dev
,
780 this->tx_addr
, skb
->len
,
783 DTX(("skb(%p) ", skb
));
784 bp
->tx_skbs
[elem
] = NULL
;
785 dev_kfree_skb_irq(skb
);
787 elem
= NEXT_TX(elem
);
789 DTX((" DONE, tx_old=%d\n", elem
));
792 if (netif_queue_stopped(dev
) &&
793 TX_BUFFS_AVAIL(bp
) > 0)
794 netif_wake_queue(bp
->dev
);
796 spin_unlock(&bp
->lock
);
799 /* BigMAC receive complete service routines. */
800 static void bigmac_rx(struct bigmac
*bp
)
802 struct be_rxd
*rxbase
= &bp
->bmac_block
->be_rxd
[0];
804 int elem
= bp
->rx_new
, drops
= 0;
807 this = &rxbase
[elem
];
808 while (!((flags
= this->rx_flags
) & RXD_OWN
)) {
810 int len
= (flags
& RXD_LENGTH
); /* FCS not included */
812 /* Check for errors. */
813 if (len
< ETH_ZLEN
) {
814 bp
->enet_stats
.rx_errors
++;
815 bp
->enet_stats
.rx_length_errors
++;
818 /* Return it to the BigMAC. */
819 bp
->enet_stats
.rx_dropped
++;
821 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
824 skb
= bp
->rx_skbs
[elem
];
825 if (len
> RX_COPY_THRESHOLD
) {
826 struct sk_buff
*new_skb
;
828 /* Now refill the entry, if we can. */
829 new_skb
= big_mac_alloc_skb(RX_BUF_ALLOC_SIZE
, GFP_ATOMIC
);
830 if (new_skb
== NULL
) {
834 dma_unmap_single(&bp
->bigmac_op
->dev
,
836 RX_BUF_ALLOC_SIZE
- 34,
838 bp
->rx_skbs
[elem
] = new_skb
;
839 skb_put(new_skb
, ETH_FRAME_LEN
);
840 skb_reserve(new_skb
, 34);
842 dma_map_single(&bp
->bigmac_op
->dev
,
844 RX_BUF_ALLOC_SIZE
- 34,
847 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
849 /* Trim the original skb for the netif. */
852 struct sk_buff
*copy_skb
= netdev_alloc_skb(bp
->dev
, len
+ 2);
854 if (copy_skb
== NULL
) {
858 skb_reserve(copy_skb
, 2);
859 skb_put(copy_skb
, len
);
860 dma_sync_single_for_cpu(&bp
->bigmac_op
->dev
,
863 skb_copy_to_linear_data(copy_skb
, (unsigned char *)skb
->data
, len
);
864 dma_sync_single_for_device(&bp
->bigmac_op
->dev
,
868 /* Reuse original ring buffer. */
870 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
875 /* No checksums done by the BigMAC ;-( */
876 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
878 bp
->enet_stats
.rx_packets
++;
879 bp
->enet_stats
.rx_bytes
+= len
;
881 elem
= NEXT_RX(elem
);
882 this = &rxbase
[elem
];
886 printk(KERN_NOTICE
"%s: Memory squeeze, deferring packet.\n", bp
->dev
->name
);
889 static irqreturn_t
bigmac_interrupt(int irq
, void *dev_id
)
891 struct bigmac
*bp
= (struct bigmac
*) dev_id
;
892 u32 qec_status
, bmac_status
;
894 DIRQ(("bigmac_interrupt: "));
896 /* Latch status registers now. */
897 bmac_status
= sbus_readl(bp
->creg
+ CREG_STAT
);
898 qec_status
= sbus_readl(bp
->gregs
+ GLOB_STAT
);
900 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status
, bmac_status
));
901 if ((qec_status
& (GLOB_STAT_ER
| GLOB_STAT_BM
)) ||
902 (bmac_status
& CREG_STAT_ERRORS
))
903 bigmac_is_medium_rare(bp
, qec_status
, bmac_status
);
905 if (bmac_status
& CREG_STAT_TXIRQ
)
908 if (bmac_status
& CREG_STAT_RXIRQ
)
914 static int bigmac_open(struct net_device
*dev
)
916 struct bigmac
*bp
= netdev_priv(dev
);
919 ret
= request_irq(dev
->irq
, bigmac_interrupt
, IRQF_SHARED
, dev
->name
, bp
);
921 printk(KERN_ERR
"BIGMAC: Can't order irq %d to go.\n", dev
->irq
);
924 init_timer(&bp
->bigmac_timer
);
925 ret
= bigmac_init_hw(bp
, 0);
927 free_irq(dev
->irq
, bp
);
931 static int bigmac_close(struct net_device
*dev
)
933 struct bigmac
*bp
= netdev_priv(dev
);
935 del_timer(&bp
->bigmac_timer
);
936 bp
->timer_state
= asleep
;
940 bigmac_clean_rings(bp
);
941 free_irq(dev
->irq
, bp
);
945 static void bigmac_tx_timeout(struct net_device
*dev
)
947 struct bigmac
*bp
= netdev_priv(dev
);
949 bigmac_init_hw(bp
, 0);
950 netif_wake_queue(dev
);
953 /* Put a packet on the wire. */
954 static int bigmac_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
956 struct bigmac
*bp
= netdev_priv(dev
);
961 mapping
= dma_map_single(&bp
->bigmac_op
->dev
, skb
->data
,
964 /* Avoid a race... */
965 spin_lock_irq(&bp
->lock
);
967 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len
, entry
));
968 bp
->bmac_block
->be_txd
[entry
].tx_flags
= TXD_UPDATE
;
969 bp
->tx_skbs
[entry
] = skb
;
970 bp
->bmac_block
->be_txd
[entry
].tx_addr
= mapping
;
971 bp
->bmac_block
->be_txd
[entry
].tx_flags
=
972 (TXD_OWN
| TXD_SOP
| TXD_EOP
| (len
& TXD_LENGTH
));
973 bp
->tx_new
= NEXT_TX(entry
);
974 if (TX_BUFFS_AVAIL(bp
) <= 0)
975 netif_stop_queue(dev
);
976 spin_unlock_irq(&bp
->lock
);
979 sbus_writel(CREG_CTRL_TWAKEUP
, bp
->creg
+ CREG_CTRL
);
985 static struct net_device_stats
*bigmac_get_stats(struct net_device
*dev
)
987 struct bigmac
*bp
= netdev_priv(dev
);
989 bigmac_get_counters(bp
, bp
->bregs
);
990 return &bp
->enet_stats
;
993 static void bigmac_set_multicast(struct net_device
*dev
)
995 struct bigmac
*bp
= netdev_priv(dev
);
996 void __iomem
*bregs
= bp
->bregs
;
997 struct netdev_hw_addr
*ha
;
1001 /* Disable the receiver. The bit self-clears when
1002 * the operation is complete.
1004 tmp
= sbus_readl(bregs
+ BMAC_RXCFG
);
1005 tmp
&= ~(BIGMAC_RXCFG_ENABLE
);
1006 sbus_writel(tmp
, bregs
+ BMAC_RXCFG
);
1007 while ((sbus_readl(bregs
+ BMAC_RXCFG
) & BIGMAC_RXCFG_ENABLE
) != 0)
1010 if ((dev
->flags
& IFF_ALLMULTI
) || (netdev_mc_count(dev
) > 64)) {
1011 sbus_writel(0xffff, bregs
+ BMAC_HTABLE0
);
1012 sbus_writel(0xffff, bregs
+ BMAC_HTABLE1
);
1013 sbus_writel(0xffff, bregs
+ BMAC_HTABLE2
);
1014 sbus_writel(0xffff, bregs
+ BMAC_HTABLE3
);
1015 } else if (dev
->flags
& IFF_PROMISC
) {
1016 tmp
= sbus_readl(bregs
+ BMAC_RXCFG
);
1017 tmp
|= BIGMAC_RXCFG_PMISC
;
1018 sbus_writel(tmp
, bregs
+ BMAC_RXCFG
);
1020 u16 hash_table
[4] = { 0 };
1022 netdev_for_each_mc_addr(ha
, dev
) {
1023 crc
= ether_crc_le(6, ha
->addr
);
1025 hash_table
[crc
>> 4] |= 1 << (crc
& 0xf);
1027 sbus_writel(hash_table
[0], bregs
+ BMAC_HTABLE0
);
1028 sbus_writel(hash_table
[1], bregs
+ BMAC_HTABLE1
);
1029 sbus_writel(hash_table
[2], bregs
+ BMAC_HTABLE2
);
1030 sbus_writel(hash_table
[3], bregs
+ BMAC_HTABLE3
);
1033 /* Re-enable the receiver. */
1034 tmp
= sbus_readl(bregs
+ BMAC_RXCFG
);
1035 tmp
|= BIGMAC_RXCFG_ENABLE
;
1036 sbus_writel(tmp
, bregs
+ BMAC_RXCFG
);
1039 /* Ethtool support... */
1040 static void bigmac_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1042 strlcpy(info
->driver
, "sunbmac", sizeof(info
->driver
));
1043 strlcpy(info
->version
, "2.0", sizeof(info
->version
));
1046 static u32
bigmac_get_link(struct net_device
*dev
)
1048 struct bigmac
*bp
= netdev_priv(dev
);
1050 spin_lock_irq(&bp
->lock
);
1051 bp
->sw_bmsr
= bigmac_tcvr_read(bp
, bp
->tregs
, MII_BMSR
);
1052 spin_unlock_irq(&bp
->lock
);
1054 return (bp
->sw_bmsr
& BMSR_LSTATUS
);
1057 static const struct ethtool_ops bigmac_ethtool_ops
= {
1058 .get_drvinfo
= bigmac_get_drvinfo
,
1059 .get_link
= bigmac_get_link
,
1062 static const struct net_device_ops bigmac_ops
= {
1063 .ndo_open
= bigmac_open
,
1064 .ndo_stop
= bigmac_close
,
1065 .ndo_start_xmit
= bigmac_start_xmit
,
1066 .ndo_get_stats
= bigmac_get_stats
,
1067 .ndo_set_rx_mode
= bigmac_set_multicast
,
1068 .ndo_tx_timeout
= bigmac_tx_timeout
,
1069 .ndo_change_mtu
= eth_change_mtu
,
1070 .ndo_set_mac_address
= eth_mac_addr
,
1071 .ndo_validate_addr
= eth_validate_addr
,
1074 static int bigmac_ether_init(struct platform_device
*op
,
1075 struct platform_device
*qec_op
)
1077 static int version_printed
;
1078 struct net_device
*dev
;
1079 u8 bsizes
, bsizes_more
;
1083 /* Get a new device struct for this interface. */
1084 dev
= alloc_etherdev(sizeof(struct bigmac
));
1088 if (version_printed
++ == 0)
1089 printk(KERN_INFO
"%s", version
);
1091 for (i
= 0; i
< 6; i
++)
1092 dev
->dev_addr
[i
] = idprom
->id_ethaddr
[i
];
1094 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1095 bp
= netdev_priv(dev
);
1096 bp
->qec_op
= qec_op
;
1099 SET_NETDEV_DEV(dev
, &op
->dev
);
1101 spin_lock_init(&bp
->lock
);
1103 /* Map in QEC global control registers. */
1104 bp
->gregs
= of_ioremap(&qec_op
->resource
[0], 0,
1105 GLOB_REG_SIZE
, "BigMAC QEC GLobal Regs");
1107 printk(KERN_ERR
"BIGMAC: Cannot map QEC global registers.\n");
1108 goto fail_and_cleanup
;
1111 /* Make sure QEC is in BigMAC mode. */
1112 if ((sbus_readl(bp
->gregs
+ GLOB_CTRL
) & 0xf0000000) != GLOB_CTRL_BMODE
) {
1113 printk(KERN_ERR
"BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1114 goto fail_and_cleanup
;
1117 /* Reset the QEC. */
1118 if (qec_global_reset(bp
->gregs
))
1119 goto fail_and_cleanup
;
1121 /* Get supported SBUS burst sizes. */
1122 bsizes
= of_getintprop_default(qec_op
->dev
.of_node
, "burst-sizes", 0xff);
1123 bsizes_more
= of_getintprop_default(qec_op
->dev
.of_node
, "burst-sizes", 0xff);
1126 if (bsizes_more
!= 0xff)
1127 bsizes
&= bsizes_more
;
1128 if (bsizes
== 0xff || (bsizes
& DMA_BURST16
) == 0 ||
1129 (bsizes
& DMA_BURST32
) == 0)
1130 bsizes
= (DMA_BURST32
- 1);
1131 bp
->bigmac_bursts
= bsizes
;
1133 /* Perform QEC initialization. */
1136 /* Map in the BigMAC channel registers. */
1137 bp
->creg
= of_ioremap(&op
->resource
[0], 0,
1138 CREG_REG_SIZE
, "BigMAC QEC Channel Regs");
1140 printk(KERN_ERR
"BIGMAC: Cannot map QEC channel registers.\n");
1141 goto fail_and_cleanup
;
1144 /* Map in the BigMAC control registers. */
1145 bp
->bregs
= of_ioremap(&op
->resource
[1], 0,
1146 BMAC_REG_SIZE
, "BigMAC Primary Regs");
1148 printk(KERN_ERR
"BIGMAC: Cannot map BigMAC primary registers.\n");
1149 goto fail_and_cleanup
;
1152 /* Map in the BigMAC transceiver registers, this is how you poke at
1155 bp
->tregs
= of_ioremap(&op
->resource
[2], 0,
1156 TCVR_REG_SIZE
, "BigMAC Transceiver Regs");
1158 printk(KERN_ERR
"BIGMAC: Cannot map BigMAC transceiver registers.\n");
1159 goto fail_and_cleanup
;
1162 /* Stop the BigMAC. */
1165 /* Allocate transmit/receive descriptor DVMA block. */
1166 bp
->bmac_block
= dma_alloc_coherent(&bp
->bigmac_op
->dev
,
1168 &bp
->bblock_dvma
, GFP_ATOMIC
);
1169 if (bp
->bmac_block
== NULL
|| bp
->bblock_dvma
== 0)
1170 goto fail_and_cleanup
;
1172 /* Get the board revision of this BigMAC. */
1173 bp
->board_rev
= of_getintprop_default(bp
->bigmac_op
->dev
.of_node
,
1174 "board-version", 1);
1176 /* Init auto-negotiation timer state. */
1177 init_timer(&bp
->bigmac_timer
);
1178 bp
->timer_state
= asleep
;
1179 bp
->timer_ticks
= 0;
1181 /* Backlink to generic net device struct. */
1184 /* Set links to our BigMAC open and close routines. */
1185 dev
->ethtool_ops
= &bigmac_ethtool_ops
;
1186 dev
->netdev_ops
= &bigmac_ops
;
1187 dev
->watchdog_timeo
= 5*HZ
;
1189 /* Finish net device registration. */
1190 dev
->irq
= bp
->bigmac_op
->archdata
.irqs
[0];
1193 if (register_netdev(dev
)) {
1194 printk(KERN_ERR
"BIGMAC: Cannot register device.\n");
1195 goto fail_and_cleanup
;
1198 dev_set_drvdata(&bp
->bigmac_op
->dev
, bp
);
1200 printk(KERN_INFO
"%s: BigMAC 100baseT Ethernet %pM\n",
1201 dev
->name
, dev
->dev_addr
);
1206 /* Something went wrong, undo whatever we did so far. */
1207 /* Free register mappings if any. */
1209 of_iounmap(&qec_op
->resource
[0], bp
->gregs
, GLOB_REG_SIZE
);
1211 of_iounmap(&op
->resource
[0], bp
->creg
, CREG_REG_SIZE
);
1213 of_iounmap(&op
->resource
[1], bp
->bregs
, BMAC_REG_SIZE
);
1215 of_iounmap(&op
->resource
[2], bp
->tregs
, TCVR_REG_SIZE
);
1218 dma_free_coherent(&bp
->bigmac_op
->dev
,
1223 /* This also frees the co-located private data */
1228 /* QEC can be the parent of either QuadEthernet or a BigMAC. We want
1231 static int bigmac_sbus_probe(struct platform_device
*op
)
1233 struct device
*parent
= op
->dev
.parent
;
1234 struct platform_device
*qec_op
;
1236 qec_op
= to_platform_device(parent
);
1238 return bigmac_ether_init(op
, qec_op
);
1241 static int bigmac_sbus_remove(struct platform_device
*op
)
1243 struct bigmac
*bp
= dev_get_drvdata(&op
->dev
);
1244 struct device
*parent
= op
->dev
.parent
;
1245 struct net_device
*net_dev
= bp
->dev
;
1246 struct platform_device
*qec_op
;
1248 qec_op
= to_platform_device(parent
);
1250 unregister_netdev(net_dev
);
1252 of_iounmap(&qec_op
->resource
[0], bp
->gregs
, GLOB_REG_SIZE
);
1253 of_iounmap(&op
->resource
[0], bp
->creg
, CREG_REG_SIZE
);
1254 of_iounmap(&op
->resource
[1], bp
->bregs
, BMAC_REG_SIZE
);
1255 of_iounmap(&op
->resource
[2], bp
->tregs
, TCVR_REG_SIZE
);
1256 dma_free_coherent(&op
->dev
,
1261 free_netdev(net_dev
);
1263 dev_set_drvdata(&op
->dev
, NULL
);
1268 static const struct of_device_id bigmac_sbus_match
[] = {
1275 MODULE_DEVICE_TABLE(of
, bigmac_sbus_match
);
1277 static struct platform_driver bigmac_sbus_driver
= {
1280 .owner
= THIS_MODULE
,
1281 .of_match_table
= bigmac_sbus_match
,
1283 .probe
= bigmac_sbus_probe
,
1284 .remove
= bigmac_sbus_remove
,
1287 module_platform_driver(bigmac_sbus_driver
);