1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2009-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
22 * associated with it (_SHIFT, _MASK, and _WORD).
23 * EG. For a bit field that is in the 7th bit of the "field4" field of a
24 * structure and is 2 bits in size the following #defines must exist:
30 * #define example_bit_field_SHIFT 7
31 * #define example_bit_field_MASK 0x03
32 * #define example_bit_field_WORD field4
35 * Then the macros below may be used to get or set the value of that field.
36 * EG. To get the value of the bit field from the above example:
38 * value = bf_get(example_bit_field, &t1);
39 * And then to set that bit field:
40 * bf_set(example_bit_field, &t1, 2);
41 * Or clear that bit field:
42 * bf_set(example_bit_field, &t1, 0);
44 #define bf_get_be32(name, ptr) \
45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
46 #define bf_get_le32(name, ptr) \
47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
48 #define bf_get(name, ptr) \
49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
50 #define bf_set_le32(name, ptr, value) \
51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
53 ~(name##_MASK << name##_SHIFT)))))
54 #define bf_set(name, ptr, value) \
55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
63 struct lpfc_sli_intf
{
65 #define lpfc_sli_intf_valid_SHIFT 29
66 #define lpfc_sli_intf_valid_MASK 0x00000007
67 #define lpfc_sli_intf_valid_WORD word0
68 #define LPFC_SLI_INTF_VALID 6
69 #define lpfc_sli_intf_sli_hint2_SHIFT 24
70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
71 #define lpfc_sli_intf_sli_hint2_WORD word0
72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
73 #define lpfc_sli_intf_sli_hint1_SHIFT 16
74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
75 #define lpfc_sli_intf_sli_hint1_WORD word0
76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
77 #define LPFC_SLI_INTF_SLI_HINT1_1 1
78 #define LPFC_SLI_INTF_SLI_HINT1_2 2
79 #define lpfc_sli_intf_if_type_SHIFT 12
80 #define lpfc_sli_intf_if_type_MASK 0x0000000F
81 #define lpfc_sli_intf_if_type_WORD word0
82 #define LPFC_SLI_INTF_IF_TYPE_0 0
83 #define LPFC_SLI_INTF_IF_TYPE_1 1
84 #define LPFC_SLI_INTF_IF_TYPE_2 2
85 #define lpfc_sli_intf_sli_family_SHIFT 8
86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
87 #define lpfc_sli_intf_sli_family_WORD word0
88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
92 #define lpfc_sli_intf_slirev_SHIFT 4
93 #define lpfc_sli_intf_slirev_MASK 0x0000000F
94 #define lpfc_sli_intf_slirev_WORD word0
95 #define LPFC_SLI_INTF_REV_SLI3 3
96 #define LPFC_SLI_INTF_REV_SLI4 4
97 #define lpfc_sli_intf_func_type_SHIFT 0
98 #define lpfc_sli_intf_func_type_MASK 0x00000001
99 #define lpfc_sli_intf_func_type_WORD word0
100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1
104 #define LPFC_SLI4_MBX_EMBED true
105 #define LPFC_SLI4_MBX_NEMBED false
107 #define LPFC_SLI4_MB_WORD_COUNT 64
108 #define LPFC_MAX_MQ_PAGE 8
109 #define LPFC_MAX_WQ_PAGE 8
110 #define LPFC_MAX_CQ_PAGE 4
111 #define LPFC_MAX_EQ_PAGE 8
113 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
114 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
115 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
117 /* Define SLI4 Alignment requirements. */
118 #define LPFC_ALIGN_16_BYTE 16
119 #define LPFC_ALIGN_64_BYTE 64
121 /* Define SLI4 specific definitions. */
122 #define LPFC_MQ_CQE_BYTE_OFFSET 256
123 #define LPFC_MBX_CMD_HDR_LENGTH 16
124 #define LPFC_MBX_ERROR_RANGE 0x4000
125 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
126 #define LPFC_BMBX_BIT1_ADDR_LO 0
127 #define LPFC_RPI_HDR_COUNT 64
128 #define LPFC_HDR_TEMPLATE_SIZE 4096
129 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
130 #define LPFC_FCF_RECORD_WD_CNT 132
131 #define LPFC_ENTIRE_FCF_DATABASE 0
132 #define LPFC_DFLT_FCF_INDEX 0
134 /* Virtual function numbers */
168 /* PCI function numbers */
169 #define LPFC_PCI_FUNC0 0
170 #define LPFC_PCI_FUNC1 1
171 #define LPFC_PCI_FUNC2 2
172 #define LPFC_PCI_FUNC3 3
173 #define LPFC_PCI_FUNC4 4
175 /* SLI4 interface type-2 PDEV_CTL register */
176 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
177 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
178 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
179 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
180 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
181 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
182 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
183 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
185 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
187 /* Active interrupt test count */
188 #define LPFC_ACT_INTR_CNT 4
190 /* Delay Multiplier constant */
191 #define LPFC_DMULT_CONST 651042
193 /* Configuration of Interrupts / sec for entire HBA port */
194 #define LPFC_MIN_IMAX 5000
195 #define LPFC_MAX_IMAX 5000000
196 #define LPFC_DEF_IMAX 50000
198 /* PORT_CAPABILITIES constants. */
199 #define LPFC_MAX_SUPPORTED_PAGES 8
205 #ifdef __BIG_ENDIAN_BITFIELD
206 uint32_t bdeFlags
:8; /* BDE Flags 0 IS A SUPPORTED
208 uint32_t bdeSize
:24; /* Size of buffer (in bytes) */
209 #else /* __LITTLE_ENDIAN_BITFIELD */
210 uint32_t bdeSize
:24; /* Size of buffer (in bytes) */
211 uint32_t bdeFlags
:8; /* BDE Flags 0 IS A SUPPORTED
214 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
215 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
216 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
217 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
218 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
219 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
220 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
227 struct lpfc_sli4_flags
{
229 #define lpfc_idx_rsrc_rdy_SHIFT 0
230 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
231 #define lpfc_idx_rsrc_rdy_WORD word0
232 #define LPFC_IDX_RSRC_RDY 1
233 #define lpfc_rpi_rsrc_rdy_SHIFT 1
234 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
235 #define lpfc_rpi_rsrc_rdy_WORD word0
236 #define LPFC_RPI_RSRC_RDY 1
237 #define lpfc_vpi_rsrc_rdy_SHIFT 2
238 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
239 #define lpfc_vpi_rsrc_rdy_WORD word0
240 #define LPFC_VPI_RSRC_RDY 1
241 #define lpfc_vfi_rsrc_rdy_SHIFT 3
242 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
243 #define lpfc_vfi_rsrc_rdy_WORD word0
244 #define LPFC_VFI_RSRC_RDY 1
247 struct sli4_bls_rsp
{
248 uint32_t word0_rsvd
; /* Word0 must be reserved */
250 #define lpfc_abts_orig_SHIFT 0
251 #define lpfc_abts_orig_MASK 0x00000001
252 #define lpfc_abts_orig_WORD word1
253 #define LPFC_ABTS_UNSOL_RSP 1
254 #define LPFC_ABTS_UNSOL_INT 0
256 #define lpfc_abts_rxid_SHIFT 0
257 #define lpfc_abts_rxid_MASK 0x0000FFFF
258 #define lpfc_abts_rxid_WORD word2
259 #define lpfc_abts_oxid_SHIFT 16
260 #define lpfc_abts_oxid_MASK 0x0000FFFF
261 #define lpfc_abts_oxid_WORD word2
263 #define lpfc_vndr_code_SHIFT 0
264 #define lpfc_vndr_code_MASK 0x000000FF
265 #define lpfc_vndr_code_WORD word3
266 #define lpfc_rsn_expln_SHIFT 8
267 #define lpfc_rsn_expln_MASK 0x000000FF
268 #define lpfc_rsn_expln_WORD word3
269 #define lpfc_rsn_code_SHIFT 16
270 #define lpfc_rsn_code_MASK 0x000000FF
271 #define lpfc_rsn_code_WORD word3
274 uint32_t word5_rsvd
; /* Word5 must be reserved */
277 /* event queue entry structure */
280 #define lpfc_eqe_resource_id_SHIFT 16
281 #define lpfc_eqe_resource_id_MASK 0x000000FF
282 #define lpfc_eqe_resource_id_WORD word0
283 #define lpfc_eqe_minor_code_SHIFT 4
284 #define lpfc_eqe_minor_code_MASK 0x00000FFF
285 #define lpfc_eqe_minor_code_WORD word0
286 #define lpfc_eqe_major_code_SHIFT 1
287 #define lpfc_eqe_major_code_MASK 0x00000007
288 #define lpfc_eqe_major_code_WORD word0
289 #define lpfc_eqe_valid_SHIFT 0
290 #define lpfc_eqe_valid_MASK 0x00000001
291 #define lpfc_eqe_valid_WORD word0
294 /* completion queue entry structure (common fields for all cqe types) */
300 #define lpfc_cqe_valid_SHIFT 31
301 #define lpfc_cqe_valid_MASK 0x00000001
302 #define lpfc_cqe_valid_WORD word3
303 #define lpfc_cqe_code_SHIFT 16
304 #define lpfc_cqe_code_MASK 0x000000FF
305 #define lpfc_cqe_code_WORD word3
308 /* Completion Queue Entry Status Codes */
309 #define CQE_STATUS_SUCCESS 0x0
310 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
311 #define CQE_STATUS_REMOTE_STOP 0x2
312 #define CQE_STATUS_LOCAL_REJECT 0x3
313 #define CQE_STATUS_NPORT_RJT 0x4
314 #define CQE_STATUS_FABRIC_RJT 0x5
315 #define CQE_STATUS_NPORT_BSY 0x6
316 #define CQE_STATUS_FABRIC_BSY 0x7
317 #define CQE_STATUS_INTERMED_RSP 0x8
318 #define CQE_STATUS_LS_RJT 0x9
319 #define CQE_STATUS_CMD_REJECT 0xb
320 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
321 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
322 #define CQE_STATUS_DI_ERROR 0x16
324 /* Used when mapping CQE status to IOCB */
325 #define LPFC_IOCB_STATUS_MASK 0xf
327 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
328 #define CQE_HW_STATUS_NO_ERR 0x0
329 #define CQE_HW_STATUS_UNDERRUN 0x1
330 #define CQE_HW_STATUS_OVERRUN 0x2
332 /* Completion Queue Entry Codes */
333 #define CQE_CODE_COMPL_WQE 0x1
334 #define CQE_CODE_RELEASE_WQE 0x2
335 #define CQE_CODE_RECEIVE 0x4
336 #define CQE_CODE_XRI_ABORTED 0x5
337 #define CQE_CODE_RECEIVE_V1 0x9
340 * Define mask value for xri_aborted and wcqe completed CQE extended status.
341 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
343 #define WCQE_PARAM_MASK 0x1FF;
345 /* completion queue entry for wqe completions */
346 struct lpfc_wcqe_complete
{
348 #define lpfc_wcqe_c_request_tag_SHIFT 16
349 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
350 #define lpfc_wcqe_c_request_tag_WORD word0
351 #define lpfc_wcqe_c_status_SHIFT 8
352 #define lpfc_wcqe_c_status_MASK 0x000000FF
353 #define lpfc_wcqe_c_status_WORD word0
354 #define lpfc_wcqe_c_hw_status_SHIFT 0
355 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
356 #define lpfc_wcqe_c_hw_status_WORD word0
357 uint32_t total_data_placed
;
359 #define lpfc_wcqe_c_bg_edir_SHIFT 5
360 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
361 #define lpfc_wcqe_c_bg_edir_WORD parameter
362 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3
363 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
364 #define lpfc_wcqe_c_bg_tdpv_WORD parameter
365 #define lpfc_wcqe_c_bg_re_SHIFT 2
366 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
367 #define lpfc_wcqe_c_bg_re_WORD parameter
368 #define lpfc_wcqe_c_bg_ae_SHIFT 1
369 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
370 #define lpfc_wcqe_c_bg_ae_WORD parameter
371 #define lpfc_wcqe_c_bg_ge_SHIFT 0
372 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
373 #define lpfc_wcqe_c_bg_ge_WORD parameter
375 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
376 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
377 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
378 #define lpfc_wcqe_c_xb_SHIFT 28
379 #define lpfc_wcqe_c_xb_MASK 0x00000001
380 #define lpfc_wcqe_c_xb_WORD word3
381 #define lpfc_wcqe_c_pv_SHIFT 27
382 #define lpfc_wcqe_c_pv_MASK 0x00000001
383 #define lpfc_wcqe_c_pv_WORD word3
384 #define lpfc_wcqe_c_priority_SHIFT 24
385 #define lpfc_wcqe_c_priority_MASK 0x00000007
386 #define lpfc_wcqe_c_priority_WORD word3
387 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
388 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
389 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
392 /* completion queue entry for wqe release */
393 struct lpfc_wcqe_release
{
397 #define lpfc_wcqe_r_wq_id_SHIFT 16
398 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
399 #define lpfc_wcqe_r_wq_id_WORD word2
400 #define lpfc_wcqe_r_wqe_index_SHIFT 0
401 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
402 #define lpfc_wcqe_r_wqe_index_WORD word2
404 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
405 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
406 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
407 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
408 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
409 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
412 struct sli4_wcqe_xri_aborted
{
414 #define lpfc_wcqe_xa_status_SHIFT 8
415 #define lpfc_wcqe_xa_status_MASK 0x000000FF
416 #define lpfc_wcqe_xa_status_WORD word0
419 #define lpfc_wcqe_xa_remote_xid_SHIFT 16
420 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
421 #define lpfc_wcqe_xa_remote_xid_WORD word2
422 #define lpfc_wcqe_xa_xri_SHIFT 0
423 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
424 #define lpfc_wcqe_xa_xri_WORD word2
426 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
427 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
428 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
429 #define lpfc_wcqe_xa_ia_SHIFT 30
430 #define lpfc_wcqe_xa_ia_MASK 0x00000001
431 #define lpfc_wcqe_xa_ia_WORD word3
432 #define CQE_XRI_ABORTED_IA_REMOTE 0
433 #define CQE_XRI_ABORTED_IA_LOCAL 1
434 #define lpfc_wcqe_xa_br_SHIFT 29
435 #define lpfc_wcqe_xa_br_MASK 0x00000001
436 #define lpfc_wcqe_xa_br_WORD word3
437 #define CQE_XRI_ABORTED_BR_BA_ACC 0
438 #define CQE_XRI_ABORTED_BR_BA_RJT 1
439 #define lpfc_wcqe_xa_eo_SHIFT 28
440 #define lpfc_wcqe_xa_eo_MASK 0x00000001
441 #define lpfc_wcqe_xa_eo_WORD word3
442 #define CQE_XRI_ABORTED_EO_REMOTE 0
443 #define CQE_XRI_ABORTED_EO_LOCAL 1
444 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
445 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
446 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
449 /* completion queue entry structure for rqe completion */
452 #define lpfc_rcqe_bindex_SHIFT 16
453 #define lpfc_rcqe_bindex_MASK 0x0000FFF
454 #define lpfc_rcqe_bindex_WORD word0
455 #define lpfc_rcqe_status_SHIFT 8
456 #define lpfc_rcqe_status_MASK 0x000000FF
457 #define lpfc_rcqe_status_WORD word0
458 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
459 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
460 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
461 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
463 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
464 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
465 #define lpfc_rcqe_fcf_id_v1_WORD word1
467 #define lpfc_rcqe_length_SHIFT 16
468 #define lpfc_rcqe_length_MASK 0x0000FFFF
469 #define lpfc_rcqe_length_WORD word2
470 #define lpfc_rcqe_rq_id_SHIFT 6
471 #define lpfc_rcqe_rq_id_MASK 0x000003FF
472 #define lpfc_rcqe_rq_id_WORD word2
473 #define lpfc_rcqe_fcf_id_SHIFT 0
474 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
475 #define lpfc_rcqe_fcf_id_WORD word2
476 #define lpfc_rcqe_rq_id_v1_SHIFT 0
477 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
478 #define lpfc_rcqe_rq_id_v1_WORD word2
480 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
481 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
482 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
483 #define lpfc_rcqe_port_SHIFT 30
484 #define lpfc_rcqe_port_MASK 0x00000001
485 #define lpfc_rcqe_port_WORD word3
486 #define lpfc_rcqe_hdr_length_SHIFT 24
487 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
488 #define lpfc_rcqe_hdr_length_WORD word3
489 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
490 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
491 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
492 #define lpfc_rcqe_eof_SHIFT 8
493 #define lpfc_rcqe_eof_MASK 0x000000FF
494 #define lpfc_rcqe_eof_WORD word3
495 #define FCOE_EOFn 0x41
496 #define FCOE_EOFt 0x42
497 #define FCOE_EOFni 0x49
498 #define FCOE_EOFa 0x50
499 #define lpfc_rcqe_sof_SHIFT 0
500 #define lpfc_rcqe_sof_MASK 0x000000FF
501 #define lpfc_rcqe_sof_WORD word3
502 #define FCOE_SOFi2 0x2d
503 #define FCOE_SOFi3 0x2e
504 #define FCOE_SOFn2 0x35
505 #define FCOE_SOFn3 0x36
513 /* buffer descriptors */
518 #define lpfc_bde4_last_SHIFT 31
519 #define lpfc_bde4_last_MASK 0x00000001
520 #define lpfc_bde4_last_WORD word2
521 #define lpfc_bde4_sge_offset_SHIFT 0
522 #define lpfc_bde4_sge_offset_MASK 0x000003FF
523 #define lpfc_bde4_sge_offset_WORD word2
525 #define lpfc_bde4_length_SHIFT 0
526 #define lpfc_bde4_length_MASK 0x000000FF
527 #define lpfc_bde4_length_WORD word3
530 struct lpfc_register
{
534 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
535 #define LPFC_UERR_STATUS_HI 0x00A4
536 #define LPFC_UERR_STATUS_LO 0x00A0
537 #define LPFC_UE_MASK_HI 0x00AC
538 #define LPFC_UE_MASK_LO 0x00A8
540 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
541 #define LPFC_SLI_INTF 0x0058
543 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
544 #define lpfc_port_smphr_perr_SHIFT 31
545 #define lpfc_port_smphr_perr_MASK 0x1
546 #define lpfc_port_smphr_perr_WORD word0
547 #define lpfc_port_smphr_sfi_SHIFT 30
548 #define lpfc_port_smphr_sfi_MASK 0x1
549 #define lpfc_port_smphr_sfi_WORD word0
550 #define lpfc_port_smphr_nip_SHIFT 29
551 #define lpfc_port_smphr_nip_MASK 0x1
552 #define lpfc_port_smphr_nip_WORD word0
553 #define lpfc_port_smphr_ipc_SHIFT 28
554 #define lpfc_port_smphr_ipc_MASK 0x1
555 #define lpfc_port_smphr_ipc_WORD word0
556 #define lpfc_port_smphr_scr1_SHIFT 27
557 #define lpfc_port_smphr_scr1_MASK 0x1
558 #define lpfc_port_smphr_scr1_WORD word0
559 #define lpfc_port_smphr_scr2_SHIFT 26
560 #define lpfc_port_smphr_scr2_MASK 0x1
561 #define lpfc_port_smphr_scr2_WORD word0
562 #define lpfc_port_smphr_host_scratch_SHIFT 16
563 #define lpfc_port_smphr_host_scratch_MASK 0xFF
564 #define lpfc_port_smphr_host_scratch_WORD word0
565 #define lpfc_port_smphr_port_status_SHIFT 0
566 #define lpfc_port_smphr_port_status_MASK 0xFFFF
567 #define lpfc_port_smphr_port_status_WORD word0
569 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
570 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
571 #define LPFC_POST_STAGE_HOST_RDY 0x0002
572 #define LPFC_POST_STAGE_BE_RESET 0x0003
573 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
574 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
575 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
576 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
577 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
578 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
579 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
580 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
581 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
582 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
583 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
584 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
585 #define LPFC_POST_STAGE_ARMFW_START 0x0800
586 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
587 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
588 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
589 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
590 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
591 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
592 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
593 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
594 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
595 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
596 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
597 #define LPFC_POST_STAGE_RC_DONE 0x0B07
598 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
599 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
600 #define LPFC_POST_STAGE_PORT_READY 0xC000
601 #define LPFC_POST_STAGE_PORT_UE 0xF000
603 #define LPFC_CTL_PORT_STA_OFFSET 0x404
604 #define lpfc_sliport_status_err_SHIFT 31
605 #define lpfc_sliport_status_err_MASK 0x1
606 #define lpfc_sliport_status_err_WORD word0
607 #define lpfc_sliport_status_end_SHIFT 30
608 #define lpfc_sliport_status_end_MASK 0x1
609 #define lpfc_sliport_status_end_WORD word0
610 #define lpfc_sliport_status_oti_SHIFT 29
611 #define lpfc_sliport_status_oti_MASK 0x1
612 #define lpfc_sliport_status_oti_WORD word0
613 #define lpfc_sliport_status_rn_SHIFT 24
614 #define lpfc_sliport_status_rn_MASK 0x1
615 #define lpfc_sliport_status_rn_WORD word0
616 #define lpfc_sliport_status_rdy_SHIFT 23
617 #define lpfc_sliport_status_rdy_MASK 0x1
618 #define lpfc_sliport_status_rdy_WORD word0
619 #define MAX_IF_TYPE_2_RESETS 1000
621 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
622 #define lpfc_sliport_ctrl_end_SHIFT 30
623 #define lpfc_sliport_ctrl_end_MASK 0x1
624 #define lpfc_sliport_ctrl_end_WORD word0
625 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
626 #define LPFC_SLIPORT_BIG_ENDIAN 1
627 #define lpfc_sliport_ctrl_ip_SHIFT 27
628 #define lpfc_sliport_ctrl_ip_MASK 0x1
629 #define lpfc_sliport_ctrl_ip_WORD word0
630 #define LPFC_SLIPORT_INIT_PORT 1
632 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
633 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
635 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
638 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
640 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
641 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
643 #define LPFC_HST_ISR0 0x0C18
644 #define LPFC_HST_ISR1 0x0C1C
645 #define LPFC_HST_ISR2 0x0C20
646 #define LPFC_HST_ISR3 0x0C24
647 #define LPFC_HST_ISR4 0x0C28
649 #define LPFC_HST_IMR0 0x0C48
650 #define LPFC_HST_IMR1 0x0C4C
651 #define LPFC_HST_IMR2 0x0C50
652 #define LPFC_HST_IMR3 0x0C54
653 #define LPFC_HST_IMR4 0x0C58
655 #define LPFC_HST_ISCR0 0x0C78
656 #define LPFC_HST_ISCR1 0x0C7C
657 #define LPFC_HST_ISCR2 0x0C80
658 #define LPFC_HST_ISCR3 0x0C84
659 #define LPFC_HST_ISCR4 0x0C88
661 #define LPFC_SLI4_INTR0 BIT0
662 #define LPFC_SLI4_INTR1 BIT1
663 #define LPFC_SLI4_INTR2 BIT2
664 #define LPFC_SLI4_INTR3 BIT3
665 #define LPFC_SLI4_INTR4 BIT4
666 #define LPFC_SLI4_INTR5 BIT5
667 #define LPFC_SLI4_INTR6 BIT6
668 #define LPFC_SLI4_INTR7 BIT7
669 #define LPFC_SLI4_INTR8 BIT8
670 #define LPFC_SLI4_INTR9 BIT9
671 #define LPFC_SLI4_INTR10 BIT10
672 #define LPFC_SLI4_INTR11 BIT11
673 #define LPFC_SLI4_INTR12 BIT12
674 #define LPFC_SLI4_INTR13 BIT13
675 #define LPFC_SLI4_INTR14 BIT14
676 #define LPFC_SLI4_INTR15 BIT15
677 #define LPFC_SLI4_INTR16 BIT16
678 #define LPFC_SLI4_INTR17 BIT17
679 #define LPFC_SLI4_INTR18 BIT18
680 #define LPFC_SLI4_INTR19 BIT19
681 #define LPFC_SLI4_INTR20 BIT20
682 #define LPFC_SLI4_INTR21 BIT21
683 #define LPFC_SLI4_INTR22 BIT22
684 #define LPFC_SLI4_INTR23 BIT23
685 #define LPFC_SLI4_INTR24 BIT24
686 #define LPFC_SLI4_INTR25 BIT25
687 #define LPFC_SLI4_INTR26 BIT26
688 #define LPFC_SLI4_INTR27 BIT27
689 #define LPFC_SLI4_INTR28 BIT28
690 #define LPFC_SLI4_INTR29 BIT29
691 #define LPFC_SLI4_INTR30 BIT30
692 #define LPFC_SLI4_INTR31 BIT31
695 * The Doorbell registers defined here exist in different BAR
696 * register sets depending on the UCNA Port's reported if_type
697 * value. For UCNA ports running SLI4 and if_type 0, they reside in
698 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
699 * BAR0. The offsets are the same so the driver must account for
700 * any base address difference.
702 #define LPFC_RQ_DOORBELL 0x00A0
703 #define lpfc_rq_doorbell_num_posted_SHIFT 16
704 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
705 #define lpfc_rq_doorbell_num_posted_WORD word0
706 #define lpfc_rq_doorbell_id_SHIFT 0
707 #define lpfc_rq_doorbell_id_MASK 0xFFFF
708 #define lpfc_rq_doorbell_id_WORD word0
710 #define LPFC_WQ_DOORBELL 0x0040
711 #define lpfc_wq_doorbell_num_posted_SHIFT 24
712 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF
713 #define lpfc_wq_doorbell_num_posted_WORD word0
714 #define lpfc_wq_doorbell_index_SHIFT 16
715 #define lpfc_wq_doorbell_index_MASK 0x00FF
716 #define lpfc_wq_doorbell_index_WORD word0
717 #define lpfc_wq_doorbell_id_SHIFT 0
718 #define lpfc_wq_doorbell_id_MASK 0xFFFF
719 #define lpfc_wq_doorbell_id_WORD word0
721 #define LPFC_EQCQ_DOORBELL 0x0120
722 #define lpfc_eqcq_doorbell_se_SHIFT 31
723 #define lpfc_eqcq_doorbell_se_MASK 0x0001
724 #define lpfc_eqcq_doorbell_se_WORD word0
725 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
726 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
727 #define lpfc_eqcq_doorbell_arm_SHIFT 29
728 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
729 #define lpfc_eqcq_doorbell_arm_WORD word0
730 #define lpfc_eqcq_doorbell_num_released_SHIFT 16
731 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
732 #define lpfc_eqcq_doorbell_num_released_WORD word0
733 #define lpfc_eqcq_doorbell_qt_SHIFT 10
734 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
735 #define lpfc_eqcq_doorbell_qt_WORD word0
736 #define LPFC_QUEUE_TYPE_COMPLETION 0
737 #define LPFC_QUEUE_TYPE_EVENT 1
738 #define lpfc_eqcq_doorbell_eqci_SHIFT 9
739 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
740 #define lpfc_eqcq_doorbell_eqci_WORD word0
741 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
742 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
743 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0
744 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
745 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
746 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0
747 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
748 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
749 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0
750 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
751 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
752 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0
753 #define LPFC_CQID_HI_FIELD_SHIFT 10
754 #define LPFC_EQID_HI_FIELD_SHIFT 9
756 #define LPFC_BMBX 0x0160
757 #define lpfc_bmbx_addr_SHIFT 2
758 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
759 #define lpfc_bmbx_addr_WORD word0
760 #define lpfc_bmbx_hi_SHIFT 1
761 #define lpfc_bmbx_hi_MASK 0x0001
762 #define lpfc_bmbx_hi_WORD word0
763 #define lpfc_bmbx_rdy_SHIFT 0
764 #define lpfc_bmbx_rdy_MASK 0x0001
765 #define lpfc_bmbx_rdy_WORD word0
767 #define LPFC_MQ_DOORBELL 0x0140
768 #define lpfc_mq_doorbell_num_posted_SHIFT 16
769 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
770 #define lpfc_mq_doorbell_num_posted_WORD word0
771 #define lpfc_mq_doorbell_id_SHIFT 0
772 #define lpfc_mq_doorbell_id_MASK 0xFFFF
773 #define lpfc_mq_doorbell_id_WORD word0
775 struct lpfc_sli4_cfg_mhdr
{
777 #define lpfc_mbox_hdr_emb_SHIFT 0
778 #define lpfc_mbox_hdr_emb_MASK 0x00000001
779 #define lpfc_mbox_hdr_emb_WORD word1
780 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3
781 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
782 #define lpfc_mbox_hdr_sge_cnt_WORD word1
783 uint32_t payload_length
;
789 union lpfc_sli4_cfg_shdr
{
792 #define lpfc_mbox_hdr_opcode_SHIFT 0
793 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
794 #define lpfc_mbox_hdr_opcode_WORD word6
795 #define lpfc_mbox_hdr_subsystem_SHIFT 8
796 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
797 #define lpfc_mbox_hdr_subsystem_WORD word6
798 #define lpfc_mbox_hdr_port_number_SHIFT 16
799 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
800 #define lpfc_mbox_hdr_port_number_WORD word6
801 #define lpfc_mbox_hdr_domain_SHIFT 24
802 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
803 #define lpfc_mbox_hdr_domain_WORD word6
805 uint32_t request_length
;
807 #define lpfc_mbox_hdr_version_SHIFT 0
808 #define lpfc_mbox_hdr_version_MASK 0x000000FF
809 #define lpfc_mbox_hdr_version_WORD word9
810 #define lpfc_mbox_hdr_pf_num_SHIFT 16
811 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
812 #define lpfc_mbox_hdr_pf_num_WORD word9
813 #define lpfc_mbox_hdr_vh_num_SHIFT 24
814 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
815 #define lpfc_mbox_hdr_vh_num_WORD word9
816 #define LPFC_Q_CREATE_VERSION_2 2
817 #define LPFC_Q_CREATE_VERSION_1 1
818 #define LPFC_Q_CREATE_VERSION_0 0
819 #define LPFC_OPCODE_VERSION_0 0
820 #define LPFC_OPCODE_VERSION_1 1
824 #define lpfc_mbox_hdr_opcode_SHIFT 0
825 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
826 #define lpfc_mbox_hdr_opcode_WORD word6
827 #define lpfc_mbox_hdr_subsystem_SHIFT 8
828 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
829 #define lpfc_mbox_hdr_subsystem_WORD word6
830 #define lpfc_mbox_hdr_domain_SHIFT 24
831 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
832 #define lpfc_mbox_hdr_domain_WORD word6
834 #define lpfc_mbox_hdr_status_SHIFT 0
835 #define lpfc_mbox_hdr_status_MASK 0x000000FF
836 #define lpfc_mbox_hdr_status_WORD word7
837 #define lpfc_mbox_hdr_add_status_SHIFT 8
838 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
839 #define lpfc_mbox_hdr_add_status_WORD word7
840 uint32_t response_length
;
841 uint32_t actual_response_length
;
845 /* Mailbox Header structures.
846 * struct mbox_header is defined for first generation SLI4_CFG mailbox
847 * calls deployed for BE-based ports.
849 * struct sli4_mbox_header is defined for second generation SLI4
850 * ports that don't deploy the SLI4_CFG mechanism.
853 struct lpfc_sli4_cfg_mhdr cfg_mhdr
;
854 union lpfc_sli4_cfg_shdr cfg_shdr
;
857 #define LPFC_EXTENT_LOCAL 0
858 #define LPFC_TIMEOUT_DEFAULT 0
859 #define LPFC_EXTENT_VERSION_DEFAULT 0
861 /* Subsystem Definitions */
862 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
863 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
864 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
866 /* Device Specific Definitions */
868 /* The HOST ENDIAN defines are in Big Endian format. */
869 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
870 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
873 #define LPFC_MBOX_OPCODE_NA 0x00
874 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
875 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
876 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
877 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
878 #define LPFC_MBOX_OPCODE_NOP 0x21
879 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
880 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
881 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
882 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
883 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
884 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
885 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
886 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
887 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
888 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
889 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
890 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
891 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
892 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
893 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
894 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
895 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
896 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
897 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
898 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
899 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
900 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
901 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
904 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
905 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
906 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
907 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
908 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
909 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
910 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
911 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
912 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
913 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
914 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
915 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
916 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
917 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
919 /* Mailbox command structures */
922 #define lpfc_eq_context_size_SHIFT 31
923 #define lpfc_eq_context_size_MASK 0x00000001
924 #define lpfc_eq_context_size_WORD word0
925 #define LPFC_EQE_SIZE_4 0x0
926 #define LPFC_EQE_SIZE_16 0x1
927 #define lpfc_eq_context_valid_SHIFT 29
928 #define lpfc_eq_context_valid_MASK 0x00000001
929 #define lpfc_eq_context_valid_WORD word0
931 #define lpfc_eq_context_count_SHIFT 26
932 #define lpfc_eq_context_count_MASK 0x00000003
933 #define lpfc_eq_context_count_WORD word1
934 #define LPFC_EQ_CNT_256 0x0
935 #define LPFC_EQ_CNT_512 0x1
936 #define LPFC_EQ_CNT_1024 0x2
937 #define LPFC_EQ_CNT_2048 0x3
938 #define LPFC_EQ_CNT_4096 0x4
940 #define lpfc_eq_context_delay_multi_SHIFT 13
941 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
942 #define lpfc_eq_context_delay_multi_WORD word2
946 struct eq_delay_info
{
949 uint32_t delay_multi
;
951 #define LPFC_MAX_EQ_DELAY 8
953 struct sgl_page_pairs
{
954 uint32_t sgl_pg0_addr_lo
;
955 uint32_t sgl_pg0_addr_hi
;
956 uint32_t sgl_pg1_addr_lo
;
957 uint32_t sgl_pg1_addr_hi
;
960 struct lpfc_mbx_post_sgl_pages
{
961 struct mbox_header header
;
963 #define lpfc_post_sgl_pages_xri_SHIFT 0
964 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
965 #define lpfc_post_sgl_pages_xri_WORD word0
966 #define lpfc_post_sgl_pages_xricnt_SHIFT 16
967 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
968 #define lpfc_post_sgl_pages_xricnt_WORD word0
969 struct sgl_page_pairs sgl_pg_pairs
[1];
972 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
973 struct lpfc_mbx_post_uembed_sgl_page1
{
974 union lpfc_sli4_cfg_shdr cfg_shdr
;
976 struct sgl_page_pairs sgl_pg_pairs
;
979 struct lpfc_mbx_sge
{
985 struct lpfc_mbx_nembed_cmd
{
986 struct lpfc_sli4_cfg_mhdr cfg_mhdr
;
987 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
988 struct lpfc_mbx_sge sge
[LPFC_SLI4_MBX_SGE_MAX_PAGES
];
991 struct lpfc_mbx_nembed_sge_virt
{
992 void *addr
[LPFC_SLI4_MBX_SGE_MAX_PAGES
];
995 struct lpfc_mbx_eq_create
{
996 struct mbox_header header
;
1000 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1001 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1002 #define lpfc_mbx_eq_create_num_pages_WORD word0
1003 struct eq_context context
;
1004 struct dma_address page
[LPFC_MAX_EQ_PAGE
];
1008 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1009 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1010 #define lpfc_mbx_eq_create_q_id_WORD word0
1015 struct lpfc_mbx_modify_eq_delay
{
1016 struct mbox_header header
;
1020 struct eq_delay_info eq
[LPFC_MAX_EQ_DELAY
];
1028 struct lpfc_mbx_eq_destroy
{
1029 struct mbox_header header
;
1033 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1034 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1035 #define lpfc_mbx_eq_destroy_q_id_WORD word0
1043 struct lpfc_mbx_nop
{
1044 struct mbox_header header
;
1045 uint32_t context
[2];
1050 #define lpfc_cq_context_event_SHIFT 31
1051 #define lpfc_cq_context_event_MASK 0x00000001
1052 #define lpfc_cq_context_event_WORD word0
1053 #define lpfc_cq_context_valid_SHIFT 29
1054 #define lpfc_cq_context_valid_MASK 0x00000001
1055 #define lpfc_cq_context_valid_WORD word0
1056 #define lpfc_cq_context_count_SHIFT 27
1057 #define lpfc_cq_context_count_MASK 0x00000003
1058 #define lpfc_cq_context_count_WORD word0
1059 #define LPFC_CQ_CNT_256 0x0
1060 #define LPFC_CQ_CNT_512 0x1
1061 #define LPFC_CQ_CNT_1024 0x2
1063 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1064 #define lpfc_cq_eq_id_MASK 0x000000FF
1065 #define lpfc_cq_eq_id_WORD word1
1066 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1067 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1068 #define lpfc_cq_eq_id_2_WORD word1
1073 struct lpfc_mbx_cq_create
{
1074 struct mbox_header header
;
1078 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1079 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1080 #define lpfc_mbx_cq_create_page_size_WORD word0
1081 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1082 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1083 #define lpfc_mbx_cq_create_num_pages_WORD word0
1084 struct cq_context context
;
1085 struct dma_address page
[LPFC_MAX_CQ_PAGE
];
1089 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1090 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1091 #define lpfc_mbx_cq_create_q_id_WORD word0
1096 struct lpfc_mbx_cq_destroy
{
1097 struct mbox_header header
;
1101 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1102 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1103 #define lpfc_mbx_cq_destroy_q_id_WORD word0
1118 struct lpfc_mbx_wq_create
{
1119 struct mbox_header header
;
1121 struct { /* Version 0 Request */
1123 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1124 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF
1125 #define lpfc_mbx_wq_create_num_pages_WORD word0
1126 #define lpfc_mbx_wq_create_cq_id_SHIFT 16
1127 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1128 #define lpfc_mbx_wq_create_cq_id_WORD word0
1129 struct dma_address page
[LPFC_MAX_WQ_PAGE
];
1131 struct { /* Version 1 Request */
1132 uint32_t word0
; /* Word 0 is the same as in v0 */
1134 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1135 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1136 #define lpfc_mbx_wq_create_page_size_WORD word1
1137 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1138 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1139 #define lpfc_mbx_wq_create_wqe_size_WORD word1
1140 #define LPFC_WQ_WQE_SIZE_64 0x5
1141 #define LPFC_WQ_WQE_SIZE_128 0x6
1142 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1143 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1144 #define lpfc_mbx_wq_create_wqe_count_WORD word1
1146 struct dma_address page
[LPFC_MAX_WQ_PAGE
-1];
1150 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1151 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1152 #define lpfc_mbx_wq_create_q_id_WORD word0
1157 struct lpfc_mbx_wq_destroy
{
1158 struct mbox_header header
;
1162 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1163 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1164 #define lpfc_mbx_wq_destroy_q_id_WORD word0
1172 #define LPFC_HDR_BUF_SIZE 128
1173 #define LPFC_DATA_BUF_SIZE 2048
1176 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1177 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1178 #define lpfc_rq_context_rqe_count_WORD word0
1179 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1180 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1181 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1182 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1183 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */
1184 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1185 #define lpfc_rq_context_rqe_count_1_WORD word0
1186 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */
1187 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1188 #define lpfc_rq_context_rqe_size_WORD word0
1189 #define LPFC_RQE_SIZE_8 2
1190 #define LPFC_RQE_SIZE_16 3
1191 #define LPFC_RQE_SIZE_32 4
1192 #define LPFC_RQE_SIZE_64 5
1193 #define LPFC_RQE_SIZE_128 6
1194 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1195 #define lpfc_rq_context_page_size_MASK 0x000000FF
1196 #define lpfc_rq_context_page_size_WORD word0
1199 #define lpfc_rq_context_cq_id_SHIFT 16
1200 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1201 #define lpfc_rq_context_cq_id_WORD word2
1202 #define lpfc_rq_context_buf_size_SHIFT 0
1203 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1204 #define lpfc_rq_context_buf_size_WORD word2
1205 uint32_t buffer_size
; /* Version 1 Only */
1208 struct lpfc_mbx_rq_create
{
1209 struct mbox_header header
;
1213 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1214 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1215 #define lpfc_mbx_rq_create_num_pages_WORD word0
1216 struct rq_context context
;
1217 struct dma_address page
[LPFC_MAX_WQ_PAGE
];
1221 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1222 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1223 #define lpfc_mbx_rq_create_q_id_WORD word0
1228 struct lpfc_mbx_rq_destroy
{
1229 struct mbox_header header
;
1233 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1234 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1235 #define lpfc_mbx_rq_destroy_q_id_WORD word0
1245 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1246 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1247 #define lpfc_mq_context_cq_id_WORD word0
1248 #define lpfc_mq_context_ring_size_SHIFT 16
1249 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1250 #define lpfc_mq_context_ring_size_WORD word0
1251 #define LPFC_MQ_RING_SIZE_16 0x5
1252 #define LPFC_MQ_RING_SIZE_32 0x6
1253 #define LPFC_MQ_RING_SIZE_64 0x7
1254 #define LPFC_MQ_RING_SIZE_128 0x8
1256 #define lpfc_mq_context_valid_SHIFT 31
1257 #define lpfc_mq_context_valid_MASK 0x00000001
1258 #define lpfc_mq_context_valid_WORD word1
1263 struct lpfc_mbx_mq_create
{
1264 struct mbox_header header
;
1268 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1269 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1270 #define lpfc_mbx_mq_create_num_pages_WORD word0
1271 struct mq_context context
;
1272 struct dma_address page
[LPFC_MAX_MQ_PAGE
];
1276 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1277 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1278 #define lpfc_mbx_mq_create_q_id_WORD word0
1283 struct lpfc_mbx_mq_create_ext
{
1284 struct mbox_header header
;
1288 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1289 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1290 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1291 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1292 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1293 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1294 uint32_t async_evt_bmap
;
1295 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1296 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1297 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1298 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1299 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1300 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1301 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1302 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1303 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1304 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1305 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1306 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1307 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1308 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1309 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1310 struct mq_context context
;
1311 struct dma_address page
[LPFC_MAX_MQ_PAGE
];
1315 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1316 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1317 #define lpfc_mbx_mq_create_q_id_WORD word0
1320 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1321 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1322 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1325 struct lpfc_mbx_mq_destroy
{
1326 struct mbox_header header
;
1330 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1331 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1332 #define lpfc_mbx_mq_destroy_q_id_WORD word0
1340 /* Start Gen 2 SLI4 Mailbox definitions: */
1342 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1343 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1344 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1345 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1346 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1348 struct lpfc_mbx_get_rsrc_extent_info
{
1349 struct mbox_header header
;
1353 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1354 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1355 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1359 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1360 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1361 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1362 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1363 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1364 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1369 struct lpfc_id_range
{
1371 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1372 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1373 #define lpfc_mbx_rsrc_id_word4_0_WORD word5
1374 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1375 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1376 #define lpfc_mbx_rsrc_id_word4_1_WORD word5
1379 struct lpfc_mbx_set_link_diag_state
{
1380 struct mbox_header header
;
1384 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1385 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1386 #define lpfc_mbx_set_diag_state_diag_WORD word0
1387 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2
1388 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1389 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0
1390 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1391 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1
1392 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16
1393 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1394 #define lpfc_mbx_set_diag_state_link_num_WORD word0
1395 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1396 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1397 #define lpfc_mbx_set_diag_state_link_type_WORD word0
1405 struct lpfc_mbx_set_link_diag_loopback
{
1406 struct mbox_header header
;
1410 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1411 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1412 #define lpfc_mbx_set_diag_lpbk_type_WORD word0
1413 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1414 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1415 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1416 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
1417 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1418 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
1419 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
1420 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1421 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
1429 struct lpfc_mbx_run_link_diag_test
{
1430 struct mbox_header header
;
1434 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16
1435 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1436 #define lpfc_mbx_run_diag_test_link_num_WORD word0
1437 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22
1438 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1439 #define lpfc_mbx_run_diag_test_link_type_WORD word0
1441 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1442 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1443 #define lpfc_mbx_run_diag_test_test_id_WORD word1
1444 #define lpfc_mbx_run_diag_test_loops_SHIFT 16
1445 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1446 #define lpfc_mbx_run_diag_test_loops_WORD word1
1448 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1449 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1450 #define lpfc_mbx_run_diag_test_test_ver_WORD word2
1451 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16
1452 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1453 #define lpfc_mbx_run_diag_test_err_act_WORD word2
1462 * struct lpfc_mbx_alloc_rsrc_extents:
1463 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1464 * 6 words of header + 4 words of shared subcommand header +
1465 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1467 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1468 * for extents payload.
1470 * 212/2 (bytes per extent) = 106 extents.
1471 * 106/2 (extents per word) = 53 words.
1472 * lpfc_id_range id is statically size to 53.
1474 * This mailbox definition is used for ALLOC or GET_ALLOCATED
1475 * extent ranges. For ALLOC, the type and cnt are required.
1476 * For GET_ALLOCATED, only the type is required.
1478 struct lpfc_mbx_alloc_rsrc_extents
{
1479 struct mbox_header header
;
1483 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1484 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1485 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
1486 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
1487 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1488 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
1492 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1493 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1494 #define lpfc_mbx_rsrc_cnt_WORD word4
1495 struct lpfc_id_range id
[53];
1501 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1502 * structure shares the same SHIFT/MASK/WORD defines provided in the
1503 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1504 * the structures defined above. This non-embedded structure provides for the
1505 * maximum number of extents supported by the port.
1507 struct lpfc_mbx_nembed_rsrc_extent
{
1508 union lpfc_sli4_cfg_shdr cfg_shdr
;
1510 struct lpfc_id_range id
;
1513 struct lpfc_mbx_dealloc_rsrc_extents
{
1514 struct mbox_header header
;
1517 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
1518 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
1519 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
1524 /* Start SLI4 FCoE specific mbox structures. */
1526 struct lpfc_mbx_post_hdr_tmpl
{
1527 struct mbox_header header
;
1529 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1530 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1531 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1532 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1533 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1534 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1535 uint32_t rpi_paddr_lo
;
1536 uint32_t rpi_paddr_hi
;
1539 struct sli4_sge
{ /* SLI-4 */
1544 #define lpfc_sli4_sge_offset_SHIFT 0
1545 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
1546 #define lpfc_sli4_sge_offset_WORD word2
1547 #define lpfc_sli4_sge_type_SHIFT 27
1548 #define lpfc_sli4_sge_type_MASK 0x0000000F
1549 #define lpfc_sli4_sge_type_WORD word2
1550 #define LPFC_SGE_TYPE_DATA 0x0
1551 #define LPFC_SGE_TYPE_DIF 0x4
1552 #define LPFC_SGE_TYPE_LSP 0x5
1553 #define LPFC_SGE_TYPE_PEDIF 0x6
1554 #define LPFC_SGE_TYPE_PESEED 0x7
1555 #define LPFC_SGE_TYPE_DISEED 0x8
1556 #define LPFC_SGE_TYPE_ENC 0x9
1557 #define LPFC_SGE_TYPE_ATM 0xA
1558 #define LPFC_SGE_TYPE_SKIP 0xC
1559 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
1560 #define lpfc_sli4_sge_last_MASK 0x00000001
1561 #define lpfc_sli4_sge_last_WORD word2
1565 struct sli4_sge_diseed
{ /* SLI-4 */
1567 uint32_t ref_tag_tran
;
1570 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
1571 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
1572 #define lpfc_sli4_sge_dif_apptran_WORD word2
1573 #define lpfc_sli4_sge_dif_af_SHIFT 24
1574 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
1575 #define lpfc_sli4_sge_dif_af_WORD word2
1576 #define lpfc_sli4_sge_dif_na_SHIFT 25
1577 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
1578 #define lpfc_sli4_sge_dif_na_WORD word2
1579 #define lpfc_sli4_sge_dif_hi_SHIFT 26
1580 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
1581 #define lpfc_sli4_sge_dif_hi_WORD word2
1582 #define lpfc_sli4_sge_dif_type_SHIFT 27
1583 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
1584 #define lpfc_sli4_sge_dif_type_WORD word2
1585 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
1586 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
1587 #define lpfc_sli4_sge_dif_last_WORD word2
1589 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
1590 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
1591 #define lpfc_sli4_sge_dif_apptag_WORD word3
1592 #define lpfc_sli4_sge_dif_bs_SHIFT 16
1593 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
1594 #define lpfc_sli4_sge_dif_bs_WORD word3
1595 #define lpfc_sli4_sge_dif_ai_SHIFT 19
1596 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
1597 #define lpfc_sli4_sge_dif_ai_WORD word3
1598 #define lpfc_sli4_sge_dif_me_SHIFT 20
1599 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
1600 #define lpfc_sli4_sge_dif_me_WORD word3
1601 #define lpfc_sli4_sge_dif_re_SHIFT 21
1602 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
1603 #define lpfc_sli4_sge_dif_re_WORD word3
1604 #define lpfc_sli4_sge_dif_ce_SHIFT 22
1605 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
1606 #define lpfc_sli4_sge_dif_ce_WORD word3
1607 #define lpfc_sli4_sge_dif_nr_SHIFT 23
1608 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
1609 #define lpfc_sli4_sge_dif_nr_WORD word3
1610 #define lpfc_sli4_sge_dif_oprx_SHIFT 24
1611 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
1612 #define lpfc_sli4_sge_dif_oprx_WORD word3
1613 #define lpfc_sli4_sge_dif_optx_SHIFT 28
1614 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
1615 #define lpfc_sli4_sge_dif_optx_WORD word3
1616 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
1620 uint32_t max_rcv_size
;
1621 uint32_t fka_adv_period
;
1622 uint32_t fip_priority
;
1624 #define lpfc_fcf_record_mac_0_SHIFT 0
1625 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
1626 #define lpfc_fcf_record_mac_0_WORD word3
1627 #define lpfc_fcf_record_mac_1_SHIFT 8
1628 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
1629 #define lpfc_fcf_record_mac_1_WORD word3
1630 #define lpfc_fcf_record_mac_2_SHIFT 16
1631 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
1632 #define lpfc_fcf_record_mac_2_WORD word3
1633 #define lpfc_fcf_record_mac_3_SHIFT 24
1634 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
1635 #define lpfc_fcf_record_mac_3_WORD word3
1637 #define lpfc_fcf_record_mac_4_SHIFT 0
1638 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
1639 #define lpfc_fcf_record_mac_4_WORD word4
1640 #define lpfc_fcf_record_mac_5_SHIFT 8
1641 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
1642 #define lpfc_fcf_record_mac_5_WORD word4
1643 #define lpfc_fcf_record_fcf_avail_SHIFT 16
1644 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
1645 #define lpfc_fcf_record_fcf_avail_WORD word4
1646 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24
1647 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
1648 #define lpfc_fcf_record_mac_addr_prov_WORD word4
1649 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
1650 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
1652 #define lpfc_fcf_record_fab_name_0_SHIFT 0
1653 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
1654 #define lpfc_fcf_record_fab_name_0_WORD word5
1655 #define lpfc_fcf_record_fab_name_1_SHIFT 8
1656 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
1657 #define lpfc_fcf_record_fab_name_1_WORD word5
1658 #define lpfc_fcf_record_fab_name_2_SHIFT 16
1659 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
1660 #define lpfc_fcf_record_fab_name_2_WORD word5
1661 #define lpfc_fcf_record_fab_name_3_SHIFT 24
1662 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
1663 #define lpfc_fcf_record_fab_name_3_WORD word5
1665 #define lpfc_fcf_record_fab_name_4_SHIFT 0
1666 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
1667 #define lpfc_fcf_record_fab_name_4_WORD word6
1668 #define lpfc_fcf_record_fab_name_5_SHIFT 8
1669 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
1670 #define lpfc_fcf_record_fab_name_5_WORD word6
1671 #define lpfc_fcf_record_fab_name_6_SHIFT 16
1672 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
1673 #define lpfc_fcf_record_fab_name_6_WORD word6
1674 #define lpfc_fcf_record_fab_name_7_SHIFT 24
1675 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
1676 #define lpfc_fcf_record_fab_name_7_WORD word6
1678 #define lpfc_fcf_record_fc_map_0_SHIFT 0
1679 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
1680 #define lpfc_fcf_record_fc_map_0_WORD word7
1681 #define lpfc_fcf_record_fc_map_1_SHIFT 8
1682 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
1683 #define lpfc_fcf_record_fc_map_1_WORD word7
1684 #define lpfc_fcf_record_fc_map_2_SHIFT 16
1685 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
1686 #define lpfc_fcf_record_fc_map_2_WORD word7
1687 #define lpfc_fcf_record_fcf_valid_SHIFT 24
1688 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF
1689 #define lpfc_fcf_record_fcf_valid_WORD word7
1691 #define lpfc_fcf_record_fcf_index_SHIFT 0
1692 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
1693 #define lpfc_fcf_record_fcf_index_WORD word8
1694 #define lpfc_fcf_record_fcf_state_SHIFT 16
1695 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
1696 #define lpfc_fcf_record_fcf_state_WORD word8
1697 uint8_t vlan_bitmap
[512];
1699 #define lpfc_fcf_record_switch_name_0_SHIFT 0
1700 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
1701 #define lpfc_fcf_record_switch_name_0_WORD word137
1702 #define lpfc_fcf_record_switch_name_1_SHIFT 8
1703 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
1704 #define lpfc_fcf_record_switch_name_1_WORD word137
1705 #define lpfc_fcf_record_switch_name_2_SHIFT 16
1706 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
1707 #define lpfc_fcf_record_switch_name_2_WORD word137
1708 #define lpfc_fcf_record_switch_name_3_SHIFT 24
1709 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
1710 #define lpfc_fcf_record_switch_name_3_WORD word137
1712 #define lpfc_fcf_record_switch_name_4_SHIFT 0
1713 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
1714 #define lpfc_fcf_record_switch_name_4_WORD word138
1715 #define lpfc_fcf_record_switch_name_5_SHIFT 8
1716 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
1717 #define lpfc_fcf_record_switch_name_5_WORD word138
1718 #define lpfc_fcf_record_switch_name_6_SHIFT 16
1719 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
1720 #define lpfc_fcf_record_switch_name_6_WORD word138
1721 #define lpfc_fcf_record_switch_name_7_SHIFT 24
1722 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
1723 #define lpfc_fcf_record_switch_name_7_WORD word138
1726 struct lpfc_mbx_read_fcf_tbl
{
1727 union lpfc_sli4_cfg_shdr cfg_shdr
;
1731 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
1732 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
1733 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10
1740 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
1741 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
1742 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
1745 struct lpfc_mbx_add_fcf_tbl_entry
{
1746 union lpfc_sli4_cfg_shdr cfg_shdr
;
1748 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
1749 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
1750 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
1751 struct lpfc_mbx_sge fcf_sge
;
1754 struct lpfc_mbx_del_fcf_tbl_entry
{
1755 struct mbox_header header
;
1757 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
1758 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
1759 #define lpfc_mbx_del_fcf_tbl_count_WORD word10
1760 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
1761 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
1762 #define lpfc_mbx_del_fcf_tbl_index_WORD word10
1765 struct lpfc_mbx_redisc_fcf_tbl
{
1766 struct mbox_header header
;
1768 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
1769 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
1770 #define lpfc_mbx_redisc_fcf_count_WORD word10
1773 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
1774 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
1775 #define lpfc_mbx_redisc_fcf_index_WORD word12
1778 struct lpfc_mbx_query_fw_cfg
{
1779 struct mbox_header header
;
1780 uint32_t config_number
;
1783 uint32_t function_mode
;
1784 /* firmware Function Mode */
1785 #define lpfc_function_mode_toe_SHIFT 0
1786 #define lpfc_function_mode_toe_MASK 0x00000001
1787 #define lpfc_function_mode_toe_WORD function_mode
1788 #define lpfc_function_mode_nic_SHIFT 1
1789 #define lpfc_function_mode_nic_MASK 0x00000001
1790 #define lpfc_function_mode_nic_WORD function_mode
1791 #define lpfc_function_mode_rdma_SHIFT 2
1792 #define lpfc_function_mode_rdma_MASK 0x00000001
1793 #define lpfc_function_mode_rdma_WORD function_mode
1794 #define lpfc_function_mode_vm_SHIFT 3
1795 #define lpfc_function_mode_vm_MASK 0x00000001
1796 #define lpfc_function_mode_vm_WORD function_mode
1797 #define lpfc_function_mode_iscsi_i_SHIFT 4
1798 #define lpfc_function_mode_iscsi_i_MASK 0x00000001
1799 #define lpfc_function_mode_iscsi_i_WORD function_mode
1800 #define lpfc_function_mode_iscsi_t_SHIFT 5
1801 #define lpfc_function_mode_iscsi_t_MASK 0x00000001
1802 #define lpfc_function_mode_iscsi_t_WORD function_mode
1803 #define lpfc_function_mode_fcoe_i_SHIFT 6
1804 #define lpfc_function_mode_fcoe_i_MASK 0x00000001
1805 #define lpfc_function_mode_fcoe_i_WORD function_mode
1806 #define lpfc_function_mode_fcoe_t_SHIFT 7
1807 #define lpfc_function_mode_fcoe_t_MASK 0x00000001
1808 #define lpfc_function_mode_fcoe_t_WORD function_mode
1809 #define lpfc_function_mode_dal_SHIFT 8
1810 #define lpfc_function_mode_dal_MASK 0x00000001
1811 #define lpfc_function_mode_dal_WORD function_mode
1812 #define lpfc_function_mode_lro_SHIFT 9
1813 #define lpfc_function_mode_lro_MASK 0x00000001
1814 #define lpfc_function_mode_lro_WORD function_mode
1815 #define lpfc_function_mode_flex10_SHIFT 10
1816 #define lpfc_function_mode_flex10_MASK 0x00000001
1817 #define lpfc_function_mode_flex10_WORD function_mode
1818 #define lpfc_function_mode_ncsi_SHIFT 11
1819 #define lpfc_function_mode_ncsi_MASK 0x00000001
1820 #define lpfc_function_mode_ncsi_WORD function_mode
1823 /* Status field for embedded SLI_CONFIG mailbox command */
1824 #define STATUS_SUCCESS 0x0
1825 #define STATUS_FAILED 0x1
1826 #define STATUS_ILLEGAL_REQUEST 0x2
1827 #define STATUS_ILLEGAL_FIELD 0x3
1828 #define STATUS_INSUFFICIENT_BUFFER 0x4
1829 #define STATUS_UNAUTHORIZED_REQUEST 0x5
1830 #define STATUS_FLASHROM_SAVE_FAILED 0x17
1831 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
1832 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
1833 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
1834 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
1835 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
1836 #define STATUS_ASSERT_FAILED 0x1e
1837 #define STATUS_INVALID_SESSION 0x1f
1838 #define STATUS_INVALID_CONNECTION 0x20
1839 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
1840 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
1841 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
1842 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
1843 #define STATUS_FLASHROM_READ_FAILED 0x27
1844 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
1845 #define STATUS_ERROR_ACITMAIN 0x2a
1846 #define STATUS_REBOOT_REQUIRED 0x2c
1847 #define STATUS_FCF_IN_USE 0x3a
1848 #define STATUS_FCF_TABLE_EMPTY 0x43
1850 struct lpfc_mbx_sli4_config
{
1851 struct mbox_header header
;
1854 struct lpfc_mbx_init_vfi
{
1856 #define lpfc_init_vfi_vr_SHIFT 31
1857 #define lpfc_init_vfi_vr_MASK 0x00000001
1858 #define lpfc_init_vfi_vr_WORD word1
1859 #define lpfc_init_vfi_vt_SHIFT 30
1860 #define lpfc_init_vfi_vt_MASK 0x00000001
1861 #define lpfc_init_vfi_vt_WORD word1
1862 #define lpfc_init_vfi_vf_SHIFT 29
1863 #define lpfc_init_vfi_vf_MASK 0x00000001
1864 #define lpfc_init_vfi_vf_WORD word1
1865 #define lpfc_init_vfi_vp_SHIFT 28
1866 #define lpfc_init_vfi_vp_MASK 0x00000001
1867 #define lpfc_init_vfi_vp_WORD word1
1868 #define lpfc_init_vfi_vfi_SHIFT 0
1869 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
1870 #define lpfc_init_vfi_vfi_WORD word1
1872 #define lpfc_init_vfi_vpi_SHIFT 16
1873 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
1874 #define lpfc_init_vfi_vpi_WORD word2
1875 #define lpfc_init_vfi_fcfi_SHIFT 0
1876 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
1877 #define lpfc_init_vfi_fcfi_WORD word2
1879 #define lpfc_init_vfi_pri_SHIFT 13
1880 #define lpfc_init_vfi_pri_MASK 0x00000007
1881 #define lpfc_init_vfi_pri_WORD word3
1882 #define lpfc_init_vfi_vf_id_SHIFT 1
1883 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
1884 #define lpfc_init_vfi_vf_id_WORD word3
1886 #define lpfc_init_vfi_hop_count_SHIFT 24
1887 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
1888 #define lpfc_init_vfi_hop_count_WORD word4
1890 #define MBX_VFI_IN_USE 0x9F02
1893 struct lpfc_mbx_reg_vfi
{
1895 #define lpfc_reg_vfi_vp_SHIFT 28
1896 #define lpfc_reg_vfi_vp_MASK 0x00000001
1897 #define lpfc_reg_vfi_vp_WORD word1
1898 #define lpfc_reg_vfi_vfi_SHIFT 0
1899 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
1900 #define lpfc_reg_vfi_vfi_WORD word1
1902 #define lpfc_reg_vfi_vpi_SHIFT 16
1903 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
1904 #define lpfc_reg_vfi_vpi_WORD word2
1905 #define lpfc_reg_vfi_fcfi_SHIFT 0
1906 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
1907 #define lpfc_reg_vfi_fcfi_WORD word2
1909 struct ulp_bde64 bde
;
1913 #define lpfc_reg_vfi_nport_id_SHIFT 0
1914 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
1915 #define lpfc_reg_vfi_nport_id_WORD word10
1918 struct lpfc_mbx_init_vpi
{
1920 #define lpfc_init_vpi_vfi_SHIFT 16
1921 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
1922 #define lpfc_init_vpi_vfi_WORD word1
1923 #define lpfc_init_vpi_vpi_SHIFT 0
1924 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
1925 #define lpfc_init_vpi_vpi_WORD word1
1928 struct lpfc_mbx_read_vpi
{
1929 uint32_t word1_rsvd
;
1931 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
1932 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
1933 #define lpfc_mbx_read_vpi_vnportid_WORD word2
1934 uint32_t word3_rsvd
;
1936 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
1937 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
1938 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4
1939 #define lpfc_mbx_read_vpi_pb_SHIFT 15
1940 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
1941 #define lpfc_mbx_read_vpi_pb_WORD word4
1942 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
1943 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
1944 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4
1945 #define lpfc_mbx_read_vpi_ns_SHIFT 30
1946 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
1947 #define lpfc_mbx_read_vpi_ns_WORD word4
1948 #define lpfc_mbx_read_vpi_hl_SHIFT 31
1949 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
1950 #define lpfc_mbx_read_vpi_hl_WORD word4
1951 uint32_t word5_rsvd
;
1953 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
1954 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
1955 #define lpfc_mbx_read_vpi_vpi_WORD word6
1957 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
1958 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
1959 #define lpfc_mbx_read_vpi_mac_0_WORD word7
1960 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8
1961 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
1962 #define lpfc_mbx_read_vpi_mac_1_WORD word7
1963 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16
1964 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
1965 #define lpfc_mbx_read_vpi_mac_2_WORD word7
1966 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24
1967 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
1968 #define lpfc_mbx_read_vpi_mac_3_WORD word7
1970 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
1971 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
1972 #define lpfc_mbx_read_vpi_mac_4_WORD word8
1973 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8
1974 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
1975 #define lpfc_mbx_read_vpi_mac_5_WORD word8
1976 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
1977 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
1978 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8
1979 #define lpfc_mbx_read_vpi_vv_SHIFT 28
1980 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
1981 #define lpfc_mbx_read_vpi_vv_WORD word8
1984 struct lpfc_mbx_unreg_vfi
{
1985 uint32_t word1_rsvd
;
1987 #define lpfc_unreg_vfi_vfi_SHIFT 0
1988 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
1989 #define lpfc_unreg_vfi_vfi_WORD word2
1992 struct lpfc_mbx_resume_rpi
{
1994 #define lpfc_resume_rpi_index_SHIFT 0
1995 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
1996 #define lpfc_resume_rpi_index_WORD word1
1997 #define lpfc_resume_rpi_ii_SHIFT 30
1998 #define lpfc_resume_rpi_ii_MASK 0x00000003
1999 #define lpfc_resume_rpi_ii_WORD word1
2000 #define RESUME_INDEX_RPI 0
2001 #define RESUME_INDEX_VPI 1
2002 #define RESUME_INDEX_VFI 2
2003 #define RESUME_INDEX_FCFI 3
2007 #define REG_FCF_INVALID_QID 0xFFFF
2008 struct lpfc_mbx_reg_fcfi
{
2010 #define lpfc_reg_fcfi_info_index_SHIFT 0
2011 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2012 #define lpfc_reg_fcfi_info_index_WORD word1
2013 #define lpfc_reg_fcfi_fcfi_SHIFT 16
2014 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2015 #define lpfc_reg_fcfi_fcfi_WORD word1
2017 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2018 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2019 #define lpfc_reg_fcfi_rq_id1_WORD word2
2020 #define lpfc_reg_fcfi_rq_id0_SHIFT 16
2021 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2022 #define lpfc_reg_fcfi_rq_id0_WORD word2
2024 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2025 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2026 #define lpfc_reg_fcfi_rq_id3_WORD word3
2027 #define lpfc_reg_fcfi_rq_id2_SHIFT 16
2028 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2029 #define lpfc_reg_fcfi_rq_id2_WORD word3
2031 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2032 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2033 #define lpfc_reg_fcfi_type_match0_WORD word4
2034 #define lpfc_reg_fcfi_type_mask0_SHIFT 16
2035 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2036 #define lpfc_reg_fcfi_type_mask0_WORD word4
2037 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2038 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2039 #define lpfc_reg_fcfi_rctl_match0_WORD word4
2040 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2041 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2042 #define lpfc_reg_fcfi_rctl_mask0_WORD word4
2044 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2045 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2046 #define lpfc_reg_fcfi_type_match1_WORD word5
2047 #define lpfc_reg_fcfi_type_mask1_SHIFT 16
2048 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2049 #define lpfc_reg_fcfi_type_mask1_WORD word5
2050 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2051 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2052 #define lpfc_reg_fcfi_rctl_match1_WORD word5
2053 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2054 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2055 #define lpfc_reg_fcfi_rctl_mask1_WORD word5
2057 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2058 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2059 #define lpfc_reg_fcfi_type_match2_WORD word6
2060 #define lpfc_reg_fcfi_type_mask2_SHIFT 16
2061 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2062 #define lpfc_reg_fcfi_type_mask2_WORD word6
2063 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2064 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2065 #define lpfc_reg_fcfi_rctl_match2_WORD word6
2066 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2067 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2068 #define lpfc_reg_fcfi_rctl_mask2_WORD word6
2070 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2071 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2072 #define lpfc_reg_fcfi_type_match3_WORD word7
2073 #define lpfc_reg_fcfi_type_mask3_SHIFT 16
2074 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2075 #define lpfc_reg_fcfi_type_mask3_WORD word7
2076 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2077 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2078 #define lpfc_reg_fcfi_rctl_match3_WORD word7
2079 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2080 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2081 #define lpfc_reg_fcfi_rctl_mask3_WORD word7
2083 #define lpfc_reg_fcfi_mam_SHIFT 13
2084 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2085 #define lpfc_reg_fcfi_mam_WORD word8
2086 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2087 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2088 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2089 #define lpfc_reg_fcfi_vv_SHIFT 12
2090 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2091 #define lpfc_reg_fcfi_vv_WORD word8
2092 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2093 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2094 #define lpfc_reg_fcfi_vlan_tag_WORD word8
2097 struct lpfc_mbx_unreg_fcfi
{
2100 #define lpfc_unreg_fcfi_SHIFT 0
2101 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2102 #define lpfc_unreg_fcfi_WORD word2
2105 struct lpfc_mbx_read_rev
{
2107 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2108 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2109 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2110 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2111 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2112 #define lpfc_mbx_rd_rev_fcoe_WORD word1
2113 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2114 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2115 #define lpfc_mbx_rd_rev_cee_ver_WORD word1
2116 #define LPFC_PREDCBX_CEE_MODE 0
2117 #define LPFC_DCBX_CEE_MODE 1
2118 #define lpfc_mbx_rd_rev_vpd_SHIFT 29
2119 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2120 #define lpfc_mbx_rd_rev_vpd_WORD word1
2121 uint32_t first_hw_rev
;
2122 uint32_t second_hw_rev
;
2123 uint32_t word4_rsvd
;
2124 uint32_t third_hw_rev
;
2126 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2127 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2128 #define lpfc_mbx_rd_rev_fcph_low_WORD word6
2129 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2130 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2131 #define lpfc_mbx_rd_rev_fcph_high_WORD word6
2132 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2133 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2134 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2135 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2136 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2137 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2138 uint32_t word7_rsvd
;
2140 uint8_t fw_name
[16];
2141 uint32_t ulp_fw_id_rev
;
2142 uint8_t ulp_fw_name
[16];
2143 uint32_t word18_47_rsvd
[30];
2145 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2146 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2147 #define lpfc_mbx_rd_rev_avail_len_WORD word48
2148 uint32_t vpd_paddr_low
;
2149 uint32_t vpd_paddr_high
;
2150 uint32_t avail_vpd_len
;
2151 uint32_t rsvd_52_63
[12];
2154 struct lpfc_mbx_read_config
{
2156 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2157 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2158 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2160 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2161 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2162 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2163 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2164 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2165 #define lpfc_mbx_rd_conf_lnk_type_WORD word2
2166 #define LPFC_LNK_TYPE_GE 0
2167 #define LPFC_LNK_TYPE_FC 1
2168 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2169 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2170 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2171 #define lpfc_mbx_rd_conf_topology_SHIFT 24
2172 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2173 #define lpfc_mbx_rd_conf_topology_WORD word2
2176 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2177 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2178 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2181 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2182 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2183 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2187 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2188 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2189 #define lpfc_mbx_rd_conf_lmt_WORD word9
2193 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2194 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2195 #define lpfc_mbx_rd_conf_xri_base_WORD word12
2196 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16
2197 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2198 #define lpfc_mbx_rd_conf_xri_count_WORD word12
2200 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2201 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2202 #define lpfc_mbx_rd_conf_rpi_base_WORD word13
2203 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
2204 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2205 #define lpfc_mbx_rd_conf_rpi_count_WORD word13
2207 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2208 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2209 #define lpfc_mbx_rd_conf_vpi_base_WORD word14
2210 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
2211 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2212 #define lpfc_mbx_rd_conf_vpi_count_WORD word14
2214 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2215 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2216 #define lpfc_mbx_rd_conf_vfi_base_WORD word15
2217 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
2218 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2219 #define lpfc_mbx_rd_conf_vfi_count_WORD word15
2221 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
2222 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2223 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16
2225 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2226 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2227 #define lpfc_mbx_rd_conf_rq_count_WORD word17
2228 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16
2229 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2230 #define lpfc_mbx_rd_conf_eq_count_WORD word17
2232 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2233 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2234 #define lpfc_mbx_rd_conf_wq_count_WORD word18
2235 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16
2236 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2237 #define lpfc_mbx_rd_conf_cq_count_WORD word18
2240 struct lpfc_mbx_request_features
{
2242 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2243 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2244 #define lpfc_mbx_rq_ftr_qry_WORD word1
2246 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2247 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2248 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
2249 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
2250 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2251 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
2252 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
2253 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2254 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2
2255 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
2256 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2257 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2
2258 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
2259 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2260 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
2261 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
2262 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2263 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
2264 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
2265 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2266 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
2267 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
2268 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2269 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
2270 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11
2271 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2272 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2
2274 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2275 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2276 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
2277 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
2278 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2279 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
2280 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
2281 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2282 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
2283 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
2284 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2285 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
2286 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
2287 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2288 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
2289 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
2290 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2291 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
2292 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
2293 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2294 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
2295 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
2296 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2297 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
2298 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11
2299 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2300 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3
2303 struct lpfc_mbx_supp_pages
{
2306 #define qs_MASK 0x00000001
2307 #define qs_WORD word1
2309 #define wr_MASK 0x00000001
2310 #define wr_WORD word1
2312 #define pf_MASK 0x000000ff
2313 #define pf_WORD word1
2314 #define cpn_SHIFT 16
2315 #define cpn_MASK 0x000000ff
2316 #define cpn_WORD word1
2318 #define list_offset_SHIFT 0
2319 #define list_offset_MASK 0x000000ff
2320 #define list_offset_WORD word2
2321 #define next_offset_SHIFT 8
2322 #define next_offset_MASK 0x000000ff
2323 #define next_offset_WORD word2
2324 #define elem_cnt_SHIFT 16
2325 #define elem_cnt_MASK 0x000000ff
2326 #define elem_cnt_WORD word2
2328 #define pn_0_SHIFT 24
2329 #define pn_0_MASK 0x000000ff
2330 #define pn_0_WORD word3
2331 #define pn_1_SHIFT 16
2332 #define pn_1_MASK 0x000000ff
2333 #define pn_1_WORD word3
2334 #define pn_2_SHIFT 8
2335 #define pn_2_MASK 0x000000ff
2336 #define pn_2_WORD word3
2337 #define pn_3_SHIFT 0
2338 #define pn_3_MASK 0x000000ff
2339 #define pn_3_WORD word3
2341 #define pn_4_SHIFT 24
2342 #define pn_4_MASK 0x000000ff
2343 #define pn_4_WORD word4
2344 #define pn_5_SHIFT 16
2345 #define pn_5_MASK 0x000000ff
2346 #define pn_5_WORD word4
2347 #define pn_6_SHIFT 8
2348 #define pn_6_MASK 0x000000ff
2349 #define pn_6_WORD word4
2350 #define pn_7_SHIFT 0
2351 #define pn_7_MASK 0x000000ff
2352 #define pn_7_WORD word4
2354 #define LPFC_SUPP_PAGES 0
2355 #define LPFC_BLOCK_GUARD_PROFILES 1
2356 #define LPFC_SLI4_PARAMETERS 2
2359 struct lpfc_mbx_pc_sli4_params
{
2362 #define qs_MASK 0x00000001
2363 #define qs_WORD word1
2365 #define wr_MASK 0x00000001
2366 #define wr_WORD word1
2368 #define pf_MASK 0x000000ff
2369 #define pf_WORD word1
2370 #define cpn_SHIFT 16
2371 #define cpn_MASK 0x000000ff
2372 #define cpn_WORD word1
2374 #define if_type_SHIFT 0
2375 #define if_type_MASK 0x00000007
2376 #define if_type_WORD word2
2377 #define sli_rev_SHIFT 4
2378 #define sli_rev_MASK 0x0000000f
2379 #define sli_rev_WORD word2
2380 #define sli_family_SHIFT 8
2381 #define sli_family_MASK 0x000000ff
2382 #define sli_family_WORD word2
2383 #define featurelevel_1_SHIFT 16
2384 #define featurelevel_1_MASK 0x000000ff
2385 #define featurelevel_1_WORD word2
2386 #define featurelevel_2_SHIFT 24
2387 #define featurelevel_2_MASK 0x0000001f
2388 #define featurelevel_2_WORD word2
2390 #define fcoe_SHIFT 0
2391 #define fcoe_MASK 0x00000001
2392 #define fcoe_WORD word3
2394 #define fc_MASK 0x00000001
2395 #define fc_WORD word3
2397 #define nic_MASK 0x00000001
2398 #define nic_WORD word3
2399 #define iscsi_SHIFT 3
2400 #define iscsi_MASK 0x00000001
2401 #define iscsi_WORD word3
2402 #define rdma_SHIFT 4
2403 #define rdma_MASK 0x00000001
2404 #define rdma_WORD word3
2405 uint32_t sge_supp_len
;
2406 #define SLI4_PAGE_SIZE 4096
2408 #define if_page_sz_SHIFT 0
2409 #define if_page_sz_MASK 0x0000ffff
2410 #define if_page_sz_WORD word5
2411 #define loopbk_scope_SHIFT 24
2412 #define loopbk_scope_MASK 0x0000000f
2413 #define loopbk_scope_WORD word5
2414 #define rq_db_window_SHIFT 28
2415 #define rq_db_window_MASK 0x0000000f
2416 #define rq_db_window_WORD word5
2418 #define eq_pages_SHIFT 0
2419 #define eq_pages_MASK 0x0000000f
2420 #define eq_pages_WORD word6
2421 #define eqe_size_SHIFT 8
2422 #define eqe_size_MASK 0x000000ff
2423 #define eqe_size_WORD word6
2425 #define cq_pages_SHIFT 0
2426 #define cq_pages_MASK 0x0000000f
2427 #define cq_pages_WORD word7
2428 #define cqe_size_SHIFT 8
2429 #define cqe_size_MASK 0x000000ff
2430 #define cqe_size_WORD word7
2432 #define mq_pages_SHIFT 0
2433 #define mq_pages_MASK 0x0000000f
2434 #define mq_pages_WORD word8
2435 #define mqe_size_SHIFT 8
2436 #define mqe_size_MASK 0x000000ff
2437 #define mqe_size_WORD word8
2438 #define mq_elem_cnt_SHIFT 16
2439 #define mq_elem_cnt_MASK 0x000000ff
2440 #define mq_elem_cnt_WORD word8
2442 #define wq_pages_SHIFT 0
2443 #define wq_pages_MASK 0x0000ffff
2444 #define wq_pages_WORD word9
2445 #define wqe_size_SHIFT 8
2446 #define wqe_size_MASK 0x000000ff
2447 #define wqe_size_WORD word9
2449 #define rq_pages_SHIFT 0
2450 #define rq_pages_MASK 0x0000ffff
2451 #define rq_pages_WORD word10
2452 #define rqe_size_SHIFT 8
2453 #define rqe_size_MASK 0x000000ff
2454 #define rqe_size_WORD word10
2456 #define hdr_pages_SHIFT 0
2457 #define hdr_pages_MASK 0x0000000f
2458 #define hdr_pages_WORD word11
2459 #define hdr_size_SHIFT 8
2460 #define hdr_size_MASK 0x0000000f
2461 #define hdr_size_WORD word11
2462 #define hdr_pp_align_SHIFT 16
2463 #define hdr_pp_align_MASK 0x0000ffff
2464 #define hdr_pp_align_WORD word11
2466 #define sgl_pages_SHIFT 0
2467 #define sgl_pages_MASK 0x0000000f
2468 #define sgl_pages_WORD word12
2469 #define sgl_pp_align_SHIFT 16
2470 #define sgl_pp_align_MASK 0x0000ffff
2471 #define sgl_pp_align_WORD word12
2472 uint32_t rsvd_13_63
[51];
2474 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
2475 &(~((SLI4_PAGE_SIZE)-1)))
2477 struct lpfc_sli4_parameters
{
2479 #define cfg_prot_type_SHIFT 0
2480 #define cfg_prot_type_MASK 0x000000FF
2481 #define cfg_prot_type_WORD word0
2483 #define cfg_ft_SHIFT 0
2484 #define cfg_ft_MASK 0x00000001
2485 #define cfg_ft_WORD word1
2486 #define cfg_sli_rev_SHIFT 4
2487 #define cfg_sli_rev_MASK 0x0000000f
2488 #define cfg_sli_rev_WORD word1
2489 #define cfg_sli_family_SHIFT 8
2490 #define cfg_sli_family_MASK 0x0000000f
2491 #define cfg_sli_family_WORD word1
2492 #define cfg_if_type_SHIFT 12
2493 #define cfg_if_type_MASK 0x0000000f
2494 #define cfg_if_type_WORD word1
2495 #define cfg_sli_hint_1_SHIFT 16
2496 #define cfg_sli_hint_1_MASK 0x000000ff
2497 #define cfg_sli_hint_1_WORD word1
2498 #define cfg_sli_hint_2_SHIFT 24
2499 #define cfg_sli_hint_2_MASK 0x0000001f
2500 #define cfg_sli_hint_2_WORD word1
2504 #define cfg_cqv_SHIFT 14
2505 #define cfg_cqv_MASK 0x00000003
2506 #define cfg_cqv_WORD word4
2509 #define cfg_mqv_SHIFT 14
2510 #define cfg_mqv_MASK 0x00000003
2511 #define cfg_mqv_WORD word6
2514 #define cfg_wqv_SHIFT 14
2515 #define cfg_wqv_MASK 0x00000003
2516 #define cfg_wqv_WORD word8
2519 #define cfg_rqv_SHIFT 14
2520 #define cfg_rqv_MASK 0x00000003
2521 #define cfg_rqv_WORD word10
2523 #define cfg_rq_db_window_SHIFT 28
2524 #define cfg_rq_db_window_MASK 0x0000000f
2525 #define cfg_rq_db_window_WORD word11
2527 #define cfg_fcoe_SHIFT 0
2528 #define cfg_fcoe_MASK 0x00000001
2529 #define cfg_fcoe_WORD word12
2530 #define cfg_ext_SHIFT 1
2531 #define cfg_ext_MASK 0x00000001
2532 #define cfg_ext_WORD word12
2533 #define cfg_hdrr_SHIFT 2
2534 #define cfg_hdrr_MASK 0x00000001
2535 #define cfg_hdrr_WORD word12
2536 #define cfg_phwq_SHIFT 15
2537 #define cfg_phwq_MASK 0x00000001
2538 #define cfg_phwq_WORD word12
2539 #define cfg_loopbk_scope_SHIFT 28
2540 #define cfg_loopbk_scope_MASK 0x0000000f
2541 #define cfg_loopbk_scope_WORD word12
2542 uint32_t sge_supp_len
;
2544 #define cfg_sgl_page_cnt_SHIFT 0
2545 #define cfg_sgl_page_cnt_MASK 0x0000000f
2546 #define cfg_sgl_page_cnt_WORD word14
2547 #define cfg_sgl_page_size_SHIFT 8
2548 #define cfg_sgl_page_size_MASK 0x000000ff
2549 #define cfg_sgl_page_size_WORD word14
2550 #define cfg_sgl_pp_align_SHIFT 16
2551 #define cfg_sgl_pp_align_MASK 0x000000ff
2552 #define cfg_sgl_pp_align_WORD word14
2560 struct lpfc_mbx_get_sli4_parameters
{
2561 struct mbox_header header
;
2562 struct lpfc_sli4_parameters sli4_parameters
;
2565 struct lpfc_rscr_desc_generic
{
2566 #define LPFC_RSRC_DESC_WSIZE 18
2567 uint32_t desc
[LPFC_RSRC_DESC_WSIZE
];
2570 struct lpfc_rsrc_desc_pcie
{
2572 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
2573 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
2574 #define lpfc_rsrc_desc_pcie_type_WORD word0
2575 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
2577 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
2578 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
2579 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1
2582 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
2583 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
2584 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
2585 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
2586 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
2587 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
2588 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
2589 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
2590 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3
2592 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
2593 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
2594 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
2597 struct lpfc_rsrc_desc_fcfcoe
{
2599 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
2600 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
2601 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0
2602 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
2604 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
2605 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
2606 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
2607 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
2608 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
2609 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
2611 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
2612 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
2613 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
2614 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
2615 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
2616 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
2618 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
2619 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
2620 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
2621 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
2622 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
2623 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
2625 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
2626 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
2627 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
2628 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
2629 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
2630 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
2632 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
2633 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
2634 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
2635 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
2636 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
2637 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
2646 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
2647 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
2648 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
2649 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
2650 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
2651 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
2652 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
2653 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
2654 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
2655 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
2656 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
2657 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
2658 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
2659 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
2660 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
2663 struct lpfc_func_cfg
{
2664 #define LPFC_RSRC_DESC_MAX_NUM 2
2665 uint32_t rsrc_desc_count
;
2666 struct lpfc_rscr_desc_generic desc
[LPFC_RSRC_DESC_MAX_NUM
];
2669 struct lpfc_mbx_get_func_cfg
{
2670 struct mbox_header header
;
2671 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
2672 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
2673 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
2674 struct lpfc_func_cfg func_cfg
;
2677 struct lpfc_prof_cfg
{
2678 #define LPFC_RSRC_DESC_MAX_NUM 2
2679 uint32_t rsrc_desc_count
;
2680 struct lpfc_rscr_desc_generic desc
[LPFC_RSRC_DESC_MAX_NUM
];
2683 struct lpfc_mbx_get_prof_cfg
{
2684 struct mbox_header header
;
2685 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
2686 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
2687 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
2691 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
2692 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
2693 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
2694 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
2695 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
2696 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
2699 struct lpfc_prof_cfg prof_cfg
;
2704 struct lpfc_controller_attribute
{
2705 uint32_t version_string
[8];
2706 uint32_t manufacturer_name
[8];
2707 uint32_t supported_modes
;
2709 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
2710 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
2711 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17
2712 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8
2713 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
2714 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17
2715 uint32_t mbx_da_struct_ver
;
2716 uint32_t ep_fw_da_struct_ver
;
2717 uint32_t ncsi_ver_str
[3];
2718 uint32_t dflt_ext_timeout
;
2719 uint32_t model_number
[8];
2720 uint32_t description
[16];
2721 uint32_t serial_number
[8];
2722 uint32_t ip_ver_str
[8];
2723 uint32_t fw_ver_str
[8];
2724 uint32_t bios_ver_str
[8];
2725 uint32_t redboot_ver_str
[8];
2726 uint32_t driver_ver_str
[8];
2727 uint32_t flash_fw_ver_str
[8];
2728 uint32_t functionality
;
2730 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
2731 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
2732 #define lpfc_cntl_attr_max_cbd_len_WORD word105
2733 #define lpfc_cntl_attr_asic_rev_SHIFT 16
2734 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
2735 #define lpfc_cntl_attr_asic_rev_WORD word105
2736 #define lpfc_cntl_attr_gen_guid0_SHIFT 24
2737 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
2738 #define lpfc_cntl_attr_gen_guid0_WORD word105
2739 uint32_t gen_guid1_12
[3];
2741 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
2742 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
2743 #define lpfc_cntl_attr_gen_guid13_14_WORD word109
2744 #define lpfc_cntl_attr_gen_guid15_SHIFT 16
2745 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
2746 #define lpfc_cntl_attr_gen_guid15_WORD word109
2747 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
2748 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
2749 #define lpfc_cntl_attr_hba_port_cnt_WORD word109
2751 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
2752 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
2753 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110
2754 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24
2755 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
2756 #define lpfc_cntl_attr_multi_func_dev_WORD word110
2758 #define lpfc_cntl_attr_cache_valid_SHIFT 0
2759 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
2760 #define lpfc_cntl_attr_cache_valid_WORD word111
2761 #define lpfc_cntl_attr_hba_status_SHIFT 8
2762 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
2763 #define lpfc_cntl_attr_hba_status_WORD word111
2764 #define lpfc_cntl_attr_max_domain_SHIFT 16
2765 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
2766 #define lpfc_cntl_attr_max_domain_WORD word111
2767 #define lpfc_cntl_attr_lnk_numb_SHIFT 24
2768 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
2769 #define lpfc_cntl_attr_lnk_numb_WORD word111
2770 #define lpfc_cntl_attr_lnk_type_SHIFT 30
2771 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
2772 #define lpfc_cntl_attr_lnk_type_WORD word111
2773 uint32_t fw_post_status
;
2774 uint32_t hba_mtu
[8];
2776 uint32_t reserved1
[3];
2778 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
2779 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
2780 #define lpfc_cntl_attr_pci_vendor_id_WORD word125
2781 #define lpfc_cntl_attr_pci_device_id_SHIFT 16
2782 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
2783 #define lpfc_cntl_attr_pci_device_id_WORD word125
2785 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
2786 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
2787 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126
2788 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
2789 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
2790 #define lpfc_cntl_attr_pci_subsys_id_WORD word126
2792 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
2793 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
2794 #define lpfc_cntl_attr_pci_bus_num_WORD word127
2795 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8
2796 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
2797 #define lpfc_cntl_attr_pci_dev_num_WORD word127
2798 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
2799 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
2800 #define lpfc_cntl_attr_pci_fnc_num_WORD word127
2801 #define lpfc_cntl_attr_inf_type_SHIFT 24
2802 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
2803 #define lpfc_cntl_attr_inf_type_WORD word127
2804 uint32_t unique_id
[2];
2806 #define lpfc_cntl_attr_num_netfil_SHIFT 0
2807 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
2808 #define lpfc_cntl_attr_num_netfil_WORD word130
2809 uint32_t reserved2
[4];
2812 struct lpfc_mbx_get_cntl_attributes
{
2813 union lpfc_sli4_cfg_shdr cfg_shdr
;
2814 struct lpfc_controller_attribute cntl_attr
;
2817 struct lpfc_mbx_get_port_name
{
2818 struct mbox_header header
;
2822 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
2823 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
2824 #define lpfc_mbx_get_port_name_lnk_type_WORD word4
2828 #define lpfc_mbx_get_port_name_name0_SHIFT 0
2829 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
2830 #define lpfc_mbx_get_port_name_name0_WORD word4
2831 #define lpfc_mbx_get_port_name_name1_SHIFT 8
2832 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
2833 #define lpfc_mbx_get_port_name_name1_WORD word4
2834 #define lpfc_mbx_get_port_name_name2_SHIFT 16
2835 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
2836 #define lpfc_mbx_get_port_name_name2_WORD word4
2837 #define lpfc_mbx_get_port_name_name3_SHIFT 24
2838 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
2839 #define lpfc_mbx_get_port_name_name3_WORD word4
2840 #define LPFC_LINK_NUMBER_0 0
2841 #define LPFC_LINK_NUMBER_1 1
2842 #define LPFC_LINK_NUMBER_2 2
2843 #define LPFC_LINK_NUMBER_3 3
2848 /* Mailbox Completion Queue Error Messages */
2849 #define MB_CQE_STATUS_SUCCESS 0x0
2850 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
2851 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
2852 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
2853 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
2854 #define MB_CQE_STATUS_DMA_FAILED 0x5
2856 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8
2857 struct lpfc_mbx_wr_object
{
2858 struct mbox_header header
;
2862 #define lpfc_wr_object_eof_SHIFT 31
2863 #define lpfc_wr_object_eof_MASK 0x00000001
2864 #define lpfc_wr_object_eof_WORD word4
2865 #define lpfc_wr_object_write_length_SHIFT 0
2866 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
2867 #define lpfc_wr_object_write_length_WORD word4
2868 uint32_t write_offset
;
2869 uint32_t object_name
[26];
2871 struct ulp_bde64 bde
[LPFC_MBX_WR_CONFIG_MAX_BDE
];
2874 uint32_t actual_write_length
;
2879 /* mailbox queue entry structure */
2882 #define lpfc_mqe_status_SHIFT 16
2883 #define lpfc_mqe_status_MASK 0x0000FFFF
2884 #define lpfc_mqe_status_WORD word0
2885 #define lpfc_mqe_command_SHIFT 8
2886 #define lpfc_mqe_command_MASK 0x000000FF
2887 #define lpfc_mqe_command_WORD word0
2889 uint32_t mb_words
[LPFC_SLI4_MB_WORD_COUNT
- 1];
2890 /* sli4 mailbox commands */
2891 struct lpfc_mbx_sli4_config sli4_config
;
2892 struct lpfc_mbx_init_vfi init_vfi
;
2893 struct lpfc_mbx_reg_vfi reg_vfi
;
2894 struct lpfc_mbx_reg_vfi unreg_vfi
;
2895 struct lpfc_mbx_init_vpi init_vpi
;
2896 struct lpfc_mbx_resume_rpi resume_rpi
;
2897 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl
;
2898 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry
;
2899 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry
;
2900 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl
;
2901 struct lpfc_mbx_reg_fcfi reg_fcfi
;
2902 struct lpfc_mbx_unreg_fcfi unreg_fcfi
;
2903 struct lpfc_mbx_mq_create mq_create
;
2904 struct lpfc_mbx_mq_create_ext mq_create_ext
;
2905 struct lpfc_mbx_eq_create eq_create
;
2906 struct lpfc_mbx_modify_eq_delay eq_delay
;
2907 struct lpfc_mbx_cq_create cq_create
;
2908 struct lpfc_mbx_wq_create wq_create
;
2909 struct lpfc_mbx_rq_create rq_create
;
2910 struct lpfc_mbx_mq_destroy mq_destroy
;
2911 struct lpfc_mbx_eq_destroy eq_destroy
;
2912 struct lpfc_mbx_cq_destroy cq_destroy
;
2913 struct lpfc_mbx_wq_destroy wq_destroy
;
2914 struct lpfc_mbx_rq_destroy rq_destroy
;
2915 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info
;
2916 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents
;
2917 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents
;
2918 struct lpfc_mbx_post_sgl_pages post_sgl_pages
;
2919 struct lpfc_mbx_nembed_cmd nembed_cmd
;
2920 struct lpfc_mbx_read_rev read_rev
;
2921 struct lpfc_mbx_read_vpi read_vpi
;
2922 struct lpfc_mbx_read_config rd_config
;
2923 struct lpfc_mbx_request_features req_ftrs
;
2924 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl
;
2925 struct lpfc_mbx_query_fw_cfg query_fw_cfg
;
2926 struct lpfc_mbx_supp_pages supp_pages
;
2927 struct lpfc_mbx_pc_sli4_params sli4_params
;
2928 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters
;
2929 struct lpfc_mbx_set_link_diag_state link_diag_state
;
2930 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback
;
2931 struct lpfc_mbx_run_link_diag_test link_diag_test
;
2932 struct lpfc_mbx_get_func_cfg get_func_cfg
;
2933 struct lpfc_mbx_get_prof_cfg get_prof_cfg
;
2934 struct lpfc_mbx_wr_object wr_object
;
2935 struct lpfc_mbx_get_port_name get_port_name
;
2936 struct lpfc_mbx_nop nop
;
2942 #define lpfc_mcqe_status_SHIFT 0
2943 #define lpfc_mcqe_status_MASK 0x0000FFFF
2944 #define lpfc_mcqe_status_WORD word0
2945 #define lpfc_mcqe_ext_status_SHIFT 16
2946 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
2947 #define lpfc_mcqe_ext_status_WORD word0
2951 #define lpfc_trailer_valid_SHIFT 31
2952 #define lpfc_trailer_valid_MASK 0x00000001
2953 #define lpfc_trailer_valid_WORD trailer
2954 #define lpfc_trailer_async_SHIFT 30
2955 #define lpfc_trailer_async_MASK 0x00000001
2956 #define lpfc_trailer_async_WORD trailer
2957 #define lpfc_trailer_hpi_SHIFT 29
2958 #define lpfc_trailer_hpi_MASK 0x00000001
2959 #define lpfc_trailer_hpi_WORD trailer
2960 #define lpfc_trailer_completed_SHIFT 28
2961 #define lpfc_trailer_completed_MASK 0x00000001
2962 #define lpfc_trailer_completed_WORD trailer
2963 #define lpfc_trailer_consumed_SHIFT 27
2964 #define lpfc_trailer_consumed_MASK 0x00000001
2965 #define lpfc_trailer_consumed_WORD trailer
2966 #define lpfc_trailer_type_SHIFT 16
2967 #define lpfc_trailer_type_MASK 0x000000FF
2968 #define lpfc_trailer_type_WORD trailer
2969 #define lpfc_trailer_code_SHIFT 8
2970 #define lpfc_trailer_code_MASK 0x000000FF
2971 #define lpfc_trailer_code_WORD trailer
2972 #define LPFC_TRAILER_CODE_LINK 0x1
2973 #define LPFC_TRAILER_CODE_FCOE 0x2
2974 #define LPFC_TRAILER_CODE_DCBX 0x3
2975 #define LPFC_TRAILER_CODE_GRP5 0x5
2976 #define LPFC_TRAILER_CODE_FC 0x10
2977 #define LPFC_TRAILER_CODE_SLI 0x11
2980 struct lpfc_acqe_link
{
2982 #define lpfc_acqe_link_speed_SHIFT 24
2983 #define lpfc_acqe_link_speed_MASK 0x000000FF
2984 #define lpfc_acqe_link_speed_WORD word0
2985 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
2986 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
2987 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
2988 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
2989 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
2990 #define lpfc_acqe_link_duplex_SHIFT 16
2991 #define lpfc_acqe_link_duplex_MASK 0x000000FF
2992 #define lpfc_acqe_link_duplex_WORD word0
2993 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
2994 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
2995 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
2996 #define lpfc_acqe_link_status_SHIFT 8
2997 #define lpfc_acqe_link_status_MASK 0x000000FF
2998 #define lpfc_acqe_link_status_WORD word0
2999 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
3000 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
3001 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
3002 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
3003 #define lpfc_acqe_link_type_SHIFT 6
3004 #define lpfc_acqe_link_type_MASK 0x00000003
3005 #define lpfc_acqe_link_type_WORD word0
3006 #define lpfc_acqe_link_number_SHIFT 0
3007 #define lpfc_acqe_link_number_MASK 0x0000003F
3008 #define lpfc_acqe_link_number_WORD word0
3010 #define lpfc_acqe_link_fault_SHIFT 0
3011 #define lpfc_acqe_link_fault_MASK 0x000000FF
3012 #define lpfc_acqe_link_fault_WORD word1
3013 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
3014 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
3015 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
3016 #define lpfc_acqe_logical_link_speed_SHIFT 16
3017 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
3018 #define lpfc_acqe_logical_link_speed_WORD word1
3021 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
3022 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
3025 struct lpfc_acqe_fip
{
3028 #define lpfc_acqe_fip_fcf_count_SHIFT 0
3029 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3030 #define lpfc_acqe_fip_fcf_count_WORD word1
3031 #define lpfc_acqe_fip_event_type_SHIFT 16
3032 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3033 #define lpfc_acqe_fip_event_type_WORD word1
3036 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3037 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3038 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3039 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
3040 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3043 struct lpfc_acqe_dcbx
{
3050 struct lpfc_acqe_grp5
{
3052 #define lpfc_acqe_grp5_type_SHIFT 6
3053 #define lpfc_acqe_grp5_type_MASK 0x00000003
3054 #define lpfc_acqe_grp5_type_WORD word0
3055 #define lpfc_acqe_grp5_number_SHIFT 0
3056 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3057 #define lpfc_acqe_grp5_number_WORD word0
3059 #define lpfc_acqe_grp5_llink_spd_SHIFT 16
3060 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3061 #define lpfc_acqe_grp5_llink_spd_WORD word1
3066 struct lpfc_acqe_fc_la
{
3068 #define lpfc_acqe_fc_la_speed_SHIFT 24
3069 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3070 #define lpfc_acqe_fc_la_speed_WORD word0
3071 #define LPFC_FC_LA_SPEED_UNKOWN 0x0
3072 #define LPFC_FC_LA_SPEED_1G 0x1
3073 #define LPFC_FC_LA_SPEED_2G 0x2
3074 #define LPFC_FC_LA_SPEED_4G 0x4
3075 #define LPFC_FC_LA_SPEED_8G 0x8
3076 #define LPFC_FC_LA_SPEED_10G 0xA
3077 #define LPFC_FC_LA_SPEED_16G 0x10
3078 #define lpfc_acqe_fc_la_topology_SHIFT 16
3079 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3080 #define lpfc_acqe_fc_la_topology_WORD word0
3081 #define LPFC_FC_LA_TOP_UNKOWN 0x0
3082 #define LPFC_FC_LA_TOP_P2P 0x1
3083 #define LPFC_FC_LA_TOP_FCAL 0x2
3084 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3085 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3086 #define lpfc_acqe_fc_la_att_type_SHIFT 8
3087 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3088 #define lpfc_acqe_fc_la_att_type_WORD word0
3089 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
3090 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
3091 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
3092 #define lpfc_acqe_fc_la_port_type_SHIFT 6
3093 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
3094 #define lpfc_acqe_fc_la_port_type_WORD word0
3095 #define LPFC_LINK_TYPE_ETHERNET 0x0
3096 #define LPFC_LINK_TYPE_FC 0x1
3097 #define lpfc_acqe_fc_la_port_number_SHIFT 0
3098 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
3099 #define lpfc_acqe_fc_la_port_number_WORD word0
3101 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16
3102 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
3103 #define lpfc_acqe_fc_la_llink_spd_WORD word1
3104 #define lpfc_acqe_fc_la_fault_SHIFT 0
3105 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
3106 #define lpfc_acqe_fc_la_fault_WORD word1
3107 #define LPFC_FC_LA_FAULT_NONE 0x0
3108 #define LPFC_FC_LA_FAULT_LOCAL 0x1
3109 #define LPFC_FC_LA_FAULT_REMOTE 0x2
3112 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
3113 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
3116 struct lpfc_acqe_misconfigured_event
{
3119 #define lpfc_sli_misconfigured_port0_SHIFT 0
3120 #define lpfc_sli_misconfigured_port0_MASK 0x000000FF
3121 #define lpfc_sli_misconfigured_port0_WORD word0
3122 #define lpfc_sli_misconfigured_port1_SHIFT 8
3123 #define lpfc_sli_misconfigured_port1_MASK 0x000000FF
3124 #define lpfc_sli_misconfigured_port1_WORD word0
3125 #define lpfc_sli_misconfigured_port2_SHIFT 16
3126 #define lpfc_sli_misconfigured_port2_MASK 0x000000FF
3127 #define lpfc_sli_misconfigured_port2_WORD word0
3128 #define lpfc_sli_misconfigured_port3_SHIFT 24
3129 #define lpfc_sli_misconfigured_port3_MASK 0x000000FF
3130 #define lpfc_sli_misconfigured_port3_WORD word0
3132 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
3133 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
3134 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
3135 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
3138 struct lpfc_acqe_sli
{
3139 uint32_t event_data1
;
3140 uint32_t event_data2
;
3143 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
3144 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
3145 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
3146 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
3147 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
3148 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
3152 * Define the bootstrap mailbox (bmbx) region used to communicate
3153 * mailbox command between the host and port. The mailbox consists
3154 * of a payload area of 256 bytes and a completion queue of length
3157 struct lpfc_bmbx_create
{
3158 struct lpfc_mqe mqe
;
3159 struct lpfc_mcqe mcqe
;
3162 #define SGL_ALIGN_SZ 64
3163 #define SGL_PAGE_SIZE 4096
3164 /* align SGL addr on a size boundary - adjust address up */
3165 #define NO_XRI 0xffff
3169 #define wqe_xri_tag_SHIFT 0
3170 #define wqe_xri_tag_MASK 0x0000FFFF
3171 #define wqe_xri_tag_WORD word6
3172 #define wqe_ctxt_tag_SHIFT 16
3173 #define wqe_ctxt_tag_MASK 0x0000FFFF
3174 #define wqe_ctxt_tag_WORD word6
3176 #define wqe_dif_SHIFT 0
3177 #define wqe_dif_MASK 0x00000003
3178 #define wqe_dif_WORD word7
3179 #define wqe_ct_SHIFT 2
3180 #define wqe_ct_MASK 0x00000003
3181 #define wqe_ct_WORD word7
3182 #define wqe_status_SHIFT 4
3183 #define wqe_status_MASK 0x0000000f
3184 #define wqe_status_WORD word7
3185 #define wqe_cmnd_SHIFT 8
3186 #define wqe_cmnd_MASK 0x000000ff
3187 #define wqe_cmnd_WORD word7
3188 #define wqe_class_SHIFT 16
3189 #define wqe_class_MASK 0x00000007
3190 #define wqe_class_WORD word7
3191 #define wqe_ar_SHIFT 19
3192 #define wqe_ar_MASK 0x00000001
3193 #define wqe_ar_WORD word7
3194 #define wqe_ag_SHIFT wqe_ar_SHIFT
3195 #define wqe_ag_MASK wqe_ar_MASK
3196 #define wqe_ag_WORD wqe_ar_WORD
3197 #define wqe_pu_SHIFT 20
3198 #define wqe_pu_MASK 0x00000003
3199 #define wqe_pu_WORD word7
3200 #define wqe_erp_SHIFT 22
3201 #define wqe_erp_MASK 0x00000001
3202 #define wqe_erp_WORD word7
3203 #define wqe_conf_SHIFT wqe_erp_SHIFT
3204 #define wqe_conf_MASK wqe_erp_MASK
3205 #define wqe_conf_WORD wqe_erp_WORD
3206 #define wqe_lnk_SHIFT 23
3207 #define wqe_lnk_MASK 0x00000001
3208 #define wqe_lnk_WORD word7
3209 #define wqe_tmo_SHIFT 24
3210 #define wqe_tmo_MASK 0x000000ff
3211 #define wqe_tmo_WORD word7
3212 uint32_t abort_tag
; /* word 8 in WQE */
3214 #define wqe_reqtag_SHIFT 0
3215 #define wqe_reqtag_MASK 0x0000FFFF
3216 #define wqe_reqtag_WORD word9
3217 #define wqe_temp_rpi_SHIFT 16
3218 #define wqe_temp_rpi_MASK 0x0000FFFF
3219 #define wqe_temp_rpi_WORD word9
3220 #define wqe_rcvoxid_SHIFT 16
3221 #define wqe_rcvoxid_MASK 0x0000FFFF
3222 #define wqe_rcvoxid_WORD word9
3224 #define wqe_ebde_cnt_SHIFT 0
3225 #define wqe_ebde_cnt_MASK 0x0000000f
3226 #define wqe_ebde_cnt_WORD word10
3227 #define wqe_lenloc_SHIFT 7
3228 #define wqe_lenloc_MASK 0x00000003
3229 #define wqe_lenloc_WORD word10
3230 #define LPFC_WQE_LENLOC_NONE 0
3231 #define LPFC_WQE_LENLOC_WORD3 1
3232 #define LPFC_WQE_LENLOC_WORD12 2
3233 #define LPFC_WQE_LENLOC_WORD4 3
3234 #define wqe_qosd_SHIFT 9
3235 #define wqe_qosd_MASK 0x00000001
3236 #define wqe_qosd_WORD word10
3237 #define wqe_xbl_SHIFT 11
3238 #define wqe_xbl_MASK 0x00000001
3239 #define wqe_xbl_WORD word10
3240 #define wqe_iod_SHIFT 13
3241 #define wqe_iod_MASK 0x00000001
3242 #define wqe_iod_WORD word10
3243 #define LPFC_WQE_IOD_WRITE 0
3244 #define LPFC_WQE_IOD_READ 1
3245 #define wqe_dbde_SHIFT 14
3246 #define wqe_dbde_MASK 0x00000001
3247 #define wqe_dbde_WORD word10
3248 #define wqe_wqes_SHIFT 15
3249 #define wqe_wqes_MASK 0x00000001
3250 #define wqe_wqes_WORD word10
3251 /* Note that this field overlaps above fields */
3252 #define wqe_wqid_SHIFT 1
3253 #define wqe_wqid_MASK 0x00007fff
3254 #define wqe_wqid_WORD word10
3255 #define wqe_pri_SHIFT 16
3256 #define wqe_pri_MASK 0x00000007
3257 #define wqe_pri_WORD word10
3258 #define wqe_pv_SHIFT 19
3259 #define wqe_pv_MASK 0x00000001
3260 #define wqe_pv_WORD word10
3261 #define wqe_xc_SHIFT 21
3262 #define wqe_xc_MASK 0x00000001
3263 #define wqe_xc_WORD word10
3264 #define wqe_sr_SHIFT 22
3265 #define wqe_sr_MASK 0x00000001
3266 #define wqe_sr_WORD word10
3267 #define wqe_ccpe_SHIFT 23
3268 #define wqe_ccpe_MASK 0x00000001
3269 #define wqe_ccpe_WORD word10
3270 #define wqe_ccp_SHIFT 24
3271 #define wqe_ccp_MASK 0x000000ff
3272 #define wqe_ccp_WORD word10
3274 #define wqe_cmd_type_SHIFT 0
3275 #define wqe_cmd_type_MASK 0x0000000f
3276 #define wqe_cmd_type_WORD word11
3277 #define wqe_els_id_SHIFT 4
3278 #define wqe_els_id_MASK 0x00000003
3279 #define wqe_els_id_WORD word11
3280 #define LPFC_ELS_ID_FLOGI 3
3281 #define LPFC_ELS_ID_FDISC 2
3282 #define LPFC_ELS_ID_LOGO 1
3283 #define LPFC_ELS_ID_DEFAULT 0
3284 #define wqe_wqec_SHIFT 7
3285 #define wqe_wqec_MASK 0x00000001
3286 #define wqe_wqec_WORD word11
3287 #define wqe_cqid_SHIFT 16
3288 #define wqe_cqid_MASK 0x0000ffff
3289 #define wqe_cqid_WORD word11
3290 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
3295 #define wqe_els_did_SHIFT 0
3296 #define wqe_els_did_MASK 0x00FFFFFF
3297 #define wqe_els_did_WORD word5
3298 #define wqe_xmit_bls_pt_SHIFT 28
3299 #define wqe_xmit_bls_pt_MASK 0x00000003
3300 #define wqe_xmit_bls_pt_WORD word5
3301 #define wqe_xmit_bls_ar_SHIFT 30
3302 #define wqe_xmit_bls_ar_MASK 0x00000001
3303 #define wqe_xmit_bls_ar_WORD word5
3304 #define wqe_xmit_bls_xo_SHIFT 31
3305 #define wqe_xmit_bls_xo_MASK 0x00000001
3306 #define wqe_xmit_bls_xo_WORD word5
3309 struct lpfc_wqe_generic
{
3310 struct ulp_bde64 bde
;
3314 struct wqe_common wqe_com
;
3315 uint32_t payload
[4];
3318 struct els_request64_wqe
{
3319 struct ulp_bde64 bde
;
3320 uint32_t payload_len
;
3322 #define els_req64_sid_SHIFT 0
3323 #define els_req64_sid_MASK 0x00FFFFFF
3324 #define els_req64_sid_WORD word4
3325 #define els_req64_sp_SHIFT 24
3326 #define els_req64_sp_MASK 0x00000001
3327 #define els_req64_sp_WORD word4
3328 #define els_req64_vf_SHIFT 25
3329 #define els_req64_vf_MASK 0x00000001
3330 #define els_req64_vf_WORD word4
3331 struct wqe_did wqe_dest
;
3332 struct wqe_common wqe_com
; /* words 6-11 */
3334 #define els_req64_vfid_SHIFT 1
3335 #define els_req64_vfid_MASK 0x00000FFF
3336 #define els_req64_vfid_WORD word12
3337 #define els_req64_pri_SHIFT 13
3338 #define els_req64_pri_MASK 0x00000007
3339 #define els_req64_pri_WORD word12
3341 #define els_req64_hopcnt_SHIFT 24
3342 #define els_req64_hopcnt_MASK 0x000000ff
3343 #define els_req64_hopcnt_WORD word13
3344 uint32_t reserved
[2];
3347 struct xmit_els_rsp64_wqe
{
3348 struct ulp_bde64 bde
;
3349 uint32_t response_payload_len
;
3351 #define els_rsp64_sid_SHIFT 0
3352 #define els_rsp64_sid_MASK 0x00FFFFFF
3353 #define els_rsp64_sid_WORD word4
3354 #define els_rsp64_sp_SHIFT 24
3355 #define els_rsp64_sp_MASK 0x00000001
3356 #define els_rsp64_sp_WORD word4
3357 struct wqe_did wqe_dest
;
3358 struct wqe_common wqe_com
; /* words 6-11 */
3360 #define wqe_rsp_temp_rpi_SHIFT 0
3361 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
3362 #define wqe_rsp_temp_rpi_WORD word12
3363 uint32_t rsvd_13_15
[3];
3366 struct xmit_bls_rsp64_wqe
{
3368 /* Payload0 for BA_ACC */
3369 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16
3370 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
3371 #define xmit_bls_rsp64_acc_seq_id_WORD payload0
3372 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
3373 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
3374 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
3375 /* Payload0 for BA_RJT */
3376 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
3377 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
3378 #define xmit_bls_rsp64_rjt_vspec_WORD payload0
3379 #define xmit_bls_rsp64_rjt_expc_SHIFT 8
3380 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
3381 #define xmit_bls_rsp64_rjt_expc_WORD payload0
3382 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
3383 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
3384 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0
3386 #define xmit_bls_rsp64_rxid_SHIFT 0
3387 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
3388 #define xmit_bls_rsp64_rxid_WORD word1
3389 #define xmit_bls_rsp64_oxid_SHIFT 16
3390 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
3391 #define xmit_bls_rsp64_oxid_WORD word1
3393 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
3394 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
3395 #define xmit_bls_rsp64_seqcnthi_WORD word2
3396 #define xmit_bls_rsp64_seqcntlo_SHIFT 16
3397 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
3398 #define xmit_bls_rsp64_seqcntlo_WORD word2
3401 struct wqe_did wqe_dest
;
3402 struct wqe_common wqe_com
; /* words 6-11 */
3404 #define xmit_bls_rsp64_temprpi_SHIFT 0
3405 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
3406 #define xmit_bls_rsp64_temprpi_WORD word12
3407 uint32_t rsvd_13_15
[3];
3410 struct wqe_rctl_dfctl
{
3412 #define wqe_si_SHIFT 2
3413 #define wqe_si_MASK 0x000000001
3414 #define wqe_si_WORD word5
3415 #define wqe_la_SHIFT 3
3416 #define wqe_la_MASK 0x000000001
3417 #define wqe_la_WORD word5
3418 #define wqe_xo_SHIFT 6
3419 #define wqe_xo_MASK 0x000000001
3420 #define wqe_xo_WORD word5
3421 #define wqe_ls_SHIFT 7
3422 #define wqe_ls_MASK 0x000000001
3423 #define wqe_ls_WORD word5
3424 #define wqe_dfctl_SHIFT 8
3425 #define wqe_dfctl_MASK 0x0000000ff
3426 #define wqe_dfctl_WORD word5
3427 #define wqe_type_SHIFT 16
3428 #define wqe_type_MASK 0x0000000ff
3429 #define wqe_type_WORD word5
3430 #define wqe_rctl_SHIFT 24
3431 #define wqe_rctl_MASK 0x0000000ff
3432 #define wqe_rctl_WORD word5
3435 struct xmit_seq64_wqe
{
3436 struct ulp_bde64 bde
;
3438 uint32_t relative_offset
;
3439 struct wqe_rctl_dfctl wge_ctl
;
3440 struct wqe_common wqe_com
; /* words 6-11 */
3442 uint32_t rsvd_12_15
[3];
3444 struct xmit_bcast64_wqe
{
3445 struct ulp_bde64 bde
;
3446 uint32_t seq_payload_len
;
3448 struct wqe_rctl_dfctl wge_ctl
; /* word 5 */
3449 struct wqe_common wqe_com
; /* words 6-11 */
3450 uint32_t rsvd_12_15
[4];
3453 struct gen_req64_wqe
{
3454 struct ulp_bde64 bde
;
3455 uint32_t request_payload_len
;
3456 uint32_t relative_offset
;
3457 struct wqe_rctl_dfctl wge_ctl
; /* word 5 */
3458 struct wqe_common wqe_com
; /* words 6-11 */
3459 uint32_t rsvd_12_15
[4];
3462 struct create_xri_wqe
{
3463 uint32_t rsrvd
[5]; /* words 0-4 */
3464 struct wqe_did wqe_dest
; /* word 5 */
3465 struct wqe_common wqe_com
; /* words 6-11 */
3466 uint32_t rsvd_12_15
[4]; /* word 12-15 */
3469 #define T_REQUEST_TAG 3
3472 struct abort_cmd_wqe
{
3475 #define abort_cmd_ia_SHIFT 0
3476 #define abort_cmd_ia_MASK 0x000000001
3477 #define abort_cmd_ia_WORD word3
3478 #define abort_cmd_criteria_SHIFT 8
3479 #define abort_cmd_criteria_MASK 0x0000000ff
3480 #define abort_cmd_criteria_WORD word3
3483 struct wqe_common wqe_com
; /* words 6-11 */
3484 uint32_t rsvd_12_15
[4]; /* word 12-15 */
3487 struct fcp_iwrite64_wqe
{
3488 struct ulp_bde64 bde
;
3489 uint32_t payload_offset_len
;
3490 uint32_t total_xfer_len
;
3491 uint32_t initial_xfer_len
;
3492 struct wqe_common wqe_com
; /* words 6-11 */
3494 struct ulp_bde64 ph_bde
; /* words 13-15 */
3497 struct fcp_iread64_wqe
{
3498 struct ulp_bde64 bde
;
3499 uint32_t payload_offset_len
; /* word 3 */
3500 uint32_t total_xfer_len
; /* word 4 */
3501 uint32_t rsrvd5
; /* word 5 */
3502 struct wqe_common wqe_com
; /* words 6-11 */
3504 struct ulp_bde64 ph_bde
; /* words 13-15 */
3507 struct fcp_icmnd64_wqe
{
3508 struct ulp_bde64 bde
; /* words 0-2 */
3509 uint32_t rsrvd3
; /* word 3 */
3510 uint32_t rsrvd4
; /* word 4 */
3511 uint32_t rsrvd5
; /* word 5 */
3512 struct wqe_common wqe_com
; /* words 6-11 */
3513 uint32_t rsvd_12_15
[4]; /* word 12-15 */
3519 struct lpfc_wqe_generic generic
;
3520 struct fcp_icmnd64_wqe fcp_icmd
;
3521 struct fcp_iread64_wqe fcp_iread
;
3522 struct fcp_iwrite64_wqe fcp_iwrite
;
3523 struct abort_cmd_wqe abort_cmd
;
3524 struct create_xri_wqe create_xri
;
3525 struct xmit_bcast64_wqe xmit_bcast64
;
3526 struct xmit_seq64_wqe xmit_sequence
;
3527 struct xmit_bls_rsp64_wqe xmit_bls_rsp
;
3528 struct xmit_els_rsp64_wqe xmit_els_rsp
;
3529 struct els_request64_wqe els_req
;
3530 struct gen_req64_wqe gen_req
;
3533 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001
3534 #define LPFC_FILE_TYPE_GROUP 0xf7
3535 #define LPFC_FILE_ID_GROUP 0xa2
3536 struct lpfc_grp_hdr
{
3538 uint32_t magic_number
;
3540 #define lpfc_grp_hdr_file_type_SHIFT 24
3541 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
3542 #define lpfc_grp_hdr_file_type_WORD word2
3543 #define lpfc_grp_hdr_id_SHIFT 16
3544 #define lpfc_grp_hdr_id_MASK 0x000000FF
3545 #define lpfc_grp_hdr_id_WORD word2
3546 uint8_t rev_name
[128];
3548 uint8_t revision
[32];
3551 #define FCP_COMMAND 0x0
3552 #define FCP_COMMAND_DATA_OUT 0x1
3553 #define ELS_COMMAND_NON_FIP 0xC
3554 #define ELS_COMMAND_FIP 0xD
3555 #define OTHER_COMMAND 0x8
3557 #define LPFC_FW_DUMP 1
3558 #define LPFC_FW_RESET 2
3559 #define LPFC_DV_RESET 3