2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base
= 0;
35 unsigned long pci_dram_offset
= 0;
36 int pcibios_assign_bus_offset
= 1;
38 /* Default PCI flags is 0 */
39 unsigned int ppc_pci_flags
;
41 void pcibios_make_OF_bus_map(void);
43 static void fixup_broken_pcnet32(struct pci_dev
* dev
);
44 static int reparent_resources(struct resource
*parent
, struct resource
*res
);
45 static void fixup_cpc710_pci64(struct pci_dev
* dev
);
47 static u8
* pci_to_OF_bus_map
;
50 /* By default, we don't re-assign bus numbers. We do this only on
53 static int pci_assign_all_buses
;
57 static int pci_bus_count
;
60 fixup_hide_host_resource_fsl(struct pci_dev
* dev
)
62 int i
, class = dev
->class >> 8;
64 if ((class == PCI_CLASS_PROCESSOR_POWERPC
) &&
65 (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) &&
66 (dev
->bus
->parent
== NULL
)) {
67 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
68 dev
->resource
[i
].start
= 0;
69 dev
->resource
[i
].end
= 0;
70 dev
->resource
[i
].flags
= 0;
74 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
78 fixup_broken_pcnet32(struct pci_dev
* dev
)
80 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
81 dev
->vendor
= PCI_VENDOR_ID_AMD
;
82 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
85 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
88 fixup_cpc710_pci64(struct pci_dev
* dev
)
90 /* Hide the PCI64 BARs from the kernel as their content doesn't
91 * fit well in the resource management
93 dev
->resource
[0].start
= dev
->resource
[0].end
= 0;
94 dev
->resource
[0].flags
= 0;
95 dev
->resource
[1].start
= dev
->resource
[1].end
= 0;
96 dev
->resource
[1].flags
= 0;
98 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CPC710_PCI64
, fixup_cpc710_pci64
);
100 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
102 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
103 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
109 * We need to avoid collisions with `mirrored' VGA ports
110 * and other strange ISA hardware, so we always want the
111 * addresses to be allocated in the 0x000-0x0ff region
114 * Why? Because some silly external IO cards only decode
115 * the low 10 bits of the IO address. The 0x00-0xff region
116 * is reserved for motherboard devices that decode all 16
117 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
118 * but we want to try to avoid allocating at 0x2900-0x2bff
119 * which might have be mirrored at 0x0100-0x03ff..
121 void pcibios_align_resource(void *data
, struct resource
*res
,
122 resource_size_t size
, resource_size_t align
)
124 struct pci_dev
*dev
= data
;
126 if (res
->flags
& IORESOURCE_IO
) {
127 resource_size_t start
= res
->start
;
129 if (skip_isa_ioresource_align(dev
))
132 start
= (start
+ 0x3ff) & ~0x3ff;
137 EXPORT_SYMBOL(pcibios_align_resource
);
140 * Handle resources of PCI devices. If the world were perfect, we could
141 * just allocate all the resource regions and do nothing more. It isn't.
142 * On the other hand, we cannot just re-allocate all devices, as it would
143 * require us to know lots of host bridge internals. So we attempt to
144 * keep as much of the original configuration as possible, but tweak it
145 * when it's found to be wrong.
147 * Known BIOS problems we have to work around:
148 * - I/O or memory regions not configured
149 * - regions configured, but not enabled in the command register
150 * - bogus I/O addresses above 64K used
151 * - expansion ROMs left enabled (this may sound harmless, but given
152 * the fact the PCI specs explicitly allow address decoders to be
153 * shared between expansion ROMs and other resource regions, it's
154 * at least dangerous)
157 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
158 * This gives us fixed barriers on where we can allocate.
159 * (2) Allocate resources for all enabled devices. If there is
160 * a collision, just mark the resource as unallocated. Also
161 * disable expansion ROMs during this step.
162 * (3) Try to allocate resources for disabled devices. If the
163 * resources were assigned correctly, everything goes well,
164 * if they weren't, they won't disturb allocation of other
166 * (4) Assign new addresses to resources which were either
167 * not configured at all or misconfigured. If explicitly
168 * requested by the user, configure expansion ROM address
173 pcibios_allocate_bus_resources(struct list_head
*bus_list
)
177 struct resource
*res
, *pr
;
179 /* Depth-First Search on bus tree */
180 list_for_each_entry(bus
, bus_list
, node
) {
181 for (i
= 0; i
< 4; ++i
) {
182 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
183 || res
->start
> res
->end
)
185 if (bus
->parent
== NULL
)
186 pr
= (res
->flags
& IORESOURCE_IO
)?
187 &ioport_resource
: &iomem_resource
;
189 /* Don't bother with non-root busses when
190 * re-assigning all resources.
192 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
194 pr
= pci_find_parent_resource(bus
->self
, res
);
196 /* this happens when the generic PCI
197 * code (wrongly) decides that this
198 * bridge is transparent -- paulus
204 DBG("PCI: dev %s (bus 0x%02x) bridge rsrc %d: %016llx..%016llx "
205 "(f:0x%08lx), parent %p\n",
206 bus
->self
? pci_name(bus
->self
) : "PHB", bus
->number
, i
,
207 (u64
)res
->start
, (u64
)res
->end
, res
->flags
, pr
);
209 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
210 if (request_resource(pr
, res
) == 0)
213 * Must be a conflict with an existing entry.
214 * Move that entry (or entries) under the
215 * bridge resource and try again.
217 if (reparent_resources(pr
, res
) == 0)
221 "PCI: Cannot allocate resource region "
222 "%d of PCI bridge %d, will remap\n",
224 res
->flags
|= IORESOURCE_UNSET
;
226 pcibios_allocate_bus_resources(&bus
->children
);
231 * Reparent resource children of pr that conflict with res
232 * under res, and make res replace those children.
235 reparent_resources(struct resource
*parent
, struct resource
*res
)
237 struct resource
*p
, **pp
;
238 struct resource
**firstpp
= NULL
;
240 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
241 if (p
->end
< res
->start
)
243 if (res
->end
< p
->start
)
245 if (p
->start
< res
->start
|| p
->end
> res
->end
)
246 return -1; /* not completely contained */
251 return -1; /* didn't find any conflicting entries? */
252 res
->parent
= parent
;
253 res
->child
= *firstpp
;
257 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
259 DBG(KERN_INFO
"PCI: reparented %s [%llx..%llx] under %s\n",
260 p
->name
, (u64
)p
->start
, (u64
)p
->end
, res
->name
);
266 update_bridge_resource(struct pci_dev
*dev
, struct resource
*res
)
268 u8 io_base_lo
, io_limit_lo
;
269 u16 mem_base
, mem_limit
;
271 resource_size_t start
, end
, off
;
272 struct pci_controller
*hose
= dev
->sysdata
;
275 printk("update_bridge_base: no hose?\n");
278 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
279 pci_write_config_word(dev
, PCI_COMMAND
,
280 cmd
& ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
));
281 if (res
->flags
& IORESOURCE_IO
) {
282 off
= (unsigned long) hose
->io_base_virt
- isa_io_base
;
283 start
= res
->start
- off
;
284 end
= res
->end
- off
;
285 io_base_lo
= (start
>> 8) & PCI_IO_RANGE_MASK
;
286 io_limit_lo
= (end
>> 8) & PCI_IO_RANGE_MASK
;
288 io_base_lo
|= PCI_IO_RANGE_TYPE_32
;
290 io_base_lo
|= PCI_IO_RANGE_TYPE_16
;
291 pci_write_config_word(dev
, PCI_IO_BASE_UPPER16
,
293 pci_write_config_word(dev
, PCI_IO_LIMIT_UPPER16
,
295 pci_write_config_byte(dev
, PCI_IO_BASE
, io_base_lo
);
296 pci_write_config_byte(dev
, PCI_IO_LIMIT
, io_limit_lo
);
298 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
300 off
= hose
->pci_mem_offset
;
301 mem_base
= ((res
->start
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
302 mem_limit
= ((res
->end
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
303 pci_write_config_word(dev
, PCI_MEMORY_BASE
, mem_base
);
304 pci_write_config_word(dev
, PCI_MEMORY_LIMIT
, mem_limit
);
306 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
307 == (IORESOURCE_MEM
| IORESOURCE_PREFETCH
)) {
308 off
= hose
->pci_mem_offset
;
309 mem_base
= ((res
->start
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
310 mem_limit
= ((res
->end
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
311 pci_write_config_word(dev
, PCI_PREF_MEMORY_BASE
, mem_base
);
312 pci_write_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, mem_limit
);
315 DBG(KERN_ERR
"PCI: ugh, bridge %s res has flags=%lx\n",
316 pci_name(dev
), res
->flags
);
318 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
321 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
323 struct resource
*pr
, *r
= &dev
->resource
[idx
];
325 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx (f=%lx)\n",
326 pci_name(dev
), idx
, (u64
)r
->start
, (u64
)r
->end
, r
->flags
);
327 pr
= pci_find_parent_resource(dev
, r
);
328 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) || request_resource(pr
, r
) < 0) {
329 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
330 " of device %s, will remap\n", idx
, pci_name(dev
));
332 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
333 pr
, (u64
)pr
->start
, (u64
)pr
->end
, pr
->flags
);
334 /* We'll assign a new address later */
335 r
->flags
|= IORESOURCE_UNSET
;
342 pcibios_allocate_resources(int pass
)
344 struct pci_dev
*dev
= NULL
;
349 for_each_pci_dev(dev
) {
350 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
351 for (idx
= 0; idx
< 6; idx
++) {
352 r
= &dev
->resource
[idx
];
353 if (r
->parent
) /* Already allocated */
355 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
356 continue; /* Not assigned at all */
357 if (r
->flags
& IORESOURCE_IO
)
358 disabled
= !(command
& PCI_COMMAND_IO
);
360 disabled
= !(command
& PCI_COMMAND_MEMORY
);
361 if (pass
== disabled
)
362 alloc_resource(dev
, idx
);
366 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
367 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
368 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
370 DBG("PCI: Switching off ROM of %s\n", pci_name(dev
));
371 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
372 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
373 pci_write_config_dword(dev
, dev
->rom_base_reg
,
374 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
381 * Functions below are used on OpenFirmware machines.
384 make_one_node_map(struct device_node
* node
, u8 pci_bus
)
386 const int *bus_range
;
389 if (pci_bus
>= pci_bus_count
)
391 bus_range
= of_get_property(node
, "bus-range", &len
);
392 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
393 printk(KERN_WARNING
"Can't get bus-range for %s, "
394 "assuming it starts at 0\n", node
->full_name
);
395 pci_to_OF_bus_map
[pci_bus
] = 0;
397 pci_to_OF_bus_map
[pci_bus
] = bus_range
[0];
399 for (node
=node
->child
; node
!= 0;node
= node
->sibling
) {
401 const unsigned int *class_code
, *reg
;
403 class_code
= of_get_property(node
, "class-code", NULL
);
404 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
405 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
407 reg
= of_get_property(node
, "reg", NULL
);
410 dev
= pci_get_bus_and_slot(pci_bus
, ((reg
[0] >> 8) & 0xff));
411 if (!dev
|| !dev
->subordinate
) {
415 make_one_node_map(node
, dev
->subordinate
->number
);
421 pcibios_make_OF_bus_map(void)
424 struct pci_controller
*hose
, *tmp
;
425 struct property
*map_prop
;
426 struct device_node
*dn
;
428 pci_to_OF_bus_map
= kmalloc(pci_bus_count
, GFP_KERNEL
);
429 if (!pci_to_OF_bus_map
) {
430 printk(KERN_ERR
"Can't allocate OF bus map !\n");
434 /* We fill the bus map with invalid values, that helps
437 for (i
=0; i
<pci_bus_count
; i
++)
438 pci_to_OF_bus_map
[i
] = 0xff;
440 /* For each hose, we begin searching bridges */
441 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
442 struct device_node
* node
= hose
->dn
;
446 make_one_node_map(node
, hose
->first_busno
);
448 dn
= of_find_node_by_path("/");
449 map_prop
= of_find_property(dn
, "pci-OF-bus-map", NULL
);
451 BUG_ON(pci_bus_count
> map_prop
->length
);
452 memcpy(map_prop
->value
, pci_to_OF_bus_map
, pci_bus_count
);
456 printk("PCI->OF bus map:\n");
457 for (i
=0; i
<pci_bus_count
; i
++) {
458 if (pci_to_OF_bus_map
[i
] == 0xff)
460 printk("%d -> %d\n", i
, pci_to_OF_bus_map
[i
]);
465 typedef int (*pci_OF_scan_iterator
)(struct device_node
* node
, void* data
);
467 static struct device_node
*
468 scan_OF_pci_childs(struct device_node
* node
, pci_OF_scan_iterator filter
, void* data
)
470 struct device_node
* sub_node
;
472 for (; node
!= 0;node
= node
->sibling
) {
473 const unsigned int *class_code
;
475 if (filter(node
, data
))
478 /* For PCI<->PCI bridges or CardBus bridges, we go down
479 * Note: some OFs create a parent node "multifunc-device" as
480 * a fake root for all functions of a multi-function device,
481 * we go down them as well.
483 class_code
= of_get_property(node
, "class-code", NULL
);
484 if ((!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
485 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
)) &&
486 strcmp(node
->name
, "multifunc-device"))
488 sub_node
= scan_OF_pci_childs(node
->child
, filter
, data
);
495 static struct device_node
*scan_OF_for_pci_dev(struct device_node
*parent
,
498 struct device_node
*np
= NULL
;
502 while ((np
= of_get_next_child(parent
, np
)) != NULL
) {
503 reg
= of_get_property(np
, "reg", &psize
);
504 if (reg
== NULL
|| psize
< 4)
506 if (((reg
[0] >> 8) & 0xff) == devfn
)
513 static struct device_node
*scan_OF_for_pci_bus(struct pci_bus
*bus
)
515 struct device_node
*parent
, *np
;
517 /* Are we a root bus ? */
518 if (bus
->self
== NULL
|| bus
->parent
== NULL
) {
519 struct pci_controller
*hose
= pci_bus_to_host(bus
);
522 return of_node_get(hose
->dn
);
525 /* not a root bus, we need to get our parent */
526 parent
= scan_OF_for_pci_bus(bus
->parent
);
530 /* now iterate for children for a match */
531 np
= scan_OF_for_pci_dev(parent
, bus
->self
->devfn
);
538 * Scans the OF tree for a device node matching a PCI device
541 pci_busdev_to_OF_node(struct pci_bus
*bus
, int devfn
)
543 struct device_node
*parent
, *np
;
548 DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus
->number
, devfn
);
549 parent
= scan_OF_for_pci_bus(bus
);
552 DBG(" parent is %s\n", parent
? parent
->full_name
: "<NULL>");
553 np
= scan_OF_for_pci_dev(parent
, devfn
);
555 DBG(" result is %s\n", np
? np
->full_name
: "<NULL>");
557 /* XXX most callers don't release the returned node
558 * mostly because ppc64 doesn't increase the refcount,
559 * we need to fix that.
563 EXPORT_SYMBOL(pci_busdev_to_OF_node
);
566 pci_device_to_OF_node(struct pci_dev
*dev
)
568 return pci_busdev_to_OF_node(dev
->bus
, dev
->devfn
);
570 EXPORT_SYMBOL(pci_device_to_OF_node
);
573 find_OF_pci_device_filter(struct device_node
* node
, void* data
)
575 return ((void *)node
== data
);
579 * Returns the PCI device matching a given OF node
582 pci_device_from_OF_node(struct device_node
* node
, u8
* bus
, u8
* devfn
)
584 const unsigned int *reg
;
585 struct pci_controller
* hose
;
586 struct pci_dev
* dev
= NULL
;
590 /* Make sure it's really a PCI device */
591 hose
= pci_find_hose_for_OF_device(node
);
592 if (!hose
|| !hose
->dn
)
594 if (!scan_OF_pci_childs(hose
->dn
->child
,
595 find_OF_pci_device_filter
, (void *)node
))
597 reg
= of_get_property(node
, "reg", NULL
);
600 *bus
= (reg
[0] >> 16) & 0xff;
601 *devfn
= ((reg
[0] >> 8) & 0xff);
603 /* Ok, here we need some tweak. If we have already renumbered
604 * all busses, we can't rely on the OF bus number any more.
605 * the pci_to_OF_bus_map is not enough as several PCI busses
606 * may match the same OF bus number.
608 if (!pci_to_OF_bus_map
)
611 for_each_pci_dev(dev
)
612 if (pci_to_OF_bus_map
[dev
->bus
->number
] == *bus
&&
613 dev
->devfn
== *devfn
) {
614 *bus
= dev
->bus
->number
;
621 EXPORT_SYMBOL(pci_device_from_OF_node
);
623 /* We create the "pci-OF-bus-map" property now so it appears in the
627 pci_create_OF_bus_map(void)
629 struct property
* of_prop
;
630 struct device_node
*dn
;
632 of_prop
= (struct property
*) alloc_bootmem(sizeof(struct property
) + 256);
635 dn
= of_find_node_by_path("/");
637 memset(of_prop
, -1, sizeof(struct property
) + 256);
638 of_prop
->name
= "pci-OF-bus-map";
639 of_prop
->length
= 256;
640 of_prop
->value
= &of_prop
[1];
641 prom_add_property(dn
, of_prop
);
646 #else /* CONFIG_PPC_OF */
647 void pcibios_make_OF_bus_map(void)
650 #endif /* CONFIG_PPC_OF */
655 struct pci_controller
*hose
, *tmp
;
659 printk(KERN_INFO
"PCI: Probing PCI hardware\n");
661 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_BUS
)
662 pci_assign_all_buses
= 1;
664 /* Scan all of the recorded PCI controllers. */
665 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
666 if (pci_assign_all_buses
)
667 hose
->first_busno
= next_busno
;
668 hose
->last_busno
= 0xff;
669 bus
= pci_scan_bus_parented(hose
->parent
, hose
->first_busno
,
672 pci_bus_add_devices(bus
);
673 hose
->last_busno
= bus
->subordinate
;
674 if (pci_assign_all_buses
|| next_busno
<= hose
->last_busno
)
675 next_busno
= hose
->last_busno
+ pcibios_assign_bus_offset
;
677 pci_bus_count
= next_busno
;
679 /* OpenFirmware based machines need a map of OF bus
680 * numbers vs. kernel bus numbers since we may have to
683 if (pci_assign_all_buses
&& have_of
)
684 pcibios_make_OF_bus_map();
686 /* Call machine dependent fixup */
687 if (ppc_md
.pcibios_fixup
)
688 ppc_md
.pcibios_fixup();
690 /* Allocate and assign resources. If we re-assign everything, then
691 * we skip the allocate phase
693 pcibios_allocate_bus_resources(&pci_root_buses
);
694 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
695 pcibios_allocate_resources(0);
696 pcibios_allocate_resources(1);
698 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
699 DBG("PCI: Assigning unassigned resouces...\n");
700 pci_assign_unassigned_resources();
703 /* Call machine dependent post-init code */
704 if (ppc_md
.pcibios_after_init
)
705 ppc_md
.pcibios_after_init();
710 subsys_initcall(pcibios_init
);
712 void __devinit
pcibios_do_bus_setup(struct pci_bus
*bus
)
714 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
715 unsigned long io_offset
;
716 struct resource
*res
;
719 /* Hookup PHB resources */
720 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
721 if (bus
->parent
== NULL
) {
722 /* This is a host bridge - fill in its resources */
725 bus
->resource
[0] = res
= &hose
->io_resource
;
728 printk(KERN_ERR
"I/O resource not set for host"
729 " bridge %d\n", hose
->global_number
);
731 res
->end
= IO_SPACE_LIMIT
;
732 res
->flags
= IORESOURCE_IO
;
734 res
->start
= (res
->start
+ io_offset
) & 0xffffffffu
;
735 res
->end
= (res
->end
+ io_offset
) & 0xffffffffu
;
737 for (i
= 0; i
< 3; ++i
) {
738 res
= &hose
->mem_resources
[i
];
742 printk(KERN_ERR
"Memory resource not set for "
743 "host bridge %d\n", hose
->global_number
);
744 res
->start
= hose
->pci_mem_offset
;
746 res
->flags
= IORESOURCE_MEM
;
748 bus
->resource
[i
+1] = res
;
753 /* the next one is stolen from the alpha port... */
755 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
757 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
758 /* XXX FIXME - update OF device tree node interrupt property */
761 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
767 if (ppc_md
.pcibios_enable_device_hook
)
768 if (ppc_md
.pcibios_enable_device_hook(dev
, 0))
771 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
773 for (idx
=0; idx
<6; idx
++) {
774 r
= &dev
->resource
[idx
];
775 if (r
->flags
& IORESOURCE_UNSET
) {
776 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", pci_name(dev
));
779 if (r
->flags
& IORESOURCE_IO
)
780 cmd
|= PCI_COMMAND_IO
;
781 if (r
->flags
& IORESOURCE_MEM
)
782 cmd
|= PCI_COMMAND_MEMORY
;
784 if (cmd
!= old_cmd
) {
785 printk("PCI: Enabling device %s (%04x -> %04x)\n",
786 pci_name(dev
), old_cmd
, cmd
);
787 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
792 static struct pci_controller
*
793 pci_bus_to_hose(int bus
)
795 struct pci_controller
*hose
, *tmp
;
797 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
798 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
803 /* Provide information on locations of various I/O regions in physical
804 * memory. Do this on a per-card basis so that we choose the right
806 * Note that the returned IO or memory base is a physical address
809 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
811 struct pci_controller
* hose
;
812 long result
= -EOPNOTSUPP
;
814 hose
= pci_bus_to_hose(bus
);
819 case IOBASE_BRIDGE_NUMBER
:
820 return (long)hose
->first_busno
;
822 return (long)hose
->pci_mem_offset
;
824 return (long)hose
->io_base_phys
;
826 return (long)isa_io_base
;
828 return (long)isa_mem_base
;
834 unsigned long pci_address_to_pio(phys_addr_t address
)
836 struct pci_controller
*hose
, *tmp
;
838 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
839 unsigned int size
= hose
->io_resource
.end
-
840 hose
->io_resource
.start
+ 1;
841 if (address
>= hose
->io_base_phys
&&
842 address
< (hose
->io_base_phys
+ size
)) {
844 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
845 return base
+ (address
- hose
->io_base_phys
);
848 return (unsigned int)-1;
850 EXPORT_SYMBOL(pci_address_to_pio
);
853 * Null PCI config access functions, for the case when we can't
856 #define NULL_PCI_OP(rw, size, type) \
858 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
860 return PCIBIOS_DEVICE_NOT_FOUND; \
864 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
867 return PCIBIOS_DEVICE_NOT_FOUND
;
871 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
874 return PCIBIOS_DEVICE_NOT_FOUND
;
877 static struct pci_ops null_pci_ops
=
879 .read
= null_read_config
,
880 .write
= null_write_config
,
884 * These functions are used early on before PCI scanning is done
885 * and all of the pci_dev and pci_bus structures have been created.
887 static struct pci_bus
*
888 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
890 static struct pci_bus bus
;
893 hose
= pci_bus_to_hose(busnr
);
895 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
899 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
903 #define EARLY_PCI_OP(rw, size, type) \
904 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
905 int devfn, int offset, type value) \
907 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
908 devfn, offset, value); \
911 EARLY_PCI_OP(read
, byte
, u8
*)
912 EARLY_PCI_OP(read
, word
, u16
*)
913 EARLY_PCI_OP(read
, dword
, u32
*)
914 EARLY_PCI_OP(write
, byte
, u8
)
915 EARLY_PCI_OP(write
, word
, u16
)
916 EARLY_PCI_OP(write
, dword
, u32
)
918 extern int pci_bus_find_capability (struct pci_bus
*bus
, unsigned int devfn
, int cap
);
919 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
922 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);