?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pinctrl: nomadik: delete ancient pin control API
[linux-2.6.git] / drivers / pinctrl / pinctrl-nomadik.c
blob89280bc8123c97d4de89587362aa24fab4432172
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/pinctrl/pinconf.h>
34 /* Since we request GPIOs from ourself */
35 #include <linux/pinctrl/consumer.h>
36 #include <linux/platform_data/pinctrl-nomadik.h>
37 #include "pinctrl-nomadik.h"
38 #include "core.h"
39
40 /*
41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
42 * AMBA device, managing 32 pins and alternate functions. The logic block
43 * is currently used in the Nomadik and ux500.
44 *
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 */
47
48 struct nmk_gpio_chip {
49 struct gpio_chip chip;
50 struct irq_domain *domain;
51 void __iomem *addr;
52 struct clk *clk;
53 unsigned int bank;
54 unsigned int parent_irq;
55 int secondary_parent_irq;
56 u32 (*get_secondary_status)(unsigned int bank);
57 void (*set_ioforce)(bool enable);
58 spinlock_t lock;
59 bool sleepmode;
60 /* Keep track of configured edges */
61 u32 edge_rising;
62 u32 edge_falling;
63 u32 real_wake;
64 u32 rwimsc;
65 u32 fwimsc;
66 u32 rimsc;
67 u32 fimsc;
68 u32 pull_up;
69 u32 lowemi;
70 };
71
72 /**
73 * struct nmk_pinctrl - state container for the Nomadik pin controller
74 * @dev: containing device pointer
75 * @pctl: corresponding pin controller device
76 * @soc: SoC data for this specific chip
77 * @prcm_base: PRCM register range virtual base
78 */
79 struct nmk_pinctrl {
80 struct device *dev;
81 struct pinctrl_dev *pctl;
82 const struct nmk_pinctrl_soc_data *soc;
83 void __iomem *prcm_base;
84 };
85
86 static struct nmk_gpio_chip *
87 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
88
89 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
90
91 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
92
93 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
94 unsigned offset, int gpio_mode)
95 {
96 u32 bit = 1 << offset;
97 u32 afunc, bfunc;
98
99 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
100 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
101 if (gpio_mode & NMK_GPIO_ALT_A)
102 afunc |= bit;
103 if (gpio_mode & NMK_GPIO_ALT_B)
104 bfunc |= bit;
105 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
106 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
107 }
108
109 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
110 unsigned offset, enum nmk_gpio_slpm mode)
111 {
112 u32 bit = 1 << offset;
113 u32 slpm;
114
115 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
116 if (mode == NMK_GPIO_SLPM_NOCHANGE)
117 slpm |= bit;
118 else
119 slpm &= ~bit;
120 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
121 }
122
123 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
124 unsigned offset, enum nmk_gpio_pull pull)
125 {
126 u32 bit = 1 << offset;
127 u32 pdis;
128
129 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
130 if (pull == NMK_GPIO_PULL_NONE) {
131 pdis |= bit;
132 nmk_chip->pull_up &= ~bit;
133 } else {
134 pdis &= ~bit;
135 }
136
137 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
138
139 if (pull == NMK_GPIO_PULL_UP) {
140 nmk_chip->pull_up |= bit;
141 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
142 } else if (pull == NMK_GPIO_PULL_DOWN) {
143 nmk_chip->pull_up &= ~bit;
144 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
145 }
146 }
147
148 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
149 unsigned offset, bool lowemi)
150 {
151 u32 bit = BIT(offset);
152 bool enabled = nmk_chip->lowemi & bit;
153
154 if (lowemi == enabled)
155 return;
156
157 if (lowemi)
158 nmk_chip->lowemi |= bit;
159 else
160 nmk_chip->lowemi &= ~bit;
161
162 writel_relaxed(nmk_chip->lowemi,
163 nmk_chip->addr + NMK_GPIO_LOWEMI);
164 }
165
166 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
167 unsigned offset)
168 {
169 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
170 }
171
172 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
173 unsigned offset, int val)
174 {
175 if (val)
176 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
177 else
178 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
179 }
180
181 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
182 unsigned offset, int val)
183 {
184 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
185 __nmk_gpio_set_output(nmk_chip, offset, val);
186 }
187
188 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
189 unsigned offset, int gpio_mode,
190 bool glitch)
191 {
192 u32 rwimsc = nmk_chip->rwimsc;
193 u32 fwimsc = nmk_chip->fwimsc;
194
195 if (glitch && nmk_chip->set_ioforce) {
196 u32 bit = BIT(offset);
197
198 /* Prevent spurious wakeups */
199 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
200 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
201
202 nmk_chip->set_ioforce(true);
203 }
204
205 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
206
207 if (glitch && nmk_chip->set_ioforce) {
208 nmk_chip->set_ioforce(false);
209
210 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
211 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
212 }
213 }
214
215 static void
216 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
217 {
218 u32 falling = nmk_chip->fimsc & BIT(offset);
219 u32 rising = nmk_chip->rimsc & BIT(offset);
220 int gpio = nmk_chip->chip.base + offset;
221 int irq = irq_find_mapping(nmk_chip->domain, offset);
222 struct irq_data *d = irq_get_irq_data(irq);
223
224 if (!rising && !falling)
225 return;
226
227 if (!d || !irqd_irq_disabled(d))
228 return;
229
230 if (rising) {
231 nmk_chip->rimsc &= ~BIT(offset);
232 writel_relaxed(nmk_chip->rimsc,
233 nmk_chip->addr + NMK_GPIO_RIMSC);
234 }
235
236 if (falling) {
237 nmk_chip->fimsc &= ~BIT(offset);
238 writel_relaxed(nmk_chip->fimsc,
239 nmk_chip->addr + NMK_GPIO_FIMSC);
240 }
241
242 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
243 }
244
245 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
246 {
247 u32 val;
248
249 val = readl(reg);
250 val = ((val & ~mask) | (value & mask));
251 writel(val, reg);
252 }
253
254 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
255 unsigned offset, unsigned alt_num)
256 {
257 int i;
258 u16 reg;
259 u8 bit;
260 u8 alt_index;
261 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
262 const u16 *gpiocr_regs;
263
264 if (!npct->prcm_base)
265 return;
266
267 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
268 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
269 alt_num);
270 return;
271 }
272
273 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
274 if (npct->soc->altcx_pins[i].pin == offset)
275 break;
276 }
277 if (i == npct->soc->npins_altcx) {
278 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
279 offset);
280 return;
281 }
282
283 pin_desc = npct->soc->altcx_pins + i;
284 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
285
286 /*
287 * If alt_num is NULL, just clear current ALTCx selection
288 * to make sure we come back to a pure ALTC selection
289 */
290 if (!alt_num) {
291 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
292 if (pin_desc->altcx[i].used == true) {
293 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
294 bit = pin_desc->altcx[i].control_bit;
295 if (readl(npct->prcm_base + reg) & BIT(bit)) {
296 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
297 dev_dbg(npct->dev,
298 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
299 offset, i+1);
300 }
301 }
302 }
303 return;
304 }
305
306 alt_index = alt_num - 1;
307 if (pin_desc->altcx[alt_index].used == false) {
308 dev_warn(npct->dev,
309 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
310 offset, alt_num);
311 return;
312 }
313
314 /*
315 * Check if any other ALTCx functions are activated on this pin
316 * and disable it first.
317 */
318 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
319 if (i == alt_index)
320 continue;
321 if (pin_desc->altcx[i].used == true) {
322 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
323 bit = pin_desc->altcx[i].control_bit;
324 if (readl(npct->prcm_base + reg) & BIT(bit)) {
325 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
326 dev_dbg(npct->dev,
327 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
328 offset, i+1);
329 }
330 }
331 }
332
333 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
334 bit = pin_desc->altcx[alt_index].control_bit;
335 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
336 offset, alt_index+1);
337 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
338 }
339
340 /*
341 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
342 * - Save SLPM registers
343 * - Set SLPM=0 for the IOs you want to switch and others to 1
344 * - Configure the GPIO registers for the IOs that are being switched
345 * - Set IOFORCE=1
346 * - Modify the AFLSA/B registers for the IOs that are being switched
347 * - Set IOFORCE=0
348 * - Restore SLPM registers
349 * - Any spurious wake up event during switch sequence to be ignored and
350 * cleared
351 */
352 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
353 {
354 int i;
355
356 for (i = 0; i < NUM_BANKS; i++) {
357 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
358 unsigned int temp = slpm[i];
359
360 if (!chip)
361 break;
362
363 clk_enable(chip->clk);
364
365 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
366 writel(temp, chip->addr + NMK_GPIO_SLPC);
367 }
368 }
369
370 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
371 {
372 int i;
373
374 for (i = 0; i < NUM_BANKS; i++) {
375 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
376
377 if (!chip)
378 break;
379
380 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
381
382 clk_disable(chip->clk);
383 }
384 }
385
386 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
387 {
388 int i;
389 u16 reg;
390 u8 bit;
391 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
392 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
393 const u16 *gpiocr_regs;
394
395 if (!npct->prcm_base)
396 return NMK_GPIO_ALT_C;
397
398 for (i = 0; i < npct->soc->npins_altcx; i++) {
399 if (npct->soc->altcx_pins[i].pin == gpio)
400 break;
401 }
402 if (i == npct->soc->npins_altcx)
403 return NMK_GPIO_ALT_C;
404
405 pin_desc = npct->soc->altcx_pins + i;
406 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
407 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
408 if (pin_desc->altcx[i].used == true) {
409 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
410 bit = pin_desc->altcx[i].control_bit;
411 if (readl(npct->prcm_base + reg) & BIT(bit))
412 return NMK_GPIO_ALT_C+i+1;
413 }
414 }
415 return NMK_GPIO_ALT_C;
416 }
417
418 int nmk_gpio_get_mode(int gpio)
419 {
420 struct nmk_gpio_chip *nmk_chip;
421 u32 afunc, bfunc, bit;
422
423 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
424 if (!nmk_chip)
425 return -EINVAL;
426
427 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
428
429 clk_enable(nmk_chip->clk);
430
431 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
432 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
433
434 clk_disable(nmk_chip->clk);
435
436 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
437 }
438 EXPORT_SYMBOL(nmk_gpio_get_mode);
439
440
441 /* IRQ functions */
442 static inline int nmk_gpio_get_bitmask(int gpio)
443 {
444 return 1 << (gpio % NMK_GPIO_PER_CHIP);
445 }
446
447 static void nmk_gpio_irq_ack(struct irq_data *d)
448 {
449 struct nmk_gpio_chip *nmk_chip;
450
451 nmk_chip = irq_data_get_irq_chip_data(d);
452 if (!nmk_chip)
453 return;
454
455 clk_enable(nmk_chip->clk);
456 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
457 clk_disable(nmk_chip->clk);
458 }
459
460 enum nmk_gpio_irq_type {
461 NORMAL,
462 WAKE,
463 };
464
465 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
466 int gpio, enum nmk_gpio_irq_type which,
467 bool enable)
468 {
469 u32 bitmask = nmk_gpio_get_bitmask(gpio);
470 u32 *rimscval;
471 u32 *fimscval;
472 u32 rimscreg;
473 u32 fimscreg;
474
475 if (which == NORMAL) {
476 rimscreg = NMK_GPIO_RIMSC;
477 fimscreg = NMK_GPIO_FIMSC;
478 rimscval = &nmk_chip->rimsc;
479 fimscval = &nmk_chip->fimsc;
480 } else {
481 rimscreg = NMK_GPIO_RWIMSC;
482 fimscreg = NMK_GPIO_FWIMSC;
483 rimscval = &nmk_chip->rwimsc;
484 fimscval = &nmk_chip->fwimsc;
485 }
486
487 /* we must individually set/clear the two edges */
488 if (nmk_chip->edge_rising & bitmask) {
489 if (enable)
490 *rimscval |= bitmask;
491 else
492 *rimscval &= ~bitmask;
493 writel(*rimscval, nmk_chip->addr + rimscreg);
494 }
495 if (nmk_chip->edge_falling & bitmask) {
496 if (enable)
497 *fimscval |= bitmask;
498 else
499 *fimscval &= ~bitmask;
500 writel(*fimscval, nmk_chip->addr + fimscreg);
501 }
502 }
503
504 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
505 int gpio, bool on)
506 {
507 /*
508 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
509 * disabled, since setting SLPM to 1 increases power consumption, and
510 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
511 */
512 if (nmk_chip->sleepmode && on) {
513 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
514 NMK_GPIO_SLPM_WAKEUP_ENABLE);
515 }
516
517 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
518 }
519
520 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
521 {
522 struct nmk_gpio_chip *nmk_chip;
523 unsigned long flags;
524 u32 bitmask;
525
526 nmk_chip = irq_data_get_irq_chip_data(d);
527 bitmask = nmk_gpio_get_bitmask(d->hwirq);
528 if (!nmk_chip)
529 return -EINVAL;
530
531 clk_enable(nmk_chip->clk);
532 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
533 spin_lock(&nmk_chip->lock);
534
535 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
536
537 if (!(nmk_chip->real_wake & bitmask))
538 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
539
540 spin_unlock(&nmk_chip->lock);
541 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
542 clk_disable(nmk_chip->clk);
543
544 return 0;
545 }
546
547 static void nmk_gpio_irq_mask(struct irq_data *d)
548 {
549 nmk_gpio_irq_maskunmask(d, false);
550 }
551
552 static void nmk_gpio_irq_unmask(struct irq_data *d)
553 {
554 nmk_gpio_irq_maskunmask(d, true);
555 }
556
557 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
558 {
559 struct nmk_gpio_chip *nmk_chip;
560 unsigned long flags;
561 u32 bitmask;
562
563 nmk_chip = irq_data_get_irq_chip_data(d);
564 if (!nmk_chip)
565 return -EINVAL;
566 bitmask = nmk_gpio_get_bitmask(d->hwirq);
567
568 clk_enable(nmk_chip->clk);
569 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
570 spin_lock(&nmk_chip->lock);
571
572 if (irqd_irq_disabled(d))
573 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
574
575 if (on)
576 nmk_chip->real_wake |= bitmask;
577 else
578 nmk_chip->real_wake &= ~bitmask;
579
580 spin_unlock(&nmk_chip->lock);
581 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
582 clk_disable(nmk_chip->clk);
583
584 return 0;
585 }
586
587 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
588 {
589 bool enabled = !irqd_irq_disabled(d);
590 bool wake = irqd_is_wakeup_set(d);
591 struct nmk_gpio_chip *nmk_chip;
592 unsigned long flags;
593 u32 bitmask;
594
595 nmk_chip = irq_data_get_irq_chip_data(d);
596 bitmask = nmk_gpio_get_bitmask(d->hwirq);
597 if (!nmk_chip)
598 return -EINVAL;
599 if (type & IRQ_TYPE_LEVEL_HIGH)
600 return -EINVAL;
601 if (type & IRQ_TYPE_LEVEL_LOW)
602 return -EINVAL;
603
604 clk_enable(nmk_chip->clk);
605 spin_lock_irqsave(&nmk_chip->lock, flags);
606
607 if (enabled)
608 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
609
610 if (enabled || wake)
611 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
612
613 nmk_chip->edge_rising &= ~bitmask;
614 if (type & IRQ_TYPE_EDGE_RISING)
615 nmk_chip->edge_rising |= bitmask;
616
617 nmk_chip->edge_falling &= ~bitmask;
618 if (type & IRQ_TYPE_EDGE_FALLING)
619 nmk_chip->edge_falling |= bitmask;
620
621 if (enabled)
622 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
623
624 if (enabled || wake)
625 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
626
627 spin_unlock_irqrestore(&nmk_chip->lock, flags);
628 clk_disable(nmk_chip->clk);
629
630 return 0;
631 }
632
633 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
634 {
635 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
636
637 clk_enable(nmk_chip->clk);
638 nmk_gpio_irq_unmask(d);
639 return 0;
640 }
641
642 static void nmk_gpio_irq_shutdown(struct irq_data *d)
643 {
644 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
645
646 nmk_gpio_irq_mask(d);
647 clk_disable(nmk_chip->clk);
648 }
649
650 static struct irq_chip nmk_gpio_irq_chip = {
651 .name = "Nomadik-GPIO",
652 .irq_ack = nmk_gpio_irq_ack,
653 .irq_mask = nmk_gpio_irq_mask,
654 .irq_unmask = nmk_gpio_irq_unmask,
655 .irq_set_type = nmk_gpio_irq_set_type,
656 .irq_set_wake = nmk_gpio_irq_set_wake,
657 .irq_startup = nmk_gpio_irq_startup,
658 .irq_shutdown = nmk_gpio_irq_shutdown,
659 .flags = IRQCHIP_MASK_ON_SUSPEND,
660 };
661
662 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
663 u32 status)
664 {
665 struct nmk_gpio_chip *nmk_chip;
666 struct irq_chip *host_chip = irq_get_chip(irq);
667
668 chained_irq_enter(host_chip, desc);
669
670 nmk_chip = irq_get_handler_data(irq);
671 while (status) {
672 int bit = __ffs(status);
673
674 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
675 status &= ~BIT(bit);
676 }
677
678 chained_irq_exit(host_chip, desc);
679 }
680
681 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
682 {
683 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
684 u32 status;
685
686 clk_enable(nmk_chip->clk);
687 status = readl(nmk_chip->addr + NMK_GPIO_IS);
688 clk_disable(nmk_chip->clk);
689
690 __nmk_gpio_irq_handler(irq, desc, status);
691 }
692
693 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
694 struct irq_desc *desc)
695 {
696 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
697 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
698
699 __nmk_gpio_irq_handler(irq, desc, status);
700 }
701
702 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
703 {
704 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
705 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
706
707 if (nmk_chip->secondary_parent_irq >= 0) {
708 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
709 nmk_gpio_secondary_irq_handler);
710 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
711 }
712
713 return 0;
714 }
715
716 /* I/O Functions */
717
718 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
719 {
720 /*
721 * Map back to global GPIO space and request muxing, the direction
722 * parameter does not matter for this controller.
723 */
724 int gpio = chip->base + offset;
725
726 return pinctrl_request_gpio(gpio);
727 }
728
729 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
730 {
731 int gpio = chip->base + offset;
732
733 pinctrl_free_gpio(gpio);
734 }
735
736 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
737 {
738 struct nmk_gpio_chip *nmk_chip =
739 container_of(chip, struct nmk_gpio_chip, chip);
740
741 clk_enable(nmk_chip->clk);
742
743 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
744
745 clk_disable(nmk_chip->clk);
746
747 return 0;
748 }
749
750 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
751 {
752 struct nmk_gpio_chip *nmk_chip =
753 container_of(chip, struct nmk_gpio_chip, chip);
754 u32 bit = 1 << offset;
755 int value;
756
757 clk_enable(nmk_chip->clk);
758
759 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
760
761 clk_disable(nmk_chip->clk);
762
763 return value;
764 }
765
766 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
767 int val)
768 {
769 struct nmk_gpio_chip *nmk_chip =
770 container_of(chip, struct nmk_gpio_chip, chip);
771
772 clk_enable(nmk_chip->clk);
773
774 __nmk_gpio_set_output(nmk_chip, offset, val);
775
776 clk_disable(nmk_chip->clk);
777 }
778
779 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
780 int val)
781 {
782 struct nmk_gpio_chip *nmk_chip =
783 container_of(chip, struct nmk_gpio_chip, chip);
784
785 clk_enable(nmk_chip->clk);
786
787 __nmk_gpio_make_output(nmk_chip, offset, val);
788
789 clk_disable(nmk_chip->clk);
790
791 return 0;
792 }
793
794 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
795 {
796 struct nmk_gpio_chip *nmk_chip =
797 container_of(chip, struct nmk_gpio_chip, chip);
798
799 return irq_create_mapping(nmk_chip->domain, offset);
800 }
801
802 #ifdef CONFIG_DEBUG_FS
803
804 #include <linux/seq_file.h>
805
806 static void nmk_gpio_dbg_show_one(struct seq_file *s,
807 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
808 unsigned offset, unsigned gpio)
809 {
810 const char *label = gpiochip_is_requested(chip, offset);
811 struct nmk_gpio_chip *nmk_chip =
812 container_of(chip, struct nmk_gpio_chip, chip);
813 int mode;
814 bool is_out;
815 bool pull;
816 u32 bit = 1 << offset;
817 const char *modes[] = {
818 [NMK_GPIO_ALT_GPIO] = "gpio",
819 [NMK_GPIO_ALT_A] = "altA",
820 [NMK_GPIO_ALT_B] = "altB",
821 [NMK_GPIO_ALT_C] = "altC",
822 [NMK_GPIO_ALT_C+1] = "altC1",
823 [NMK_GPIO_ALT_C+2] = "altC2",
824 [NMK_GPIO_ALT_C+3] = "altC3",
825 [NMK_GPIO_ALT_C+4] = "altC4",
826 };
827
828 clk_enable(nmk_chip->clk);
829 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
830 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
831 mode = nmk_gpio_get_mode(gpio);
832 if ((mode == NMK_GPIO_ALT_C) && pctldev)
833 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
834
835 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
836 gpio, label ?: "(none)",
837 is_out ? "out" : "in ",
838 chip->get
839 ? (chip->get(chip, offset) ? "hi" : "lo")
840 : "? ",
841 (mode < 0) ? "unknown" : modes[mode],
842 pull ? "pull" : "none");
843
844 if (label && !is_out) {
845 int irq = gpio_to_irq(gpio);
846 struct irq_desc *desc = irq_to_desc(irq);
847
848 /* This races with request_irq(), set_irq_type(),
849 * and set_irq_wake() ... but those are "rare".
850 */
851 if (irq >= 0 && desc->action) {
852 char *trigger;
853 u32 bitmask = nmk_gpio_get_bitmask(gpio);
854
855 if (nmk_chip->edge_rising & bitmask)
856 trigger = "edge-rising";
857 else if (nmk_chip->edge_falling & bitmask)
858 trigger = "edge-falling";
859 else
860 trigger = "edge-undefined";
861
862 seq_printf(s, " irq-%d %s%s",
863 irq, trigger,
864 irqd_is_wakeup_set(&desc->irq_data)
865 ? " wakeup" : "");
866 }
867 }
868 clk_disable(nmk_chip->clk);
869 }
870
871 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
872 {
873 unsigned i;
874 unsigned gpio = chip->base;
875
876 for (i = 0; i < chip->ngpio; i++, gpio++) {
877 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
878 seq_printf(s, "\n");
879 }
880 }
881
882 #else
883 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
884 struct pinctrl_dev *pctldev,
885 struct gpio_chip *chip,
886 unsigned offset, unsigned gpio)
887 {
888 }
889 #define nmk_gpio_dbg_show NULL
890 #endif
891
892 /* This structure is replicated for each GPIO block allocated at probe time */
893 static struct gpio_chip nmk_gpio_template = {
894 .request = nmk_gpio_request,
895 .free = nmk_gpio_free,
896 .direction_input = nmk_gpio_make_input,
897 .get = nmk_gpio_get_input,
898 .direction_output = nmk_gpio_make_output,
899 .set = nmk_gpio_set_output,
900 .to_irq = nmk_gpio_to_irq,
901 .dbg_show = nmk_gpio_dbg_show,
902 .can_sleep = 0,
903 };
904
905 void nmk_gpio_clocks_enable(void)
906 {
907 int i;
908
909 for (i = 0; i < NUM_BANKS; i++) {
910 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
911
912 if (!chip)
913 continue;
914
915 clk_enable(chip->clk);
916 }
917 }
918
919 void nmk_gpio_clocks_disable(void)
920 {
921 int i;
922
923 for (i = 0; i < NUM_BANKS; i++) {
924 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
925
926 if (!chip)
927 continue;
928
929 clk_disable(chip->clk);
930 }
931 }
932
933 /*
934 * Called from the suspend/resume path to only keep the real wakeup interrupts
935 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
936 * and not the rest of the interrupts which we needed to have as wakeups for
937 * cpuidle.
938 *
939 * PM ops are not used since this needs to be done at the end, after all the
940 * other drivers are done with their suspend callbacks.
941 */
942 void nmk_gpio_wakeups_suspend(void)
943 {
944 int i;
945
946 for (i = 0; i < NUM_BANKS; i++) {
947 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
948
949 if (!chip)
950 break;
951
952 clk_enable(chip->clk);
953
954 writel(chip->rwimsc & chip->real_wake,
955 chip->addr + NMK_GPIO_RWIMSC);
956 writel(chip->fwimsc & chip->real_wake,
957 chip->addr + NMK_GPIO_FWIMSC);
958
959 clk_disable(chip->clk);
960 }
961 }
962
963 void nmk_gpio_wakeups_resume(void)
964 {
965 int i;
966
967 for (i = 0; i < NUM_BANKS; i++) {
968 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
969
970 if (!chip)
971 break;
972
973 clk_enable(chip->clk);
974
975 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
976 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
977
978 clk_disable(chip->clk);
979 }
980 }
981
982 /*
983 * Read the pull up/pull down status.
984 * A bit set in 'pull_up' means that pull up
985 * is selected if pull is enabled in PDIS register.
986 * Note: only pull up/down set via this driver can
987 * be detected due to HW limitations.
988 */
989 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
990 {
991 if (gpio_bank < NUM_BANKS) {
992 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
993
994 if (!chip)
995 return;
996
997 *pull_up = chip->pull_up;
998 }
999 }
1000
1001 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1002 irq_hw_number_t hwirq)
1003 {
1004 struct nmk_gpio_chip *nmk_chip = d->host_data;
1005
1006 if (!nmk_chip)
1007 return -EINVAL;
1008
1009 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1010 set_irq_flags(irq, IRQF_VALID);
1011 irq_set_chip_data(irq, nmk_chip);
1012 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1013
1014 return 0;
1015 }
1016
1017 static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1018 .map = nmk_gpio_irq_map,
1019 .xlate = irq_domain_xlate_twocell,
1020 };
1021
1022 static int nmk_gpio_probe(struct platform_device *dev)
1023 {
1024 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1025 struct device_node *np = dev->dev.of_node;
1026 struct nmk_gpio_chip *nmk_chip;
1027 struct gpio_chip *chip;
1028 struct resource *res;
1029 struct clk *clk;
1030 int secondary_irq;
1031 void __iomem *base;
1032 int irq_start = 0;
1033 int irq;
1034 int ret;
1035
1036 if (!pdata && !np) {
1037 dev_err(&dev->dev, "No platform data or device tree found\n");
1038 return -ENODEV;
1039 }
1040
1041 if (np) {
1042 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1043 if (!pdata)
1044 return -ENOMEM;
1045
1046 if (of_get_property(np, "st,supports-sleepmode", NULL))
1047 pdata->supports_sleepmode = true;
1048
1049 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1050 dev_err(&dev->dev, "gpio-bank property not found\n");
1051 return -EINVAL;
1052 }
1053
1054 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1055 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1056 }
1057
1058 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1059 if (!res)
1060 return -ENOENT;
1061
1062 irq = platform_get_irq(dev, 0);
1063 if (irq < 0)
1064 return irq;
1065
1066 secondary_irq = platform_get_irq(dev, 1);
1067 if (secondary_irq >= 0 && !pdata->get_secondary_status)
1068 return -EINVAL;
1069
1070 base = devm_ioremap_resource(&dev->dev, res);
1071 if (IS_ERR(base))
1072 return PTR_ERR(base);
1073
1074 clk = devm_clk_get(&dev->dev, NULL);
1075 if (IS_ERR(clk))
1076 return PTR_ERR(clk);
1077 clk_prepare(clk);
1078
1079 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1080 if (!nmk_chip)
1081 return -ENOMEM;
1082
1083 /*
1084 * The virt address in nmk_chip->addr is in the nomadik register space,
1085 * so we can simply convert the resource address, without remapping
1086 */
1087 nmk_chip->bank = dev->id;
1088 nmk_chip->clk = clk;
1089 nmk_chip->addr = base;
1090 nmk_chip->chip = nmk_gpio_template;
1091 nmk_chip->parent_irq = irq;
1092 nmk_chip->secondary_parent_irq = secondary_irq;
1093 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1094 nmk_chip->set_ioforce = pdata->set_ioforce;
1095 nmk_chip->sleepmode = pdata->supports_sleepmode;
1096 spin_lock_init(&nmk_chip->lock);
1097
1098 chip = &nmk_chip->chip;
1099 chip->base = pdata->first_gpio;
1100 chip->ngpio = pdata->num_gpio;
1101 chip->label = pdata->name ?: dev_name(&dev->dev);
1102 chip->dev = &dev->dev;
1103 chip->owner = THIS_MODULE;
1104
1105 clk_enable(nmk_chip->clk);
1106 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1107 clk_disable(nmk_chip->clk);
1108
1109 #ifdef CONFIG_OF_GPIO
1110 chip->of_node = np;
1111 #endif
1112
1113 ret = gpiochip_add(&nmk_chip->chip);
1114 if (ret)
1115 return ret;
1116
1117 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1118
1119 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1120
1121 platform_set_drvdata(dev, nmk_chip);
1122
1123 if (!np)
1124 irq_start = pdata->first_irq;
1125 nmk_chip->domain = irq_domain_add_simple(np,
1126 NMK_GPIO_PER_CHIP, irq_start,
1127 &nmk_gpio_irq_simple_ops, nmk_chip);
1128 if (!nmk_chip->domain) {
1129 dev_err(&dev->dev, "failed to create irqdomain\n");
1130 /* Just do this, no matter if it fails */
1131 ret = gpiochip_remove(&nmk_chip->chip);
1132 return -ENOSYS;
1133 }
1134
1135 nmk_gpio_init_irq(nmk_chip);
1136
1137 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1138
1139 return 0;
1140 }
1141
1142 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1143 {
1144 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1145
1146 return npct->soc->ngroups;
1147 }
1148
1149 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1150 unsigned selector)
1151 {
1152 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1153
1154 return npct->soc->groups[selector].name;
1155 }
1156
1157 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1158 const unsigned **pins,
1159 unsigned *num_pins)
1160 {
1161 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1162
1163 *pins = npct->soc->groups[selector].pins;
1164 *num_pins = npct->soc->groups[selector].npins;
1165 return 0;
1166 }
1167
1168 static struct pinctrl_gpio_range *
1169 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1170 {
1171 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1172 int i;
1173
1174 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1175 struct pinctrl_gpio_range *range;
1176
1177 range = &npct->soc->gpio_ranges[i];
1178 if (offset >= range->pin_base &&
1179 offset <= (range->pin_base + range->npins - 1))
1180 return range;
1181 }
1182 return NULL;
1183 }
1184
1185 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1186 unsigned offset)
1187 {
1188 struct pinctrl_gpio_range *range;
1189 struct gpio_chip *chip;
1190
1191 range = nmk_match_gpio_range(pctldev, offset);
1192 if (!range || !range->gc) {
1193 seq_printf(s, "invalid pin offset");
1194 return;
1195 }
1196 chip = range->gc;
1197 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1198 }
1199
1200 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1201 struct pinctrl_map *map, unsigned num_maps)
1202 {
1203 int i;
1204
1205 for (i = 0; i < num_maps; i++)
1206 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1207 kfree(map[i].data.configs.configs);
1208 kfree(map);
1209 }
1210
1211 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1212 unsigned *num_maps, unsigned reserve)
1213 {
1214 unsigned old_num = *reserved_maps;
1215 unsigned new_num = *num_maps + reserve;
1216 struct pinctrl_map *new_map;
1217
1218 if (old_num >= new_num)
1219 return 0;
1220
1221 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1222 if (!new_map)
1223 return -ENOMEM;
1224
1225 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1226
1227 *map = new_map;
1228 *reserved_maps = new_num;
1229
1230 return 0;
1231 }
1232
1233 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1234 unsigned *num_maps, const char *group,
1235 const char *function)
1236 {
1237 if (*num_maps == *reserved_maps)
1238 return -ENOSPC;
1239
1240 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1241 (*map)[*num_maps].data.mux.group = group;
1242 (*map)[*num_maps].data.mux.function = function;
1243 (*num_maps)++;
1244
1245 return 0;
1246 }
1247
1248 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1249 unsigned *reserved_maps,
1250 unsigned *num_maps, const char *group,
1251 unsigned long *configs, unsigned num_configs)
1252 {
1253 unsigned long *dup_configs;
1254
1255 if (*num_maps == *reserved_maps)
1256 return -ENOSPC;
1257
1258 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1259 GFP_KERNEL);
1260 if (!dup_configs)
1261 return -ENOMEM;
1262
1263 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1264
1265 (*map)[*num_maps].data.configs.group_or_pin = group;
1266 (*map)[*num_maps].data.configs.configs = dup_configs;
1267 (*map)[*num_maps].data.configs.num_configs = num_configs;
1268 (*num_maps)++;
1269
1270 return 0;
1271 }
1272
1273 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1274 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1275 .size = ARRAY_SIZE(y), }
1276
1277 static const unsigned long nmk_pin_input_modes[] = {
1278 PIN_INPUT_NOPULL,
1279 PIN_INPUT_PULLUP,
1280 PIN_INPUT_PULLDOWN,
1281 };
1282
1283 static const unsigned long nmk_pin_output_modes[] = {
1284 PIN_OUTPUT_LOW,
1285 PIN_OUTPUT_HIGH,
1286 PIN_DIR_OUTPUT,
1287 };
1288
1289 static const unsigned long nmk_pin_sleep_modes[] = {
1290 PIN_SLEEPMODE_DISABLED,
1291 PIN_SLEEPMODE_ENABLED,
1292 };
1293
1294 static const unsigned long nmk_pin_sleep_input_modes[] = {
1295 PIN_SLPM_INPUT_NOPULL,
1296 PIN_SLPM_INPUT_PULLUP,
1297 PIN_SLPM_INPUT_PULLDOWN,
1298 PIN_SLPM_DIR_INPUT,
1299 };
1300
1301 static const unsigned long nmk_pin_sleep_output_modes[] = {
1302 PIN_SLPM_OUTPUT_LOW,
1303 PIN_SLPM_OUTPUT_HIGH,
1304 PIN_SLPM_DIR_OUTPUT,
1305 };
1306
1307 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1308 PIN_SLPM_WAKEUP_DISABLE,
1309 PIN_SLPM_WAKEUP_ENABLE,
1310 };
1311
1312 static const unsigned long nmk_pin_gpio_modes[] = {
1313 PIN_GPIOMODE_DISABLED,
1314 PIN_GPIOMODE_ENABLED,
1315 };
1316
1317 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1318 PIN_SLPM_PDIS_DISABLED,
1319 PIN_SLPM_PDIS_ENABLED,
1320 };
1321
1322 struct nmk_cfg_param {
1323 const char *property;
1324 unsigned long config;
1325 const unsigned long *choice;
1326 int size;
1327 };
1328
1329 static const struct nmk_cfg_param nmk_cfg_params[] = {
1330 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1331 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1332 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1333 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1334 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1335 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1336 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1337 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1338 };
1339
1340 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1341 {
1342 int ret = 0;
1343
1344 if (nmk_cfg_params[index].choice == NULL)
1345 *config = nmk_cfg_params[index].config;
1346 else {
1347 /* test if out of range */
1348 if (val < nmk_cfg_params[index].size) {
1349 *config = nmk_cfg_params[index].config |
1350 nmk_cfg_params[index].choice[val];
1351 }
1352 }
1353 return ret;
1354 }
1355
1356 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1357 {
1358 int i, pin_number;
1359 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1360
1361 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1362 for (i = 0; i < npct->soc->npins; i++)
1363 if (npct->soc->pins[i].number == pin_number)
1364 return npct->soc->pins[i].name;
1365 return NULL;
1366 }
1367
1368 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1369 unsigned long *configs)
1370 {
1371 bool has_config = 0;
1372 unsigned long cfg = 0;
1373 int i, val, ret;
1374
1375 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1376 ret = of_property_read_u32(np,
1377 nmk_cfg_params[i].property, &val);
1378 if (ret != -EINVAL) {
1379 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1380 *configs |= cfg;
1381 has_config = 1;
1382 }
1383 }
1384 }
1385
1386 return has_config;
1387 }
1388
1389 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1390 struct device_node *np,
1391 struct pinctrl_map **map,
1392 unsigned *reserved_maps,
1393 unsigned *num_maps)
1394 {
1395 int ret;
1396 const char *function = NULL;
1397 unsigned long configs = 0;
1398 bool has_config = 0;
1399 unsigned reserve = 0;
1400 struct property *prop;
1401 const char *group, *gpio_name;
1402 struct device_node *np_config;
1403
1404 ret = of_property_read_string(np, "ste,function", &function);
1405 if (ret >= 0)
1406 reserve = 1;
1407
1408 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1409
1410 np_config = of_parse_phandle(np, "ste,config", 0);
1411 if (np_config)
1412 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1413
1414 ret = of_property_count_strings(np, "ste,pins");
1415 if (ret < 0)
1416 goto exit;
1417
1418 if (has_config)
1419 reserve++;
1420
1421 reserve *= ret;
1422
1423 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1424 if (ret < 0)
1425 goto exit;
1426
1427 of_property_for_each_string(np, "ste,pins", prop, group) {
1428 if (function) {
1429 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1430 group, function);
1431 if (ret < 0)
1432 goto exit;
1433 }
1434 if (has_config) {
1435 gpio_name = nmk_find_pin_name(pctldev, group);
1436
1437 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1438 gpio_name, &configs, 1);
1439 if (ret < 0)
1440 goto exit;
1441 }
1442
1443 }
1444 exit:
1445 return ret;
1446 }
1447
1448 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1449 struct device_node *np_config,
1450 struct pinctrl_map **map, unsigned *num_maps)
1451 {
1452 unsigned reserved_maps;
1453 struct device_node *np;
1454 int ret;
1455
1456 reserved_maps = 0;
1457 *map = NULL;
1458 *num_maps = 0;
1459
1460 for_each_child_of_node(np_config, np) {
1461 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1462 &reserved_maps, num_maps);
1463 if (ret < 0) {
1464 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1465 return ret;
1466 }
1467 }
1468
1469 return 0;
1470 }
1471
1472 static const struct pinctrl_ops nmk_pinctrl_ops = {
1473 .get_groups_count = nmk_get_groups_cnt,
1474 .get_group_name = nmk_get_group_name,
1475 .get_group_pins = nmk_get_group_pins,
1476 .pin_dbg_show = nmk_pin_dbg_show,
1477 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1478 .dt_free_map = nmk_pinctrl_dt_free_map,
1479 };
1480
1481 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1482 {
1483 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1484
1485 return npct->soc->nfunctions;
1486 }
1487
1488 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1489 unsigned function)
1490 {
1491 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1492
1493 return npct->soc->functions[function].name;
1494 }
1495
1496 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1497 unsigned function,
1498 const char * const **groups,
1499 unsigned * const num_groups)
1500 {
1501 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1502
1503 *groups = npct->soc->functions[function].groups;
1504 *num_groups = npct->soc->functions[function].ngroups;
1505
1506 return 0;
1507 }
1508
1509 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1510 unsigned group)
1511 {
1512 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1513 const struct nmk_pingroup *g;
1514 static unsigned int slpm[NUM_BANKS];
1515 unsigned long flags;
1516 bool glitch;
1517 int ret = -EINVAL;
1518 int i;
1519
1520 g = &npct->soc->groups[group];
1521
1522 if (g->altsetting < 0)
1523 return -EINVAL;
1524
1525 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1526
1527 /*
1528 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1529 * we may pass through an undesired state. In this case we take
1530 * some extra care.
1531 *
1532 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1533 * - Save SLPM registers (since we have a shadow register in the
1534 * nmk_chip we're using that as backup)
1535 * - Set SLPM=0 for the IOs you want to switch and others to 1
1536 * - Configure the GPIO registers for the IOs that are being switched
1537 * - Set IOFORCE=1
1538 * - Modify the AFLSA/B registers for the IOs that are being switched
1539 * - Set IOFORCE=0
1540 * - Restore SLPM registers
1541 * - Any spurious wake up event during switch sequence to be ignored
1542 * and cleared
1543 *
1544 * We REALLY need to save ALL slpm registers, because the external
1545 * IOFORCE will switch *all* ports to their sleepmode setting to as
1546 * to avoid glitches. (Not just one port!)
1547 */
1548 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1549
1550 if (glitch) {
1551 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1552
1553 /* Initially don't put any pins to sleep when switching */
1554 memset(slpm, 0xff, sizeof(slpm));
1555
1556 /*
1557 * Then mask the pins that need to be sleeping now when we're
1558 * switching to the ALT C function.
1559 */
1560 for (i = 0; i < g->npins; i++)
1561 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1562 nmk_gpio_glitch_slpm_init(slpm);
1563 }
1564
1565 for (i = 0; i < g->npins; i++) {
1566 struct pinctrl_gpio_range *range;
1567 struct nmk_gpio_chip *nmk_chip;
1568 struct gpio_chip *chip;
1569 unsigned bit;
1570
1571 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1572 if (!range) {
1573 dev_err(npct->dev,
1574 "invalid pin offset %d in group %s at index %d\n",
1575 g->pins[i], g->name, i);
1576 goto out_glitch;
1577 }
1578 if (!range->gc) {
1579 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1580 g->pins[i], g->name, i);
1581 goto out_glitch;
1582 }
1583 chip = range->gc;
1584 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1585 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1586
1587 clk_enable(nmk_chip->clk);
1588 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1589 /*
1590 * If the pin is switching to altfunc, and there was an
1591 * interrupt installed on it which has been lazy disabled,
1592 * actually mask the interrupt to prevent spurious interrupts
1593 * that would occur while the pin is under control of the
1594 * peripheral. Only SKE does this.
1595 */
1596 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1597
1598 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1599 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1600 clk_disable(nmk_chip->clk);
1601
1602 /*
1603 * Call PRCM GPIOCR config function in case ALTC
1604 * has been selected:
1605 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1606 * must be set.
1607 * - If selection is pure ALTC and previous selection was ALTCx,
1608 * then some bits in PRCM GPIOCR registers must be cleared.
1609 */
1610 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1611 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1612 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1613 }
1614
1615 /* When all pins are successfully reconfigured we get here */
1616 ret = 0;
1617
1618 out_glitch:
1619 if (glitch) {
1620 nmk_gpio_glitch_slpm_restore(slpm);
1621 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1622 }
1623
1624 return ret;
1625 }
1626
1627 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1628 unsigned function, unsigned group)
1629 {
1630 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1631 const struct nmk_pingroup *g;
1632
1633 g = &npct->soc->groups[group];
1634
1635 if (g->altsetting < 0)
1636 return;
1637
1638 /* Poke out the mux, set the pin to some default state? */
1639 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1640 }
1641
1642 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1643 struct pinctrl_gpio_range *range,
1644 unsigned offset)
1645 {
1646 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1647 struct nmk_gpio_chip *nmk_chip;
1648 struct gpio_chip *chip;
1649 unsigned bit;
1650
1651 if (!range) {
1652 dev_err(npct->dev, "invalid range\n");
1653 return -EINVAL;
1654 }
1655 if (!range->gc) {
1656 dev_err(npct->dev, "missing GPIO chip in range\n");
1657 return -EINVAL;
1658 }
1659 chip = range->gc;
1660 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1661
1662 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1663
1664 clk_enable(nmk_chip->clk);
1665 bit = offset % NMK_GPIO_PER_CHIP;
1666 /* There is no glitch when converting any pin to GPIO */
1667 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1668 clk_disable(nmk_chip->clk);
1669
1670 return 0;
1671 }
1672
1673 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1674 struct pinctrl_gpio_range *range,
1675 unsigned offset)
1676 {
1677 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1678
1679 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1680 /* Set the pin to some default state, GPIO is usually default */
1681 }
1682
1683 static const struct pinmux_ops nmk_pinmux_ops = {
1684 .get_functions_count = nmk_pmx_get_funcs_cnt,
1685 .get_function_name = nmk_pmx_get_func_name,
1686 .get_function_groups = nmk_pmx_get_func_groups,
1687 .enable = nmk_pmx_enable,
1688 .disable = nmk_pmx_disable,
1689 .gpio_request_enable = nmk_gpio_request_enable,
1690 .gpio_disable_free = nmk_gpio_disable_free,
1691 };
1692
1693 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1694 unsigned long *config)
1695 {
1696 /* Not implemented */
1697 return -EINVAL;
1698 }
1699
1700 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1701 unsigned long config)
1702 {
1703 static const char *pullnames[] = {
1704 [NMK_GPIO_PULL_NONE] = "none",
1705 [NMK_GPIO_PULL_UP] = "up",
1706 [NMK_GPIO_PULL_DOWN] = "down",
1707 [3] /* illegal */ = "??"
1708 };
1709 static const char *slpmnames[] = {
1710 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1711 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1712 };
1713 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1714 struct nmk_gpio_chip *nmk_chip;
1715 struct pinctrl_gpio_range *range;
1716 struct gpio_chip *chip;
1717 unsigned bit;
1718
1719 /*
1720 * The pin config contains pin number and altfunction fields, here
1721 * we just ignore that part. It's being handled by the framework and
1722 * pinmux callback respectively.
1723 */
1724 pin_cfg_t cfg = (pin_cfg_t) config;
1725 int pull = PIN_PULL(cfg);
1726 int slpm = PIN_SLPM(cfg);
1727 int output = PIN_DIR(cfg);
1728 int val = PIN_VAL(cfg);
1729 bool lowemi = PIN_LOWEMI(cfg);
1730 bool gpiomode = PIN_GPIOMODE(cfg);
1731 bool sleep = PIN_SLEEPMODE(cfg);
1732
1733 range = nmk_match_gpio_range(pctldev, pin);
1734 if (!range) {
1735 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1736 return -EINVAL;
1737 }
1738 if (!range->gc) {
1739 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1740 pin);
1741 return -EINVAL;
1742 }
1743 chip = range->gc;
1744 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1745
1746 if (sleep) {
1747 int slpm_pull = PIN_SLPM_PULL(cfg);
1748 int slpm_output = PIN_SLPM_DIR(cfg);
1749 int slpm_val = PIN_SLPM_VAL(cfg);
1750
1751 /* All pins go into GPIO mode at sleep */
1752 gpiomode = true;
1753
1754 /*
1755 * The SLPM_* values are normal values + 1 to allow zero to
1756 * mean "same as normal".
1757 */
1758 if (slpm_pull)
1759 pull = slpm_pull - 1;
1760 if (slpm_output)
1761 output = slpm_output - 1;
1762 if (slpm_val)
1763 val = slpm_val - 1;
1764
1765 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1766 pin,
1767 slpm_pull ? pullnames[pull] : "same",
1768 slpm_output ? (output ? "output" : "input") : "same",
1769 slpm_val ? (val ? "high" : "low") : "same");
1770 }
1771
1772 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1773 pin, cfg, pullnames[pull], slpmnames[slpm],
1774 output ? "output " : "input",
1775 output ? (val ? "high" : "low") : "",
1776 lowemi ? "on" : "off");
1777
1778 clk_enable(nmk_chip->clk);
1779 bit = pin % NMK_GPIO_PER_CHIP;
1780 if (gpiomode)
1781 /* No glitch when going to GPIO mode */
1782 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1783 if (output)
1784 __nmk_gpio_make_output(nmk_chip, bit, val);
1785 else {
1786 __nmk_gpio_make_input(nmk_chip, bit);
1787 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1788 }
1789 /* TODO: isn't this only applicable on output pins? */
1790 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1791
1792 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1793 clk_disable(nmk_chip->clk);
1794 return 0;
1795 }
1796
1797 static const struct pinconf_ops nmk_pinconf_ops = {
1798 .pin_config_get = nmk_pin_config_get,
1799 .pin_config_set = nmk_pin_config_set,
1800 };
1801
1802 static struct pinctrl_desc nmk_pinctrl_desc = {
1803 .name = "pinctrl-nomadik",
1804 .pctlops = &nmk_pinctrl_ops,
1805 .pmxops = &nmk_pinmux_ops,
1806 .confops = &nmk_pinconf_ops,
1807 .owner = THIS_MODULE,
1808 };
1809
1810 static const struct of_device_id nmk_pinctrl_match[] = {
1811 {
1812 .compatible = "stericsson,stn8815-pinctrl",
1813 .data = (void *)PINCTRL_NMK_STN8815,
1814 },
1815 {
1816 .compatible = "stericsson,db8500-pinctrl",
1817 .data = (void *)PINCTRL_NMK_DB8500,
1818 },
1819 {
1820 .compatible = "stericsson,db8540-pinctrl",
1821 .data = (void *)PINCTRL_NMK_DB8540,
1822 },
1823 {},
1824 };
1825
1826 static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
1827 {
1828 struct nmk_pinctrl *npct;
1829
1830 npct = platform_get_drvdata(pdev);
1831 if (!npct)
1832 return -EINVAL;
1833
1834 return pinctrl_force_sleep(npct->pctl);
1835 }
1836
1837 static int nmk_pinctrl_resume(struct platform_device *pdev)
1838 {
1839 struct nmk_pinctrl *npct;
1840
1841 npct = platform_get_drvdata(pdev);
1842 if (!npct)
1843 return -EINVAL;
1844
1845 return pinctrl_force_default(npct->pctl);
1846 }
1847
1848 static int nmk_pinctrl_probe(struct platform_device *pdev)
1849 {
1850 const struct platform_device_id *platid = platform_get_device_id(pdev);
1851 struct device_node *np = pdev->dev.of_node;
1852 struct device_node *prcm_np;
1853 struct nmk_pinctrl *npct;
1854 struct resource *res;
1855 unsigned int version = 0;
1856 int i;
1857
1858 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1859 if (!npct)
1860 return -ENOMEM;
1861
1862 if (platid)
1863 version = platid->driver_data;
1864 else if (np) {
1865 const struct of_device_id *match;
1866
1867 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1868 if (!match)
1869 return -ENODEV;
1870 version = (unsigned int) match->data;
1871 }
1872
1873 /* Poke in other ASIC variants here */
1874 if (version == PINCTRL_NMK_STN8815)
1875 nmk_pinctrl_stn8815_init(&npct->soc);
1876 if (version == PINCTRL_NMK_DB8500)
1877 nmk_pinctrl_db8500_init(&npct->soc);
1878 if (version == PINCTRL_NMK_DB8540)
1879 nmk_pinctrl_db8540_init(&npct->soc);
1880
1881 if (np) {
1882 prcm_np = of_parse_phandle(np, "prcm", 0);
1883 if (prcm_np)
1884 npct->prcm_base = of_iomap(prcm_np, 0);
1885 }
1886
1887 /* Allow platform passed information to over-write DT. */
1888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1889 if (res)
1890 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1891 resource_size(res));
1892 if (!npct->prcm_base) {
1893 if (version == PINCTRL_NMK_STN8815) {
1894 dev_info(&pdev->dev,
1895 "No PRCM base, "
1896 "assuming no ALT-Cx control is available\n");
1897 } else {
1898 dev_err(&pdev->dev, "missing PRCM base address\n");
1899 return -EINVAL;
1900 }
1901 }
1902
1903 /*
1904 * We need all the GPIO drivers to probe FIRST, or we will not be able
1905 * to obtain references to the struct gpio_chip * for them, and we
1906 * need this to proceed.
1907 */
1908 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1909 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
1910 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1911 return -EPROBE_DEFER;
1912 }
1913 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
1914 }
1915
1916 nmk_pinctrl_desc.pins = npct->soc->pins;
1917 nmk_pinctrl_desc.npins = npct->soc->npins;
1918 npct->dev = &pdev->dev;
1919
1920 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1921 if (!npct->pctl) {
1922 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1923 return -EINVAL;
1924 }
1925
1926 /* We will handle a range of GPIO pins */
1927 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1928 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1929
1930 platform_set_drvdata(pdev, npct);
1931 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1932
1933 return 0;
1934 }
1935
1936 static const struct of_device_id nmk_gpio_match[] = {
1937 { .compatible = "st,nomadik-gpio", },
1938 {}
1939 };
1940
1941 static struct platform_driver nmk_gpio_driver = {
1942 .driver = {
1943 .owner = THIS_MODULE,
1944 .name = "gpio",
1945 .of_match_table = nmk_gpio_match,
1946 },
1947 .probe = nmk_gpio_probe,
1948 };
1949
1950 static const struct platform_device_id nmk_pinctrl_id[] = {
1951 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1952 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1953 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1954 { }
1955 };
1956
1957 static struct platform_driver nmk_pinctrl_driver = {
1958 .driver = {
1959 .owner = THIS_MODULE,
1960 .name = "pinctrl-nomadik",
1961 .of_match_table = nmk_pinctrl_match,
1962 },
1963 .probe = nmk_pinctrl_probe,
1964 .id_table = nmk_pinctrl_id,
1965 #ifdef CONFIG_PM
1966 .suspend = nmk_pinctrl_suspend,
1967 .resume = nmk_pinctrl_resume,
1968 #endif
1969 };
1970
1971 static int __init nmk_gpio_init(void)
1972 {
1973 int ret;
1974
1975 ret = platform_driver_register(&nmk_gpio_driver);
1976 if (ret)
1977 return ret;
1978 return platform_driver_register(&nmk_pinctrl_driver);
1979 }
1980
1981 core_initcall(nmk_gpio_init);
1982
1983 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1984 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1985 MODULE_LICENSE("GPL");
Linus' kernel tree