2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
,
43 static __must_check
int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
);
47 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
49 bool map_and_fenceable
);
50 static void i915_gem_clear_fence_reg(struct drm_device
*dev
,
51 struct drm_i915_fence_reg
*reg
);
52 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
53 struct drm_i915_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file
);
56 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
);
58 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
67 dev_priv
->mm
.object_count
++;
68 dev_priv
->mm
.object_memory
+= size
;
71 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
74 dev_priv
->mm
.object_count
--;
75 dev_priv
->mm
.object_memory
-= size
;
79 i915_gem_wait_for_error(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 struct completion
*x
= &dev_priv
->error_completion
;
86 if (!atomic_read(&dev_priv
->mm
.wedged
))
89 ret
= wait_for_completion_interruptible(x
);
93 if (atomic_read(&dev_priv
->mm
.wedged
)) {
94 /* GPU is hung, bump the completion count to account for
95 * the token we just consumed so that we never hit zero and
96 * end up waiting upon a subsequent completion event that
99 spin_lock_irqsave(&x
->wait
.lock
, flags
);
101 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
106 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
110 ret
= i915_gem_wait_for_error(dev
);
114 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
118 WARN_ON(i915_verify_lists(dev
));
123 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
125 return obj
->gtt_space
&& !obj
->active
&& obj
->pin_count
== 0;
128 void i915_gem_do_init(struct drm_device
*dev
,
130 unsigned long mappable_end
,
133 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
135 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
);
137 dev_priv
->mm
.gtt_start
= start
;
138 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
139 dev_priv
->mm
.gtt_end
= end
;
140 dev_priv
->mm
.gtt_total
= end
- start
;
141 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
143 /* Take over this portion of the GTT */
144 intel_gtt_clear_range(start
/ PAGE_SIZE
, (end
-start
) / PAGE_SIZE
);
148 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_gem_init
*args
= data
;
153 if (args
->gtt_start
>= args
->gtt_end
||
154 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
157 mutex_lock(&dev
->struct_mutex
);
158 i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
159 mutex_unlock(&dev
->struct_mutex
);
165 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
166 struct drm_file
*file
)
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
169 struct drm_i915_gem_get_aperture
*args
= data
;
170 struct drm_i915_gem_object
*obj
;
173 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
177 mutex_lock(&dev
->struct_mutex
);
178 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
179 pinned
+= obj
->gtt_space
->size
;
180 mutex_unlock(&dev
->struct_mutex
);
182 args
->aper_size
= dev_priv
->mm
.gtt_total
;
183 args
->aper_available_size
= args
->aper_size
-pinned
;
189 * Creates a new mm object and returns a handle to it.
192 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
193 struct drm_file
*file
)
195 struct drm_i915_gem_create
*args
= data
;
196 struct drm_i915_gem_object
*obj
;
200 args
->size
= roundup(args
->size
, PAGE_SIZE
);
202 /* Allocate the new object */
203 obj
= i915_gem_alloc_object(dev
, args
->size
);
207 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
209 drm_gem_object_release(&obj
->base
);
210 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
215 /* drop reference from allocate - handle holds it now */
216 drm_gem_object_unreference(&obj
->base
);
217 trace_i915_gem_object_create(obj
);
219 args
->handle
= handle
;
223 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
225 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
227 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
228 obj
->tiling_mode
!= I915_TILING_NONE
;
232 slow_shmem_copy(struct page
*dst_page
,
234 struct page
*src_page
,
238 char *dst_vaddr
, *src_vaddr
;
240 dst_vaddr
= kmap(dst_page
);
241 src_vaddr
= kmap(src_page
);
243 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
250 slow_shmem_bit17_copy(struct page
*gpu_page
,
252 struct page
*cpu_page
,
257 char *gpu_vaddr
, *cpu_vaddr
;
259 /* Use the unswizzled path if this page isn't affected. */
260 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
262 return slow_shmem_copy(cpu_page
, cpu_offset
,
263 gpu_page
, gpu_offset
, length
);
265 return slow_shmem_copy(gpu_page
, gpu_offset
,
266 cpu_page
, cpu_offset
, length
);
269 gpu_vaddr
= kmap(gpu_page
);
270 cpu_vaddr
= kmap(cpu_page
);
272 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
273 * XORing with the other bits (A9 for Y, A9 and A10 for X)
276 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
277 int this_length
= min(cacheline_end
- gpu_offset
, length
);
278 int swizzled_gpu_offset
= gpu_offset
^ 64;
281 memcpy(cpu_vaddr
+ cpu_offset
,
282 gpu_vaddr
+ swizzled_gpu_offset
,
285 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
286 cpu_vaddr
+ cpu_offset
,
289 cpu_offset
+= this_length
;
290 gpu_offset
+= this_length
;
291 length
-= this_length
;
299 * This is the fast shmem pread path, which attempts to copy_from_user directly
300 * from the backing pages of the object to the user's address space. On a
301 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
304 i915_gem_shmem_pread_fast(struct drm_device
*dev
,
305 struct drm_i915_gem_object
*obj
,
306 struct drm_i915_gem_pread
*args
,
307 struct drm_file
*file
)
309 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
312 char __user
*user_data
;
313 int page_offset
, page_length
;
315 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
318 offset
= args
->offset
;
325 /* Operation in this page
327 * page_offset = offset within page
328 * page_length = bytes to copy for this page
330 page_offset
= offset
& (PAGE_SIZE
-1);
331 page_length
= remain
;
332 if ((page_offset
+ remain
) > PAGE_SIZE
)
333 page_length
= PAGE_SIZE
- page_offset
;
335 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
336 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
338 return PTR_ERR(page
);
340 vaddr
= kmap_atomic(page
);
341 ret
= __copy_to_user_inatomic(user_data
,
344 kunmap_atomic(vaddr
);
346 mark_page_accessed(page
);
347 page_cache_release(page
);
351 remain
-= page_length
;
352 user_data
+= page_length
;
353 offset
+= page_length
;
360 * This is the fallback shmem pread path, which allocates temporary storage
361 * in kernel space to copy_to_user into outside of the struct_mutex, so we
362 * can copy out of the object's backing pages while holding the struct mutex
363 * and not take page faults.
366 i915_gem_shmem_pread_slow(struct drm_device
*dev
,
367 struct drm_i915_gem_object
*obj
,
368 struct drm_i915_gem_pread
*args
,
369 struct drm_file
*file
)
371 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
372 struct mm_struct
*mm
= current
->mm
;
373 struct page
**user_pages
;
375 loff_t offset
, pinned_pages
, i
;
376 loff_t first_data_page
, last_data_page
, num_pages
;
377 int shmem_page_offset
;
378 int data_page_index
, data_page_offset
;
381 uint64_t data_ptr
= args
->data_ptr
;
382 int do_bit17_swizzling
;
386 /* Pin the user pages containing the data. We can't fault while
387 * holding the struct mutex, yet we want to hold it while
388 * dereferencing the user data.
390 first_data_page
= data_ptr
/ PAGE_SIZE
;
391 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
392 num_pages
= last_data_page
- first_data_page
+ 1;
394 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
395 if (user_pages
== NULL
)
398 mutex_unlock(&dev
->struct_mutex
);
399 down_read(&mm
->mmap_sem
);
400 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
401 num_pages
, 1, 0, user_pages
, NULL
);
402 up_read(&mm
->mmap_sem
);
403 mutex_lock(&dev
->struct_mutex
);
404 if (pinned_pages
< num_pages
) {
409 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
415 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
417 offset
= args
->offset
;
422 /* Operation in this page
424 * shmem_page_offset = offset within page in shmem file
425 * data_page_index = page number in get_user_pages return
426 * data_page_offset = offset with data_page_index page.
427 * page_length = bytes to copy for this page
429 shmem_page_offset
= offset
& ~PAGE_MASK
;
430 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
431 data_page_offset
= data_ptr
& ~PAGE_MASK
;
433 page_length
= remain
;
434 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
435 page_length
= PAGE_SIZE
- shmem_page_offset
;
436 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
437 page_length
= PAGE_SIZE
- data_page_offset
;
439 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
440 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
442 return PTR_ERR(page
);
444 if (do_bit17_swizzling
) {
445 slow_shmem_bit17_copy(page
,
447 user_pages
[data_page_index
],
452 slow_shmem_copy(user_pages
[data_page_index
],
459 mark_page_accessed(page
);
460 page_cache_release(page
);
462 remain
-= page_length
;
463 data_ptr
+= page_length
;
464 offset
+= page_length
;
468 for (i
= 0; i
< pinned_pages
; i
++) {
469 SetPageDirty(user_pages
[i
]);
470 mark_page_accessed(user_pages
[i
]);
471 page_cache_release(user_pages
[i
]);
473 drm_free_large(user_pages
);
479 * Reads data from the object referenced by handle.
481 * On error, the contents of *data are undefined.
484 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
485 struct drm_file
*file
)
487 struct drm_i915_gem_pread
*args
= data
;
488 struct drm_i915_gem_object
*obj
;
494 if (!access_ok(VERIFY_WRITE
,
495 (char __user
*)(uintptr_t)args
->data_ptr
,
499 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
504 ret
= i915_mutex_lock_interruptible(dev
);
508 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
514 /* Bounds check source. */
515 if (args
->offset
> obj
->base
.size
||
516 args
->size
> obj
->base
.size
- args
->offset
) {
521 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
523 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
530 if (!i915_gem_object_needs_bit17_swizzle(obj
))
531 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file
);
533 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file
);
536 drm_gem_object_unreference(&obj
->base
);
538 mutex_unlock(&dev
->struct_mutex
);
542 /* This is the fast write path which cannot handle
543 * page faults in the source data
547 fast_user_write(struct io_mapping
*mapping
,
548 loff_t page_base
, int page_offset
,
549 char __user
*user_data
,
553 unsigned long unwritten
;
555 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
556 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
558 io_mapping_unmap_atomic(vaddr_atomic
);
562 /* Here's the write path which can sleep for
567 slow_kernel_write(struct io_mapping
*mapping
,
568 loff_t gtt_base
, int gtt_offset
,
569 struct page
*user_page
, int user_offset
,
572 char __iomem
*dst_vaddr
;
575 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
576 src_vaddr
= kmap(user_page
);
578 memcpy_toio(dst_vaddr
+ gtt_offset
,
579 src_vaddr
+ user_offset
,
583 io_mapping_unmap(dst_vaddr
);
587 * This is the fast pwrite path, where we copy the data directly from the
588 * user into the GTT, uncached.
591 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
592 struct drm_i915_gem_object
*obj
,
593 struct drm_i915_gem_pwrite
*args
,
594 struct drm_file
*file
)
596 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
598 loff_t offset
, page_base
;
599 char __user
*user_data
;
600 int page_offset
, page_length
;
602 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
605 offset
= obj
->gtt_offset
+ args
->offset
;
608 /* Operation in this page
610 * page_base = page offset within aperture
611 * page_offset = offset within page
612 * page_length = bytes to copy for this page
614 page_base
= (offset
& ~(PAGE_SIZE
-1));
615 page_offset
= offset
& (PAGE_SIZE
-1);
616 page_length
= remain
;
617 if ((page_offset
+ remain
) > PAGE_SIZE
)
618 page_length
= PAGE_SIZE
- page_offset
;
620 /* If we get a fault while copying data, then (presumably) our
621 * source page isn't available. Return the error and we'll
622 * retry in the slow path.
624 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
625 page_offset
, user_data
, page_length
))
629 remain
-= page_length
;
630 user_data
+= page_length
;
631 offset
+= page_length
;
638 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
639 * the memory and maps it using kmap_atomic for copying.
641 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
642 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
645 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
,
646 struct drm_i915_gem_object
*obj
,
647 struct drm_i915_gem_pwrite
*args
,
648 struct drm_file
*file
)
650 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
652 loff_t gtt_page_base
, offset
;
653 loff_t first_data_page
, last_data_page
, num_pages
;
654 loff_t pinned_pages
, i
;
655 struct page
**user_pages
;
656 struct mm_struct
*mm
= current
->mm
;
657 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
659 uint64_t data_ptr
= args
->data_ptr
;
663 /* Pin the user pages containing the data. We can't fault while
664 * holding the struct mutex, and all of the pwrite implementations
665 * want to hold it while dereferencing the user data.
667 first_data_page
= data_ptr
/ PAGE_SIZE
;
668 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
669 num_pages
= last_data_page
- first_data_page
+ 1;
671 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
672 if (user_pages
== NULL
)
675 mutex_unlock(&dev
->struct_mutex
);
676 down_read(&mm
->mmap_sem
);
677 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
678 num_pages
, 0, 0, user_pages
, NULL
);
679 up_read(&mm
->mmap_sem
);
680 mutex_lock(&dev
->struct_mutex
);
681 if (pinned_pages
< num_pages
) {
683 goto out_unpin_pages
;
686 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
688 goto out_unpin_pages
;
690 ret
= i915_gem_object_put_fence(obj
);
692 goto out_unpin_pages
;
694 offset
= obj
->gtt_offset
+ args
->offset
;
697 /* Operation in this page
699 * gtt_page_base = page offset within aperture
700 * gtt_page_offset = offset within page in aperture
701 * data_page_index = page number in get_user_pages return
702 * data_page_offset = offset with data_page_index page.
703 * page_length = bytes to copy for this page
705 gtt_page_base
= offset
& PAGE_MASK
;
706 gtt_page_offset
= offset
& ~PAGE_MASK
;
707 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
708 data_page_offset
= data_ptr
& ~PAGE_MASK
;
710 page_length
= remain
;
711 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
712 page_length
= PAGE_SIZE
- gtt_page_offset
;
713 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
714 page_length
= PAGE_SIZE
- data_page_offset
;
716 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
717 gtt_page_base
, gtt_page_offset
,
718 user_pages
[data_page_index
],
722 remain
-= page_length
;
723 offset
+= page_length
;
724 data_ptr
+= page_length
;
728 for (i
= 0; i
< pinned_pages
; i
++)
729 page_cache_release(user_pages
[i
]);
730 drm_free_large(user_pages
);
736 * This is the fast shmem pwrite path, which attempts to directly
737 * copy_from_user into the kmapped pages backing the object.
740 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
,
741 struct drm_i915_gem_object
*obj
,
742 struct drm_i915_gem_pwrite
*args
,
743 struct drm_file
*file
)
745 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
748 char __user
*user_data
;
749 int page_offset
, page_length
;
751 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
754 offset
= args
->offset
;
762 /* Operation in this page
764 * page_offset = offset within page
765 * page_length = bytes to copy for this page
767 page_offset
= offset
& (PAGE_SIZE
-1);
768 page_length
= remain
;
769 if ((page_offset
+ remain
) > PAGE_SIZE
)
770 page_length
= PAGE_SIZE
- page_offset
;
772 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
773 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
775 return PTR_ERR(page
);
777 vaddr
= kmap_atomic(page
, KM_USER0
);
778 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
781 kunmap_atomic(vaddr
, KM_USER0
);
783 set_page_dirty(page
);
784 mark_page_accessed(page
);
785 page_cache_release(page
);
787 /* If we get a fault while copying data, then (presumably) our
788 * source page isn't available. Return the error and we'll
789 * retry in the slow path.
794 remain
-= page_length
;
795 user_data
+= page_length
;
796 offset
+= page_length
;
803 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
804 * the memory and maps it using kmap_atomic for copying.
806 * This avoids taking mmap_sem for faulting on the user's address while the
807 * struct_mutex is held.
810 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
,
811 struct drm_i915_gem_object
*obj
,
812 struct drm_i915_gem_pwrite
*args
,
813 struct drm_file
*file
)
815 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
816 struct mm_struct
*mm
= current
->mm
;
817 struct page
**user_pages
;
819 loff_t offset
, pinned_pages
, i
;
820 loff_t first_data_page
, last_data_page
, num_pages
;
821 int shmem_page_offset
;
822 int data_page_index
, data_page_offset
;
825 uint64_t data_ptr
= args
->data_ptr
;
826 int do_bit17_swizzling
;
830 /* Pin the user pages containing the data. We can't fault while
831 * holding the struct mutex, and all of the pwrite implementations
832 * want to hold it while dereferencing the user data.
834 first_data_page
= data_ptr
/ PAGE_SIZE
;
835 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
836 num_pages
= last_data_page
- first_data_page
+ 1;
838 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
839 if (user_pages
== NULL
)
842 mutex_unlock(&dev
->struct_mutex
);
843 down_read(&mm
->mmap_sem
);
844 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
845 num_pages
, 0, 0, user_pages
, NULL
);
846 up_read(&mm
->mmap_sem
);
847 mutex_lock(&dev
->struct_mutex
);
848 if (pinned_pages
< num_pages
) {
853 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
857 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
859 offset
= args
->offset
;
865 /* Operation in this page
867 * shmem_page_offset = offset within page in shmem file
868 * data_page_index = page number in get_user_pages return
869 * data_page_offset = offset with data_page_index page.
870 * page_length = bytes to copy for this page
872 shmem_page_offset
= offset
& ~PAGE_MASK
;
873 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
874 data_page_offset
= data_ptr
& ~PAGE_MASK
;
876 page_length
= remain
;
877 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
878 page_length
= PAGE_SIZE
- shmem_page_offset
;
879 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
880 page_length
= PAGE_SIZE
- data_page_offset
;
882 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
883 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
889 if (do_bit17_swizzling
) {
890 slow_shmem_bit17_copy(page
,
892 user_pages
[data_page_index
],
897 slow_shmem_copy(page
,
899 user_pages
[data_page_index
],
904 set_page_dirty(page
);
905 mark_page_accessed(page
);
906 page_cache_release(page
);
908 remain
-= page_length
;
909 data_ptr
+= page_length
;
910 offset
+= page_length
;
914 for (i
= 0; i
< pinned_pages
; i
++)
915 page_cache_release(user_pages
[i
]);
916 drm_free_large(user_pages
);
922 * Writes data to the object referenced by handle.
924 * On error, the contents of the buffer that were to be modified are undefined.
927 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
928 struct drm_file
*file
)
930 struct drm_i915_gem_pwrite
*args
= data
;
931 struct drm_i915_gem_object
*obj
;
937 if (!access_ok(VERIFY_READ
,
938 (char __user
*)(uintptr_t)args
->data_ptr
,
942 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
947 ret
= i915_mutex_lock_interruptible(dev
);
951 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
957 /* Bounds check destination. */
958 if (args
->offset
> obj
->base
.size
||
959 args
->size
> obj
->base
.size
- args
->offset
) {
964 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
973 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
974 else if (obj
->gtt_space
&&
975 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
976 ret
= i915_gem_object_pin(obj
, 0, true);
980 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
984 ret
= i915_gem_object_put_fence(obj
);
988 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
990 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
993 i915_gem_object_unpin(obj
);
995 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1000 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1001 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1003 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1007 drm_gem_object_unreference(&obj
->base
);
1009 mutex_unlock(&dev
->struct_mutex
);
1014 * Called when user space prepares to use an object with the CPU, either
1015 * through the mmap ioctl's mapping or a GTT mapping.
1018 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1019 struct drm_file
*file
)
1021 struct drm_i915_gem_set_domain
*args
= data
;
1022 struct drm_i915_gem_object
*obj
;
1023 uint32_t read_domains
= args
->read_domains
;
1024 uint32_t write_domain
= args
->write_domain
;
1027 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1030 /* Only handle setting domains to types used by the CPU. */
1031 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1034 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1037 /* Having something in the write domain implies it's in the read
1038 * domain, and only that read domain. Enforce that in the request.
1040 if (write_domain
!= 0 && read_domains
!= write_domain
)
1043 ret
= i915_mutex_lock_interruptible(dev
);
1047 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1053 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1054 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1056 /* Silently promote "you're not bound, there was nothing to do"
1057 * to success, since the client was just asking us to
1058 * make sure everything was done.
1063 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1066 drm_gem_object_unreference(&obj
->base
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file
)
1079 struct drm_i915_gem_sw_finish
*args
= data
;
1080 struct drm_i915_gem_object
*obj
;
1083 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1086 ret
= i915_mutex_lock_interruptible(dev
);
1090 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1096 /* Pinned buffers may be scanout, so flush the cache */
1098 i915_gem_object_flush_cpu_write_domain(obj
);
1100 drm_gem_object_unreference(&obj
->base
);
1102 mutex_unlock(&dev
->struct_mutex
);
1107 * Maps the contents of an object, returning the address it is mapped
1110 * While the mapping holds a reference on the contents of the object, it doesn't
1111 * imply a ref on the object itself.
1114 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1115 struct drm_file
*file
)
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1118 struct drm_i915_gem_mmap
*args
= data
;
1119 struct drm_gem_object
*obj
;
1122 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1125 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1129 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1130 drm_gem_object_unreference_unlocked(obj
);
1134 down_write(¤t
->mm
->mmap_sem
);
1135 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1136 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1138 up_write(¤t
->mm
->mmap_sem
);
1139 drm_gem_object_unreference_unlocked(obj
);
1140 if (IS_ERR((void *)addr
))
1143 args
->addr_ptr
= (uint64_t) addr
;
1149 * i915_gem_fault - fault a page into the GTT
1150 * vma: VMA in question
1153 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154 * from userspace. The fault handler takes care of binding the object to
1155 * the GTT (if needed), allocating and programming a fence register (again,
1156 * only if needed based on whether the old reg is still valid or the object
1157 * is tiled) and inserting a new PTE into the faulting process.
1159 * Note that the faulting process may involve evicting existing objects
1160 * from the GTT and/or fence registers to make room. So performance may
1161 * suffer if the GTT working set is large or there are few fence registers
1164 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1166 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1167 struct drm_device
*dev
= obj
->base
.dev
;
1168 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1169 pgoff_t page_offset
;
1172 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1174 /* We don't use vmf->pgoff since that has the fake offset */
1175 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1178 ret
= i915_mutex_lock_interruptible(dev
);
1182 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1184 /* Now bind it into the GTT if needed */
1185 if (!obj
->map_and_fenceable
) {
1186 ret
= i915_gem_object_unbind(obj
);
1190 if (!obj
->gtt_space
) {
1191 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1196 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1200 if (obj
->tiling_mode
== I915_TILING_NONE
)
1201 ret
= i915_gem_object_put_fence(obj
);
1203 ret
= i915_gem_object_get_fence(obj
, NULL
, true);
1207 if (i915_gem_object_is_inactive(obj
))
1208 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1210 obj
->fault_mappable
= true;
1212 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1215 /* Finally, remap it using the new GTT offset */
1216 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1218 mutex_unlock(&dev
->struct_mutex
);
1223 /* Give the error handler a chance to run and move the
1224 * objects off the GPU active list. Next time we service the
1225 * fault, we should be able to transition the page into the
1226 * GTT without touching the GPU (and so avoid further
1227 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1228 * with coherency, just lost writes.
1234 return VM_FAULT_NOPAGE
;
1236 return VM_FAULT_OOM
;
1238 return VM_FAULT_SIGBUS
;
1243 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1244 * @obj: obj in question
1246 * GEM memory mapping works by handing back to userspace a fake mmap offset
1247 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1248 * up the object based on the offset and sets up the various memory mapping
1251 * This routine allocates and attaches a fake offset for @obj.
1254 i915_gem_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1256 struct drm_device
*dev
= obj
->base
.dev
;
1257 struct drm_gem_mm
*mm
= dev
->mm_private
;
1258 struct drm_map_list
*list
;
1259 struct drm_local_map
*map
;
1262 /* Set the object up for mmap'ing */
1263 list
= &obj
->base
.map_list
;
1264 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1269 map
->type
= _DRM_GEM
;
1270 map
->size
= obj
->base
.size
;
1273 /* Get a DRM GEM mmap offset allocated... */
1274 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1275 obj
->base
.size
/ PAGE_SIZE
,
1277 if (!list
->file_offset_node
) {
1278 DRM_ERROR("failed to allocate offset for bo %d\n",
1284 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1285 obj
->base
.size
/ PAGE_SIZE
,
1287 if (!list
->file_offset_node
) {
1292 list
->hash
.key
= list
->file_offset_node
->start
;
1293 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1295 DRM_ERROR("failed to add to map hash\n");
1302 drm_mm_put_block(list
->file_offset_node
);
1311 * i915_gem_release_mmap - remove physical page mappings
1312 * @obj: obj in question
1314 * Preserve the reservation of the mmapping with the DRM core code, but
1315 * relinquish ownership of the pages back to the system.
1317 * It is vital that we remove the page mapping if we have mapped a tiled
1318 * object through the GTT and then lose the fence register due to
1319 * resource pressure. Similarly if the object has been moved out of the
1320 * aperture, than pages mapped into userspace must be revoked. Removing the
1321 * mapping will then trigger a page fault on the next user access, allowing
1322 * fixup by i915_gem_fault().
1325 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1327 if (!obj
->fault_mappable
)
1330 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1331 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1334 obj
->fault_mappable
= false;
1338 i915_gem_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1340 struct drm_device
*dev
= obj
->base
.dev
;
1341 struct drm_gem_mm
*mm
= dev
->mm_private
;
1342 struct drm_map_list
*list
= &obj
->base
.map_list
;
1344 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1345 drm_mm_put_block(list
->file_offset_node
);
1351 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj
)
1353 struct drm_device
*dev
= obj
->base
.dev
;
1356 if (INTEL_INFO(dev
)->gen
>= 4 ||
1357 obj
->tiling_mode
== I915_TILING_NONE
)
1358 return obj
->base
.size
;
1360 /* Previous chips need a power-of-two fence region when tiling */
1361 if (INTEL_INFO(dev
)->gen
== 3)
1366 while (size
< obj
->base
.size
)
1373 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1374 * @obj: object to check
1376 * Return the required GTT alignment for an object, taking into account
1377 * potential fence register mapping.
1380 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj
)
1382 struct drm_device
*dev
= obj
->base
.dev
;
1385 * Minimum alignment is 4k (GTT page size), but might be greater
1386 * if a fence register is needed for the object.
1388 if (INTEL_INFO(dev
)->gen
>= 4 ||
1389 obj
->tiling_mode
== I915_TILING_NONE
)
1393 * Previous chips need to be aligned to the size of the smallest
1394 * fence register that can contain the object.
1396 return i915_gem_get_gtt_size(obj
);
1400 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1402 * @obj: object to check
1404 * Return the required GTT alignment for an object, only taking into account
1405 * unfenced tiled surface requirements.
1408 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj
)
1410 struct drm_device
*dev
= obj
->base
.dev
;
1414 * Minimum alignment is 4k (GTT page size) for sane hw.
1416 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1417 obj
->tiling_mode
== I915_TILING_NONE
)
1421 * Older chips need unfenced tiled buffers to be aligned to the left
1422 * edge of an even tile row (where tile rows are counted as if the bo is
1423 * placed in a fenced gtt region).
1426 (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
1431 return tile_height
* obj
->stride
* 2;
1435 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1437 * @data: GTT mapping ioctl data
1438 * @file: GEM object info
1440 * Simply returns the fake offset to userspace so it can mmap it.
1441 * The mmap call will end up in drm_gem_mmap(), which will set things
1442 * up so we can get faults in the handler above.
1444 * The fault handler will take care of binding the object into the GTT
1445 * (since it may have been evicted to make room for something), allocating
1446 * a fence register, and mapping the appropriate aperture address into
1450 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1451 struct drm_file
*file
)
1453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1454 struct drm_i915_gem_mmap_gtt
*args
= data
;
1455 struct drm_i915_gem_object
*obj
;
1458 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1461 ret
= i915_mutex_lock_interruptible(dev
);
1465 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1471 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1476 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1477 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1482 if (!obj
->base
.map_list
.map
) {
1483 ret
= i915_gem_create_mmap_offset(obj
);
1488 args
->offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1491 drm_gem_object_unreference(&obj
->base
);
1493 mutex_unlock(&dev
->struct_mutex
);
1498 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1502 struct address_space
*mapping
;
1503 struct inode
*inode
;
1506 /* Get the list of pages out of our struct file. They'll be pinned
1507 * at this point until we release them.
1509 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1510 BUG_ON(obj
->pages
!= NULL
);
1511 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1512 if (obj
->pages
== NULL
)
1515 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1516 mapping
= inode
->i_mapping
;
1517 for (i
= 0; i
< page_count
; i
++) {
1518 page
= read_cache_page_gfp(mapping
, i
,
1526 obj
->pages
[i
] = page
;
1529 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1530 i915_gem_object_do_bit_17_swizzle(obj
);
1536 page_cache_release(obj
->pages
[i
]);
1538 drm_free_large(obj
->pages
);
1540 return PTR_ERR(page
);
1544 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1546 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1549 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1551 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1552 i915_gem_object_save_bit_17_swizzle(obj
);
1554 if (obj
->madv
== I915_MADV_DONTNEED
)
1557 for (i
= 0; i
< page_count
; i
++) {
1559 set_page_dirty(obj
->pages
[i
]);
1561 if (obj
->madv
== I915_MADV_WILLNEED
)
1562 mark_page_accessed(obj
->pages
[i
]);
1564 page_cache_release(obj
->pages
[i
]);
1568 drm_free_large(obj
->pages
);
1573 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1574 struct intel_ring_buffer
*ring
,
1577 struct drm_device
*dev
= obj
->base
.dev
;
1578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1580 BUG_ON(ring
== NULL
);
1583 /* Add a reference if we're newly entering the active list. */
1585 drm_gem_object_reference(&obj
->base
);
1589 /* Move from whatever list we were on to the tail of execution. */
1590 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1591 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1593 obj
->last_rendering_seqno
= seqno
;
1594 if (obj
->fenced_gpu_access
) {
1595 struct drm_i915_fence_reg
*reg
;
1597 BUG_ON(obj
->fence_reg
== I915_FENCE_REG_NONE
);
1599 obj
->last_fenced_seqno
= seqno
;
1600 obj
->last_fenced_ring
= ring
;
1602 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1603 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
1608 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1610 list_del_init(&obj
->ring_list
);
1611 obj
->last_rendering_seqno
= 0;
1615 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1617 struct drm_device
*dev
= obj
->base
.dev
;
1618 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1620 BUG_ON(!obj
->active
);
1621 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1623 i915_gem_object_move_off_active(obj
);
1627 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1629 struct drm_device
*dev
= obj
->base
.dev
;
1630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 if (obj
->pin_count
!= 0)
1633 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.pinned_list
);
1635 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1637 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1638 BUG_ON(!obj
->active
);
1641 i915_gem_object_move_off_active(obj
);
1642 obj
->fenced_gpu_access
= false;
1645 obj
->pending_gpu_write
= false;
1646 drm_gem_object_unreference(&obj
->base
);
1648 WARN_ON(i915_verify_lists(dev
));
1651 /* Immediately discard the backing storage */
1653 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1655 struct inode
*inode
;
1657 /* Our goal here is to return as much of the memory as
1658 * is possible back to the system as we are called from OOM.
1659 * To do this we must instruct the shmfs to drop all of its
1660 * backing pages, *now*. Here we mirror the actions taken
1661 * when by shmem_delete_inode() to release the backing store.
1663 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1664 truncate_inode_pages(inode
->i_mapping
, 0);
1665 if (inode
->i_op
->truncate_range
)
1666 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1668 obj
->madv
= __I915_MADV_PURGED
;
1672 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1674 return obj
->madv
== I915_MADV_DONTNEED
;
1678 i915_gem_process_flushing_list(struct intel_ring_buffer
*ring
,
1679 uint32_t flush_domains
)
1681 struct drm_i915_gem_object
*obj
, *next
;
1683 list_for_each_entry_safe(obj
, next
,
1684 &ring
->gpu_write_list
,
1686 if (obj
->base
.write_domain
& flush_domains
) {
1687 uint32_t old_write_domain
= obj
->base
.write_domain
;
1689 obj
->base
.write_domain
= 0;
1690 list_del_init(&obj
->gpu_write_list
);
1691 i915_gem_object_move_to_active(obj
, ring
,
1692 i915_gem_next_request_seqno(ring
));
1694 trace_i915_gem_object_change_domain(obj
,
1695 obj
->base
.read_domains
,
1702 i915_add_request(struct intel_ring_buffer
*ring
,
1703 struct drm_file
*file
,
1704 struct drm_i915_gem_request
*request
)
1706 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1711 BUG_ON(request
== NULL
);
1713 ret
= ring
->add_request(ring
, &seqno
);
1717 trace_i915_gem_request_add(ring
, seqno
);
1719 request
->seqno
= seqno
;
1720 request
->ring
= ring
;
1721 request
->emitted_jiffies
= jiffies
;
1722 was_empty
= list_empty(&ring
->request_list
);
1723 list_add_tail(&request
->list
, &ring
->request_list
);
1726 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1728 spin_lock(&file_priv
->mm
.lock
);
1729 request
->file_priv
= file_priv
;
1730 list_add_tail(&request
->client_list
,
1731 &file_priv
->mm
.request_list
);
1732 spin_unlock(&file_priv
->mm
.lock
);
1735 ring
->outstanding_lazy_request
= false;
1737 if (!dev_priv
->mm
.suspended
) {
1738 mod_timer(&dev_priv
->hangcheck_timer
,
1739 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1741 queue_delayed_work(dev_priv
->wq
,
1742 &dev_priv
->mm
.retire_work
, HZ
);
1748 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1750 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1755 spin_lock(&file_priv
->mm
.lock
);
1756 list_del(&request
->client_list
);
1757 request
->file_priv
= NULL
;
1758 spin_unlock(&file_priv
->mm
.lock
);
1761 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1762 struct intel_ring_buffer
*ring
)
1764 while (!list_empty(&ring
->request_list
)) {
1765 struct drm_i915_gem_request
*request
;
1767 request
= list_first_entry(&ring
->request_list
,
1768 struct drm_i915_gem_request
,
1771 list_del(&request
->list
);
1772 i915_gem_request_remove_from_client(request
);
1776 while (!list_empty(&ring
->active_list
)) {
1777 struct drm_i915_gem_object
*obj
;
1779 obj
= list_first_entry(&ring
->active_list
,
1780 struct drm_i915_gem_object
,
1783 obj
->base
.write_domain
= 0;
1784 list_del_init(&obj
->gpu_write_list
);
1785 i915_gem_object_move_to_inactive(obj
);
1789 static void i915_gem_reset_fences(struct drm_device
*dev
)
1791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1794 for (i
= 0; i
< 16; i
++) {
1795 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1796 struct drm_i915_gem_object
*obj
= reg
->obj
;
1801 if (obj
->tiling_mode
)
1802 i915_gem_release_mmap(obj
);
1804 reg
->obj
->fence_reg
= I915_FENCE_REG_NONE
;
1805 reg
->obj
->fenced_gpu_access
= false;
1806 reg
->obj
->last_fenced_seqno
= 0;
1807 reg
->obj
->last_fenced_ring
= NULL
;
1808 i915_gem_clear_fence_reg(dev
, reg
);
1812 void i915_gem_reset(struct drm_device
*dev
)
1814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1815 struct drm_i915_gem_object
*obj
;
1818 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1819 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->ring
[i
]);
1821 /* Remove anything from the flushing lists. The GPU cache is likely
1822 * to be lost on reset along with the data, so simply move the
1823 * lost bo to the inactive list.
1825 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1826 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1827 struct drm_i915_gem_object
,
1830 obj
->base
.write_domain
= 0;
1831 list_del_init(&obj
->gpu_write_list
);
1832 i915_gem_object_move_to_inactive(obj
);
1835 /* Move everything out of the GPU domains to ensure we do any
1836 * necessary invalidation upon reuse.
1838 list_for_each_entry(obj
,
1839 &dev_priv
->mm
.inactive_list
,
1842 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1845 /* The fence registers are invalidated so clear them out */
1846 i915_gem_reset_fences(dev
);
1850 * This function clears the request list as sequence numbers are passed.
1853 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1858 if (list_empty(&ring
->request_list
))
1861 WARN_ON(i915_verify_lists(ring
->dev
));
1863 seqno
= ring
->get_seqno(ring
);
1865 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1866 if (seqno
>= ring
->sync_seqno
[i
])
1867 ring
->sync_seqno
[i
] = 0;
1869 while (!list_empty(&ring
->request_list
)) {
1870 struct drm_i915_gem_request
*request
;
1872 request
= list_first_entry(&ring
->request_list
,
1873 struct drm_i915_gem_request
,
1876 if (!i915_seqno_passed(seqno
, request
->seqno
))
1879 trace_i915_gem_request_retire(ring
, request
->seqno
);
1881 list_del(&request
->list
);
1882 i915_gem_request_remove_from_client(request
);
1886 /* Move any buffers on the active list that are no longer referenced
1887 * by the ringbuffer to the flushing/inactive lists as appropriate.
1889 while (!list_empty(&ring
->active_list
)) {
1890 struct drm_i915_gem_object
*obj
;
1892 obj
= list_first_entry(&ring
->active_list
,
1893 struct drm_i915_gem_object
,
1896 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1899 if (obj
->base
.write_domain
!= 0)
1900 i915_gem_object_move_to_flushing(obj
);
1902 i915_gem_object_move_to_inactive(obj
);
1905 if (unlikely(ring
->trace_irq_seqno
&&
1906 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1907 ring
->irq_put(ring
);
1908 ring
->trace_irq_seqno
= 0;
1911 WARN_ON(i915_verify_lists(ring
->dev
));
1915 i915_gem_retire_requests(struct drm_device
*dev
)
1917 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1920 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1921 struct drm_i915_gem_object
*obj
, *next
;
1923 /* We must be careful that during unbind() we do not
1924 * accidentally infinitely recurse into retire requests.
1926 * retire -> free -> unbind -> wait -> retire_ring
1928 list_for_each_entry_safe(obj
, next
,
1929 &dev_priv
->mm
.deferred_free_list
,
1931 i915_gem_free_object_tail(obj
);
1934 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1935 i915_gem_retire_requests_ring(&dev_priv
->ring
[i
]);
1939 i915_gem_retire_work_handler(struct work_struct
*work
)
1941 drm_i915_private_t
*dev_priv
;
1942 struct drm_device
*dev
;
1946 dev_priv
= container_of(work
, drm_i915_private_t
,
1947 mm
.retire_work
.work
);
1948 dev
= dev_priv
->dev
;
1950 /* Come back later if the device is busy... */
1951 if (!mutex_trylock(&dev
->struct_mutex
)) {
1952 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1956 i915_gem_retire_requests(dev
);
1958 /* Send a periodic flush down the ring so we don't hold onto GEM
1959 * objects indefinitely.
1962 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1963 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
1965 if (!list_empty(&ring
->gpu_write_list
)) {
1966 struct drm_i915_gem_request
*request
;
1969 ret
= i915_gem_flush_ring(ring
,
1970 0, I915_GEM_GPU_DOMAINS
);
1971 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1972 if (ret
|| request
== NULL
||
1973 i915_add_request(ring
, NULL
, request
))
1977 idle
&= list_empty(&ring
->request_list
);
1980 if (!dev_priv
->mm
.suspended
&& !idle
)
1981 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1983 mutex_unlock(&dev
->struct_mutex
);
1987 * Waits for a sequence number to be signaled, and cleans up the
1988 * request and object lists appropriately for that event.
1991 i915_wait_request(struct intel_ring_buffer
*ring
,
1995 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2001 if (atomic_read(&dev_priv
->mm
.wedged
)) {
2002 struct completion
*x
= &dev_priv
->error_completion
;
2003 bool recovery_complete
;
2004 unsigned long flags
;
2006 /* Give the error handler a chance to run. */
2007 spin_lock_irqsave(&x
->wait
.lock
, flags
);
2008 recovery_complete
= x
->done
> 0;
2009 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
2011 return recovery_complete
? -EIO
: -EAGAIN
;
2014 if (seqno
== ring
->outstanding_lazy_request
) {
2015 struct drm_i915_gem_request
*request
;
2017 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2018 if (request
== NULL
)
2021 ret
= i915_add_request(ring
, NULL
, request
);
2027 seqno
= request
->seqno
;
2030 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2031 if (HAS_PCH_SPLIT(ring
->dev
))
2032 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2034 ier
= I915_READ(IER
);
2036 DRM_ERROR("something (likely vbetool) disabled "
2037 "interrupts, re-enabling\n");
2038 i915_driver_irq_preinstall(ring
->dev
);
2039 i915_driver_irq_postinstall(ring
->dev
);
2042 trace_i915_gem_request_wait_begin(ring
, seqno
);
2044 ring
->waiting_seqno
= seqno
;
2045 if (ring
->irq_get(ring
)) {
2047 ret
= wait_event_interruptible(ring
->irq_queue
,
2048 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2049 || atomic_read(&dev_priv
->mm
.wedged
));
2051 wait_event(ring
->irq_queue
,
2052 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2053 || atomic_read(&dev_priv
->mm
.wedged
));
2055 ring
->irq_put(ring
);
2056 } else if (wait_for(i915_seqno_passed(ring
->get_seqno(ring
),
2058 atomic_read(&dev_priv
->mm
.wedged
), 3000))
2060 ring
->waiting_seqno
= 0;
2062 trace_i915_gem_request_wait_end(ring
, seqno
);
2064 if (atomic_read(&dev_priv
->mm
.wedged
))
2067 if (ret
&& ret
!= -ERESTARTSYS
)
2068 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2069 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2070 dev_priv
->next_seqno
);
2072 /* Directly dispatch request retiring. While we have the work queue
2073 * to handle this, the waiter on a request often wants an associated
2074 * buffer to have made it to the inactive list, and we would need
2075 * a separate wait queue to handle that.
2078 i915_gem_retire_requests_ring(ring
);
2084 * Ensures that all rendering to the object has completed and the object is
2085 * safe to unbind from the GTT or access from the CPU.
2088 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
2093 /* This function only exists to support waiting for existing rendering,
2094 * not for emitting required flushes.
2096 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2098 /* If there is rendering queued on the buffer being evicted, wait for
2102 ret
= i915_wait_request(obj
->ring
,
2103 obj
->last_rendering_seqno
,
2113 * Unbinds an object from the GTT aperture.
2116 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2120 if (obj
->gtt_space
== NULL
)
2123 if (obj
->pin_count
!= 0) {
2124 DRM_ERROR("Attempting to unbind pinned buffer\n");
2128 /* blow away mappings if mapped through GTT */
2129 i915_gem_release_mmap(obj
);
2131 /* Move the object to the CPU domain to ensure that
2132 * any possible CPU writes while it's not in the GTT
2133 * are flushed when we go to remap it. This will
2134 * also ensure that all pending GPU writes are finished
2137 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2138 if (ret
== -ERESTARTSYS
)
2140 /* Continue on if we fail due to EIO, the GPU is hung so we
2141 * should be safe and we need to cleanup or else we might
2142 * cause memory corruption through use-after-free.
2145 i915_gem_clflush_object(obj
);
2146 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2149 /* release the fence reg _after_ flushing */
2150 ret
= i915_gem_object_put_fence(obj
);
2151 if (ret
== -ERESTARTSYS
)
2154 trace_i915_gem_object_unbind(obj
);
2156 i915_gem_gtt_unbind_object(obj
);
2157 i915_gem_object_put_pages_gtt(obj
);
2159 list_del_init(&obj
->gtt_list
);
2160 list_del_init(&obj
->mm_list
);
2161 /* Avoid an unnecessary call to unbind on rebind. */
2162 obj
->map_and_fenceable
= true;
2164 drm_mm_put_block(obj
->gtt_space
);
2165 obj
->gtt_space
= NULL
;
2166 obj
->gtt_offset
= 0;
2168 if (i915_gem_object_is_purgeable(obj
))
2169 i915_gem_object_truncate(obj
);
2175 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2176 uint32_t invalidate_domains
,
2177 uint32_t flush_domains
)
2181 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2183 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2187 i915_gem_process_flushing_list(ring
, flush_domains
);
2191 static int i915_ring_idle(struct intel_ring_buffer
*ring
)
2195 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2198 if (!list_empty(&ring
->gpu_write_list
)) {
2199 ret
= i915_gem_flush_ring(ring
,
2200 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2205 return i915_wait_request(ring
,
2206 i915_gem_next_request_seqno(ring
),
2211 i915_gpu_idle(struct drm_device
*dev
)
2213 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2217 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2218 list_empty(&dev_priv
->mm
.active_list
));
2222 /* Flush everything onto the inactive list. */
2223 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2224 ret
= i915_ring_idle(&dev_priv
->ring
[i
]);
2232 static int sandybridge_write_fence_reg(struct drm_i915_gem_object
*obj
,
2233 struct intel_ring_buffer
*pipelined
)
2235 struct drm_device
*dev
= obj
->base
.dev
;
2236 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2237 u32 size
= obj
->gtt_space
->size
;
2238 int regnum
= obj
->fence_reg
;
2241 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2243 val
|= obj
->gtt_offset
& 0xfffff000;
2244 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2245 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2247 if (obj
->tiling_mode
== I915_TILING_Y
)
2248 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2249 val
|= I965_FENCE_REG_VALID
;
2252 int ret
= intel_ring_begin(pipelined
, 6);
2256 intel_ring_emit(pipelined
, MI_NOOP
);
2257 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2258 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8);
2259 intel_ring_emit(pipelined
, (u32
)val
);
2260 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8 + 4);
2261 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2262 intel_ring_advance(pipelined
);
2264 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ regnum
* 8, val
);
2269 static int i965_write_fence_reg(struct drm_i915_gem_object
*obj
,
2270 struct intel_ring_buffer
*pipelined
)
2272 struct drm_device
*dev
= obj
->base
.dev
;
2273 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2274 u32 size
= obj
->gtt_space
->size
;
2275 int regnum
= obj
->fence_reg
;
2278 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2280 val
|= obj
->gtt_offset
& 0xfffff000;
2281 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2282 if (obj
->tiling_mode
== I915_TILING_Y
)
2283 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2284 val
|= I965_FENCE_REG_VALID
;
2287 int ret
= intel_ring_begin(pipelined
, 6);
2291 intel_ring_emit(pipelined
, MI_NOOP
);
2292 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2293 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8);
2294 intel_ring_emit(pipelined
, (u32
)val
);
2295 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8 + 4);
2296 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2297 intel_ring_advance(pipelined
);
2299 I915_WRITE64(FENCE_REG_965_0
+ regnum
* 8, val
);
2304 static int i915_write_fence_reg(struct drm_i915_gem_object
*obj
,
2305 struct intel_ring_buffer
*pipelined
)
2307 struct drm_device
*dev
= obj
->base
.dev
;
2308 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2309 u32 size
= obj
->gtt_space
->size
;
2310 u32 fence_reg
, val
, pitch_val
;
2313 if (WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2314 (size
& -size
) != size
||
2315 (obj
->gtt_offset
& (size
- 1)),
2316 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2317 obj
->gtt_offset
, obj
->map_and_fenceable
, size
))
2320 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2325 /* Note: pitch better be a power of two tile widths */
2326 pitch_val
= obj
->stride
/ tile_width
;
2327 pitch_val
= ffs(pitch_val
) - 1;
2329 val
= obj
->gtt_offset
;
2330 if (obj
->tiling_mode
== I915_TILING_Y
)
2331 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2332 val
|= I915_FENCE_SIZE_BITS(size
);
2333 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2334 val
|= I830_FENCE_REG_VALID
;
2336 fence_reg
= obj
->fence_reg
;
2338 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2340 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2343 int ret
= intel_ring_begin(pipelined
, 4);
2347 intel_ring_emit(pipelined
, MI_NOOP
);
2348 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2349 intel_ring_emit(pipelined
, fence_reg
);
2350 intel_ring_emit(pipelined
, val
);
2351 intel_ring_advance(pipelined
);
2353 I915_WRITE(fence_reg
, val
);
2358 static int i830_write_fence_reg(struct drm_i915_gem_object
*obj
,
2359 struct intel_ring_buffer
*pipelined
)
2361 struct drm_device
*dev
= obj
->base
.dev
;
2362 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2363 u32 size
= obj
->gtt_space
->size
;
2364 int regnum
= obj
->fence_reg
;
2368 if (WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2369 (size
& -size
) != size
||
2370 (obj
->gtt_offset
& (size
- 1)),
2371 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2372 obj
->gtt_offset
, size
))
2375 pitch_val
= obj
->stride
/ 128;
2376 pitch_val
= ffs(pitch_val
) - 1;
2378 val
= obj
->gtt_offset
;
2379 if (obj
->tiling_mode
== I915_TILING_Y
)
2380 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2381 val
|= I830_FENCE_SIZE_BITS(size
);
2382 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2383 val
|= I830_FENCE_REG_VALID
;
2386 int ret
= intel_ring_begin(pipelined
, 4);
2390 intel_ring_emit(pipelined
, MI_NOOP
);
2391 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2392 intel_ring_emit(pipelined
, FENCE_REG_830_0
+ regnum
*4);
2393 intel_ring_emit(pipelined
, val
);
2394 intel_ring_advance(pipelined
);
2396 I915_WRITE(FENCE_REG_830_0
+ regnum
* 4, val
);
2401 static bool ring_passed_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
2403 return i915_seqno_passed(ring
->get_seqno(ring
), seqno
);
2407 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
,
2408 struct intel_ring_buffer
*pipelined
,
2413 if (obj
->fenced_gpu_access
) {
2414 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2415 ret
= i915_gem_flush_ring(obj
->last_fenced_ring
,
2416 0, obj
->base
.write_domain
);
2421 obj
->fenced_gpu_access
= false;
2424 if (obj
->last_fenced_seqno
&& pipelined
!= obj
->last_fenced_ring
) {
2425 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2426 obj
->last_fenced_seqno
)) {
2427 ret
= i915_wait_request(obj
->last_fenced_ring
,
2428 obj
->last_fenced_seqno
,
2435 obj
->last_fenced_seqno
= 0;
2436 obj
->last_fenced_ring
= NULL
;
2439 /* Ensure that all CPU reads are completed before installing a fence
2440 * and all writes before removing the fence.
2442 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2449 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2453 if (obj
->tiling_mode
)
2454 i915_gem_release_mmap(obj
);
2456 ret
= i915_gem_object_flush_fence(obj
, NULL
, true);
2460 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2461 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2462 i915_gem_clear_fence_reg(obj
->base
.dev
,
2463 &dev_priv
->fence_regs
[obj
->fence_reg
]);
2465 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2471 static struct drm_i915_fence_reg
*
2472 i915_find_fence_reg(struct drm_device
*dev
,
2473 struct intel_ring_buffer
*pipelined
)
2475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2476 struct drm_i915_fence_reg
*reg
, *first
, *avail
;
2479 /* First try to find a free reg */
2481 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2482 reg
= &dev_priv
->fence_regs
[i
];
2486 if (!reg
->obj
->pin_count
)
2493 /* None available, try to steal one or wait for a user to finish */
2494 avail
= first
= NULL
;
2495 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2496 if (reg
->obj
->pin_count
)
2503 !reg
->obj
->last_fenced_ring
||
2504 reg
->obj
->last_fenced_ring
== pipelined
) {
2517 * i915_gem_object_get_fence - set up a fence reg for an object
2518 * @obj: object to map through a fence reg
2519 * @pipelined: ring on which to queue the change, or NULL for CPU access
2520 * @interruptible: must we wait uninterruptibly for the register to retire?
2522 * When mapping objects through the GTT, userspace wants to be able to write
2523 * to them without having to worry about swizzling if the object is tiled.
2525 * This function walks the fence regs looking for a free one for @obj,
2526 * stealing one if it can't find any.
2528 * It then sets up the reg based on the object's properties: address, pitch
2529 * and tiling format.
2532 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
2533 struct intel_ring_buffer
*pipelined
,
2536 struct drm_device
*dev
= obj
->base
.dev
;
2537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2538 struct drm_i915_fence_reg
*reg
;
2541 /* XXX disable pipelining. There are bugs. Shocking. */
2544 /* Just update our place in the LRU if our fence is getting reused. */
2545 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2546 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2547 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2549 if (!obj
->fenced_gpu_access
&& !obj
->last_fenced_seqno
)
2553 if (reg
->setup_seqno
) {
2554 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2555 reg
->setup_seqno
)) {
2556 ret
= i915_wait_request(obj
->last_fenced_ring
,
2563 reg
->setup_seqno
= 0;
2565 } else if (obj
->last_fenced_ring
&&
2566 obj
->last_fenced_ring
!= pipelined
) {
2567 ret
= i915_gem_object_flush_fence(obj
,
2572 } else if (obj
->tiling_changed
) {
2573 if (obj
->fenced_gpu_access
) {
2574 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2575 ret
= i915_gem_flush_ring(obj
->ring
,
2576 0, obj
->base
.write_domain
);
2581 obj
->fenced_gpu_access
= false;
2585 if (!obj
->fenced_gpu_access
&& !obj
->last_fenced_seqno
)
2587 BUG_ON(!pipelined
&& reg
->setup_seqno
);
2589 if (obj
->tiling_changed
) {
2592 i915_gem_next_request_seqno(pipelined
);
2593 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2594 obj
->last_fenced_ring
= pipelined
;
2602 reg
= i915_find_fence_reg(dev
, pipelined
);
2606 ret
= i915_gem_object_flush_fence(obj
, pipelined
, interruptible
);
2611 struct drm_i915_gem_object
*old
= reg
->obj
;
2613 drm_gem_object_reference(&old
->base
);
2615 if (old
->tiling_mode
)
2616 i915_gem_release_mmap(old
);
2618 ret
= i915_gem_object_flush_fence(old
,
2622 drm_gem_object_unreference(&old
->base
);
2626 if (old
->last_fenced_seqno
== 0 && obj
->last_fenced_seqno
== 0)
2629 old
->fence_reg
= I915_FENCE_REG_NONE
;
2630 old
->last_fenced_ring
= pipelined
;
2631 old
->last_fenced_seqno
=
2632 pipelined
? i915_gem_next_request_seqno(pipelined
) : 0;
2634 drm_gem_object_unreference(&old
->base
);
2635 } else if (obj
->last_fenced_seqno
== 0)
2639 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2640 obj
->fence_reg
= reg
- dev_priv
->fence_regs
;
2641 obj
->last_fenced_ring
= pipelined
;
2644 pipelined
? i915_gem_next_request_seqno(pipelined
) : 0;
2645 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2648 obj
->tiling_changed
= false;
2649 switch (INTEL_INFO(dev
)->gen
) {
2651 ret
= sandybridge_write_fence_reg(obj
, pipelined
);
2655 ret
= i965_write_fence_reg(obj
, pipelined
);
2658 ret
= i915_write_fence_reg(obj
, pipelined
);
2661 ret
= i830_write_fence_reg(obj
, pipelined
);
2669 * i915_gem_clear_fence_reg - clear out fence register info
2670 * @obj: object to clear
2672 * Zeroes out the fence register itself and clears out the associated
2673 * data structures in dev_priv and obj.
2676 i915_gem_clear_fence_reg(struct drm_device
*dev
,
2677 struct drm_i915_fence_reg
*reg
)
2679 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2680 uint32_t fence_reg
= reg
- dev_priv
->fence_regs
;
2682 switch (INTEL_INFO(dev
)->gen
) {
2684 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ fence_reg
*8, 0);
2688 I915_WRITE64(FENCE_REG_965_0
+ fence_reg
*8, 0);
2692 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2695 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2697 I915_WRITE(fence_reg
, 0);
2701 list_del_init(®
->lru_list
);
2703 reg
->setup_seqno
= 0;
2707 * Finds free space in the GTT aperture and binds the object there.
2710 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2712 bool map_and_fenceable
)
2714 struct drm_device
*dev
= obj
->base
.dev
;
2715 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2716 struct drm_mm_node
*free_space
;
2717 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2718 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2719 bool mappable
, fenceable
;
2722 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2723 DRM_ERROR("Attempting to bind a purgeable object\n");
2727 fence_size
= i915_gem_get_gtt_size(obj
);
2728 fence_alignment
= i915_gem_get_gtt_alignment(obj
);
2729 unfenced_alignment
= i915_gem_get_unfenced_gtt_alignment(obj
);
2732 alignment
= map_and_fenceable
? fence_alignment
:
2734 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2735 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2739 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2741 /* If the object is bigger than the entire aperture, reject it early
2742 * before evicting everything in a vain attempt to find space.
2744 if (obj
->base
.size
>
2745 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2746 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2751 if (map_and_fenceable
)
2753 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2755 dev_priv
->mm
.gtt_mappable_end
,
2758 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2759 size
, alignment
, 0);
2761 if (free_space
!= NULL
) {
2762 if (map_and_fenceable
)
2764 drm_mm_get_block_range_generic(free_space
,
2766 dev_priv
->mm
.gtt_mappable_end
,
2770 drm_mm_get_block(free_space
, size
, alignment
);
2772 if (obj
->gtt_space
== NULL
) {
2773 /* If the gtt is empty and we're still having trouble
2774 * fitting our object in, we're out of memory.
2776 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2784 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2786 drm_mm_put_block(obj
->gtt_space
);
2787 obj
->gtt_space
= NULL
;
2789 if (ret
== -ENOMEM
) {
2790 /* first try to reclaim some memory by clearing the GTT */
2791 ret
= i915_gem_evict_everything(dev
, false);
2793 /* now try to shrink everyone else */
2808 ret
= i915_gem_gtt_bind_object(obj
);
2810 i915_gem_object_put_pages_gtt(obj
);
2811 drm_mm_put_block(obj
->gtt_space
);
2812 obj
->gtt_space
= NULL
;
2814 if (i915_gem_evict_everything(dev
, false))
2820 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2821 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2823 /* Assert that the object is not currently in any GPU domain. As it
2824 * wasn't in the GTT, there shouldn't be any way it could have been in
2827 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2828 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2830 obj
->gtt_offset
= obj
->gtt_space
->start
;
2833 obj
->gtt_space
->size
== fence_size
&&
2834 (obj
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2837 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2839 obj
->map_and_fenceable
= mappable
&& fenceable
;
2841 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2846 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2848 /* If we don't have a page list set up, then we're not pinned
2849 * to GPU, and we can ignore the cache flush because it'll happen
2850 * again at bind time.
2852 if (obj
->pages
== NULL
)
2855 trace_i915_gem_object_clflush(obj
);
2857 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2860 /** Flushes any GPU write domain for the object if it's dirty. */
2862 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2864 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2867 /* Queue the GPU write cache flushing we need. */
2868 return i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2871 /** Flushes the GTT write domain for the object if it's dirty. */
2873 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2875 uint32_t old_write_domain
;
2877 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2880 /* No actual flushing is required for the GTT write domain. Writes
2881 * to it immediately go to main memory as far as we know, so there's
2882 * no chipset flush. It also doesn't land in render cache.
2884 * However, we do have to enforce the order so that all writes through
2885 * the GTT land before any writes to the device, such as updates to
2890 i915_gem_release_mmap(obj
);
2892 old_write_domain
= obj
->base
.write_domain
;
2893 obj
->base
.write_domain
= 0;
2895 trace_i915_gem_object_change_domain(obj
,
2896 obj
->base
.read_domains
,
2900 /** Flushes the CPU write domain for the object if it's dirty. */
2902 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2904 uint32_t old_write_domain
;
2906 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2909 i915_gem_clflush_object(obj
);
2910 intel_gtt_chipset_flush();
2911 old_write_domain
= obj
->base
.write_domain
;
2912 obj
->base
.write_domain
= 0;
2914 trace_i915_gem_object_change_domain(obj
,
2915 obj
->base
.read_domains
,
2920 * Moves a single object to the GTT read, and possibly write domain.
2922 * This function returns when the move is complete, including waiting on
2926 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2928 uint32_t old_write_domain
, old_read_domains
;
2931 /* Not valid to be called on unbound objects. */
2932 if (obj
->gtt_space
== NULL
)
2935 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2938 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2942 if (obj
->pending_gpu_write
|| write
) {
2943 ret
= i915_gem_object_wait_rendering(obj
, true);
2948 i915_gem_object_flush_cpu_write_domain(obj
);
2950 old_write_domain
= obj
->base
.write_domain
;
2951 old_read_domains
= obj
->base
.read_domains
;
2953 /* It should now be out of any other write domains, and we can update
2954 * the domain values for our changes.
2956 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2957 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2959 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2960 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2964 trace_i915_gem_object_change_domain(obj
,
2972 * Prepare buffer for display plane. Use uninterruptible for possible flush
2973 * wait, as in modesetting process we're not supposed to be interrupted.
2976 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object
*obj
,
2977 struct intel_ring_buffer
*pipelined
)
2979 uint32_t old_read_domains
;
2982 /* Not valid to be called on unbound objects. */
2983 if (obj
->gtt_space
== NULL
)
2986 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2991 /* Currently, we are always called from an non-interruptible context. */
2992 if (pipelined
!= obj
->ring
) {
2993 ret
= i915_gem_object_wait_rendering(obj
, false);
2998 i915_gem_object_flush_cpu_write_domain(obj
);
3000 old_read_domains
= obj
->base
.read_domains
;
3001 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3003 trace_i915_gem_object_change_domain(obj
,
3005 obj
->base
.write_domain
);
3011 i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
3019 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3020 ret
= i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
3025 return i915_gem_object_wait_rendering(obj
, interruptible
);
3029 * Moves a single object to the CPU read, and possibly write domain.
3031 * This function returns when the move is complete, including waiting on
3035 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3037 uint32_t old_write_domain
, old_read_domains
;
3040 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3043 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3047 ret
= i915_gem_object_wait_rendering(obj
, true);
3051 i915_gem_object_flush_gtt_write_domain(obj
);
3053 /* If we have a partially-valid cache of the object in the CPU,
3054 * finish invalidating it and free the per-page flags.
3056 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3058 old_write_domain
= obj
->base
.write_domain
;
3059 old_read_domains
= obj
->base
.read_domains
;
3061 /* Flush the CPU cache if it's still invalid. */
3062 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3063 i915_gem_clflush_object(obj
);
3065 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3068 /* It should now be out of any other write domains, and we can update
3069 * the domain values for our changes.
3071 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3073 /* If we're writing through the CPU, then the GPU read domains will
3074 * need to be invalidated at next use.
3077 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3078 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3081 trace_i915_gem_object_change_domain(obj
,
3089 * Moves the object from a partially CPU read to a full one.
3091 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3092 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3095 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
)
3097 if (!obj
->page_cpu_valid
)
3100 /* If we're partially in the CPU read domain, finish moving it in.
3102 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3105 for (i
= 0; i
<= (obj
->base
.size
- 1) / PAGE_SIZE
; i
++) {
3106 if (obj
->page_cpu_valid
[i
])
3108 drm_clflush_pages(obj
->pages
+ i
, 1);
3112 /* Free the page_cpu_valid mappings which are now stale, whether
3113 * or not we've got I915_GEM_DOMAIN_CPU.
3115 kfree(obj
->page_cpu_valid
);
3116 obj
->page_cpu_valid
= NULL
;
3120 * Set the CPU read domain on a range of the object.
3122 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3123 * not entirely valid. The page_cpu_valid member of the object flags which
3124 * pages have been flushed, and will be respected by
3125 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3126 * of the whole object.
3128 * This function returns when the move is complete, including waiting on
3132 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
3133 uint64_t offset
, uint64_t size
)
3135 uint32_t old_read_domains
;
3138 if (offset
== 0 && size
== obj
->base
.size
)
3139 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3141 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3145 ret
= i915_gem_object_wait_rendering(obj
, true);
3149 i915_gem_object_flush_gtt_write_domain(obj
);
3151 /* If we're already fully in the CPU read domain, we're done. */
3152 if (obj
->page_cpu_valid
== NULL
&&
3153 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3156 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3157 * newly adding I915_GEM_DOMAIN_CPU
3159 if (obj
->page_cpu_valid
== NULL
) {
3160 obj
->page_cpu_valid
= kzalloc(obj
->base
.size
/ PAGE_SIZE
,
3162 if (obj
->page_cpu_valid
== NULL
)
3164 } else if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3165 memset(obj
->page_cpu_valid
, 0, obj
->base
.size
/ PAGE_SIZE
);
3167 /* Flush the cache on any pages that are still invalid from the CPU's
3170 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3172 if (obj
->page_cpu_valid
[i
])
3175 drm_clflush_pages(obj
->pages
+ i
, 1);
3177 obj
->page_cpu_valid
[i
] = 1;
3180 /* It should now be out of any other write domains, and we can update
3181 * the domain values for our changes.
3183 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3185 old_read_domains
= obj
->base
.read_domains
;
3186 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3188 trace_i915_gem_object_change_domain(obj
,
3190 obj
->base
.write_domain
);
3195 /* Throttle our rendering by waiting until the ring has completed our requests
3196 * emitted over 20 msec ago.
3198 * Note that if we were to use the current jiffies each time around the loop,
3199 * we wouldn't escape the function with any frames outstanding if the time to
3200 * render a frame was over 20ms.
3202 * This should get us reasonable parallelism between CPU and GPU but also
3203 * relatively low latency when blocking on a particular request to finish.
3206 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3209 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3210 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3211 struct drm_i915_gem_request
*request
;
3212 struct intel_ring_buffer
*ring
= NULL
;
3216 if (atomic_read(&dev_priv
->mm
.wedged
))
3219 spin_lock(&file_priv
->mm
.lock
);
3220 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3221 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3224 ring
= request
->ring
;
3225 seqno
= request
->seqno
;
3227 spin_unlock(&file_priv
->mm
.lock
);
3233 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3234 /* And wait for the seqno passing without holding any locks and
3235 * causing extra latency for others. This is safe as the irq
3236 * generation is designed to be run atomically and so is
3239 if (ring
->irq_get(ring
)) {
3240 ret
= wait_event_interruptible(ring
->irq_queue
,
3241 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3242 || atomic_read(&dev_priv
->mm
.wedged
));
3243 ring
->irq_put(ring
);
3245 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3251 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3257 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3259 bool map_and_fenceable
)
3261 struct drm_device
*dev
= obj
->base
.dev
;
3262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3265 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3266 WARN_ON(i915_verify_lists(dev
));
3268 if (obj
->gtt_space
!= NULL
) {
3269 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3270 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3271 WARN(obj
->pin_count
,
3272 "bo is already pinned with incorrect alignment:"
3273 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3274 " obj->map_and_fenceable=%d\n",
3275 obj
->gtt_offset
, alignment
,
3277 obj
->map_and_fenceable
);
3278 ret
= i915_gem_object_unbind(obj
);
3284 if (obj
->gtt_space
== NULL
) {
3285 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3291 if (obj
->pin_count
++ == 0) {
3293 list_move_tail(&obj
->mm_list
,
3294 &dev_priv
->mm
.pinned_list
);
3296 obj
->pin_mappable
|= map_and_fenceable
;
3298 WARN_ON(i915_verify_lists(dev
));
3303 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3305 struct drm_device
*dev
= obj
->base
.dev
;
3306 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3308 WARN_ON(i915_verify_lists(dev
));
3309 BUG_ON(obj
->pin_count
== 0);
3310 BUG_ON(obj
->gtt_space
== NULL
);
3312 if (--obj
->pin_count
== 0) {
3314 list_move_tail(&obj
->mm_list
,
3315 &dev_priv
->mm
.inactive_list
);
3316 obj
->pin_mappable
= false;
3318 WARN_ON(i915_verify_lists(dev
));
3322 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3323 struct drm_file
*file
)
3325 struct drm_i915_gem_pin
*args
= data
;
3326 struct drm_i915_gem_object
*obj
;
3329 ret
= i915_mutex_lock_interruptible(dev
);
3333 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3339 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3340 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3345 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3346 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3352 obj
->user_pin_count
++;
3353 obj
->pin_filp
= file
;
3354 if (obj
->user_pin_count
== 1) {
3355 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3360 /* XXX - flush the CPU caches for pinned objects
3361 * as the X server doesn't manage domains yet
3363 i915_gem_object_flush_cpu_write_domain(obj
);
3364 args
->offset
= obj
->gtt_offset
;
3366 drm_gem_object_unreference(&obj
->base
);
3368 mutex_unlock(&dev
->struct_mutex
);
3373 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3374 struct drm_file
*file
)
3376 struct drm_i915_gem_pin
*args
= data
;
3377 struct drm_i915_gem_object
*obj
;
3380 ret
= i915_mutex_lock_interruptible(dev
);
3384 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3390 if (obj
->pin_filp
!= file
) {
3391 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3396 obj
->user_pin_count
--;
3397 if (obj
->user_pin_count
== 0) {
3398 obj
->pin_filp
= NULL
;
3399 i915_gem_object_unpin(obj
);
3403 drm_gem_object_unreference(&obj
->base
);
3405 mutex_unlock(&dev
->struct_mutex
);
3410 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3411 struct drm_file
*file
)
3413 struct drm_i915_gem_busy
*args
= data
;
3414 struct drm_i915_gem_object
*obj
;
3417 ret
= i915_mutex_lock_interruptible(dev
);
3421 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3427 /* Count all active objects as busy, even if they are currently not used
3428 * by the gpu. Users of this interface expect objects to eventually
3429 * become non-busy without any further actions, therefore emit any
3430 * necessary flushes here.
3432 args
->busy
= obj
->active
;
3434 /* Unconditionally flush objects, even when the gpu still uses this
3435 * object. Userspace calling this function indicates that it wants to
3436 * use this buffer rather sooner than later, so issuing the required
3437 * flush earlier is beneficial.
3439 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3440 ret
= i915_gem_flush_ring(obj
->ring
,
3441 0, obj
->base
.write_domain
);
3442 } else if (obj
->ring
->outstanding_lazy_request
==
3443 obj
->last_rendering_seqno
) {
3444 struct drm_i915_gem_request
*request
;
3446 /* This ring is not being cleared by active usage,
3447 * so emit a request to do so.
3449 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3451 ret
= i915_add_request(obj
->ring
, NULL
,request
);
3456 /* Update the active list for the hardware's current position.
3457 * Otherwise this only updates on a delayed timer or when irqs
3458 * are actually unmasked, and our working set ends up being
3459 * larger than required.
3461 i915_gem_retire_requests_ring(obj
->ring
);
3463 args
->busy
= obj
->active
;
3466 drm_gem_object_unreference(&obj
->base
);
3468 mutex_unlock(&dev
->struct_mutex
);
3473 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3474 struct drm_file
*file_priv
)
3476 return i915_gem_ring_throttle(dev
, file_priv
);
3480 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3481 struct drm_file
*file_priv
)
3483 struct drm_i915_gem_madvise
*args
= data
;
3484 struct drm_i915_gem_object
*obj
;
3487 switch (args
->madv
) {
3488 case I915_MADV_DONTNEED
:
3489 case I915_MADV_WILLNEED
:
3495 ret
= i915_mutex_lock_interruptible(dev
);
3499 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3505 if (obj
->pin_count
) {
3510 if (obj
->madv
!= __I915_MADV_PURGED
)
3511 obj
->madv
= args
->madv
;
3513 /* if the object is no longer bound, discard its backing storage */
3514 if (i915_gem_object_is_purgeable(obj
) &&
3515 obj
->gtt_space
== NULL
)
3516 i915_gem_object_truncate(obj
);
3518 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3521 drm_gem_object_unreference(&obj
->base
);
3523 mutex_unlock(&dev
->struct_mutex
);
3527 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3531 struct drm_i915_gem_object
*obj
;
3533 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3537 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3542 i915_gem_info_add_obj(dev_priv
, size
);
3544 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3545 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3547 obj
->agp_type
= AGP_USER_MEMORY
;
3548 obj
->base
.driver_private
= NULL
;
3549 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3550 INIT_LIST_HEAD(&obj
->mm_list
);
3551 INIT_LIST_HEAD(&obj
->gtt_list
);
3552 INIT_LIST_HEAD(&obj
->ring_list
);
3553 INIT_LIST_HEAD(&obj
->exec_list
);
3554 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3555 obj
->madv
= I915_MADV_WILLNEED
;
3556 /* Avoid an unnecessary call to unbind on the first bind. */
3557 obj
->map_and_fenceable
= true;
3562 int i915_gem_init_object(struct drm_gem_object
*obj
)
3569 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
)
3571 struct drm_device
*dev
= obj
->base
.dev
;
3572 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3575 ret
= i915_gem_object_unbind(obj
);
3576 if (ret
== -ERESTARTSYS
) {
3577 list_move(&obj
->mm_list
,
3578 &dev_priv
->mm
.deferred_free_list
);
3582 if (obj
->base
.map_list
.map
)
3583 i915_gem_free_mmap_offset(obj
);
3585 drm_gem_object_release(&obj
->base
);
3586 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3588 kfree(obj
->page_cpu_valid
);
3592 trace_i915_gem_object_destroy(obj
);
3595 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3597 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3598 struct drm_device
*dev
= obj
->base
.dev
;
3600 while (obj
->pin_count
> 0)
3601 i915_gem_object_unpin(obj
);
3604 i915_gem_detach_phys_object(dev
, obj
);
3606 i915_gem_free_object_tail(obj
);
3610 i915_gem_idle(struct drm_device
*dev
)
3612 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3615 mutex_lock(&dev
->struct_mutex
);
3617 if (dev_priv
->mm
.suspended
) {
3618 mutex_unlock(&dev
->struct_mutex
);
3622 ret
= i915_gpu_idle(dev
);
3624 mutex_unlock(&dev
->struct_mutex
);
3628 /* Under UMS, be paranoid and evict. */
3629 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3630 ret
= i915_gem_evict_inactive(dev
, false);
3632 mutex_unlock(&dev
->struct_mutex
);
3637 i915_gem_reset_fences(dev
);
3639 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3640 * We need to replace this with a semaphore, or something.
3641 * And not confound mm.suspended!
3643 dev_priv
->mm
.suspended
= 1;
3644 del_timer_sync(&dev_priv
->hangcheck_timer
);
3646 i915_kernel_lost_context(dev
);
3647 i915_gem_cleanup_ringbuffer(dev
);
3649 mutex_unlock(&dev
->struct_mutex
);
3651 /* Cancel the retire work handler, which should be idle now. */
3652 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3658 i915_gem_init_ringbuffer(struct drm_device
*dev
)
3660 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3663 ret
= intel_init_render_ring_buffer(dev
);
3668 ret
= intel_init_bsd_ring_buffer(dev
);
3670 goto cleanup_render_ring
;
3674 ret
= intel_init_blt_ring_buffer(dev
);
3676 goto cleanup_bsd_ring
;
3679 dev_priv
->next_seqno
= 1;
3684 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3685 cleanup_render_ring
:
3686 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3691 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3693 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3696 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3697 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
3701 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3702 struct drm_file
*file_priv
)
3704 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3707 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3710 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3711 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3712 atomic_set(&dev_priv
->mm
.wedged
, 0);
3715 mutex_lock(&dev
->struct_mutex
);
3716 dev_priv
->mm
.suspended
= 0;
3718 ret
= i915_gem_init_ringbuffer(dev
);
3720 mutex_unlock(&dev
->struct_mutex
);
3724 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3725 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3726 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3727 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3728 BUG_ON(!list_empty(&dev_priv
->ring
[i
].active_list
));
3729 BUG_ON(!list_empty(&dev_priv
->ring
[i
].request_list
));
3731 mutex_unlock(&dev
->struct_mutex
);
3733 ret
= drm_irq_install(dev
);
3735 goto cleanup_ringbuffer
;
3740 mutex_lock(&dev
->struct_mutex
);
3741 i915_gem_cleanup_ringbuffer(dev
);
3742 dev_priv
->mm
.suspended
= 1;
3743 mutex_unlock(&dev
->struct_mutex
);
3749 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3750 struct drm_file
*file_priv
)
3752 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3755 drm_irq_uninstall(dev
);
3756 return i915_gem_idle(dev
);
3760 i915_gem_lastclose(struct drm_device
*dev
)
3764 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3767 ret
= i915_gem_idle(dev
);
3769 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3773 init_ring_lists(struct intel_ring_buffer
*ring
)
3775 INIT_LIST_HEAD(&ring
->active_list
);
3776 INIT_LIST_HEAD(&ring
->request_list
);
3777 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3781 i915_gem_load(struct drm_device
*dev
)
3784 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3786 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3787 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3788 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3789 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
3790 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3791 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
3792 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3793 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3794 init_ring_lists(&dev_priv
->ring
[i
]);
3795 for (i
= 0; i
< 16; i
++)
3796 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3797 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3798 i915_gem_retire_work_handler
);
3799 init_completion(&dev_priv
->error_completion
);
3801 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3803 u32 tmp
= I915_READ(MI_ARB_STATE
);
3804 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3805 /* arb state is a masked write, so set bit + bit in mask */
3806 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3807 I915_WRITE(MI_ARB_STATE
, tmp
);
3811 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3813 /* Old X drivers will take 0-2 for front, back, depth buffers */
3814 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3815 dev_priv
->fence_reg_start
= 3;
3817 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3818 dev_priv
->num_fence_regs
= 16;
3820 dev_priv
->num_fence_regs
= 8;
3822 /* Initialize fence registers to zero */
3823 switch (INTEL_INFO(dev
)->gen
) {
3825 for (i
= 0; i
< 16; i
++)
3826 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
3830 for (i
= 0; i
< 16; i
++)
3831 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
3834 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3835 for (i
= 0; i
< 8; i
++)
3836 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
3838 for (i
= 0; i
< 8; i
++)
3839 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
3842 i915_gem_detect_bit_6_swizzle(dev
);
3843 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3845 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3846 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3847 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3851 * Create a physically contiguous memory object for this object
3852 * e.g. for cursor + overlay regs
3854 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3855 int id
, int size
, int align
)
3857 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3858 struct drm_i915_gem_phys_object
*phys_obj
;
3861 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3864 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3870 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3871 if (!phys_obj
->handle
) {
3876 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3879 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3887 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3889 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3890 struct drm_i915_gem_phys_object
*phys_obj
;
3892 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3895 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3896 if (phys_obj
->cur_obj
) {
3897 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3901 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3903 drm_pci_free(dev
, phys_obj
->handle
);
3905 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3908 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3912 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3913 i915_gem_free_phys_object(dev
, i
);
3916 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3917 struct drm_i915_gem_object
*obj
)
3919 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3926 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3928 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3929 for (i
= 0; i
< page_count
; i
++) {
3930 struct page
*page
= read_cache_page_gfp(mapping
, i
,
3931 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3932 if (!IS_ERR(page
)) {
3933 char *dst
= kmap_atomic(page
);
3934 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3937 drm_clflush_pages(&page
, 1);
3939 set_page_dirty(page
);
3940 mark_page_accessed(page
);
3941 page_cache_release(page
);
3944 intel_gtt_chipset_flush();
3946 obj
->phys_obj
->cur_obj
= NULL
;
3947 obj
->phys_obj
= NULL
;
3951 i915_gem_attach_phys_object(struct drm_device
*dev
,
3952 struct drm_i915_gem_object
*obj
,
3956 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3962 if (id
> I915_MAX_PHYS_OBJECT
)
3965 if (obj
->phys_obj
) {
3966 if (obj
->phys_obj
->id
== id
)
3968 i915_gem_detach_phys_object(dev
, obj
);
3971 /* create a new object */
3972 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3973 ret
= i915_gem_init_phys_object(dev
, id
,
3974 obj
->base
.size
, align
);
3976 DRM_ERROR("failed to init phys object %d size: %zu\n",
3977 id
, obj
->base
.size
);
3982 /* bind to the object */
3983 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3984 obj
->phys_obj
->cur_obj
= obj
;
3986 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3988 for (i
= 0; i
< page_count
; i
++) {
3992 page
= read_cache_page_gfp(mapping
, i
,
3993 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3995 return PTR_ERR(page
);
3997 src
= kmap_atomic(page
);
3998 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3999 memcpy(dst
, src
, PAGE_SIZE
);
4002 mark_page_accessed(page
);
4003 page_cache_release(page
);
4010 i915_gem_phys_pwrite(struct drm_device
*dev
,
4011 struct drm_i915_gem_object
*obj
,
4012 struct drm_i915_gem_pwrite
*args
,
4013 struct drm_file
*file_priv
)
4015 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4016 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4018 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4019 unsigned long unwritten
;
4021 /* The physical object once assigned is fixed for the lifetime
4022 * of the obj, so we can safely drop the lock and continue
4025 mutex_unlock(&dev
->struct_mutex
);
4026 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4027 mutex_lock(&dev
->struct_mutex
);
4032 intel_gtt_chipset_flush();
4036 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4038 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4040 /* Clean up our request list when the client is going away, so that
4041 * later retire_requests won't dereference our soon-to-be-gone
4044 spin_lock(&file_priv
->mm
.lock
);
4045 while (!list_empty(&file_priv
->mm
.request_list
)) {
4046 struct drm_i915_gem_request
*request
;
4048 request
= list_first_entry(&file_priv
->mm
.request_list
,
4049 struct drm_i915_gem_request
,
4051 list_del(&request
->client_list
);
4052 request
->file_priv
= NULL
;
4054 spin_unlock(&file_priv
->mm
.lock
);
4058 i915_gpu_is_active(struct drm_device
*dev
)
4060 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4063 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4064 list_empty(&dev_priv
->mm
.active_list
);
4066 return !lists_empty
;
4070 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
4074 struct drm_i915_private
*dev_priv
=
4075 container_of(shrinker
,
4076 struct drm_i915_private
,
4077 mm
.inactive_shrinker
);
4078 struct drm_device
*dev
= dev_priv
->dev
;
4079 struct drm_i915_gem_object
*obj
, *next
;
4082 if (!mutex_trylock(&dev
->struct_mutex
))
4085 /* "fast-path" to count number of available objects */
4086 if (nr_to_scan
== 0) {
4088 list_for_each_entry(obj
,
4089 &dev_priv
->mm
.inactive_list
,
4092 mutex_unlock(&dev
->struct_mutex
);
4093 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4097 /* first scan for clean buffers */
4098 i915_gem_retire_requests(dev
);
4100 list_for_each_entry_safe(obj
, next
,
4101 &dev_priv
->mm
.inactive_list
,
4103 if (i915_gem_object_is_purgeable(obj
)) {
4104 if (i915_gem_object_unbind(obj
) == 0 &&
4110 /* second pass, evict/count anything still on the inactive list */
4112 list_for_each_entry_safe(obj
, next
,
4113 &dev_priv
->mm
.inactive_list
,
4116 i915_gem_object_unbind(obj
) == 0)
4122 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4124 * We are desperate for pages, so as a last resort, wait
4125 * for the GPU to finish and discard whatever we can.
4126 * This has a dramatic impact to reduce the number of
4127 * OOM-killer events whilst running the GPU aggressively.
4129 if (i915_gpu_idle(dev
) == 0)
4132 mutex_unlock(&dev
->struct_mutex
);
4133 return cnt
/ 100 * sysctl_vfs_cache_pressure
;