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can: mcp251x: define helper functions mcp251x_is_2510, mcp251x_is_2515
[linux-2.6.git] / drivers / net / can / mcp251x.c
blob7f8aa4ce02c581fcb05f45e51196c8b60fb4aa7d
1 /*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 *
34 *
35 *
36 * Your platform definition file should specify something like:
37 *
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .power_enable = mcp251x_power_enable,
42 * .transceiver_enable = NULL,
43 * };
44 *
45 * static struct spi_board_info spi_board_info[] = {
46 * {
47 * .modalias = "mcp2510",
48 * // or "mcp2515" depending on your controller
49 * .platform_data = &mcp251x_info,
50 * .irq = IRQ_EINT13,
51 * .max_speed_hz = 2*1000*1000,
52 * .chip_select = 2,
53 * },
54 * };
55 *
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
58 *
59 */
60
61 #include <linux/can/core.h>
62 #include <linux/can/dev.h>
63 #include <linux/can/platform/mcp251x.h>
64 #include <linux/completion.h>
65 #include <linux/delay.h>
66 #include <linux/device.h>
67 #include <linux/dma-mapping.h>
68 #include <linux/freezer.h>
69 #include <linux/interrupt.h>
70 #include <linux/io.h>
71 #include <linux/kernel.h>
72 #include <linux/module.h>
73 #include <linux/netdevice.h>
74 #include <linux/platform_device.h>
75 #include <linux/slab.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
78
79 /* SPI interface instruction set */
80 #define INSTRUCTION_WRITE 0x02
81 #define INSTRUCTION_READ 0x03
82 #define INSTRUCTION_BIT_MODIFY 0x05
83 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85 #define INSTRUCTION_RESET 0xC0
86
87 /* MPC251x registers */
88 #define CANSTAT 0x0e
89 #define CANCTRL 0x0f
90 # define CANCTRL_REQOP_MASK 0xe0
91 # define CANCTRL_REQOP_CONF 0x80
92 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
93 # define CANCTRL_REQOP_LOOPBACK 0x40
94 # define CANCTRL_REQOP_SLEEP 0x20
95 # define CANCTRL_REQOP_NORMAL 0x00
96 # define CANCTRL_OSM 0x08
97 # define CANCTRL_ABAT 0x10
98 #define TEC 0x1c
99 #define REC 0x1d
100 #define CNF1 0x2a
101 # define CNF1_SJW_SHIFT 6
102 #define CNF2 0x29
103 # define CNF2_BTLMODE 0x80
104 # define CNF2_SAM 0x40
105 # define CNF2_PS1_SHIFT 3
106 #define CNF3 0x28
107 # define CNF3_SOF 0x08
108 # define CNF3_WAKFIL 0x04
109 # define CNF3_PHSEG2_MASK 0x07
110 #define CANINTE 0x2b
111 # define CANINTE_MERRE 0x80
112 # define CANINTE_WAKIE 0x40
113 # define CANINTE_ERRIE 0x20
114 # define CANINTE_TX2IE 0x10
115 # define CANINTE_TX1IE 0x08
116 # define CANINTE_TX0IE 0x04
117 # define CANINTE_RX1IE 0x02
118 # define CANINTE_RX0IE 0x01
119 #define CANINTF 0x2c
120 # define CANINTF_MERRF 0x80
121 # define CANINTF_WAKIF 0x40
122 # define CANINTF_ERRIF 0x20
123 # define CANINTF_TX2IF 0x10
124 # define CANINTF_TX1IF 0x08
125 # define CANINTF_TX0IF 0x04
126 # define CANINTF_RX1IF 0x02
127 # define CANINTF_RX0IF 0x01
128 # define CANINTF_ERR_TX \
129 (CANINTF_ERRIF | CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
130 #define EFLG 0x2d
131 # define EFLG_EWARN 0x01
132 # define EFLG_RXWAR 0x02
133 # define EFLG_TXWAR 0x04
134 # define EFLG_RXEP 0x08
135 # define EFLG_TXEP 0x10
136 # define EFLG_TXBO 0x20
137 # define EFLG_RX0OVR 0x40
138 # define EFLG_RX1OVR 0x80
139 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
140 # define TXBCTRL_ABTF 0x40
141 # define TXBCTRL_MLOA 0x20
142 # define TXBCTRL_TXERR 0x10
143 # define TXBCTRL_TXREQ 0x08
144 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
145 # define SIDH_SHIFT 3
146 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
147 # define SIDL_SID_MASK 7
148 # define SIDL_SID_SHIFT 5
149 # define SIDL_EXIDE_SHIFT 3
150 # define SIDL_EID_SHIFT 16
151 # define SIDL_EID_MASK 3
152 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
153 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
154 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
155 # define DLC_RTR_SHIFT 6
156 #define TXBCTRL_OFF 0
157 #define TXBSIDH_OFF 1
158 #define TXBSIDL_OFF 2
159 #define TXBEID8_OFF 3
160 #define TXBEID0_OFF 4
161 #define TXBDLC_OFF 5
162 #define TXBDAT_OFF 6
163 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
164 # define RXBCTRL_BUKT 0x04
165 # define RXBCTRL_RXM0 0x20
166 # define RXBCTRL_RXM1 0x40
167 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
168 # define RXBSIDH_SHIFT 3
169 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
170 # define RXBSIDL_IDE 0x08
171 # define RXBSIDL_EID 3
172 # define RXBSIDL_SHIFT 5
173 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
174 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
175 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
176 # define RXBDLC_LEN_MASK 0x0f
177 # define RXBDLC_RTR 0x40
178 #define RXBCTRL_OFF 0
179 #define RXBSIDH_OFF 1
180 #define RXBSIDL_OFF 2
181 #define RXBEID8_OFF 3
182 #define RXBEID0_OFF 4
183 #define RXBDLC_OFF 5
184 #define RXBDAT_OFF 6
185 #define RXFSIDH(n) ((n) * 4)
186 #define RXFSIDL(n) ((n) * 4 + 1)
187 #define RXFEID8(n) ((n) * 4 + 2)
188 #define RXFEID0(n) ((n) * 4 + 3)
189 #define RXMSIDH(n) ((n) * 4 + 0x20)
190 #define RXMSIDL(n) ((n) * 4 + 0x21)
191 #define RXMEID8(n) ((n) * 4 + 0x22)
192 #define RXMEID0(n) ((n) * 4 + 0x23)
193
194 #define GET_BYTE(val, byte) \
195 (((val) >> ((byte) * 8)) & 0xff)
196 #define SET_BYTE(val, byte) \
197 (((val) & 0xff) << ((byte) * 8))
198
199 /*
200 * Buffer size required for the largest SPI transfer (i.e., reading a
201 * frame)
202 */
203 #define CAN_FRAME_MAX_DATA_LEN 8
204 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
205 #define CAN_FRAME_MAX_BITS 128
206
207 #define TX_ECHO_SKB_MAX 1
208
209 #define DEVICE_NAME "mcp251x"
210
211 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
212 module_param(mcp251x_enable_dma, int, S_IRUGO);
213 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
214
215 static struct can_bittiming_const mcp251x_bittiming_const = {
216 .name = DEVICE_NAME,
217 .tseg1_min = 3,
218 .tseg1_max = 16,
219 .tseg2_min = 2,
220 .tseg2_max = 8,
221 .sjw_max = 4,
222 .brp_min = 1,
223 .brp_max = 64,
224 .brp_inc = 1,
225 };
226
227 enum mcp251x_model {
228 CAN_MCP251X_MCP2510 = 0x2510,
229 CAN_MCP251X_MCP2515 = 0x2515,
230 };
231
232 struct mcp251x_priv {
233 struct can_priv can;
234 struct net_device *net;
235 struct spi_device *spi;
236 enum mcp251x_model model;
237
238 struct mutex mcp_lock; /* SPI device lock */
239
240 u8 *spi_tx_buf;
241 u8 *spi_rx_buf;
242 dma_addr_t spi_tx_dma;
243 dma_addr_t spi_rx_dma;
244
245 struct sk_buff *tx_skb;
246 int tx_len;
247
248 struct workqueue_struct *wq;
249 struct work_struct tx_work;
250 struct work_struct restart_work;
251
252 int force_quit;
253 int after_suspend;
254 #define AFTER_SUSPEND_UP 1
255 #define AFTER_SUSPEND_DOWN 2
256 #define AFTER_SUSPEND_POWER 4
257 #define AFTER_SUSPEND_RESTART 8
258 int restart_tx;
259 };
260
261 #define MCP251X_IS(_model) \
262 static inline int mcp251x_is_##_model(struct spi_device *spi) \
263 { \
264 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \
265 return priv->model == CAN_MCP251X_MCP##_model; \
266 }
267
268 MCP251X_IS(2510);
269 MCP251X_IS(2515);
270
271 static void mcp251x_clean(struct net_device *net)
272 {
273 struct mcp251x_priv *priv = netdev_priv(net);
274
275 if (priv->tx_skb || priv->tx_len)
276 net->stats.tx_errors++;
277 if (priv->tx_skb)
278 dev_kfree_skb(priv->tx_skb);
279 if (priv->tx_len)
280 can_free_echo_skb(priv->net, 0);
281 priv->tx_skb = NULL;
282 priv->tx_len = 0;
283 }
284
285 /*
286 * Note about handling of error return of mcp251x_spi_trans: accessing
287 * registers via SPI is not really different conceptually than using
288 * normal I/O assembler instructions, although it's much more
289 * complicated from a practical POV. So it's not advisable to always
290 * check the return value of this function. Imagine that every
291 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
292 * error();", it would be a great mess (well there are some situation
293 * when exception handling C++ like could be useful after all). So we
294 * just check that transfers are OK at the beginning of our
295 * conversation with the chip and to avoid doing really nasty things
296 * (like injecting bogus packets in the network stack).
297 */
298 static int mcp251x_spi_trans(struct spi_device *spi, int len)
299 {
300 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
301 struct spi_transfer t = {
302 .tx_buf = priv->spi_tx_buf,
303 .rx_buf = priv->spi_rx_buf,
304 .len = len,
305 .cs_change = 0,
306 };
307 struct spi_message m;
308 int ret;
309
310 spi_message_init(&m);
311
312 if (mcp251x_enable_dma) {
313 t.tx_dma = priv->spi_tx_dma;
314 t.rx_dma = priv->spi_rx_dma;
315 m.is_dma_mapped = 1;
316 }
317
318 spi_message_add_tail(&t, &m);
319
320 ret = spi_sync(spi, &m);
321 if (ret)
322 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
323 return ret;
324 }
325
326 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
327 {
328 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
329 u8 val = 0;
330
331 priv->spi_tx_buf[0] = INSTRUCTION_READ;
332 priv->spi_tx_buf[1] = reg;
333
334 mcp251x_spi_trans(spi, 3);
335 val = priv->spi_rx_buf[2];
336
337 return val;
338 }
339
340 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
341 uint8_t *v1, uint8_t *v2)
342 {
343 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
344
345 priv->spi_tx_buf[0] = INSTRUCTION_READ;
346 priv->spi_tx_buf[1] = reg;
347
348 mcp251x_spi_trans(spi, 4);
349
350 *v1 = priv->spi_rx_buf[2];
351 *v2 = priv->spi_rx_buf[3];
352 }
353
354 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
355 {
356 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
357
358 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
359 priv->spi_tx_buf[1] = reg;
360 priv->spi_tx_buf[2] = val;
361
362 mcp251x_spi_trans(spi, 3);
363 }
364
365 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
366 u8 mask, uint8_t val)
367 {
368 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
369
370 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
371 priv->spi_tx_buf[1] = reg;
372 priv->spi_tx_buf[2] = mask;
373 priv->spi_tx_buf[3] = val;
374
375 mcp251x_spi_trans(spi, 4);
376 }
377
378 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
379 int len, int tx_buf_idx)
380 {
381 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
382
383 if (mcp251x_is_2510(spi)) {
384 int i;
385
386 for (i = 1; i < TXBDAT_OFF + len; i++)
387 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
388 buf[i]);
389 } else {
390 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
391 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
392 }
393 }
394
395 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
396 int tx_buf_idx)
397 {
398 u32 sid, eid, exide, rtr;
399 u8 buf[SPI_TRANSFER_BUF_LEN];
400
401 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
402 if (exide)
403 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
404 else
405 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
406 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
407 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
408
409 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
410 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
411 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
412 (exide << SIDL_EXIDE_SHIFT) |
413 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
414 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
415 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
416 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
417 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
418 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
419 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
420 }
421
422 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
423 int buf_idx)
424 {
425 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
426
427 if (mcp251x_is_2510(spi)) {
428 int i, len;
429
430 for (i = 1; i < RXBDAT_OFF; i++)
431 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
432
433 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
434 for (; i < (RXBDAT_OFF + len); i++)
435 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
436 } else {
437 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
438 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
439 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
440 }
441 }
442
443 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
444 {
445 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
446 struct sk_buff *skb;
447 struct can_frame *frame;
448 u8 buf[SPI_TRANSFER_BUF_LEN];
449
450 skb = alloc_can_skb(priv->net, &frame);
451 if (!skb) {
452 dev_err(&spi->dev, "cannot allocate RX skb\n");
453 priv->net->stats.rx_dropped++;
454 return;
455 }
456
457 mcp251x_hw_rx_frame(spi, buf, buf_idx);
458 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
459 /* Extended ID format */
460 frame->can_id = CAN_EFF_FLAG;
461 frame->can_id |=
462 /* Extended ID part */
463 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
464 SET_BYTE(buf[RXBEID8_OFF], 1) |
465 SET_BYTE(buf[RXBEID0_OFF], 0) |
466 /* Standard ID part */
467 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
468 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
469 /* Remote transmission request */
470 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
471 frame->can_id |= CAN_RTR_FLAG;
472 } else {
473 /* Standard ID format */
474 frame->can_id =
475 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
476 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
477 }
478 /* Data length */
479 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
480 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
481
482 priv->net->stats.rx_packets++;
483 priv->net->stats.rx_bytes += frame->can_dlc;
484 netif_rx_ni(skb);
485 }
486
487 static void mcp251x_hw_sleep(struct spi_device *spi)
488 {
489 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
490 }
491
492 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
493 struct net_device *net)
494 {
495 struct mcp251x_priv *priv = netdev_priv(net);
496 struct spi_device *spi = priv->spi;
497
498 if (priv->tx_skb || priv->tx_len) {
499 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
500 return NETDEV_TX_BUSY;
501 }
502
503 if (can_dropped_invalid_skb(net, skb))
504 return NETDEV_TX_OK;
505
506 netif_stop_queue(net);
507 priv->tx_skb = skb;
508 queue_work(priv->wq, &priv->tx_work);
509
510 return NETDEV_TX_OK;
511 }
512
513 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
514 {
515 struct mcp251x_priv *priv = netdev_priv(net);
516
517 switch (mode) {
518 case CAN_MODE_START:
519 mcp251x_clean(net);
520 /* We have to delay work since SPI I/O may sleep */
521 priv->can.state = CAN_STATE_ERROR_ACTIVE;
522 priv->restart_tx = 1;
523 if (priv->can.restart_ms == 0)
524 priv->after_suspend = AFTER_SUSPEND_RESTART;
525 queue_work(priv->wq, &priv->restart_work);
526 break;
527 default:
528 return -EOPNOTSUPP;
529 }
530
531 return 0;
532 }
533
534 static int mcp251x_set_normal_mode(struct spi_device *spi)
535 {
536 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
537 unsigned long timeout;
538
539 /* Enable interrupts */
540 mcp251x_write_reg(spi, CANINTE,
541 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
542 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
543
544 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
545 /* Put device into loopback mode */
546 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
547 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
548 /* Put device into listen-only mode */
549 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
550 } else {
551 /* Put device into normal mode */
552 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
553
554 /* Wait for the device to enter normal mode */
555 timeout = jiffies + HZ;
556 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
557 schedule();
558 if (time_after(jiffies, timeout)) {
559 dev_err(&spi->dev, "MCP251x didn't"
560 " enter in normal mode\n");
561 return -EBUSY;
562 }
563 }
564 }
565 priv->can.state = CAN_STATE_ERROR_ACTIVE;
566 return 0;
567 }
568
569 static int mcp251x_do_set_bittiming(struct net_device *net)
570 {
571 struct mcp251x_priv *priv = netdev_priv(net);
572 struct can_bittiming *bt = &priv->can.bittiming;
573 struct spi_device *spi = priv->spi;
574
575 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
576 (bt->brp - 1));
577 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
578 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
579 CNF2_SAM : 0) |
580 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
581 (bt->prop_seg - 1));
582 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
583 (bt->phase_seg2 - 1));
584 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
585 mcp251x_read_reg(spi, CNF1),
586 mcp251x_read_reg(spi, CNF2),
587 mcp251x_read_reg(spi, CNF3));
588
589 return 0;
590 }
591
592 static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
593 struct spi_device *spi)
594 {
595 mcp251x_do_set_bittiming(net);
596
597 mcp251x_write_reg(spi, RXBCTRL(0),
598 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
599 mcp251x_write_reg(spi, RXBCTRL(1),
600 RXBCTRL_RXM0 | RXBCTRL_RXM1);
601 return 0;
602 }
603
604 static int mcp251x_hw_reset(struct spi_device *spi)
605 {
606 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
607 int ret;
608 unsigned long timeout;
609
610 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
611 ret = spi_write(spi, priv->spi_tx_buf, 1);
612 if (ret) {
613 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
614 return -EIO;
615 }
616
617 /* Wait for reset to finish */
618 timeout = jiffies + HZ;
619 mdelay(10);
620 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
621 != CANCTRL_REQOP_CONF) {
622 schedule();
623 if (time_after(jiffies, timeout)) {
624 dev_err(&spi->dev, "MCP251x didn't"
625 " enter in conf mode after reset\n");
626 return -EBUSY;
627 }
628 }
629 return 0;
630 }
631
632 static int mcp251x_hw_probe(struct spi_device *spi)
633 {
634 int st1, st2;
635
636 mcp251x_hw_reset(spi);
637
638 /*
639 * Please note that these are "magic values" based on after
640 * reset defaults taken from data sheet which allows us to see
641 * if we really have a chip on the bus (we avoid common all
642 * zeroes or all ones situations)
643 */
644 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
645 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
646
647 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
648
649 /* Check for power up default values */
650 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
651 }
652
653 static void mcp251x_open_clean(struct net_device *net)
654 {
655 struct mcp251x_priv *priv = netdev_priv(net);
656 struct spi_device *spi = priv->spi;
657 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
658
659 free_irq(spi->irq, priv);
660 mcp251x_hw_sleep(spi);
661 if (pdata->transceiver_enable)
662 pdata->transceiver_enable(0);
663 close_candev(net);
664 }
665
666 static int mcp251x_stop(struct net_device *net)
667 {
668 struct mcp251x_priv *priv = netdev_priv(net);
669 struct spi_device *spi = priv->spi;
670 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
671
672 close_candev(net);
673
674 priv->force_quit = 1;
675 free_irq(spi->irq, priv);
676 destroy_workqueue(priv->wq);
677 priv->wq = NULL;
678
679 mutex_lock(&priv->mcp_lock);
680
681 /* Disable and clear pending interrupts */
682 mcp251x_write_reg(spi, CANINTE, 0x00);
683 mcp251x_write_reg(spi, CANINTF, 0x00);
684
685 mcp251x_write_reg(spi, TXBCTRL(0), 0);
686 mcp251x_clean(net);
687
688 mcp251x_hw_sleep(spi);
689
690 if (pdata->transceiver_enable)
691 pdata->transceiver_enable(0);
692
693 priv->can.state = CAN_STATE_STOPPED;
694
695 mutex_unlock(&priv->mcp_lock);
696
697 return 0;
698 }
699
700 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
701 {
702 struct sk_buff *skb;
703 struct can_frame *frame;
704
705 skb = alloc_can_err_skb(net, &frame);
706 if (skb) {
707 frame->can_id = can_id;
708 frame->data[1] = data1;
709 netif_rx_ni(skb);
710 } else {
711 dev_err(&net->dev,
712 "cannot allocate error skb\n");
713 }
714 }
715
716 static void mcp251x_tx_work_handler(struct work_struct *ws)
717 {
718 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
719 tx_work);
720 struct spi_device *spi = priv->spi;
721 struct net_device *net = priv->net;
722 struct can_frame *frame;
723
724 mutex_lock(&priv->mcp_lock);
725 if (priv->tx_skb) {
726 if (priv->can.state == CAN_STATE_BUS_OFF) {
727 mcp251x_clean(net);
728 } else {
729 frame = (struct can_frame *)priv->tx_skb->data;
730
731 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
732 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
733 mcp251x_hw_tx(spi, frame, 0);
734 priv->tx_len = 1 + frame->can_dlc;
735 can_put_echo_skb(priv->tx_skb, net, 0);
736 priv->tx_skb = NULL;
737 }
738 }
739 mutex_unlock(&priv->mcp_lock);
740 }
741
742 static void mcp251x_restart_work_handler(struct work_struct *ws)
743 {
744 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
745 restart_work);
746 struct spi_device *spi = priv->spi;
747 struct net_device *net = priv->net;
748
749 mutex_lock(&priv->mcp_lock);
750 if (priv->after_suspend) {
751 mdelay(10);
752 mcp251x_hw_reset(spi);
753 mcp251x_setup(net, priv, spi);
754 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
755 mcp251x_set_normal_mode(spi);
756 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
757 netif_device_attach(net);
758 mcp251x_clean(net);
759 mcp251x_set_normal_mode(spi);
760 netif_wake_queue(net);
761 } else {
762 mcp251x_hw_sleep(spi);
763 }
764 priv->after_suspend = 0;
765 priv->force_quit = 0;
766 }
767
768 if (priv->restart_tx) {
769 priv->restart_tx = 0;
770 mcp251x_write_reg(spi, TXBCTRL(0), 0);
771 mcp251x_clean(net);
772 netif_wake_queue(net);
773 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
774 }
775 mutex_unlock(&priv->mcp_lock);
776 }
777
778 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
779 {
780 struct mcp251x_priv *priv = dev_id;
781 struct spi_device *spi = priv->spi;
782 struct net_device *net = priv->net;
783
784 mutex_lock(&priv->mcp_lock);
785 while (!priv->force_quit) {
786 enum can_state new_state;
787 u8 intf, eflag;
788 u8 clear_intf = 0;
789 int can_id = 0, data1 = 0;
790
791 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
792
793 /* receive buffer 0 */
794 if (intf & CANINTF_RX0IF) {
795 mcp251x_hw_rx(spi, 0);
796 /* Free one buffer ASAP */
797 mcp251x_write_bits(spi, CANINTF, intf & CANINTF_RX0IF,
798 0x00);
799 }
800
801 /* receive buffer 1 */
802 if (intf & CANINTF_RX1IF) {
803 mcp251x_hw_rx(spi, 1);
804 clear_intf |= CANINTF_RX1IF;
805 }
806
807 /* any error or tx interrupt we need to clear? */
808 if (intf & CANINTF_ERR_TX)
809 clear_intf |= intf & CANINTF_ERR_TX;
810 if (clear_intf)
811 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
812
813 if (eflag)
814 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
815
816 /* Update can state */
817 if (eflag & EFLG_TXBO) {
818 new_state = CAN_STATE_BUS_OFF;
819 can_id |= CAN_ERR_BUSOFF;
820 } else if (eflag & EFLG_TXEP) {
821 new_state = CAN_STATE_ERROR_PASSIVE;
822 can_id |= CAN_ERR_CRTL;
823 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
824 } else if (eflag & EFLG_RXEP) {
825 new_state = CAN_STATE_ERROR_PASSIVE;
826 can_id |= CAN_ERR_CRTL;
827 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
828 } else if (eflag & EFLG_TXWAR) {
829 new_state = CAN_STATE_ERROR_WARNING;
830 can_id |= CAN_ERR_CRTL;
831 data1 |= CAN_ERR_CRTL_TX_WARNING;
832 } else if (eflag & EFLG_RXWAR) {
833 new_state = CAN_STATE_ERROR_WARNING;
834 can_id |= CAN_ERR_CRTL;
835 data1 |= CAN_ERR_CRTL_RX_WARNING;
836 } else {
837 new_state = CAN_STATE_ERROR_ACTIVE;
838 }
839
840 /* Update can state statistics */
841 switch (priv->can.state) {
842 case CAN_STATE_ERROR_ACTIVE:
843 if (new_state >= CAN_STATE_ERROR_WARNING &&
844 new_state <= CAN_STATE_BUS_OFF)
845 priv->can.can_stats.error_warning++;
846 case CAN_STATE_ERROR_WARNING: /* fallthrough */
847 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
848 new_state <= CAN_STATE_BUS_OFF)
849 priv->can.can_stats.error_passive++;
850 break;
851 default:
852 break;
853 }
854 priv->can.state = new_state;
855
856 if (intf & CANINTF_ERRIF) {
857 /* Handle overflow counters */
858 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
859 if (eflag & EFLG_RX0OVR) {
860 net->stats.rx_over_errors++;
861 net->stats.rx_errors++;
862 }
863 if (eflag & EFLG_RX1OVR) {
864 net->stats.rx_over_errors++;
865 net->stats.rx_errors++;
866 }
867 can_id |= CAN_ERR_CRTL;
868 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
869 }
870 mcp251x_error_skb(net, can_id, data1);
871 }
872
873 if (priv->can.state == CAN_STATE_BUS_OFF) {
874 if (priv->can.restart_ms == 0) {
875 priv->force_quit = 1;
876 can_bus_off(net);
877 mcp251x_hw_sleep(spi);
878 break;
879 }
880 }
881
882 if (intf == 0)
883 break;
884
885 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
886 net->stats.tx_packets++;
887 net->stats.tx_bytes += priv->tx_len - 1;
888 if (priv->tx_len) {
889 can_get_echo_skb(net, 0);
890 priv->tx_len = 0;
891 }
892 netif_wake_queue(net);
893 }
894
895 }
896 mutex_unlock(&priv->mcp_lock);
897 return IRQ_HANDLED;
898 }
899
900 static int mcp251x_open(struct net_device *net)
901 {
902 struct mcp251x_priv *priv = netdev_priv(net);
903 struct spi_device *spi = priv->spi;
904 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
905 int ret;
906
907 ret = open_candev(net);
908 if (ret) {
909 dev_err(&spi->dev, "unable to set initial baudrate!\n");
910 return ret;
911 }
912
913 mutex_lock(&priv->mcp_lock);
914 if (pdata->transceiver_enable)
915 pdata->transceiver_enable(1);
916
917 priv->force_quit = 0;
918 priv->tx_skb = NULL;
919 priv->tx_len = 0;
920
921 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
922 IRQF_TRIGGER_FALLING, DEVICE_NAME, priv);
923 if (ret) {
924 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
925 if (pdata->transceiver_enable)
926 pdata->transceiver_enable(0);
927 close_candev(net);
928 goto open_unlock;
929 }
930
931 priv->wq = create_freezeable_workqueue("mcp251x_wq");
932 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
933 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
934
935 ret = mcp251x_hw_reset(spi);
936 if (ret) {
937 mcp251x_open_clean(net);
938 goto open_unlock;
939 }
940 ret = mcp251x_setup(net, priv, spi);
941 if (ret) {
942 mcp251x_open_clean(net);
943 goto open_unlock;
944 }
945 ret = mcp251x_set_normal_mode(spi);
946 if (ret) {
947 mcp251x_open_clean(net);
948 goto open_unlock;
949 }
950 netif_wake_queue(net);
951
952 open_unlock:
953 mutex_unlock(&priv->mcp_lock);
954 return ret;
955 }
956
957 static const struct net_device_ops mcp251x_netdev_ops = {
958 .ndo_open = mcp251x_open,
959 .ndo_stop = mcp251x_stop,
960 .ndo_start_xmit = mcp251x_hard_start_xmit,
961 };
962
963 static int __devinit mcp251x_can_probe(struct spi_device *spi)
964 {
965 struct net_device *net;
966 struct mcp251x_priv *priv;
967 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
968 int ret = -ENODEV;
969
970 if (!pdata)
971 /* Platform data is required for osc freq */
972 goto error_out;
973
974 /* Allocate can/net device */
975 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
976 if (!net) {
977 ret = -ENOMEM;
978 goto error_alloc;
979 }
980
981 net->netdev_ops = &mcp251x_netdev_ops;
982 net->flags |= IFF_ECHO;
983
984 priv = netdev_priv(net);
985 priv->can.bittiming_const = &mcp251x_bittiming_const;
986 priv->can.do_set_mode = mcp251x_do_set_mode;
987 priv->can.clock.freq = pdata->oscillator_frequency / 2;
988 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
989 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
990 priv->model = spi_get_device_id(spi)->driver_data;
991 priv->net = net;
992 dev_set_drvdata(&spi->dev, priv);
993
994 priv->spi = spi;
995 mutex_init(&priv->mcp_lock);
996
997 /* If requested, allocate DMA buffers */
998 if (mcp251x_enable_dma) {
999 spi->dev.coherent_dma_mask = ~0;
1000
1001 /*
1002 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1003 * that much and share it between Tx and Rx DMA buffers.
1004 */
1005 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1006 PAGE_SIZE,
1007 &priv->spi_tx_dma,
1008 GFP_DMA);
1009
1010 if (priv->spi_tx_buf) {
1011 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
1012 (PAGE_SIZE / 2));
1013 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1014 (PAGE_SIZE / 2));
1015 } else {
1016 /* Fall back to non-DMA */
1017 mcp251x_enable_dma = 0;
1018 }
1019 }
1020
1021 /* Allocate non-DMA buffers */
1022 if (!mcp251x_enable_dma) {
1023 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1024 if (!priv->spi_tx_buf) {
1025 ret = -ENOMEM;
1026 goto error_tx_buf;
1027 }
1028 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1029 if (!priv->spi_rx_buf) {
1030 ret = -ENOMEM;
1031 goto error_rx_buf;
1032 }
1033 }
1034
1035 if (pdata->power_enable)
1036 pdata->power_enable(1);
1037
1038 /* Call out to platform specific setup */
1039 if (pdata->board_specific_setup)
1040 pdata->board_specific_setup(spi);
1041
1042 SET_NETDEV_DEV(net, &spi->dev);
1043
1044 /* Configure the SPI bus */
1045 spi->mode = SPI_MODE_0;
1046 spi->bits_per_word = 8;
1047 spi_setup(spi);
1048
1049 /* Here is OK to not lock the MCP, no one knows about it yet */
1050 if (!mcp251x_hw_probe(spi)) {
1051 dev_info(&spi->dev, "Probe failed\n");
1052 goto error_probe;
1053 }
1054 mcp251x_hw_sleep(spi);
1055
1056 if (pdata->transceiver_enable)
1057 pdata->transceiver_enable(0);
1058
1059 ret = register_candev(net);
1060 if (!ret) {
1061 dev_info(&spi->dev, "probed\n");
1062 return ret;
1063 }
1064 error_probe:
1065 if (!mcp251x_enable_dma)
1066 kfree(priv->spi_rx_buf);
1067 error_rx_buf:
1068 if (!mcp251x_enable_dma)
1069 kfree(priv->spi_tx_buf);
1070 error_tx_buf:
1071 free_candev(net);
1072 if (mcp251x_enable_dma)
1073 dma_free_coherent(&spi->dev, PAGE_SIZE,
1074 priv->spi_tx_buf, priv->spi_tx_dma);
1075 error_alloc:
1076 if (pdata->power_enable)
1077 pdata->power_enable(0);
1078 dev_err(&spi->dev, "probe failed\n");
1079 error_out:
1080 return ret;
1081 }
1082
1083 static int __devexit mcp251x_can_remove(struct spi_device *spi)
1084 {
1085 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1086 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1087 struct net_device *net = priv->net;
1088
1089 unregister_candev(net);
1090 free_candev(net);
1091
1092 if (mcp251x_enable_dma) {
1093 dma_free_coherent(&spi->dev, PAGE_SIZE,
1094 priv->spi_tx_buf, priv->spi_tx_dma);
1095 } else {
1096 kfree(priv->spi_tx_buf);
1097 kfree(priv->spi_rx_buf);
1098 }
1099
1100 if (pdata->power_enable)
1101 pdata->power_enable(0);
1102
1103 return 0;
1104 }
1105
1106 #ifdef CONFIG_PM
1107 static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1108 {
1109 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1110 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1111 struct net_device *net = priv->net;
1112
1113 priv->force_quit = 1;
1114 disable_irq(spi->irq);
1115 /*
1116 * Note: at this point neither IST nor workqueues are running.
1117 * open/stop cannot be called anyway so locking is not needed
1118 */
1119 if (netif_running(net)) {
1120 netif_device_detach(net);
1121
1122 mcp251x_hw_sleep(spi);
1123 if (pdata->transceiver_enable)
1124 pdata->transceiver_enable(0);
1125 priv->after_suspend = AFTER_SUSPEND_UP;
1126 } else {
1127 priv->after_suspend = AFTER_SUSPEND_DOWN;
1128 }
1129
1130 if (pdata->power_enable) {
1131 pdata->power_enable(0);
1132 priv->after_suspend |= AFTER_SUSPEND_POWER;
1133 }
1134
1135 return 0;
1136 }
1137
1138 static int mcp251x_can_resume(struct spi_device *spi)
1139 {
1140 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1141 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1142
1143 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1144 pdata->power_enable(1);
1145 queue_work(priv->wq, &priv->restart_work);
1146 } else {
1147 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1148 if (pdata->transceiver_enable)
1149 pdata->transceiver_enable(1);
1150 queue_work(priv->wq, &priv->restart_work);
1151 } else {
1152 priv->after_suspend = 0;
1153 }
1154 }
1155 priv->force_quit = 0;
1156 enable_irq(spi->irq);
1157 return 0;
1158 }
1159 #else
1160 #define mcp251x_can_suspend NULL
1161 #define mcp251x_can_resume NULL
1162 #endif
1163
1164 static const struct spi_device_id mcp251x_id_table[] = {
1165 { "mcp2510", CAN_MCP251X_MCP2510 },
1166 { "mcp2515", CAN_MCP251X_MCP2515 },
1167 { },
1168 };
1169
1170 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1171
1172 static struct spi_driver mcp251x_can_driver = {
1173 .driver = {
1174 .name = DEVICE_NAME,
1175 .bus = &spi_bus_type,
1176 .owner = THIS_MODULE,
1177 },
1178
1179 .id_table = mcp251x_id_table,
1180 .probe = mcp251x_can_probe,
1181 .remove = __devexit_p(mcp251x_can_remove),
1182 .suspend = mcp251x_can_suspend,
1183 .resume = mcp251x_can_resume,
1184 };
1185
1186 static int __init mcp251x_can_init(void)
1187 {
1188 return spi_register_driver(&mcp251x_can_driver);
1189 }
1190
1191 static void __exit mcp251x_can_exit(void)
1192 {
1193 spi_unregister_driver(&mcp251x_can_driver);
1194 }
1195
1196 module_init(mcp251x_can_init);
1197 module_exit(mcp251x_can_exit);
1198
1199 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1200 "Christian Pellegrin <chripell@evolware.org>");
1201 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1202 MODULE_LICENSE("GPL v2");
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