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arm: at91: move platfarm_data to include/linux/platform_data/atmel.h
[linux-2.6.git] / drivers / net / ethernet / cadence / at91_ether.c
blob35fc6edbacf807ce098b452ede6bb43b2ee77dc6
1 /*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
3 *
4 * Copyright (C) 2003 SAN People (Pty) Ltd
5 *
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
8 *
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
11 *
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/mii.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/ethtool.h>
29 #include <linux/platform_data/macb.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/gfp.h>
33 #include <linux/phy.h>
34 #include <linux/platform_data/atmel.h>
35
36 #include <asm/io.h>
37 #include <asm/uaccess.h>
38 #include <asm/mach-types.h>
39
40 #include <mach/at91rm9200_emac.h>
41 #include <asm/gpio.h>
42
43 #include "at91_ether.h"
44
45 #define DRV_NAME "at91_ether"
46 #define DRV_VERSION "1.0"
47
48 #define LINK_POLL_INTERVAL (HZ)
49
50 /* ..................................................................... */
51
52 /*
53 * Read from a EMAC register.
54 */
55 static inline unsigned long at91_emac_read(struct at91_private *lp, unsigned int reg)
56 {
57 return __raw_readl(lp->emac_base + reg);
58 }
59
60 /*
61 * Write to a EMAC register.
62 */
63 static inline void at91_emac_write(struct at91_private *lp, unsigned int reg, unsigned long value)
64 {
65 __raw_writel(value, lp->emac_base + reg);
66 }
67
68 /* ........................... PHY INTERFACE ........................... */
69
70 /*
71 * Enable the MDIO bit in MAC control register
72 * When not called from an interrupt-handler, access to the PHY must be
73 * protected by a spinlock.
74 */
75 static void enable_mdi(struct at91_private *lp)
76 {
77 unsigned long ctl;
78
79 ctl = at91_emac_read(lp, AT91_EMAC_CTL);
80 at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
81 }
82
83 /*
84 * Disable the MDIO bit in the MAC control register
85 */
86 static void disable_mdi(struct at91_private *lp)
87 {
88 unsigned long ctl;
89
90 ctl = at91_emac_read(lp, AT91_EMAC_CTL);
91 at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
92 }
93
94 /*
95 * Wait until the PHY operation is complete.
96 */
97 static inline void at91_phy_wait(struct at91_private *lp)
98 {
99 unsigned long timeout = jiffies + 2;
100
101 while (!(at91_emac_read(lp, AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
102 if (time_after(jiffies, timeout)) {
103 printk("at91_ether: MIO timeout\n");
104 break;
105 }
106 cpu_relax();
107 }
108 }
109
110 /*
111 * Write value to the a PHY register
112 * Note: MDI interface is assumed to already have been enabled.
113 */
114 static void write_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int value)
115 {
116 at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
117 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
118
119 /* Wait until IDLE bit in Network Status register is cleared */
120 at91_phy_wait(lp);
121 }
122
123 /*
124 * Read value stored in a PHY register.
125 * Note: MDI interface is assumed to already have been enabled.
126 */
127 static void read_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int *value)
128 {
129 at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
130 | ((phy_addr & 0x1f) << 23) | (address << 18));
131
132 /* Wait until IDLE bit in Network Status register is cleared */
133 at91_phy_wait(lp);
134
135 *value = at91_emac_read(lp, AT91_EMAC_MAN) & AT91_EMAC_DATA;
136 }
137
138 /* ........................... PHY MANAGEMENT .......................... */
139
140 /*
141 * Access the PHY to determine the current link speed and mode, and update the
142 * MAC accordingly.
143 * If no link or auto-negotiation is busy, then no changes are made.
144 */
145 static void update_linkspeed(struct net_device *dev, int silent)
146 {
147 struct at91_private *lp = netdev_priv(dev);
148 unsigned int bmsr, bmcr, lpa, mac_cfg;
149 unsigned int speed, duplex;
150
151 if (!mii_link_ok(&lp->mii)) { /* no link */
152 netif_carrier_off(dev);
153 if (!silent)
154 printk(KERN_INFO "%s: Link down.\n", dev->name);
155 return;
156 }
157
158 /* Link up, or auto-negotiation still in progress */
159 read_phy(lp, lp->phy_address, MII_BMSR, &bmsr);
160 read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
161 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
162 if (!(bmsr & BMSR_ANEGCOMPLETE))
163 return; /* Do nothing - another interrupt generated when negotiation complete */
164
165 read_phy(lp, lp->phy_address, MII_LPA, &lpa);
166 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
167 else speed = SPEED_10;
168 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
169 else duplex = DUPLEX_HALF;
170 } else {
171 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
172 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
173 }
174
175 /* Update the MAC */
176 mac_cfg = at91_emac_read(lp, AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
177 if (speed == SPEED_100) {
178 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
179 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
180 else /* 100 Half Duplex */
181 mac_cfg |= AT91_EMAC_SPD;
182 } else {
183 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
184 mac_cfg |= AT91_EMAC_FD;
185 else {} /* 10 Half Duplex */
186 }
187 at91_emac_write(lp, AT91_EMAC_CFG, mac_cfg);
188
189 if (!silent)
190 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
191 netif_carrier_on(dev);
192 }
193
194 /*
195 * Handle interrupts from the PHY
196 */
197 static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
198 {
199 struct net_device *dev = (struct net_device *) dev_id;
200 struct at91_private *lp = netdev_priv(dev);
201 unsigned int phy;
202
203 /*
204 * This hander is triggered on both edges, but the PHY chips expect
205 * level-triggering. We therefore have to check if the PHY actually has
206 * an IRQ pending.
207 */
208 enable_mdi(lp);
209 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
210 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
211 if (!(phy & (1 << 0)))
212 goto done;
213 }
214 else if (lp->phy_type == MII_LXT971A_ID) {
215 read_phy(lp, lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
216 if (!(phy & (1 << 2)))
217 goto done;
218 }
219 else if (lp->phy_type == MII_BCM5221_ID) {
220 read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
221 if (!(phy & (1 << 0)))
222 goto done;
223 }
224 else if (lp->phy_type == MII_KS8721_ID) {
225 read_phy(lp, lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
226 if (!(phy & ((1 << 2) | 1)))
227 goto done;
228 }
229 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
230 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &phy);
231 if (!(phy & ((1 << 2) | 1)))
232 goto done;
233 }
234 else if (lp->phy_type == MII_DP83848_ID) {
235 read_phy(lp, lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
236 if (!(phy & (1 << 7)))
237 goto done;
238 }
239
240 update_linkspeed(dev, 0);
241
242 done:
243 disable_mdi(lp);
244
245 return IRQ_HANDLED;
246 }
247
248 /*
249 * Initialize and enable the PHY interrupt for link-state changes
250 */
251 static void enable_phyirq(struct net_device *dev)
252 {
253 struct at91_private *lp = netdev_priv(dev);
254 unsigned int dsintr, irq_number;
255 int status;
256
257 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
258 /*
259 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
260 * or board does not have it connected.
261 */
262 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
263 return;
264 }
265
266 irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
267 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
268 if (status) {
269 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
270 return;
271 }
272
273 spin_lock_irq(&lp->lock);
274 enable_mdi(lp);
275
276 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
277 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
278 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
279 write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
280 }
281 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
282 read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
283 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
284 write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
285 }
286 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
287 dsintr = (1 << 15) | ( 1 << 14);
288 write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
289 }
290 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
291 dsintr = (1 << 10) | ( 1 << 8);
292 write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
293 }
294 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
295 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
296 dsintr = dsintr | 0x500; /* set bits 8, 10 */
297 write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
298 }
299 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
300 read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
301 dsintr = dsintr | 0x3c; /* set bits 2..5 */
302 write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
303 read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
304 dsintr = dsintr | 0x3; /* set bits 0,1 */
305 write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
306 }
307
308 disable_mdi(lp);
309 spin_unlock_irq(&lp->lock);
310 }
311
312 /*
313 * Disable the PHY interrupt
314 */
315 static void disable_phyirq(struct net_device *dev)
316 {
317 struct at91_private *lp = netdev_priv(dev);
318 unsigned int dsintr;
319 unsigned int irq_number;
320
321 if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
322 del_timer_sync(&lp->check_timer);
323 return;
324 }
325
326 spin_lock_irq(&lp->lock);
327 enable_mdi(lp);
328
329 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
330 read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
331 dsintr = dsintr | 0xf00; /* set bits 8..11 */
332 write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
333 }
334 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
335 read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
336 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
337 write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
338 }
339 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
340 read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &dsintr);
341 dsintr = ~(1 << 14);
342 write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
343 }
344 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
345 read_phy(lp, lp->phy_address, MII_TPISTATUS, &dsintr);
346 dsintr = ~((1 << 10) | (1 << 8));
347 write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
348 }
349 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
350 read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
351 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
352 write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
353 }
354 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
355 read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
356 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
357 write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
358 read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
359 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
360 write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
361 }
362
363 disable_mdi(lp);
364 spin_unlock_irq(&lp->lock);
365
366 irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
367 free_irq(irq_number, dev); /* Free interrupt handler */
368 }
369
370 /*
371 * Perform a software reset of the PHY.
372 */
373 #if 0
374 static void reset_phy(struct net_device *dev)
375 {
376 struct at91_private *lp = netdev_priv(dev);
377 unsigned int bmcr;
378
379 spin_lock_irq(&lp->lock);
380 enable_mdi(lp);
381
382 /* Perform PHY reset */
383 write_phy(lp, lp->phy_address, MII_BMCR, BMCR_RESET);
384
385 /* Wait until PHY reset is complete */
386 do {
387 read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
388 } while (!(bmcr & BMCR_RESET));
389
390 disable_mdi(lp);
391 spin_unlock_irq(&lp->lock);
392 }
393 #endif
394
395 static void at91ether_check_link(unsigned long dev_id)
396 {
397 struct net_device *dev = (struct net_device *) dev_id;
398 struct at91_private *lp = netdev_priv(dev);
399
400 enable_mdi(lp);
401 update_linkspeed(dev, 1);
402 disable_mdi(lp);
403
404 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
405 }
406
407 /*
408 * Perform any PHY-specific initialization.
409 */
410 static void __init initialize_phy(struct at91_private *lp)
411 {
412 unsigned int val;
413
414 spin_lock_irq(&lp->lock);
415 enable_mdi(lp);
416
417 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
418 read_phy(lp, lp->phy_address, MII_DSCR_REG, &val);
419 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
420 lp->phy_media = PORT_FIBRE;
421 } else if (machine_is_csb337()) {
422 /* mix link activity status into LED2 link state */
423 write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x0d22);
424 } else if (machine_is_ecbat91())
425 write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x156A);
426
427 disable_mdi(lp);
428 spin_unlock_irq(&lp->lock);
429 }
430
431 /* ......................... ADDRESS MANAGEMENT ........................ */
432
433 /*
434 * NOTE: Your bootloader must always set the MAC address correctly before
435 * booting into Linux.
436 *
437 * - It must always set the MAC address after reset, even if it doesn't
438 * happen to access the Ethernet while it's booting. Some versions of
439 * U-Boot on the AT91RM9200-DK do not do this.
440 *
441 * - Likewise it must store the addresses in the correct byte order.
442 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
443 * continues to do so, for bug-compatibility).
444 */
445
446 static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
447 {
448 char addr[6];
449
450 if (machine_is_csb337()) {
451 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
452 addr[4] = (lo & 0xff00) >> 8;
453 addr[3] = (lo & 0xff0000) >> 16;
454 addr[2] = (lo & 0xff000000) >> 24;
455 addr[1] = (hi & 0xff);
456 addr[0] = (hi & 0xff00) >> 8;
457 }
458 else {
459 addr[0] = (lo & 0xff);
460 addr[1] = (lo & 0xff00) >> 8;
461 addr[2] = (lo & 0xff0000) >> 16;
462 addr[3] = (lo & 0xff000000) >> 24;
463 addr[4] = (hi & 0xff);
464 addr[5] = (hi & 0xff00) >> 8;
465 }
466
467 if (is_valid_ether_addr(addr)) {
468 memcpy(dev->dev_addr, &addr, 6);
469 return 1;
470 }
471 return 0;
472 }
473
474 /*
475 * Set the ethernet MAC address in dev->dev_addr
476 */
477 static void __init get_mac_address(struct net_device *dev)
478 {
479 struct at91_private *lp = netdev_priv(dev);
480
481 /* Check Specific-Address 1 */
482 if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA1H), at91_emac_read(lp, AT91_EMAC_SA1L)))
483 return;
484 /* Check Specific-Address 2 */
485 if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA2H), at91_emac_read(lp, AT91_EMAC_SA2L)))
486 return;
487 /* Check Specific-Address 3 */
488 if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA3H), at91_emac_read(lp, AT91_EMAC_SA3L)))
489 return;
490 /* Check Specific-Address 4 */
491 if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA4H), at91_emac_read(lp, AT91_EMAC_SA4L)))
492 return;
493
494 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
495 }
496
497 /*
498 * Program the hardware MAC address from dev->dev_addr.
499 */
500 static void update_mac_address(struct net_device *dev)
501 {
502 struct at91_private *lp = netdev_priv(dev);
503
504 at91_emac_write(lp, AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
505 at91_emac_write(lp, AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
506
507 at91_emac_write(lp, AT91_EMAC_SA2L, 0);
508 at91_emac_write(lp, AT91_EMAC_SA2H, 0);
509 }
510
511 /*
512 * Store the new hardware address in dev->dev_addr, and update the MAC.
513 */
514 static int set_mac_address(struct net_device *dev, void* addr)
515 {
516 struct sockaddr *address = addr;
517
518 if (!is_valid_ether_addr(address->sa_data))
519 return -EADDRNOTAVAIL;
520
521 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
522 update_mac_address(dev);
523
524 printk("%s: Setting MAC address to %pM\n", dev->name,
525 dev->dev_addr);
526
527 return 0;
528 }
529
530 static int inline hash_bit_value(int bitnr, __u8 *addr)
531 {
532 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
533 return 1;
534 return 0;
535 }
536
537 /*
538 * The hash address register is 64 bits long and takes up two locations in the memory map.
539 * The least significant bits are stored in EMAC_HSL and the most significant
540 * bits in EMAC_HSH.
541 *
542 * The unicast hash enable and the multicast hash enable bits in the network configuration
543 * register enable the reception of hash matched frames. The destination address is
544 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
545 * The hash function is an exclusive or of every sixth bit of the destination address.
546 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
547 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
548 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
549 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
550 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
551 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
552 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
553 * unicast indicator, and da[47] represents the most significant bit of the last byte
554 * received.
555 * If the hash index points to a bit that is set in the hash register then the frame will be
556 * matched according to whether the frame is multicast or unicast.
557 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
558 * the hash index points to a bit set in the hash register.
559 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
560 * hash index points to a bit set in the hash register.
561 * To receive all multicast frames, the hash register should be set with all ones and the
562 * multicast hash enable bit should be set in the network configuration register.
563 */
564
565 /*
566 * Return the hash index value for the specified address.
567 */
568 static int hash_get_index(__u8 *addr)
569 {
570 int i, j, bitval;
571 int hash_index = 0;
572
573 for (j = 0; j < 6; j++) {
574 for (i = 0, bitval = 0; i < 8; i++)
575 bitval ^= hash_bit_value(i*6 + j, addr);
576
577 hash_index |= (bitval << j);
578 }
579
580 return hash_index;
581 }
582
583 /*
584 * Add multicast addresses to the internal multicast-hash table.
585 */
586 static void at91ether_sethashtable(struct net_device *dev)
587 {
588 struct at91_private *lp = netdev_priv(dev);
589 struct netdev_hw_addr *ha;
590 unsigned long mc_filter[2];
591 unsigned int bitnr;
592
593 mc_filter[0] = mc_filter[1] = 0;
594
595 netdev_for_each_mc_addr(ha, dev) {
596 bitnr = hash_get_index(ha->addr);
597 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
598 }
599
600 at91_emac_write(lp, AT91_EMAC_HSL, mc_filter[0]);
601 at91_emac_write(lp, AT91_EMAC_HSH, mc_filter[1]);
602 }
603
604 /*
605 * Enable/Disable promiscuous and multicast modes.
606 */
607 static void at91ether_set_multicast_list(struct net_device *dev)
608 {
609 struct at91_private *lp = netdev_priv(dev);
610 unsigned long cfg;
611
612 cfg = at91_emac_read(lp, AT91_EMAC_CFG);
613
614 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
615 cfg |= AT91_EMAC_CAF;
616 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
617 cfg &= ~AT91_EMAC_CAF;
618
619 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
620 at91_emac_write(lp, AT91_EMAC_HSH, -1);
621 at91_emac_write(lp, AT91_EMAC_HSL, -1);
622 cfg |= AT91_EMAC_MTI;
623 } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
624 at91ether_sethashtable(dev);
625 cfg |= AT91_EMAC_MTI;
626 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
627 at91_emac_write(lp, AT91_EMAC_HSH, 0);
628 at91_emac_write(lp, AT91_EMAC_HSL, 0);
629 cfg &= ~AT91_EMAC_MTI;
630 }
631
632 at91_emac_write(lp, AT91_EMAC_CFG, cfg);
633 }
634
635 /* ......................... ETHTOOL SUPPORT ........................... */
636
637 static int mdio_read(struct net_device *dev, int phy_id, int location)
638 {
639 struct at91_private *lp = netdev_priv(dev);
640 unsigned int value;
641
642 read_phy(lp, phy_id, location, &value);
643 return value;
644 }
645
646 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
647 {
648 struct at91_private *lp = netdev_priv(dev);
649
650 write_phy(lp, phy_id, location, value);
651 }
652
653 static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
654 {
655 struct at91_private *lp = netdev_priv(dev);
656 int ret;
657
658 spin_lock_irq(&lp->lock);
659 enable_mdi(lp);
660
661 ret = mii_ethtool_gset(&lp->mii, cmd);
662
663 disable_mdi(lp);
664 spin_unlock_irq(&lp->lock);
665
666 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
667 cmd->supported = SUPPORTED_FIBRE;
668 cmd->port = PORT_FIBRE;
669 }
670
671 return ret;
672 }
673
674 static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
675 {
676 struct at91_private *lp = netdev_priv(dev);
677 int ret;
678
679 spin_lock_irq(&lp->lock);
680 enable_mdi(lp);
681
682 ret = mii_ethtool_sset(&lp->mii, cmd);
683
684 disable_mdi(lp);
685 spin_unlock_irq(&lp->lock);
686
687 return ret;
688 }
689
690 static int at91ether_nwayreset(struct net_device *dev)
691 {
692 struct at91_private *lp = netdev_priv(dev);
693 int ret;
694
695 spin_lock_irq(&lp->lock);
696 enable_mdi(lp);
697
698 ret = mii_nway_restart(&lp->mii);
699
700 disable_mdi(lp);
701 spin_unlock_irq(&lp->lock);
702
703 return ret;
704 }
705
706 static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
707 {
708 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
709 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
710 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
711 }
712
713 static const struct ethtool_ops at91ether_ethtool_ops = {
714 .get_settings = at91ether_get_settings,
715 .set_settings = at91ether_set_settings,
716 .get_drvinfo = at91ether_get_drvinfo,
717 .nway_reset = at91ether_nwayreset,
718 .get_link = ethtool_op_get_link,
719 };
720
721 static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
722 {
723 struct at91_private *lp = netdev_priv(dev);
724 int res;
725
726 if (!netif_running(dev))
727 return -EINVAL;
728
729 spin_lock_irq(&lp->lock);
730 enable_mdi(lp);
731 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
732 disable_mdi(lp);
733 spin_unlock_irq(&lp->lock);
734
735 return res;
736 }
737
738 /* ................................ MAC ................................ */
739
740 /*
741 * Initialize and start the Receiver and Transmit subsystems
742 */
743 static void at91ether_start(struct net_device *dev)
744 {
745 struct at91_private *lp = netdev_priv(dev);
746 struct recv_desc_bufs *dlist, *dlist_phys;
747 int i;
748 unsigned long ctl;
749
750 dlist = lp->dlist;
751 dlist_phys = lp->dlist_phys;
752
753 for (i = 0; i < MAX_RX_DESCR; i++) {
754 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
755 dlist->descriptors[i].size = 0;
756 }
757
758 /* Set the Wrap bit on the last descriptor */
759 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
760
761 /* Reset buffer index */
762 lp->rxBuffIndex = 0;
763
764 /* Program address of descriptor list in Rx Buffer Queue register */
765 at91_emac_write(lp, AT91_EMAC_RBQP, (unsigned long) dlist_phys);
766
767 /* Enable Receive and Transmit */
768 ctl = at91_emac_read(lp, AT91_EMAC_CTL);
769 at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
770 }
771
772 /*
773 * Open the ethernet interface
774 */
775 static int at91ether_open(struct net_device *dev)
776 {
777 struct at91_private *lp = netdev_priv(dev);
778 unsigned long ctl;
779
780 if (!is_valid_ether_addr(dev->dev_addr))
781 return -EADDRNOTAVAIL;
782
783 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
784
785 /* Clear internal statistics */
786 ctl = at91_emac_read(lp, AT91_EMAC_CTL);
787 at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
788
789 /* Update the MAC address (incase user has changed it) */
790 update_mac_address(dev);
791
792 /* Enable PHY interrupt */
793 enable_phyirq(dev);
794
795 /* Enable MAC interrupts */
796 at91_emac_write(lp, AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
797 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
798 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
799
800 /* Determine current link speed */
801 spin_lock_irq(&lp->lock);
802 enable_mdi(lp);
803 update_linkspeed(dev, 0);
804 disable_mdi(lp);
805 spin_unlock_irq(&lp->lock);
806
807 at91ether_start(dev);
808 netif_start_queue(dev);
809 return 0;
810 }
811
812 /*
813 * Close the interface
814 */
815 static int at91ether_close(struct net_device *dev)
816 {
817 struct at91_private *lp = netdev_priv(dev);
818 unsigned long ctl;
819
820 /* Disable Receiver and Transmitter */
821 ctl = at91_emac_read(lp, AT91_EMAC_CTL);
822 at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
823
824 /* Disable PHY interrupt */
825 disable_phyirq(dev);
826
827 /* Disable MAC interrupts */
828 at91_emac_write(lp, AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
829 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
830 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
831
832 netif_stop_queue(dev);
833
834 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
835
836 return 0;
837 }
838
839 /*
840 * Transmit packet.
841 */
842 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
843 {
844 struct at91_private *lp = netdev_priv(dev);
845
846 if (at91_emac_read(lp, AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
847 netif_stop_queue(dev);
848
849 /* Store packet information (to free when Tx completed) */
850 lp->skb = skb;
851 lp->skb_length = skb->len;
852 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
853 dev->stats.tx_bytes += skb->len;
854
855 /* Set address of the data in the Transmit Address register */
856 at91_emac_write(lp, AT91_EMAC_TAR, lp->skb_physaddr);
857 /* Set length of the packet in the Transmit Control register */
858 at91_emac_write(lp, AT91_EMAC_TCR, skb->len);
859
860 } else {
861 printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
862 return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
863 on this skb, he also reports -ENETDOWN and printk's, so either
864 we free and return(0) or don't free and return 1 */
865 }
866
867 return NETDEV_TX_OK;
868 }
869
870 /*
871 * Update the current statistics from the internal statistics registers.
872 */
873 static struct net_device_stats *at91ether_stats(struct net_device *dev)
874 {
875 struct at91_private *lp = netdev_priv(dev);
876 int ale, lenerr, seqe, lcol, ecol;
877
878 if (netif_running(dev)) {
879 dev->stats.rx_packets += at91_emac_read(lp, AT91_EMAC_OK); /* Good frames received */
880 ale = at91_emac_read(lp, AT91_EMAC_ALE);
881 dev->stats.rx_frame_errors += ale; /* Alignment errors */
882 lenerr = at91_emac_read(lp, AT91_EMAC_ELR) + at91_emac_read(lp, AT91_EMAC_USF);
883 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
884 seqe = at91_emac_read(lp, AT91_EMAC_SEQE);
885 dev->stats.rx_crc_errors += seqe; /* CRC error */
886 dev->stats.rx_fifo_errors += at91_emac_read(lp, AT91_EMAC_DRFC);/* Receive buffer not available */
887 dev->stats.rx_errors += (ale + lenerr + seqe
888 + at91_emac_read(lp, AT91_EMAC_CDE) + at91_emac_read(lp, AT91_EMAC_RJB));
889
890 dev->stats.tx_packets += at91_emac_read(lp, AT91_EMAC_FRA); /* Frames successfully transmitted */
891 dev->stats.tx_fifo_errors += at91_emac_read(lp, AT91_EMAC_TUE); /* Transmit FIFO underruns */
892 dev->stats.tx_carrier_errors += at91_emac_read(lp, AT91_EMAC_CSE); /* Carrier Sense errors */
893 dev->stats.tx_heartbeat_errors += at91_emac_read(lp, AT91_EMAC_SQEE);/* Heartbeat error */
894
895 lcol = at91_emac_read(lp, AT91_EMAC_LCOL);
896 ecol = at91_emac_read(lp, AT91_EMAC_ECOL);
897 dev->stats.tx_window_errors += lcol; /* Late collisions */
898 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
899
900 dev->stats.collisions += (at91_emac_read(lp, AT91_EMAC_SCOL) + at91_emac_read(lp, AT91_EMAC_MCOL) + lcol + ecol);
901 }
902 return &dev->stats;
903 }
904
905 /*
906 * Extract received frame from buffer descriptors and sent to upper layers.
907 * (Called from interrupt context)
908 */
909 static void at91ether_rx(struct net_device *dev)
910 {
911 struct at91_private *lp = netdev_priv(dev);
912 struct recv_desc_bufs *dlist;
913 unsigned char *p_recv;
914 struct sk_buff *skb;
915 unsigned int pktlen;
916
917 dlist = lp->dlist;
918 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
919 p_recv = dlist->recv_buf[lp->rxBuffIndex];
920 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
921 skb = netdev_alloc_skb(dev, pktlen + 2);
922 if (skb != NULL) {
923 skb_reserve(skb, 2);
924 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
925
926 skb->protocol = eth_type_trans(skb, dev);
927 dev->stats.rx_bytes += pktlen;
928 netif_rx(skb);
929 }
930 else {
931 dev->stats.rx_dropped += 1;
932 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
933 }
934
935 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
936 dev->stats.multicast++;
937
938 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
939 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
940 lp->rxBuffIndex = 0;
941 else
942 lp->rxBuffIndex++;
943 }
944 }
945
946 /*
947 * MAC interrupt handler
948 */
949 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
950 {
951 struct net_device *dev = (struct net_device *) dev_id;
952 struct at91_private *lp = netdev_priv(dev);
953 unsigned long intstatus, ctl;
954
955 /* MAC Interrupt Status register indicates what interrupts are pending.
956 It is automatically cleared once read. */
957 intstatus = at91_emac_read(lp, AT91_EMAC_ISR);
958
959 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
960 at91ether_rx(dev);
961
962 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
963 /* The TCOM bit is set even if the transmission failed. */
964 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
965 dev->stats.tx_errors += 1;
966
967 if (lp->skb) {
968 dev_kfree_skb_irq(lp->skb);
969 lp->skb = NULL;
970 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
971 }
972 netif_wake_queue(dev);
973 }
974
975 /* Work-around for Errata #11 */
976 if (intstatus & AT91_EMAC_RBNA) {
977 ctl = at91_emac_read(lp, AT91_EMAC_CTL);
978 at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
979 at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
980 }
981
982 if (intstatus & AT91_EMAC_ROVR)
983 printk("%s: ROVR error\n", dev->name);
984
985 return IRQ_HANDLED;
986 }
987
988 #ifdef CONFIG_NET_POLL_CONTROLLER
989 static void at91ether_poll_controller(struct net_device *dev)
990 {
991 unsigned long flags;
992
993 local_irq_save(flags);
994 at91ether_interrupt(dev->irq, dev);
995 local_irq_restore(flags);
996 }
997 #endif
998
999 static const struct net_device_ops at91ether_netdev_ops = {
1000 .ndo_open = at91ether_open,
1001 .ndo_stop = at91ether_close,
1002 .ndo_start_xmit = at91ether_start_xmit,
1003 .ndo_get_stats = at91ether_stats,
1004 .ndo_set_rx_mode = at91ether_set_multicast_list,
1005 .ndo_set_mac_address = set_mac_address,
1006 .ndo_do_ioctl = at91ether_ioctl,
1007 .ndo_validate_addr = eth_validate_addr,
1008 .ndo_change_mtu = eth_change_mtu,
1009 #ifdef CONFIG_NET_POLL_CONTROLLER
1010 .ndo_poll_controller = at91ether_poll_controller,
1011 #endif
1012 };
1013
1014 /*
1015 * Detect the PHY type, and its address.
1016 */
1017 static int __init at91ether_phy_detect(struct at91_private *lp)
1018 {
1019 unsigned int phyid1, phyid2;
1020 unsigned long phy_id;
1021 unsigned short phy_address = 0;
1022
1023 while (phy_address < PHY_MAX_ADDR) {
1024 /* Read the PHY ID registers */
1025 enable_mdi(lp);
1026 read_phy(lp, phy_address, MII_PHYSID1, &phyid1);
1027 read_phy(lp, phy_address, MII_PHYSID2, &phyid2);
1028 disable_mdi(lp);
1029
1030 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1031 switch (phy_id) {
1032 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1033 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1034 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1035 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1036 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1037 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1038 case MII_DP83848_ID: /* National Semiconductor DP83848: */
1039 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1040 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1041 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1042 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
1043 /* store detected values */
1044 lp->phy_type = phy_id; /* Type of PHY connected */
1045 lp->phy_address = phy_address; /* MDI address of PHY */
1046 return 1;
1047 }
1048
1049 phy_address++;
1050 }
1051
1052 return 0; /* not detected */
1053 }
1054
1055
1056 /*
1057 * Detect MAC & PHY and perform ethernet interface initialization
1058 */
1059 static int __init at91ether_probe(struct platform_device *pdev)
1060 {
1061 struct macb_platform_data *board_data = pdev->dev.platform_data;
1062 struct resource *regs;
1063 struct net_device *dev;
1064 struct at91_private *lp;
1065 int res;
1066
1067 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068 if (!regs)
1069 return -ENOENT;
1070
1071 dev = alloc_etherdev(sizeof(struct at91_private));
1072 if (!dev)
1073 return -ENOMEM;
1074
1075 lp = netdev_priv(dev);
1076 lp->board_data = *board_data;
1077 spin_lock_init(&lp->lock);
1078
1079 dev->base_addr = regs->start; /* physical base address */
1080 lp->emac_base = ioremap(regs->start, regs->end - regs->start + 1);
1081 if (!lp->emac_base) {
1082 res = -ENOMEM;
1083 goto err_free_dev;
1084 }
1085
1086 /* Clock */
1087 lp->ether_clk = clk_get(&pdev->dev, "ether_clk");
1088 if (IS_ERR(lp->ether_clk)) {
1089 res = PTR_ERR(lp->ether_clk);
1090 goto err_ioumap;
1091 }
1092 clk_enable(lp->ether_clk);
1093
1094 /* Install the interrupt handler */
1095 dev->irq = platform_get_irq(pdev, 0);
1096 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
1097 res = -EBUSY;
1098 goto err_disable_clock;
1099 }
1100
1101 /* Allocate memory for DMA Receive descriptors */
1102 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
1103 if (lp->dlist == NULL) {
1104 res = -ENOMEM;
1105 goto err_free_irq;
1106 }
1107
1108 ether_setup(dev);
1109 dev->netdev_ops = &at91ether_netdev_ops;
1110 dev->ethtool_ops = &at91ether_ethtool_ops;
1111 platform_set_drvdata(pdev, dev);
1112 SET_NETDEV_DEV(dev, &pdev->dev);
1113
1114 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
1115 update_mac_address(dev); /* Program ethernet address into MAC */
1116
1117 at91_emac_write(lp, AT91_EMAC_CTL, 0);
1118
1119 if (board_data->is_rmii)
1120 at91_emac_write(lp, AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
1121 else
1122 at91_emac_write(lp, AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
1123
1124 /* Detect PHY */
1125 if (!at91ether_phy_detect(lp)) {
1126 printk(KERN_ERR "at91_ether: Could not detect ethernet PHY\n");
1127 res = -ENODEV;
1128 goto err_free_dmamem;
1129 }
1130
1131 initialize_phy(lp);
1132
1133 lp->mii.dev = dev; /* Support for ethtool */
1134 lp->mii.mdio_read = mdio_read;
1135 lp->mii.mdio_write = mdio_write;
1136 lp->mii.phy_id = lp->phy_address;
1137 lp->mii.phy_id_mask = 0x1f;
1138 lp->mii.reg_num_mask = 0x1f;
1139
1140 /* Register the network interface */
1141 res = register_netdev(dev);
1142 if (res)
1143 goto err_free_dmamem;
1144
1145 /* Determine current link speed */
1146 spin_lock_irq(&lp->lock);
1147 enable_mdi(lp);
1148 update_linkspeed(dev, 0);
1149 disable_mdi(lp);
1150 spin_unlock_irq(&lp->lock);
1151 netif_carrier_off(dev); /* will be enabled in open() */
1152
1153 /* If board has no PHY IRQ, use a timer to poll the PHY */
1154 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1155 gpio_request(board_data->phy_irq_pin, "ethernet_phy");
1156 } else {
1157 /* If board has no PHY IRQ, use a timer to poll the PHY */
1158 init_timer(&lp->check_timer);
1159 lp->check_timer.data = (unsigned long)dev;
1160 lp->check_timer.function = at91ether_check_link;
1161 }
1162
1163 /* Display ethernet banner */
1164 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
1165 dev->name, (uint) dev->base_addr, dev->irq,
1166 at91_emac_read(lp, AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1167 at91_emac_read(lp, AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
1168 dev->dev_addr);
1169 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
1170 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
1171 else if (lp->phy_type == MII_LXT971A_ID)
1172 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1173 else if (lp->phy_type == MII_RTL8201_ID)
1174 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1175 else if (lp->phy_type == MII_BCM5221_ID)
1176 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1177 else if (lp->phy_type == MII_DP83847_ID)
1178 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1179 else if (lp->phy_type == MII_DP83848_ID)
1180 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
1181 else if (lp->phy_type == MII_AC101L_ID)
1182 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1183 else if (lp->phy_type == MII_KS8721_ID)
1184 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1185 else if (lp->phy_type == MII_T78Q21x3_ID)
1186 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1187 else if (lp->phy_type == MII_LAN83C185_ID)
1188 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
1189
1190 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
1191
1192 return 0;
1193
1194
1195 err_free_dmamem:
1196 platform_set_drvdata(pdev, NULL);
1197 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1198 err_free_irq:
1199 free_irq(dev->irq, dev);
1200 err_disable_clock:
1201 clk_disable(lp->ether_clk);
1202 clk_put(lp->ether_clk);
1203 err_ioumap:
1204 iounmap(lp->emac_base);
1205 err_free_dev:
1206 free_netdev(dev);
1207 return res;
1208 }
1209
1210 static int __devexit at91ether_remove(struct platform_device *pdev)
1211 {
1212 struct net_device *dev = platform_get_drvdata(pdev);
1213 struct at91_private *lp = netdev_priv(dev);
1214
1215 if (gpio_is_valid(lp->board_data.phy_irq_pin))
1216 gpio_free(lp->board_data.phy_irq_pin);
1217
1218 unregister_netdev(dev);
1219 free_irq(dev->irq, dev);
1220 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1221 clk_put(lp->ether_clk);
1222
1223 platform_set_drvdata(pdev, NULL);
1224 free_netdev(dev);
1225 return 0;
1226 }
1227
1228 #ifdef CONFIG_PM
1229
1230 static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1231 {
1232 struct net_device *net_dev = platform_get_drvdata(pdev);
1233 struct at91_private *lp = netdev_priv(net_dev);
1234
1235 if (netif_running(net_dev)) {
1236 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1237 int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
1238 disable_irq(phy_irq);
1239 }
1240
1241 netif_stop_queue(net_dev);
1242 netif_device_detach(net_dev);
1243
1244 clk_disable(lp->ether_clk);
1245 }
1246 return 0;
1247 }
1248
1249 static int at91ether_resume(struct platform_device *pdev)
1250 {
1251 struct net_device *net_dev = platform_get_drvdata(pdev);
1252 struct at91_private *lp = netdev_priv(net_dev);
1253
1254 if (netif_running(net_dev)) {
1255 clk_enable(lp->ether_clk);
1256
1257 netif_device_attach(net_dev);
1258 netif_start_queue(net_dev);
1259
1260 if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
1261 int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
1262 enable_irq(phy_irq);
1263 }
1264 }
1265 return 0;
1266 }
1267
1268 #else
1269 #define at91ether_suspend NULL
1270 #define at91ether_resume NULL
1271 #endif
1272
1273 static struct platform_driver at91ether_driver = {
1274 .remove = __devexit_p(at91ether_remove),
1275 .suspend = at91ether_suspend,
1276 .resume = at91ether_resume,
1277 .driver = {
1278 .name = DRV_NAME,
1279 .owner = THIS_MODULE,
1280 },
1281 };
1282
1283 static int __init at91ether_init(void)
1284 {
1285 return platform_driver_probe(&at91ether_driver, at91ether_probe);
1286 }
1287
1288 static void __exit at91ether_exit(void)
1289 {
1290 platform_driver_unregister(&at91ether_driver);
1291 }
1292
1293 module_init(at91ether_init)
1294 module_exit(at91ether_exit)
1295
1296 MODULE_LICENSE("GPL");
1297 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1298 MODULE_AUTHOR("Andrew Victor");
1299 MODULE_ALIAS("platform:" DRV_NAME);
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