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arm: at91: move platfarm_data to include/linux/platform_data/atmel.h
[linux-2.6.git] / drivers / mmc / host / atmel-mci.c
blob8689989258263039e07eec53d9a86f3e837f40da
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/types.h>
31 #include <linux/platform_data/atmel.h>
32
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/sdio.h>
35
36 #include <mach/atmel-mci.h>
37 #include <linux/atmel-mci.h>
38 #include <linux/atmel_pdc.h>
39
40 #include <asm/io.h>
41 #include <asm/unaligned.h>
42
43 #include <mach/cpu.h>
44
45 #include "atmel-mci-regs.h"
46
47 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
48 #define ATMCI_DMA_THRESHOLD 16
49
50 enum {
51 EVENT_CMD_RDY = 0,
52 EVENT_XFER_COMPLETE,
53 EVENT_NOTBUSY,
54 EVENT_DATA_ERROR,
55 };
56
57 enum atmel_mci_state {
58 STATE_IDLE = 0,
59 STATE_SENDING_CMD,
60 STATE_DATA_XFER,
61 STATE_WAITING_NOTBUSY,
62 STATE_SENDING_STOP,
63 STATE_END_REQUEST,
64 };
65
66 enum atmci_xfer_dir {
67 XFER_RECEIVE = 0,
68 XFER_TRANSMIT,
69 };
70
71 enum atmci_pdc_buf {
72 PDC_FIRST_BUF = 0,
73 PDC_SECOND_BUF,
74 };
75
76 struct atmel_mci_caps {
77 bool has_dma_conf_reg;
78 bool has_pdc;
79 bool has_cfg_reg;
80 bool has_cstor_reg;
81 bool has_highspeed;
82 bool has_rwproof;
83 bool has_odd_clk_div;
84 bool has_bad_data_ordering;
85 bool need_reset_after_xfer;
86 bool need_blksz_mul_4;
87 bool need_notbusy_for_read_ops;
88 };
89
90 struct atmel_mci_dma {
91 struct dma_chan *chan;
92 struct dma_async_tx_descriptor *data_desc;
93 };
94
95 /**
96 * struct atmel_mci - MMC controller state shared between all slots
97 * @lock: Spinlock protecting the queue and associated data.
98 * @regs: Pointer to MMIO registers.
99 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
100 * @pio_offset: Offset into the current scatterlist entry.
101 * @buffer: Buffer used if we don't have the r/w proof capability. We
102 * don't have the time to switch pdc buffers so we have to use only
103 * one buffer for the full transaction.
104 * @buf_size: size of the buffer.
105 * @phys_buf_addr: buffer address needed for pdc.
106 * @cur_slot: The slot which is currently using the controller.
107 * @mrq: The request currently being processed on @cur_slot,
108 * or NULL if the controller is idle.
109 * @cmd: The command currently being sent to the card, or NULL.
110 * @data: The data currently being transferred, or NULL if no data
111 * transfer is in progress.
112 * @data_size: just data->blocks * data->blksz.
113 * @dma: DMA client state.
114 * @data_chan: DMA channel being used for the current data transfer.
115 * @cmd_status: Snapshot of SR taken upon completion of the current
116 * command. Only valid when EVENT_CMD_COMPLETE is pending.
117 * @data_status: Snapshot of SR taken upon completion of the current
118 * data transfer. Only valid when EVENT_DATA_COMPLETE or
119 * EVENT_DATA_ERROR is pending.
120 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
121 * to be sent.
122 * @tasklet: Tasklet running the request state machine.
123 * @pending_events: Bitmask of events flagged by the interrupt handler
124 * to be processed by the tasklet.
125 * @completed_events: Bitmask of events which the state machine has
126 * processed.
127 * @state: Tasklet state.
128 * @queue: List of slots waiting for access to the controller.
129 * @need_clock_update: Update the clock rate before the next request.
130 * @need_reset: Reset controller before next request.
131 * @timer: Timer to balance the data timeout error flag which cannot rise.
132 * @mode_reg: Value of the MR register.
133 * @cfg_reg: Value of the CFG register.
134 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
135 * rate and timeout calculations.
136 * @mapbase: Physical address of the MMIO registers.
137 * @mck: The peripheral bus clock hooked up to the MMC controller.
138 * @pdev: Platform device associated with the MMC controller.
139 * @slot: Slots sharing this MMC controller.
140 * @caps: MCI capabilities depending on MCI version.
141 * @prepare_data: function to setup MCI before data transfer which
142 * depends on MCI capabilities.
143 * @submit_data: function to start data transfer which depends on MCI
144 * capabilities.
145 * @stop_transfer: function to stop data transfer which depends on MCI
146 * capabilities.
147 *
148 * Locking
149 * =======
150 *
151 * @lock is a softirq-safe spinlock protecting @queue as well as
152 * @cur_slot, @mrq and @state. These must always be updated
153 * at the same time while holding @lock.
154 *
155 * @lock also protects mode_reg and need_clock_update since these are
156 * used to synchronize mode register updates with the queue
157 * processing.
158 *
159 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
160 * and must always be written at the same time as the slot is added to
161 * @queue.
162 *
163 * @pending_events and @completed_events are accessed using atomic bit
164 * operations, so they don't need any locking.
165 *
166 * None of the fields touched by the interrupt handler need any
167 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
168 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
169 * interrupts must be disabled and @data_status updated with a
170 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
171 * CMDRDY interrupt must be disabled and @cmd_status updated with a
172 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
173 * bytes_xfered field of @data must be written. This is ensured by
174 * using barriers.
175 */
176 struct atmel_mci {
177 spinlock_t lock;
178 void __iomem *regs;
179
180 struct scatterlist *sg;
181 unsigned int pio_offset;
182 unsigned int *buffer;
183 unsigned int buf_size;
184 dma_addr_t buf_phys_addr;
185
186 struct atmel_mci_slot *cur_slot;
187 struct mmc_request *mrq;
188 struct mmc_command *cmd;
189 struct mmc_data *data;
190 unsigned int data_size;
191
192 struct atmel_mci_dma dma;
193 struct dma_chan *data_chan;
194 struct dma_slave_config dma_conf;
195
196 u32 cmd_status;
197 u32 data_status;
198 u32 stop_cmdr;
199
200 struct tasklet_struct tasklet;
201 unsigned long pending_events;
202 unsigned long completed_events;
203 enum atmel_mci_state state;
204 struct list_head queue;
205
206 bool need_clock_update;
207 bool need_reset;
208 struct timer_list timer;
209 u32 mode_reg;
210 u32 cfg_reg;
211 unsigned long bus_hz;
212 unsigned long mapbase;
213 struct clk *mck;
214 struct platform_device *pdev;
215
216 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
217
218 struct atmel_mci_caps caps;
219
220 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
221 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
222 void (*stop_transfer)(struct atmel_mci *host);
223 };
224
225 /**
226 * struct atmel_mci_slot - MMC slot state
227 * @mmc: The mmc_host representing this slot.
228 * @host: The MMC controller this slot is using.
229 * @sdc_reg: Value of SDCR to be written before using this slot.
230 * @sdio_irq: SDIO irq mask for this slot.
231 * @mrq: mmc_request currently being processed or waiting to be
232 * processed, or NULL when the slot is idle.
233 * @queue_node: List node for placing this node in the @queue list of
234 * &struct atmel_mci.
235 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
236 * @flags: Random state bits associated with the slot.
237 * @detect_pin: GPIO pin used for card detection, or negative if not
238 * available.
239 * @wp_pin: GPIO pin used for card write protect sending, or negative
240 * if not available.
241 * @detect_is_active_high: The state of the detect pin when it is active.
242 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
243 */
244 struct atmel_mci_slot {
245 struct mmc_host *mmc;
246 struct atmel_mci *host;
247
248 u32 sdc_reg;
249 u32 sdio_irq;
250
251 struct mmc_request *mrq;
252 struct list_head queue_node;
253
254 unsigned int clock;
255 unsigned long flags;
256 #define ATMCI_CARD_PRESENT 0
257 #define ATMCI_CARD_NEED_INIT 1
258 #define ATMCI_SHUTDOWN 2
259 #define ATMCI_SUSPENDED 3
260
261 int detect_pin;
262 int wp_pin;
263 bool detect_is_active_high;
264
265 struct timer_list detect_timer;
266 };
267
268 #define atmci_test_and_clear_pending(host, event) \
269 test_and_clear_bit(event, &host->pending_events)
270 #define atmci_set_completed(host, event) \
271 set_bit(event, &host->completed_events)
272 #define atmci_set_pending(host, event) \
273 set_bit(event, &host->pending_events)
274
275 /*
276 * The debugfs stuff below is mostly optimized away when
277 * CONFIG_DEBUG_FS is not set.
278 */
279 static int atmci_req_show(struct seq_file *s, void *v)
280 {
281 struct atmel_mci_slot *slot = s->private;
282 struct mmc_request *mrq;
283 struct mmc_command *cmd;
284 struct mmc_command *stop;
285 struct mmc_data *data;
286
287 /* Make sure we get a consistent snapshot */
288 spin_lock_bh(&slot->host->lock);
289 mrq = slot->mrq;
290
291 if (mrq) {
292 cmd = mrq->cmd;
293 data = mrq->data;
294 stop = mrq->stop;
295
296 if (cmd)
297 seq_printf(s,
298 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
299 cmd->opcode, cmd->arg, cmd->flags,
300 cmd->resp[0], cmd->resp[1], cmd->resp[2],
301 cmd->resp[3], cmd->error);
302 if (data)
303 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
304 data->bytes_xfered, data->blocks,
305 data->blksz, data->flags, data->error);
306 if (stop)
307 seq_printf(s,
308 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
309 stop->opcode, stop->arg, stop->flags,
310 stop->resp[0], stop->resp[1], stop->resp[2],
311 stop->resp[3], stop->error);
312 }
313
314 spin_unlock_bh(&slot->host->lock);
315
316 return 0;
317 }
318
319 static int atmci_req_open(struct inode *inode, struct file *file)
320 {
321 return single_open(file, atmci_req_show, inode->i_private);
322 }
323
324 static const struct file_operations atmci_req_fops = {
325 .owner = THIS_MODULE,
326 .open = atmci_req_open,
327 .read = seq_read,
328 .llseek = seq_lseek,
329 .release = single_release,
330 };
331
332 static void atmci_show_status_reg(struct seq_file *s,
333 const char *regname, u32 value)
334 {
335 static const char *sr_bit[] = {
336 [0] = "CMDRDY",
337 [1] = "RXRDY",
338 [2] = "TXRDY",
339 [3] = "BLKE",
340 [4] = "DTIP",
341 [5] = "NOTBUSY",
342 [6] = "ENDRX",
343 [7] = "ENDTX",
344 [8] = "SDIOIRQA",
345 [9] = "SDIOIRQB",
346 [12] = "SDIOWAIT",
347 [14] = "RXBUFF",
348 [15] = "TXBUFE",
349 [16] = "RINDE",
350 [17] = "RDIRE",
351 [18] = "RCRCE",
352 [19] = "RENDE",
353 [20] = "RTOE",
354 [21] = "DCRCE",
355 [22] = "DTOE",
356 [23] = "CSTOE",
357 [24] = "BLKOVRE",
358 [25] = "DMADONE",
359 [26] = "FIFOEMPTY",
360 [27] = "XFRDONE",
361 [30] = "OVRE",
362 [31] = "UNRE",
363 };
364 unsigned int i;
365
366 seq_printf(s, "%s:\t0x%08x", regname, value);
367 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
368 if (value & (1 << i)) {
369 if (sr_bit[i])
370 seq_printf(s, " %s", sr_bit[i]);
371 else
372 seq_puts(s, " UNKNOWN");
373 }
374 }
375 seq_putc(s, '\n');
376 }
377
378 static int atmci_regs_show(struct seq_file *s, void *v)
379 {
380 struct atmel_mci *host = s->private;
381 u32 *buf;
382
383 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
384 if (!buf)
385 return -ENOMEM;
386
387 /*
388 * Grab a more or less consistent snapshot. Note that we're
389 * not disabling interrupts, so IMR and SR may not be
390 * consistent.
391 */
392 spin_lock_bh(&host->lock);
393 clk_enable(host->mck);
394 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
395 clk_disable(host->mck);
396 spin_unlock_bh(&host->lock);
397
398 seq_printf(s, "MR:\t0x%08x%s%s ",
399 buf[ATMCI_MR / 4],
400 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
401 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
402 if (host->caps.has_odd_clk_div)
403 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
404 ((buf[ATMCI_MR / 4] & 0xff) << 1)
405 | ((buf[ATMCI_MR / 4] >> 16) & 1));
406 else
407 seq_printf(s, "CLKDIV=%u\n",
408 (buf[ATMCI_MR / 4] & 0xff));
409 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
410 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
411 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
412 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
413 buf[ATMCI_BLKR / 4],
414 buf[ATMCI_BLKR / 4] & 0xffff,
415 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
416 if (host->caps.has_cstor_reg)
417 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
418
419 /* Don't read RSPR and RDR; it will consume the data there */
420
421 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
422 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
423
424 if (host->caps.has_dma_conf_reg) {
425 u32 val;
426
427 val = buf[ATMCI_DMA / 4];
428 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
429 val, val & 3,
430 ((val >> 4) & 3) ?
431 1 << (((val >> 4) & 3) + 1) : 1,
432 val & ATMCI_DMAEN ? " DMAEN" : "");
433 }
434 if (host->caps.has_cfg_reg) {
435 u32 val;
436
437 val = buf[ATMCI_CFG / 4];
438 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
439 val,
440 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
441 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
442 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
443 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
444 }
445
446 kfree(buf);
447
448 return 0;
449 }
450
451 static int atmci_regs_open(struct inode *inode, struct file *file)
452 {
453 return single_open(file, atmci_regs_show, inode->i_private);
454 }
455
456 static const struct file_operations atmci_regs_fops = {
457 .owner = THIS_MODULE,
458 .open = atmci_regs_open,
459 .read = seq_read,
460 .llseek = seq_lseek,
461 .release = single_release,
462 };
463
464 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
465 {
466 struct mmc_host *mmc = slot->mmc;
467 struct atmel_mci *host = slot->host;
468 struct dentry *root;
469 struct dentry *node;
470
471 root = mmc->debugfs_root;
472 if (!root)
473 return;
474
475 node = debugfs_create_file("regs", S_IRUSR, root, host,
476 &atmci_regs_fops);
477 if (IS_ERR(node))
478 return;
479 if (!node)
480 goto err;
481
482 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
483 if (!node)
484 goto err;
485
486 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
487 if (!node)
488 goto err;
489
490 node = debugfs_create_x32("pending_events", S_IRUSR, root,
491 (u32 *)&host->pending_events);
492 if (!node)
493 goto err;
494
495 node = debugfs_create_x32("completed_events", S_IRUSR, root,
496 (u32 *)&host->completed_events);
497 if (!node)
498 goto err;
499
500 return;
501
502 err:
503 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
504 }
505
506 #if defined(CONFIG_OF)
507 static const struct of_device_id atmci_dt_ids[] = {
508 { .compatible = "atmel,hsmci" },
509 { /* sentinel */ }
510 };
511
512 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
513
514 static struct mci_platform_data __devinit*
515 atmci_of_init(struct platform_device *pdev)
516 {
517 struct device_node *np = pdev->dev.of_node;
518 struct device_node *cnp;
519 struct mci_platform_data *pdata;
520 u32 slot_id;
521
522 if (!np) {
523 dev_err(&pdev->dev, "device node not found\n");
524 return ERR_PTR(-EINVAL);
525 }
526
527 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
528 if (!pdata) {
529 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
530 return ERR_PTR(-ENOMEM);
531 }
532
533 for_each_child_of_node(np, cnp) {
534 if (of_property_read_u32(cnp, "reg", &slot_id)) {
535 dev_warn(&pdev->dev, "reg property is missing for %s\n",
536 cnp->full_name);
537 continue;
538 }
539
540 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
541 dev_warn(&pdev->dev, "can't have more than %d slots\n",
542 ATMCI_MAX_NR_SLOTS);
543 break;
544 }
545
546 if (of_property_read_u32(cnp, "bus-width",
547 &pdata->slot[slot_id].bus_width))
548 pdata->slot[slot_id].bus_width = 1;
549
550 pdata->slot[slot_id].detect_pin =
551 of_get_named_gpio(cnp, "cd-gpios", 0);
552
553 pdata->slot[slot_id].detect_is_active_high =
554 of_property_read_bool(cnp, "cd-inverted");
555
556 pdata->slot[slot_id].wp_pin =
557 of_get_named_gpio(cnp, "wp-gpios", 0);
558 }
559
560 return pdata;
561 }
562 #else /* CONFIG_OF */
563 static inline struct mci_platform_data*
564 atmci_of_init(struct platform_device *dev)
565 {
566 return ERR_PTR(-EINVAL);
567 }
568 #endif
569
570 static inline unsigned int atmci_get_version(struct atmel_mci *host)
571 {
572 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
573 }
574
575 static void atmci_timeout_timer(unsigned long data)
576 {
577 struct atmel_mci *host;
578
579 host = (struct atmel_mci *)data;
580
581 dev_dbg(&host->pdev->dev, "software timeout\n");
582
583 if (host->mrq->cmd->data) {
584 host->mrq->cmd->data->error = -ETIMEDOUT;
585 host->data = NULL;
586 } else {
587 host->mrq->cmd->error = -ETIMEDOUT;
588 host->cmd = NULL;
589 }
590 host->need_reset = 1;
591 host->state = STATE_END_REQUEST;
592 smp_wmb();
593 tasklet_schedule(&host->tasklet);
594 }
595
596 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
597 unsigned int ns)
598 {
599 /*
600 * It is easier here to use us instead of ns for the timeout,
601 * it prevents from overflows during calculation.
602 */
603 unsigned int us = DIV_ROUND_UP(ns, 1000);
604
605 /* Maximum clock frequency is host->bus_hz/2 */
606 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
607 }
608
609 static void atmci_set_timeout(struct atmel_mci *host,
610 struct atmel_mci_slot *slot, struct mmc_data *data)
611 {
612 static unsigned dtomul_to_shift[] = {
613 0, 4, 7, 8, 10, 12, 16, 20
614 };
615 unsigned timeout;
616 unsigned dtocyc;
617 unsigned dtomul;
618
619 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
620 + data->timeout_clks;
621
622 for (dtomul = 0; dtomul < 8; dtomul++) {
623 unsigned shift = dtomul_to_shift[dtomul];
624 dtocyc = (timeout + (1 << shift) - 1) >> shift;
625 if (dtocyc < 15)
626 break;
627 }
628
629 if (dtomul >= 8) {
630 dtomul = 7;
631 dtocyc = 15;
632 }
633
634 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
635 dtocyc << dtomul_to_shift[dtomul]);
636 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
637 }
638
639 /*
640 * Return mask with command flags to be enabled for this command.
641 */
642 static u32 atmci_prepare_command(struct mmc_host *mmc,
643 struct mmc_command *cmd)
644 {
645 struct mmc_data *data;
646 u32 cmdr;
647
648 cmd->error = -EINPROGRESS;
649
650 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
651
652 if (cmd->flags & MMC_RSP_PRESENT) {
653 if (cmd->flags & MMC_RSP_136)
654 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
655 else
656 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
657 }
658
659 /*
660 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
661 * it's too difficult to determine whether this is an ACMD or
662 * not. Better make it 64.
663 */
664 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
665
666 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
667 cmdr |= ATMCI_CMDR_OPDCMD;
668
669 data = cmd->data;
670 if (data) {
671 cmdr |= ATMCI_CMDR_START_XFER;
672
673 if (cmd->opcode == SD_IO_RW_EXTENDED) {
674 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
675 } else {
676 if (data->flags & MMC_DATA_STREAM)
677 cmdr |= ATMCI_CMDR_STREAM;
678 else if (data->blocks > 1)
679 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
680 else
681 cmdr |= ATMCI_CMDR_BLOCK;
682 }
683
684 if (data->flags & MMC_DATA_READ)
685 cmdr |= ATMCI_CMDR_TRDIR_READ;
686 }
687
688 return cmdr;
689 }
690
691 static void atmci_send_command(struct atmel_mci *host,
692 struct mmc_command *cmd, u32 cmd_flags)
693 {
694 WARN_ON(host->cmd);
695 host->cmd = cmd;
696
697 dev_vdbg(&host->pdev->dev,
698 "start command: ARGR=0x%08x CMDR=0x%08x\n",
699 cmd->arg, cmd_flags);
700
701 atmci_writel(host, ATMCI_ARGR, cmd->arg);
702 atmci_writel(host, ATMCI_CMDR, cmd_flags);
703 }
704
705 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
706 {
707 dev_dbg(&host->pdev->dev, "send stop command\n");
708 atmci_send_command(host, data->stop, host->stop_cmdr);
709 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
710 }
711
712 /*
713 * Configure given PDC buffer taking care of alignement issues.
714 * Update host->data_size and host->sg.
715 */
716 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
717 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
718 {
719 u32 pointer_reg, counter_reg;
720 unsigned int buf_size;
721
722 if (dir == XFER_RECEIVE) {
723 pointer_reg = ATMEL_PDC_RPR;
724 counter_reg = ATMEL_PDC_RCR;
725 } else {
726 pointer_reg = ATMEL_PDC_TPR;
727 counter_reg = ATMEL_PDC_TCR;
728 }
729
730 if (buf_nb == PDC_SECOND_BUF) {
731 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
732 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
733 }
734
735 if (!host->caps.has_rwproof) {
736 buf_size = host->buf_size;
737 atmci_writel(host, pointer_reg, host->buf_phys_addr);
738 } else {
739 buf_size = sg_dma_len(host->sg);
740 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
741 }
742
743 if (host->data_size <= buf_size) {
744 if (host->data_size & 0x3) {
745 /* If size is different from modulo 4, transfer bytes */
746 atmci_writel(host, counter_reg, host->data_size);
747 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
748 } else {
749 /* Else transfer 32-bits words */
750 atmci_writel(host, counter_reg, host->data_size / 4);
751 }
752 host->data_size = 0;
753 } else {
754 /* We assume the size of a page is 32-bits aligned */
755 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
756 host->data_size -= sg_dma_len(host->sg);
757 if (host->data_size)
758 host->sg = sg_next(host->sg);
759 }
760 }
761
762 /*
763 * Configure PDC buffer according to the data size ie configuring one or two
764 * buffers. Don't use this function if you want to configure only the second
765 * buffer. In this case, use atmci_pdc_set_single_buf.
766 */
767 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
768 {
769 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
770 if (host->data_size)
771 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
772 }
773
774 /*
775 * Unmap sg lists, called when transfer is finished.
776 */
777 static void atmci_pdc_cleanup(struct atmel_mci *host)
778 {
779 struct mmc_data *data = host->data;
780
781 if (data)
782 dma_unmap_sg(&host->pdev->dev,
783 data->sg, data->sg_len,
784 ((data->flags & MMC_DATA_WRITE)
785 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
786 }
787
788 /*
789 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
790 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
791 * interrupt needed for both transfer directions.
792 */
793 static void atmci_pdc_complete(struct atmel_mci *host)
794 {
795 int transfer_size = host->data->blocks * host->data->blksz;
796 int i;
797
798 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
799
800 if ((!host->caps.has_rwproof)
801 && (host->data->flags & MMC_DATA_READ)) {
802 if (host->caps.has_bad_data_ordering)
803 for (i = 0; i < transfer_size; i++)
804 host->buffer[i] = swab32(host->buffer[i]);
805 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
806 host->buffer, transfer_size);
807 }
808
809 atmci_pdc_cleanup(host);
810
811 /*
812 * If the card was removed, data will be NULL. No point trying
813 * to send the stop command or waiting for NBUSY in this case.
814 */
815 if (host->data) {
816 dev_dbg(&host->pdev->dev,
817 "(%s) set pending xfer complete\n", __func__);
818 atmci_set_pending(host, EVENT_XFER_COMPLETE);
819 tasklet_schedule(&host->tasklet);
820 }
821 }
822
823 static void atmci_dma_cleanup(struct atmel_mci *host)
824 {
825 struct mmc_data *data = host->data;
826
827 if (data)
828 dma_unmap_sg(host->dma.chan->device->dev,
829 data->sg, data->sg_len,
830 ((data->flags & MMC_DATA_WRITE)
831 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
832 }
833
834 /*
835 * This function is called by the DMA driver from tasklet context.
836 */
837 static void atmci_dma_complete(void *arg)
838 {
839 struct atmel_mci *host = arg;
840 struct mmc_data *data = host->data;
841
842 dev_vdbg(&host->pdev->dev, "DMA complete\n");
843
844 if (host->caps.has_dma_conf_reg)
845 /* Disable DMA hardware handshaking on MCI */
846 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
847
848 atmci_dma_cleanup(host);
849
850 /*
851 * If the card was removed, data will be NULL. No point trying
852 * to send the stop command or waiting for NBUSY in this case.
853 */
854 if (data) {
855 dev_dbg(&host->pdev->dev,
856 "(%s) set pending xfer complete\n", __func__);
857 atmci_set_pending(host, EVENT_XFER_COMPLETE);
858 tasklet_schedule(&host->tasklet);
859
860 /*
861 * Regardless of what the documentation says, we have
862 * to wait for NOTBUSY even after block read
863 * operations.
864 *
865 * When the DMA transfer is complete, the controller
866 * may still be reading the CRC from the card, i.e.
867 * the data transfer is still in progress and we
868 * haven't seen all the potential error bits yet.
869 *
870 * The interrupt handler will schedule a different
871 * tasklet to finish things up when the data transfer
872 * is completely done.
873 *
874 * We may not complete the mmc request here anyway
875 * because the mmc layer may call back and cause us to
876 * violate the "don't submit new operations from the
877 * completion callback" rule of the dma engine
878 * framework.
879 */
880 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
881 }
882 }
883
884 /*
885 * Returns a mask of interrupt flags to be enabled after the whole
886 * request has been prepared.
887 */
888 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
889 {
890 u32 iflags;
891
892 data->error = -EINPROGRESS;
893
894 host->sg = data->sg;
895 host->data = data;
896 host->data_chan = NULL;
897
898 iflags = ATMCI_DATA_ERROR_FLAGS;
899
900 /*
901 * Errata: MMC data write operation with less than 12
902 * bytes is impossible.
903 *
904 * Errata: MCI Transmit Data Register (TDR) FIFO
905 * corruption when length is not multiple of 4.
906 */
907 if (data->blocks * data->blksz < 12
908 || (data->blocks * data->blksz) & 3)
909 host->need_reset = true;
910
911 host->pio_offset = 0;
912 if (data->flags & MMC_DATA_READ)
913 iflags |= ATMCI_RXRDY;
914 else
915 iflags |= ATMCI_TXRDY;
916
917 return iflags;
918 }
919
920 /*
921 * Set interrupt flags and set block length into the MCI mode register even
922 * if this value is also accessible in the MCI block register. It seems to be
923 * necessary before the High Speed MCI version. It also map sg and configure
924 * PDC registers.
925 */
926 static u32
927 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
928 {
929 u32 iflags, tmp;
930 unsigned int sg_len;
931 enum dma_data_direction dir;
932 int i;
933
934 data->error = -EINPROGRESS;
935
936 host->data = data;
937 host->sg = data->sg;
938 iflags = ATMCI_DATA_ERROR_FLAGS;
939
940 /* Enable pdc mode */
941 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
942
943 if (data->flags & MMC_DATA_READ) {
944 dir = DMA_FROM_DEVICE;
945 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
946 } else {
947 dir = DMA_TO_DEVICE;
948 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
949 }
950
951 /* Set BLKLEN */
952 tmp = atmci_readl(host, ATMCI_MR);
953 tmp &= 0x0000ffff;
954 tmp |= ATMCI_BLKLEN(data->blksz);
955 atmci_writel(host, ATMCI_MR, tmp);
956
957 /* Configure PDC */
958 host->data_size = data->blocks * data->blksz;
959 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
960
961 if ((!host->caps.has_rwproof)
962 && (host->data->flags & MMC_DATA_WRITE)) {
963 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
964 host->buffer, host->data_size);
965 if (host->caps.has_bad_data_ordering)
966 for (i = 0; i < host->data_size; i++)
967 host->buffer[i] = swab32(host->buffer[i]);
968 }
969
970 if (host->data_size)
971 atmci_pdc_set_both_buf(host,
972 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
973
974 return iflags;
975 }
976
977 static u32
978 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
979 {
980 struct dma_chan *chan;
981 struct dma_async_tx_descriptor *desc;
982 struct scatterlist *sg;
983 unsigned int i;
984 enum dma_data_direction direction;
985 enum dma_transfer_direction slave_dirn;
986 unsigned int sglen;
987 u32 maxburst;
988 u32 iflags;
989
990 data->error = -EINPROGRESS;
991
992 WARN_ON(host->data);
993 host->sg = NULL;
994 host->data = data;
995
996 iflags = ATMCI_DATA_ERROR_FLAGS;
997
998 /*
999 * We don't do DMA on "complex" transfers, i.e. with
1000 * non-word-aligned buffers or lengths. Also, we don't bother
1001 * with all the DMA setup overhead for short transfers.
1002 */
1003 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1004 return atmci_prepare_data(host, data);
1005 if (data->blksz & 3)
1006 return atmci_prepare_data(host, data);
1007
1008 for_each_sg(data->sg, sg, data->sg_len, i) {
1009 if (sg->offset & 3 || sg->length & 3)
1010 return atmci_prepare_data(host, data);
1011 }
1012
1013 /* If we don't have a channel, we can't do DMA */
1014 chan = host->dma.chan;
1015 if (chan)
1016 host->data_chan = chan;
1017
1018 if (!chan)
1019 return -ENODEV;
1020
1021 if (data->flags & MMC_DATA_READ) {
1022 direction = DMA_FROM_DEVICE;
1023 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1024 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
1025 } else {
1026 direction = DMA_TO_DEVICE;
1027 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1028 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
1029 }
1030
1031 if (host->caps.has_dma_conf_reg)
1032 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1033 ATMCI_DMAEN);
1034
1035 sglen = dma_map_sg(chan->device->dev, data->sg,
1036 data->sg_len, direction);
1037
1038 dmaengine_slave_config(chan, &host->dma_conf);
1039 desc = dmaengine_prep_slave_sg(chan,
1040 data->sg, sglen, slave_dirn,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!desc)
1043 goto unmap_exit;
1044
1045 host->dma.data_desc = desc;
1046 desc->callback = atmci_dma_complete;
1047 desc->callback_param = host;
1048
1049 return iflags;
1050 unmap_exit:
1051 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1052 return -ENOMEM;
1053 }
1054
1055 static void
1056 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1057 {
1058 return;
1059 }
1060
1061 /*
1062 * Start PDC according to transfer direction.
1063 */
1064 static void
1065 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1066 {
1067 if (data->flags & MMC_DATA_READ)
1068 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1069 else
1070 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1071 }
1072
1073 static void
1074 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1075 {
1076 struct dma_chan *chan = host->data_chan;
1077 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1078
1079 if (chan) {
1080 dmaengine_submit(desc);
1081 dma_async_issue_pending(chan);
1082 }
1083 }
1084
1085 static void atmci_stop_transfer(struct atmel_mci *host)
1086 {
1087 dev_dbg(&host->pdev->dev,
1088 "(%s) set pending xfer complete\n", __func__);
1089 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1090 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1091 }
1092
1093 /*
1094 * Stop data transfer because error(s) occurred.
1095 */
1096 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1097 {
1098 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1099 }
1100
1101 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1102 {
1103 struct dma_chan *chan = host->data_chan;
1104
1105 if (chan) {
1106 dmaengine_terminate_all(chan);
1107 atmci_dma_cleanup(host);
1108 } else {
1109 /* Data transfer was stopped by the interrupt handler */
1110 dev_dbg(&host->pdev->dev,
1111 "(%s) set pending xfer complete\n", __func__);
1112 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1113 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1114 }
1115 }
1116
1117 /*
1118 * Start a request: prepare data if needed, prepare the command and activate
1119 * interrupts.
1120 */
1121 static void atmci_start_request(struct atmel_mci *host,
1122 struct atmel_mci_slot *slot)
1123 {
1124 struct mmc_request *mrq;
1125 struct mmc_command *cmd;
1126 struct mmc_data *data;
1127 u32 iflags;
1128 u32 cmdflags;
1129
1130 mrq = slot->mrq;
1131 host->cur_slot = slot;
1132 host->mrq = mrq;
1133
1134 host->pending_events = 0;
1135 host->completed_events = 0;
1136 host->cmd_status = 0;
1137 host->data_status = 0;
1138
1139 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1140
1141 if (host->need_reset || host->caps.need_reset_after_xfer) {
1142 iflags = atmci_readl(host, ATMCI_IMR);
1143 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1144 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1145 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1146 atmci_writel(host, ATMCI_MR, host->mode_reg);
1147 if (host->caps.has_cfg_reg)
1148 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1149 atmci_writel(host, ATMCI_IER, iflags);
1150 host->need_reset = false;
1151 }
1152 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1153
1154 iflags = atmci_readl(host, ATMCI_IMR);
1155 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1156 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1157 iflags);
1158
1159 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1160 /* Send init sequence (74 clock cycles) */
1161 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1162 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1163 cpu_relax();
1164 }
1165 iflags = 0;
1166 data = mrq->data;
1167 if (data) {
1168 atmci_set_timeout(host, slot, data);
1169
1170 /* Must set block count/size before sending command */
1171 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1172 | ATMCI_BLKLEN(data->blksz));
1173 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1174 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1175
1176 iflags |= host->prepare_data(host, data);
1177 }
1178
1179 iflags |= ATMCI_CMDRDY;
1180 cmd = mrq->cmd;
1181 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1182 atmci_send_command(host, cmd, cmdflags);
1183
1184 if (data)
1185 host->submit_data(host, data);
1186
1187 if (mrq->stop) {
1188 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1189 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1190 if (!(data->flags & MMC_DATA_WRITE))
1191 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1192 if (data->flags & MMC_DATA_STREAM)
1193 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1194 else
1195 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1196 }
1197
1198 /*
1199 * We could have enabled interrupts earlier, but I suspect
1200 * that would open up a nice can of interesting race
1201 * conditions (e.g. command and data complete, but stop not
1202 * prepared yet.)
1203 */
1204 atmci_writel(host, ATMCI_IER, iflags);
1205
1206 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1207 }
1208
1209 static void atmci_queue_request(struct atmel_mci *host,
1210 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1211 {
1212 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1213 host->state);
1214
1215 spin_lock_bh(&host->lock);
1216 slot->mrq = mrq;
1217 if (host->state == STATE_IDLE) {
1218 host->state = STATE_SENDING_CMD;
1219 atmci_start_request(host, slot);
1220 } else {
1221 dev_dbg(&host->pdev->dev, "queue request\n");
1222 list_add_tail(&slot->queue_node, &host->queue);
1223 }
1224 spin_unlock_bh(&host->lock);
1225 }
1226
1227 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1228 {
1229 struct atmel_mci_slot *slot = mmc_priv(mmc);
1230 struct atmel_mci *host = slot->host;
1231 struct mmc_data *data;
1232
1233 WARN_ON(slot->mrq);
1234 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1235
1236 /*
1237 * We may "know" the card is gone even though there's still an
1238 * electrical connection. If so, we really need to communicate
1239 * this to the MMC core since there won't be any more
1240 * interrupts as the card is completely removed. Otherwise,
1241 * the MMC core might believe the card is still there even
1242 * though the card was just removed very slowly.
1243 */
1244 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1245 mrq->cmd->error = -ENOMEDIUM;
1246 mmc_request_done(mmc, mrq);
1247 return;
1248 }
1249
1250 /* We don't support multiple blocks of weird lengths. */
1251 data = mrq->data;
1252 if (data && data->blocks > 1 && data->blksz & 3) {
1253 mrq->cmd->error = -EINVAL;
1254 mmc_request_done(mmc, mrq);
1255 }
1256
1257 atmci_queue_request(host, slot, mrq);
1258 }
1259
1260 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1261 {
1262 struct atmel_mci_slot *slot = mmc_priv(mmc);
1263 struct atmel_mci *host = slot->host;
1264 unsigned int i;
1265
1266 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1267 switch (ios->bus_width) {
1268 case MMC_BUS_WIDTH_1:
1269 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1270 break;
1271 case MMC_BUS_WIDTH_4:
1272 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1273 break;
1274 }
1275
1276 if (ios->clock) {
1277 unsigned int clock_min = ~0U;
1278 u32 clkdiv;
1279
1280 spin_lock_bh(&host->lock);
1281 if (!host->mode_reg) {
1282 clk_enable(host->mck);
1283 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1284 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1285 if (host->caps.has_cfg_reg)
1286 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1287 }
1288
1289 /*
1290 * Use mirror of ios->clock to prevent race with mmc
1291 * core ios update when finding the minimum.
1292 */
1293 slot->clock = ios->clock;
1294 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1295 if (host->slot[i] && host->slot[i]->clock
1296 && host->slot[i]->clock < clock_min)
1297 clock_min = host->slot[i]->clock;
1298 }
1299
1300 /* Calculate clock divider */
1301 if (host->caps.has_odd_clk_div) {
1302 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1303 if (clkdiv > 511) {
1304 dev_warn(&mmc->class_dev,
1305 "clock %u too slow; using %lu\n",
1306 clock_min, host->bus_hz / (511 + 2));
1307 clkdiv = 511;
1308 }
1309 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1310 | ATMCI_MR_CLKODD(clkdiv & 1);
1311 } else {
1312 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1313 if (clkdiv > 255) {
1314 dev_warn(&mmc->class_dev,
1315 "clock %u too slow; using %lu\n",
1316 clock_min, host->bus_hz / (2 * 256));
1317 clkdiv = 255;
1318 }
1319 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1320 }
1321
1322 /*
1323 * WRPROOF and RDPROOF prevent overruns/underruns by
1324 * stopping the clock when the FIFO is full/empty.
1325 * This state is not expected to last for long.
1326 */
1327 if (host->caps.has_rwproof)
1328 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1329
1330 if (host->caps.has_cfg_reg) {
1331 /* setup High Speed mode in relation with card capacity */
1332 if (ios->timing == MMC_TIMING_SD_HS)
1333 host->cfg_reg |= ATMCI_CFG_HSMODE;
1334 else
1335 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1336 }
1337
1338 if (list_empty(&host->queue)) {
1339 atmci_writel(host, ATMCI_MR, host->mode_reg);
1340 if (host->caps.has_cfg_reg)
1341 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1342 } else {
1343 host->need_clock_update = true;
1344 }
1345
1346 spin_unlock_bh(&host->lock);
1347 } else {
1348 bool any_slot_active = false;
1349
1350 spin_lock_bh(&host->lock);
1351 slot->clock = 0;
1352 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1353 if (host->slot[i] && host->slot[i]->clock) {
1354 any_slot_active = true;
1355 break;
1356 }
1357 }
1358 if (!any_slot_active) {
1359 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1360 if (host->mode_reg) {
1361 atmci_readl(host, ATMCI_MR);
1362 clk_disable(host->mck);
1363 }
1364 host->mode_reg = 0;
1365 }
1366 spin_unlock_bh(&host->lock);
1367 }
1368
1369 switch (ios->power_mode) {
1370 case MMC_POWER_UP:
1371 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1372 break;
1373 default:
1374 /*
1375 * TODO: None of the currently available AVR32-based
1376 * boards allow MMC power to be turned off. Implement
1377 * power control when this can be tested properly.
1378 *
1379 * We also need to hook this into the clock management
1380 * somehow so that newly inserted cards aren't
1381 * subjected to a fast clock before we have a chance
1382 * to figure out what the maximum rate is. Currently,
1383 * there's no way to avoid this, and there never will
1384 * be for boards that don't support power control.
1385 */
1386 break;
1387 }
1388 }
1389
1390 static int atmci_get_ro(struct mmc_host *mmc)
1391 {
1392 int read_only = -ENOSYS;
1393 struct atmel_mci_slot *slot = mmc_priv(mmc);
1394
1395 if (gpio_is_valid(slot->wp_pin)) {
1396 read_only = gpio_get_value(slot->wp_pin);
1397 dev_dbg(&mmc->class_dev, "card is %s\n",
1398 read_only ? "read-only" : "read-write");
1399 }
1400
1401 return read_only;
1402 }
1403
1404 static int atmci_get_cd(struct mmc_host *mmc)
1405 {
1406 int present = -ENOSYS;
1407 struct atmel_mci_slot *slot = mmc_priv(mmc);
1408
1409 if (gpio_is_valid(slot->detect_pin)) {
1410 present = !(gpio_get_value(slot->detect_pin) ^
1411 slot->detect_is_active_high);
1412 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1413 present ? "" : "not ");
1414 }
1415
1416 return present;
1417 }
1418
1419 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1420 {
1421 struct atmel_mci_slot *slot = mmc_priv(mmc);
1422 struct atmel_mci *host = slot->host;
1423
1424 if (enable)
1425 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1426 else
1427 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1428 }
1429
1430 static const struct mmc_host_ops atmci_ops = {
1431 .request = atmci_request,
1432 .set_ios = atmci_set_ios,
1433 .get_ro = atmci_get_ro,
1434 .get_cd = atmci_get_cd,
1435 .enable_sdio_irq = atmci_enable_sdio_irq,
1436 };
1437
1438 /* Called with host->lock held */
1439 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1440 __releases(&host->lock)
1441 __acquires(&host->lock)
1442 {
1443 struct atmel_mci_slot *slot = NULL;
1444 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1445
1446 WARN_ON(host->cmd || host->data);
1447
1448 /*
1449 * Update the MMC clock rate if necessary. This may be
1450 * necessary if set_ios() is called when a different slot is
1451 * busy transferring data.
1452 */
1453 if (host->need_clock_update) {
1454 atmci_writel(host, ATMCI_MR, host->mode_reg);
1455 if (host->caps.has_cfg_reg)
1456 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1457 }
1458
1459 host->cur_slot->mrq = NULL;
1460 host->mrq = NULL;
1461 if (!list_empty(&host->queue)) {
1462 slot = list_entry(host->queue.next,
1463 struct atmel_mci_slot, queue_node);
1464 list_del(&slot->queue_node);
1465 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1466 mmc_hostname(slot->mmc));
1467 host->state = STATE_SENDING_CMD;
1468 atmci_start_request(host, slot);
1469 } else {
1470 dev_vdbg(&host->pdev->dev, "list empty\n");
1471 host->state = STATE_IDLE;
1472 }
1473
1474 del_timer(&host->timer);
1475
1476 spin_unlock(&host->lock);
1477 mmc_request_done(prev_mmc, mrq);
1478 spin_lock(&host->lock);
1479 }
1480
1481 static void atmci_command_complete(struct atmel_mci *host,
1482 struct mmc_command *cmd)
1483 {
1484 u32 status = host->cmd_status;
1485
1486 /* Read the response from the card (up to 16 bytes) */
1487 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1488 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1489 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1490 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1491
1492 if (status & ATMCI_RTOE)
1493 cmd->error = -ETIMEDOUT;
1494 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1495 cmd->error = -EILSEQ;
1496 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1497 cmd->error = -EIO;
1498 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1499 if (host->caps.need_blksz_mul_4) {
1500 cmd->error = -EINVAL;
1501 host->need_reset = 1;
1502 }
1503 } else
1504 cmd->error = 0;
1505 }
1506
1507 static void atmci_detect_change(unsigned long data)
1508 {
1509 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1510 bool present;
1511 bool present_old;
1512
1513 /*
1514 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1515 * freeing the interrupt. We must not re-enable the interrupt
1516 * if it has been freed, and if we're shutting down, it
1517 * doesn't really matter whether the card is present or not.
1518 */
1519 smp_rmb();
1520 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1521 return;
1522
1523 enable_irq(gpio_to_irq(slot->detect_pin));
1524 present = !(gpio_get_value(slot->detect_pin) ^
1525 slot->detect_is_active_high);
1526 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1527
1528 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1529 present, present_old);
1530
1531 if (present != present_old) {
1532 struct atmel_mci *host = slot->host;
1533 struct mmc_request *mrq;
1534
1535 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1536 present ? "inserted" : "removed");
1537
1538 spin_lock(&host->lock);
1539
1540 if (!present)
1541 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1542 else
1543 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1544
1545 /* Clean up queue if present */
1546 mrq = slot->mrq;
1547 if (mrq) {
1548 if (mrq == host->mrq) {
1549 /*
1550 * Reset controller to terminate any ongoing
1551 * commands or data transfers.
1552 */
1553 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1554 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1555 atmci_writel(host, ATMCI_MR, host->mode_reg);
1556 if (host->caps.has_cfg_reg)
1557 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1558
1559 host->data = NULL;
1560 host->cmd = NULL;
1561
1562 switch (host->state) {
1563 case STATE_IDLE:
1564 break;
1565 case STATE_SENDING_CMD:
1566 mrq->cmd->error = -ENOMEDIUM;
1567 if (mrq->data)
1568 host->stop_transfer(host);
1569 break;
1570 case STATE_DATA_XFER:
1571 mrq->data->error = -ENOMEDIUM;
1572 host->stop_transfer(host);
1573 break;
1574 case STATE_WAITING_NOTBUSY:
1575 mrq->data->error = -ENOMEDIUM;
1576 break;
1577 case STATE_SENDING_STOP:
1578 mrq->stop->error = -ENOMEDIUM;
1579 break;
1580 case STATE_END_REQUEST:
1581 break;
1582 }
1583
1584 atmci_request_end(host, mrq);
1585 } else {
1586 list_del(&slot->queue_node);
1587 mrq->cmd->error = -ENOMEDIUM;
1588 if (mrq->data)
1589 mrq->data->error = -ENOMEDIUM;
1590 if (mrq->stop)
1591 mrq->stop->error = -ENOMEDIUM;
1592
1593 spin_unlock(&host->lock);
1594 mmc_request_done(slot->mmc, mrq);
1595 spin_lock(&host->lock);
1596 }
1597 }
1598 spin_unlock(&host->lock);
1599
1600 mmc_detect_change(slot->mmc, 0);
1601 }
1602 }
1603
1604 static void atmci_tasklet_func(unsigned long priv)
1605 {
1606 struct atmel_mci *host = (struct atmel_mci *)priv;
1607 struct mmc_request *mrq = host->mrq;
1608 struct mmc_data *data = host->data;
1609 enum atmel_mci_state state = host->state;
1610 enum atmel_mci_state prev_state;
1611 u32 status;
1612
1613 spin_lock(&host->lock);
1614
1615 state = host->state;
1616
1617 dev_vdbg(&host->pdev->dev,
1618 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1619 state, host->pending_events, host->completed_events,
1620 atmci_readl(host, ATMCI_IMR));
1621
1622 do {
1623 prev_state = state;
1624 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1625
1626 switch (state) {
1627 case STATE_IDLE:
1628 break;
1629
1630 case STATE_SENDING_CMD:
1631 /*
1632 * Command has been sent, we are waiting for command
1633 * ready. Then we have three next states possible:
1634 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1635 * command needing it or DATA_XFER if there is data.
1636 */
1637 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1638 if (!atmci_test_and_clear_pending(host,
1639 EVENT_CMD_RDY))
1640 break;
1641
1642 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1643 host->cmd = NULL;
1644 atmci_set_completed(host, EVENT_CMD_RDY);
1645 atmci_command_complete(host, mrq->cmd);
1646 if (mrq->data) {
1647 dev_dbg(&host->pdev->dev,
1648 "command with data transfer");
1649 /*
1650 * If there is a command error don't start
1651 * data transfer.
1652 */
1653 if (mrq->cmd->error) {
1654 host->stop_transfer(host);
1655 host->data = NULL;
1656 atmci_writel(host, ATMCI_IDR,
1657 ATMCI_TXRDY | ATMCI_RXRDY
1658 | ATMCI_DATA_ERROR_FLAGS);
1659 state = STATE_END_REQUEST;
1660 } else
1661 state = STATE_DATA_XFER;
1662 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1663 dev_dbg(&host->pdev->dev,
1664 "command response need waiting notbusy");
1665 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1666 state = STATE_WAITING_NOTBUSY;
1667 } else
1668 state = STATE_END_REQUEST;
1669
1670 break;
1671
1672 case STATE_DATA_XFER:
1673 if (atmci_test_and_clear_pending(host,
1674 EVENT_DATA_ERROR)) {
1675 dev_dbg(&host->pdev->dev, "set completed data error\n");
1676 atmci_set_completed(host, EVENT_DATA_ERROR);
1677 state = STATE_END_REQUEST;
1678 break;
1679 }
1680
1681 /*
1682 * A data transfer is in progress. The event expected
1683 * to move to the next state depends of data transfer
1684 * type (PDC or DMA). Once transfer done we can move
1685 * to the next step which is WAITING_NOTBUSY in write
1686 * case and directly SENDING_STOP in read case.
1687 */
1688 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1689 if (!atmci_test_and_clear_pending(host,
1690 EVENT_XFER_COMPLETE))
1691 break;
1692
1693 dev_dbg(&host->pdev->dev,
1694 "(%s) set completed xfer complete\n",
1695 __func__);
1696 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1697
1698 if (host->caps.need_notbusy_for_read_ops ||
1699 (host->data->flags & MMC_DATA_WRITE)) {
1700 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1701 state = STATE_WAITING_NOTBUSY;
1702 } else if (host->mrq->stop) {
1703 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1704 atmci_send_stop_cmd(host, data);
1705 state = STATE_SENDING_STOP;
1706 } else {
1707 host->data = NULL;
1708 data->bytes_xfered = data->blocks * data->blksz;
1709 data->error = 0;
1710 state = STATE_END_REQUEST;
1711 }
1712 break;
1713
1714 case STATE_WAITING_NOTBUSY:
1715 /*
1716 * We can be in the state for two reasons: a command
1717 * requiring waiting not busy signal (stop command
1718 * included) or a write operation. In the latest case,
1719 * we need to send a stop command.
1720 */
1721 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1722 if (!atmci_test_and_clear_pending(host,
1723 EVENT_NOTBUSY))
1724 break;
1725
1726 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1727 atmci_set_completed(host, EVENT_NOTBUSY);
1728
1729 if (host->data) {
1730 /*
1731 * For some commands such as CMD53, even if
1732 * there is data transfer, there is no stop
1733 * command to send.
1734 */
1735 if (host->mrq->stop) {
1736 atmci_writel(host, ATMCI_IER,
1737 ATMCI_CMDRDY);
1738 atmci_send_stop_cmd(host, data);
1739 state = STATE_SENDING_STOP;
1740 } else {
1741 host->data = NULL;
1742 data->bytes_xfered = data->blocks
1743 * data->blksz;
1744 data->error = 0;
1745 state = STATE_END_REQUEST;
1746 }
1747 } else
1748 state = STATE_END_REQUEST;
1749 break;
1750
1751 case STATE_SENDING_STOP:
1752 /*
1753 * In this state, it is important to set host->data to
1754 * NULL (which is tested in the waiting notbusy state)
1755 * in order to go to the end request state instead of
1756 * sending stop again.
1757 */
1758 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1759 if (!atmci_test_and_clear_pending(host,
1760 EVENT_CMD_RDY))
1761 break;
1762
1763 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1764 host->cmd = NULL;
1765 data->bytes_xfered = data->blocks * data->blksz;
1766 data->error = 0;
1767 atmci_command_complete(host, mrq->stop);
1768 if (mrq->stop->error) {
1769 host->stop_transfer(host);
1770 atmci_writel(host, ATMCI_IDR,
1771 ATMCI_TXRDY | ATMCI_RXRDY
1772 | ATMCI_DATA_ERROR_FLAGS);
1773 state = STATE_END_REQUEST;
1774 } else {
1775 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1776 state = STATE_WAITING_NOTBUSY;
1777 }
1778 host->data = NULL;
1779 break;
1780
1781 case STATE_END_REQUEST:
1782 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1783 | ATMCI_DATA_ERROR_FLAGS);
1784 status = host->data_status;
1785 if (unlikely(status)) {
1786 host->stop_transfer(host);
1787 host->data = NULL;
1788 if (status & ATMCI_DTOE) {
1789 data->error = -ETIMEDOUT;
1790 } else if (status & ATMCI_DCRCE) {
1791 data->error = -EILSEQ;
1792 } else {
1793 data->error = -EIO;
1794 }
1795 }
1796
1797 atmci_request_end(host, host->mrq);
1798 state = STATE_IDLE;
1799 break;
1800 }
1801 } while (state != prev_state);
1802
1803 host->state = state;
1804
1805 spin_unlock(&host->lock);
1806 }
1807
1808 static void atmci_read_data_pio(struct atmel_mci *host)
1809 {
1810 struct scatterlist *sg = host->sg;
1811 void *buf = sg_virt(sg);
1812 unsigned int offset = host->pio_offset;
1813 struct mmc_data *data = host->data;
1814 u32 value;
1815 u32 status;
1816 unsigned int nbytes = 0;
1817
1818 do {
1819 value = atmci_readl(host, ATMCI_RDR);
1820 if (likely(offset + 4 <= sg->length)) {
1821 put_unaligned(value, (u32 *)(buf + offset));
1822
1823 offset += 4;
1824 nbytes += 4;
1825
1826 if (offset == sg->length) {
1827 flush_dcache_page(sg_page(sg));
1828 host->sg = sg = sg_next(sg);
1829 if (!sg)
1830 goto done;
1831
1832 offset = 0;
1833 buf = sg_virt(sg);
1834 }
1835 } else {
1836 unsigned int remaining = sg->length - offset;
1837 memcpy(buf + offset, &value, remaining);
1838 nbytes += remaining;
1839
1840 flush_dcache_page(sg_page(sg));
1841 host->sg = sg = sg_next(sg);
1842 if (!sg)
1843 goto done;
1844
1845 offset = 4 - remaining;
1846 buf = sg_virt(sg);
1847 memcpy(buf, (u8 *)&value + remaining, offset);
1848 nbytes += offset;
1849 }
1850
1851 status = atmci_readl(host, ATMCI_SR);
1852 if (status & ATMCI_DATA_ERROR_FLAGS) {
1853 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1854 | ATMCI_DATA_ERROR_FLAGS));
1855 host->data_status = status;
1856 data->bytes_xfered += nbytes;
1857 return;
1858 }
1859 } while (status & ATMCI_RXRDY);
1860
1861 host->pio_offset = offset;
1862 data->bytes_xfered += nbytes;
1863
1864 return;
1865
1866 done:
1867 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1868 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1869 data->bytes_xfered += nbytes;
1870 smp_wmb();
1871 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1872 }
1873
1874 static void atmci_write_data_pio(struct atmel_mci *host)
1875 {
1876 struct scatterlist *sg = host->sg;
1877 void *buf = sg_virt(sg);
1878 unsigned int offset = host->pio_offset;
1879 struct mmc_data *data = host->data;
1880 u32 value;
1881 u32 status;
1882 unsigned int nbytes = 0;
1883
1884 do {
1885 if (likely(offset + 4 <= sg->length)) {
1886 value = get_unaligned((u32 *)(buf + offset));
1887 atmci_writel(host, ATMCI_TDR, value);
1888
1889 offset += 4;
1890 nbytes += 4;
1891 if (offset == sg->length) {
1892 host->sg = sg = sg_next(sg);
1893 if (!sg)
1894 goto done;
1895
1896 offset = 0;
1897 buf = sg_virt(sg);
1898 }
1899 } else {
1900 unsigned int remaining = sg->length - offset;
1901
1902 value = 0;
1903 memcpy(&value, buf + offset, remaining);
1904 nbytes += remaining;
1905
1906 host->sg = sg = sg_next(sg);
1907 if (!sg) {
1908 atmci_writel(host, ATMCI_TDR, value);
1909 goto done;
1910 }
1911
1912 offset = 4 - remaining;
1913 buf = sg_virt(sg);
1914 memcpy((u8 *)&value + remaining, buf, offset);
1915 atmci_writel(host, ATMCI_TDR, value);
1916 nbytes += offset;
1917 }
1918
1919 status = atmci_readl(host, ATMCI_SR);
1920 if (status & ATMCI_DATA_ERROR_FLAGS) {
1921 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1922 | ATMCI_DATA_ERROR_FLAGS));
1923 host->data_status = status;
1924 data->bytes_xfered += nbytes;
1925 return;
1926 }
1927 } while (status & ATMCI_TXRDY);
1928
1929 host->pio_offset = offset;
1930 data->bytes_xfered += nbytes;
1931
1932 return;
1933
1934 done:
1935 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1936 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1937 data->bytes_xfered += nbytes;
1938 smp_wmb();
1939 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1940 }
1941
1942 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1943 {
1944 int i;
1945
1946 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1947 struct atmel_mci_slot *slot = host->slot[i];
1948 if (slot && (status & slot->sdio_irq)) {
1949 mmc_signal_sdio_irq(slot->mmc);
1950 }
1951 }
1952 }
1953
1954
1955 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1956 {
1957 struct atmel_mci *host = dev_id;
1958 u32 status, mask, pending;
1959 unsigned int pass_count = 0;
1960
1961 do {
1962 status = atmci_readl(host, ATMCI_SR);
1963 mask = atmci_readl(host, ATMCI_IMR);
1964 pending = status & mask;
1965 if (!pending)
1966 break;
1967
1968 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1969 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
1970 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1971 | ATMCI_RXRDY | ATMCI_TXRDY
1972 | ATMCI_ENDRX | ATMCI_ENDTX
1973 | ATMCI_RXBUFF | ATMCI_TXBUFE);
1974
1975 host->data_status = status;
1976 dev_dbg(&host->pdev->dev, "set pending data error\n");
1977 smp_wmb();
1978 atmci_set_pending(host, EVENT_DATA_ERROR);
1979 tasklet_schedule(&host->tasklet);
1980 }
1981
1982 if (pending & ATMCI_TXBUFE) {
1983 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
1984 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1985 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1986 /*
1987 * We can receive this interruption before having configured
1988 * the second pdc buffer, so we need to reconfigure first and
1989 * second buffers again
1990 */
1991 if (host->data_size) {
1992 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1993 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1994 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1995 } else {
1996 atmci_pdc_complete(host);
1997 }
1998 } else if (pending & ATMCI_ENDTX) {
1999 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2000 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2001
2002 if (host->data_size) {
2003 atmci_pdc_set_single_buf(host,
2004 XFER_TRANSMIT, PDC_SECOND_BUF);
2005 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2006 }
2007 }
2008
2009 if (pending & ATMCI_RXBUFF) {
2010 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2011 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2012 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2013 /*
2014 * We can receive this interruption before having configured
2015 * the second pdc buffer, so we need to reconfigure first and
2016 * second buffers again
2017 */
2018 if (host->data_size) {
2019 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2020 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2021 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2022 } else {
2023 atmci_pdc_complete(host);
2024 }
2025 } else if (pending & ATMCI_ENDRX) {
2026 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2027 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2028
2029 if (host->data_size) {
2030 atmci_pdc_set_single_buf(host,
2031 XFER_RECEIVE, PDC_SECOND_BUF);
2032 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2033 }
2034 }
2035
2036 /*
2037 * First mci IPs, so mainly the ones having pdc, have some
2038 * issues with the notbusy signal. You can't get it after
2039 * data transmission if you have not sent a stop command.
2040 * The appropriate workaround is to use the BLKE signal.
2041 */
2042 if (pending & ATMCI_BLKE) {
2043 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2044 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2045 smp_wmb();
2046 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2047 atmci_set_pending(host, EVENT_NOTBUSY);
2048 tasklet_schedule(&host->tasklet);
2049 }
2050
2051 if (pending & ATMCI_NOTBUSY) {
2052 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2053 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2054 smp_wmb();
2055 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2056 atmci_set_pending(host, EVENT_NOTBUSY);
2057 tasklet_schedule(&host->tasklet);
2058 }
2059
2060 if (pending & ATMCI_RXRDY)
2061 atmci_read_data_pio(host);
2062 if (pending & ATMCI_TXRDY)
2063 atmci_write_data_pio(host);
2064
2065 if (pending & ATMCI_CMDRDY) {
2066 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2067 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2068 host->cmd_status = status;
2069 smp_wmb();
2070 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2071 atmci_set_pending(host, EVENT_CMD_RDY);
2072 tasklet_schedule(&host->tasklet);
2073 }
2074
2075 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2076 atmci_sdio_interrupt(host, status);
2077
2078 } while (pass_count++ < 5);
2079
2080 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2081 }
2082
2083 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2084 {
2085 struct atmel_mci_slot *slot = dev_id;
2086
2087 /*
2088 * Disable interrupts until the pin has stabilized and check
2089 * the state then. Use mod_timer() since we may be in the
2090 * middle of the timer routine when this interrupt triggers.
2091 */
2092 disable_irq_nosync(irq);
2093 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2094
2095 return IRQ_HANDLED;
2096 }
2097
2098 static int __init atmci_init_slot(struct atmel_mci *host,
2099 struct mci_slot_pdata *slot_data, unsigned int id,
2100 u32 sdc_reg, u32 sdio_irq)
2101 {
2102 struct mmc_host *mmc;
2103 struct atmel_mci_slot *slot;
2104
2105 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2106 if (!mmc)
2107 return -ENOMEM;
2108
2109 slot = mmc_priv(mmc);
2110 slot->mmc = mmc;
2111 slot->host = host;
2112 slot->detect_pin = slot_data->detect_pin;
2113 slot->wp_pin = slot_data->wp_pin;
2114 slot->detect_is_active_high = slot_data->detect_is_active_high;
2115 slot->sdc_reg = sdc_reg;
2116 slot->sdio_irq = sdio_irq;
2117
2118 dev_dbg(&mmc->class_dev,
2119 "slot[%u]: bus_width=%u, detect_pin=%d, "
2120 "detect_is_active_high=%s, wp_pin=%d\n",
2121 id, slot_data->bus_width, slot_data->detect_pin,
2122 slot_data->detect_is_active_high ? "true" : "false",
2123 slot_data->wp_pin);
2124
2125 mmc->ops = &atmci_ops;
2126 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2127 mmc->f_max = host->bus_hz / 2;
2128 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2129 if (sdio_irq)
2130 mmc->caps |= MMC_CAP_SDIO_IRQ;
2131 if (host->caps.has_highspeed)
2132 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2133 /*
2134 * Without the read/write proof capability, it is strongly suggested to
2135 * use only one bit for data to prevent fifo underruns and overruns
2136 * which will corrupt data.
2137 */
2138 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2139 mmc->caps |= MMC_CAP_4_BIT_DATA;
2140
2141 if (atmci_get_version(host) < 0x200) {
2142 mmc->max_segs = 256;
2143 mmc->max_blk_size = 4095;
2144 mmc->max_blk_count = 256;
2145 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2146 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2147 } else {
2148 mmc->max_segs = 64;
2149 mmc->max_req_size = 32768 * 512;
2150 mmc->max_blk_size = 32768;
2151 mmc->max_blk_count = 512;
2152 }
2153
2154 /* Assume card is present initially */
2155 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2156 if (gpio_is_valid(slot->detect_pin)) {
2157 if (gpio_request(slot->detect_pin, "mmc_detect")) {
2158 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2159 slot->detect_pin = -EBUSY;
2160 } else if (gpio_get_value(slot->detect_pin) ^
2161 slot->detect_is_active_high) {
2162 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2163 }
2164 }
2165
2166 if (!gpio_is_valid(slot->detect_pin))
2167 mmc->caps |= MMC_CAP_NEEDS_POLL;
2168
2169 if (gpio_is_valid(slot->wp_pin)) {
2170 if (gpio_request(slot->wp_pin, "mmc_wp")) {
2171 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2172 slot->wp_pin = -EBUSY;
2173 }
2174 }
2175
2176 host->slot[id] = slot;
2177 mmc_add_host(mmc);
2178
2179 if (gpio_is_valid(slot->detect_pin)) {
2180 int ret;
2181
2182 setup_timer(&slot->detect_timer, atmci_detect_change,
2183 (unsigned long)slot);
2184
2185 ret = request_irq(gpio_to_irq(slot->detect_pin),
2186 atmci_detect_interrupt,
2187 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2188 "mmc-detect", slot);
2189 if (ret) {
2190 dev_dbg(&mmc->class_dev,
2191 "could not request IRQ %d for detect pin\n",
2192 gpio_to_irq(slot->detect_pin));
2193 gpio_free(slot->detect_pin);
2194 slot->detect_pin = -EBUSY;
2195 }
2196 }
2197
2198 atmci_init_debugfs(slot);
2199
2200 return 0;
2201 }
2202
2203 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2204 unsigned int id)
2205 {
2206 /* Debugfs stuff is cleaned up by mmc core */
2207
2208 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2209 smp_wmb();
2210
2211 mmc_remove_host(slot->mmc);
2212
2213 if (gpio_is_valid(slot->detect_pin)) {
2214 int pin = slot->detect_pin;
2215
2216 free_irq(gpio_to_irq(pin), slot);
2217 del_timer_sync(&slot->detect_timer);
2218 gpio_free(pin);
2219 }
2220 if (gpio_is_valid(slot->wp_pin))
2221 gpio_free(slot->wp_pin);
2222
2223 slot->host->slot[id] = NULL;
2224 mmc_free_host(slot->mmc);
2225 }
2226
2227 static bool atmci_filter(struct dma_chan *chan, void *slave)
2228 {
2229 struct mci_dma_data *sl = slave;
2230
2231 if (sl && find_slave_dev(sl) == chan->device->dev) {
2232 chan->private = slave_data_ptr(sl);
2233 return true;
2234 } else {
2235 return false;
2236 }
2237 }
2238
2239 static bool atmci_configure_dma(struct atmel_mci *host)
2240 {
2241 struct mci_platform_data *pdata;
2242
2243 if (host == NULL)
2244 return false;
2245
2246 pdata = host->pdev->dev.platform_data;
2247
2248 if (!pdata)
2249 return false;
2250
2251 if (pdata->dma_slave && find_slave_dev(pdata->dma_slave)) {
2252 dma_cap_mask_t mask;
2253
2254 /* Try to grab a DMA channel */
2255 dma_cap_zero(mask);
2256 dma_cap_set(DMA_SLAVE, mask);
2257 host->dma.chan =
2258 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
2259 }
2260 if (!host->dma.chan) {
2261 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2262 return false;
2263 } else {
2264 dev_info(&host->pdev->dev,
2265 "using %s for DMA transfers\n",
2266 dma_chan_name(host->dma.chan));
2267
2268 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2269 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2270 host->dma_conf.src_maxburst = 1;
2271 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2272 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2273 host->dma_conf.dst_maxburst = 1;
2274 host->dma_conf.device_fc = false;
2275 return true;
2276 }
2277 }
2278
2279 /*
2280 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2281 * HSMCI provides DMA support and a new config register but no more supports
2282 * PDC.
2283 */
2284 static void __init atmci_get_cap(struct atmel_mci *host)
2285 {
2286 unsigned int version;
2287
2288 version = atmci_get_version(host);
2289 dev_info(&host->pdev->dev,
2290 "version: 0x%x\n", version);
2291
2292 host->caps.has_dma_conf_reg = 0;
2293 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2294 host->caps.has_cfg_reg = 0;
2295 host->caps.has_cstor_reg = 0;
2296 host->caps.has_highspeed = 0;
2297 host->caps.has_rwproof = 0;
2298 host->caps.has_odd_clk_div = 0;
2299 host->caps.has_bad_data_ordering = 1;
2300 host->caps.need_reset_after_xfer = 1;
2301 host->caps.need_blksz_mul_4 = 1;
2302 host->caps.need_notbusy_for_read_ops = 0;
2303
2304 /* keep only major version number */
2305 switch (version & 0xf00) {
2306 case 0x500:
2307 host->caps.has_odd_clk_div = 1;
2308 case 0x400:
2309 case 0x300:
2310 host->caps.has_dma_conf_reg = 1;
2311 host->caps.has_pdc = 0;
2312 host->caps.has_cfg_reg = 1;
2313 host->caps.has_cstor_reg = 1;
2314 host->caps.has_highspeed = 1;
2315 case 0x200:
2316 host->caps.has_rwproof = 1;
2317 host->caps.need_blksz_mul_4 = 0;
2318 host->caps.need_notbusy_for_read_ops = 1;
2319 case 0x100:
2320 host->caps.has_bad_data_ordering = 0;
2321 host->caps.need_reset_after_xfer = 0;
2322 case 0x0:
2323 break;
2324 default:
2325 host->caps.has_pdc = 0;
2326 dev_warn(&host->pdev->dev,
2327 "Unmanaged mci version, set minimum capabilities\n");
2328 break;
2329 }
2330 }
2331
2332 static int __init atmci_probe(struct platform_device *pdev)
2333 {
2334 struct mci_platform_data *pdata;
2335 struct atmel_mci *host;
2336 struct resource *regs;
2337 unsigned int nr_slots;
2338 int irq;
2339 int ret;
2340
2341 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2342 if (!regs)
2343 return -ENXIO;
2344 pdata = pdev->dev.platform_data;
2345 if (!pdata) {
2346 pdata = atmci_of_init(pdev);
2347 if (IS_ERR(pdata)) {
2348 dev_err(&pdev->dev, "platform data not available\n");
2349 return PTR_ERR(pdata);
2350 }
2351 }
2352
2353 irq = platform_get_irq(pdev, 0);
2354 if (irq < 0)
2355 return irq;
2356
2357 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2358 if (!host)
2359 return -ENOMEM;
2360
2361 host->pdev = pdev;
2362 spin_lock_init(&host->lock);
2363 INIT_LIST_HEAD(&host->queue);
2364
2365 host->mck = clk_get(&pdev->dev, "mci_clk");
2366 if (IS_ERR(host->mck)) {
2367 ret = PTR_ERR(host->mck);
2368 goto err_clk_get;
2369 }
2370
2371 ret = -ENOMEM;
2372 host->regs = ioremap(regs->start, resource_size(regs));
2373 if (!host->regs)
2374 goto err_ioremap;
2375
2376 clk_enable(host->mck);
2377 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2378 host->bus_hz = clk_get_rate(host->mck);
2379 clk_disable(host->mck);
2380
2381 host->mapbase = regs->start;
2382
2383 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2384
2385 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2386 if (ret)
2387 goto err_request_irq;
2388
2389 /* Get MCI capabilities and set operations according to it */
2390 atmci_get_cap(host);
2391 if (atmci_configure_dma(host)) {
2392 host->prepare_data = &atmci_prepare_data_dma;
2393 host->submit_data = &atmci_submit_data_dma;
2394 host->stop_transfer = &atmci_stop_transfer_dma;
2395 } else if (host->caps.has_pdc) {
2396 dev_info(&pdev->dev, "using PDC\n");
2397 host->prepare_data = &atmci_prepare_data_pdc;
2398 host->submit_data = &atmci_submit_data_pdc;
2399 host->stop_transfer = &atmci_stop_transfer_pdc;
2400 } else {
2401 dev_info(&pdev->dev, "using PIO\n");
2402 host->prepare_data = &atmci_prepare_data;
2403 host->submit_data = &atmci_submit_data;
2404 host->stop_transfer = &atmci_stop_transfer;
2405 }
2406
2407 platform_set_drvdata(pdev, host);
2408
2409 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2410
2411 /* We need at least one slot to succeed */
2412 nr_slots = 0;
2413 ret = -ENODEV;
2414 if (pdata->slot[0].bus_width) {
2415 ret = atmci_init_slot(host, &pdata->slot[0],
2416 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2417 if (!ret) {
2418 nr_slots++;
2419 host->buf_size = host->slot[0]->mmc->max_req_size;
2420 }
2421 }
2422 if (pdata->slot[1].bus_width) {
2423 ret = atmci_init_slot(host, &pdata->slot[1],
2424 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2425 if (!ret) {
2426 nr_slots++;
2427 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2428 host->buf_size =
2429 host->slot[1]->mmc->max_req_size;
2430 }
2431 }
2432
2433 if (!nr_slots) {
2434 dev_err(&pdev->dev, "init failed: no slot defined\n");
2435 goto err_init_slot;
2436 }
2437
2438 if (!host->caps.has_rwproof) {
2439 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2440 &host->buf_phys_addr,
2441 GFP_KERNEL);
2442 if (!host->buffer) {
2443 ret = -ENOMEM;
2444 dev_err(&pdev->dev, "buffer allocation failed\n");
2445 goto err_init_slot;
2446 }
2447 }
2448
2449 dev_info(&pdev->dev,
2450 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2451 host->mapbase, irq, nr_slots);
2452
2453 return 0;
2454
2455 err_init_slot:
2456 if (host->dma.chan)
2457 dma_release_channel(host->dma.chan);
2458 free_irq(irq, host);
2459 err_request_irq:
2460 iounmap(host->regs);
2461 err_ioremap:
2462 clk_put(host->mck);
2463 err_clk_get:
2464 kfree(host);
2465 return ret;
2466 }
2467
2468 static int __exit atmci_remove(struct platform_device *pdev)
2469 {
2470 struct atmel_mci *host = platform_get_drvdata(pdev);
2471 unsigned int i;
2472
2473 platform_set_drvdata(pdev, NULL);
2474
2475 if (host->buffer)
2476 dma_free_coherent(&pdev->dev, host->buf_size,
2477 host->buffer, host->buf_phys_addr);
2478
2479 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2480 if (host->slot[i])
2481 atmci_cleanup_slot(host->slot[i], i);
2482 }
2483
2484 clk_enable(host->mck);
2485 atmci_writel(host, ATMCI_IDR, ~0UL);
2486 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2487 atmci_readl(host, ATMCI_SR);
2488 clk_disable(host->mck);
2489
2490 #ifdef CONFIG_MMC_ATMELMCI_DMA
2491 if (host->dma.chan)
2492 dma_release_channel(host->dma.chan);
2493 #endif
2494
2495 free_irq(platform_get_irq(pdev, 0), host);
2496 iounmap(host->regs);
2497
2498 clk_put(host->mck);
2499 kfree(host);
2500
2501 return 0;
2502 }
2503
2504 #ifdef CONFIG_PM
2505 static int atmci_suspend(struct device *dev)
2506 {
2507 struct atmel_mci *host = dev_get_drvdata(dev);
2508 int i;
2509
2510 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2511 struct atmel_mci_slot *slot = host->slot[i];
2512 int ret;
2513
2514 if (!slot)
2515 continue;
2516 ret = mmc_suspend_host(slot->mmc);
2517 if (ret < 0) {
2518 while (--i >= 0) {
2519 slot = host->slot[i];
2520 if (slot
2521 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2522 mmc_resume_host(host->slot[i]->mmc);
2523 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2524 }
2525 }
2526 return ret;
2527 } else {
2528 set_bit(ATMCI_SUSPENDED, &slot->flags);
2529 }
2530 }
2531
2532 return 0;
2533 }
2534
2535 static int atmci_resume(struct device *dev)
2536 {
2537 struct atmel_mci *host = dev_get_drvdata(dev);
2538 int i;
2539 int ret = 0;
2540
2541 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2542 struct atmel_mci_slot *slot = host->slot[i];
2543 int err;
2544
2545 slot = host->slot[i];
2546 if (!slot)
2547 continue;
2548 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2549 continue;
2550 err = mmc_resume_host(slot->mmc);
2551 if (err < 0)
2552 ret = err;
2553 else
2554 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2555 }
2556
2557 return ret;
2558 }
2559 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2560 #define ATMCI_PM_OPS (&atmci_pm)
2561 #else
2562 #define ATMCI_PM_OPS NULL
2563 #endif
2564
2565 static struct platform_driver atmci_driver = {
2566 .remove = __exit_p(atmci_remove),
2567 .driver = {
2568 .name = "atmel_mci",
2569 .pm = ATMCI_PM_OPS,
2570 .of_match_table = of_match_ptr(atmci_dt_ids),
2571 },
2572 };
2573
2574 static int __init atmci_init(void)
2575 {
2576 return platform_driver_probe(&atmci_driver, atmci_probe);
2577 }
2578
2579 static void __exit atmci_exit(void)
2580 {
2581 platform_driver_unregister(&atmci_driver);
2582 }
2583
2584 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2585 module_exit(atmci_exit);
2586
2587 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2588 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2589 MODULE_LICENSE("GPL v2");
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