2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qlge for copyright and licensing details.
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12 #include <linux/rtnetlink.h>
15 * General definitions...
17 #define DRV_NAME "qlge"
18 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
19 #define DRV_VERSION "v1.00.00-b3"
22 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
24 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
27 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
28 "%s: " fmt, __func__, ##args); \
31 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
33 #define QLGE_VENDOR_ID 0x1077
34 #define QLGE_DEVICE_ID_8012 0x8012
35 #define QLGE_DEVICE_ID_8000 0x8000
37 #define MAX_TX_RINGS MAX_CPUS
38 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
40 #define NUM_TX_RING_ENTRIES 256
41 #define NUM_RX_RING_ENTRIES 256
43 #define NUM_SMALL_BUFFERS 512
44 #define NUM_LARGE_BUFFERS 512
45 #define DB_PAGE_SIZE 4096
47 /* Calculate the number of (4k) pages required to
48 * contain a buffer queue of the given length.
50 #define MAX_DB_PAGES_PER_BQ(x) \
51 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
52 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
54 #define RX_RING_SHADOW_SPACE (sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
56 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
57 #define SMALL_BUFFER_SIZE 512
58 #define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
59 #define LARGE_BUFFER_MAX_SIZE 8192
60 #define LARGE_BUFFER_MIN_SIZE 2048
61 #define MAX_SPLIT_SIZE 1023
62 #define QLGE_SB_PAD 32
65 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
66 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
67 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
68 #define UDELAY_COUNT 3
69 #define UDELAY_DELAY 100
72 #define TX_DESC_PER_IOCB 8
73 /* The maximum number of frags we handle is based
76 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
77 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
78 #else /* all other page sizes */
79 #define TX_DESC_PER_OAL 0
82 /* MPI test register definitions. This register
83 * is used for determining alternate NIC function's
87 MPI_TEST_FUNC_PORT_CFG
= 0x1002,
88 MPI_TEST_NIC1_FUNC_SHIFT
= 1,
89 MPI_TEST_NIC2_FUNC_SHIFT
= 5,
90 MPI_TEST_NIC_FUNC_MASK
= 0x00000007,
94 * Processor Address Register (PROC_ADDR) bit definitions.
101 PROC_ADDR_RDY
= (1 << 31),
102 PROC_ADDR_R
= (1 << 30),
103 PROC_ADDR_ERR
= (1 << 29),
104 PROC_ADDR_DA
= (1 << 28),
105 PROC_ADDR_FUNC0_MBI
= 0x00001180,
106 PROC_ADDR_FUNC0_MBO
= (PROC_ADDR_FUNC0_MBI
+ MAILBOX_COUNT
),
107 PROC_ADDR_FUNC0_CTL
= 0x000011a1,
108 PROC_ADDR_FUNC2_MBI
= 0x00001280,
109 PROC_ADDR_FUNC2_MBO
= (PROC_ADDR_FUNC2_MBI
+ MAILBOX_COUNT
),
110 PROC_ADDR_FUNC2_CTL
= 0x000012a1,
111 PROC_ADDR_MPI_RISC
= 0x00000000,
112 PROC_ADDR_MDE
= 0x00010000,
113 PROC_ADDR_REGBLOCK
= 0x00020000,
114 PROC_ADDR_RISC_REG
= 0x00030000,
118 * System Register (SYS) bit definitions.
127 SYS_OMP_DLY_MASK
= 0x3f000000,
129 * There are no values defined as of edit #15.
135 * Reset/Failover Register (RST_FO) bit definitions.
138 RST_FO_TFO
= (1 << 0),
139 RST_FO_RR_MASK
= 0x00060000,
140 RST_FO_RR_CQ_CAM
= 0x00000000,
141 RST_FO_RR_DROP
= 0x00000002,
142 RST_FO_RR_DQ
= 0x00000004,
143 RST_FO_RR_RCV_FUNC_CQ
= 0x00000006,
144 RST_FO_FRB
= (1 << 12),
145 RST_FO_MOP
= (1 << 13),
146 RST_FO_REG
= (1 << 14),
147 RST_FO_FR
= (1 << 15),
151 * Function Specific Control Register (FSC) bit definitions.
154 FSC_DBRST_MASK
= 0x00070000,
155 FSC_DBRST_256
= 0x00000000,
156 FSC_DBRST_512
= 0x00000001,
157 FSC_DBRST_768
= 0x00000002,
158 FSC_DBRST_1024
= 0x00000003,
159 FSC_DBL_MASK
= 0x00180000,
160 FSC_DBL_DBRST
= 0x00000000,
161 FSC_DBL_MAX_PLD
= 0x00000008,
162 FSC_DBL_MAX_BRST
= 0x00000010,
163 FSC_DBL_128_BYTES
= 0x00000018,
165 FSC_EPC_MASK
= 0x00c00000,
166 FSC_EPC_INBOUND
= (1 << 6),
167 FSC_EPC_OUTBOUND
= (1 << 7),
168 FSC_VM_PAGESIZE_MASK
= 0x07000000,
169 FSC_VM_PAGE_2K
= 0x00000100,
170 FSC_VM_PAGE_4K
= 0x00000200,
171 FSC_VM_PAGE_8K
= 0x00000300,
172 FSC_VM_PAGE_64K
= 0x00000600,
180 * Host Command Status Register (CSR) bit definitions.
183 CSR_ERR_STS_MASK
= 0x0000003f,
185 * There are no valued defined as of edit #15.
190 CSR_CMD_PARM_SHIFT
= 22,
191 CSR_CMD_NOP
= 0x00000000,
192 CSR_CMD_SET_RST
= 0x10000000,
193 CSR_CMD_CLR_RST
= 0x20000000,
194 CSR_CMD_SET_PAUSE
= 0x30000000,
195 CSR_CMD_CLR_PAUSE
= 0x40000000,
196 CSR_CMD_SET_H2R_INT
= 0x50000000,
197 CSR_CMD_CLR_H2R_INT
= 0x60000000,
198 CSR_CMD_PAR_EN
= 0x70000000,
199 CSR_CMD_SET_BAD_PAR
= 0x80000000,
200 CSR_CMD_CLR_BAD_PAR
= 0x90000000,
201 CSR_CMD_CLR_R2PCI_INT
= 0xa0000000,
205 * Configuration Register (CFG) bit definitions.
216 CFG_Q_MASK
= 0x7f000000,
220 * Status Register (STS) bit definitions.
229 STS_FUNC_ID_MASK
= 0x000000c0,
230 STS_FUNC_ID_SHIFT
= 6,
239 * Interrupt Enable Register (INTR_EN) bit definitions.
242 INTR_EN_INTR_MASK
= 0x007f0000,
243 INTR_EN_TYPE_MASK
= 0x03000000,
244 INTR_EN_TYPE_ENABLE
= 0x00000100,
245 INTR_EN_TYPE_DISABLE
= 0x00000200,
246 INTR_EN_TYPE_READ
= 0x00000300,
247 INTR_EN_IHD
= (1 << 13),
248 INTR_EN_IHD_MASK
= (INTR_EN_IHD
<< 16),
249 INTR_EN_EI
= (1 << 14),
250 INTR_EN_EN
= (1 << 15),
254 * Interrupt Mask Register (INTR_MASK) bit definitions.
257 INTR_MASK_PI
= (1 << 0),
258 INTR_MASK_HL0
= (1 << 1),
259 INTR_MASK_LH0
= (1 << 2),
260 INTR_MASK_HL1
= (1 << 3),
261 INTR_MASK_LH1
= (1 << 4),
262 INTR_MASK_SE
= (1 << 5),
263 INTR_MASK_LSC
= (1 << 6),
264 INTR_MASK_MC
= (1 << 7),
265 INTR_MASK_LINK_IRQS
= INTR_MASK_LSC
| INTR_MASK_SE
| INTR_MASK_MC
,
269 * Register (REV_ID) bit definitions.
272 REV_ID_MASK
= 0x0000000f,
273 REV_ID_NICROLL_SHIFT
= 0,
274 REV_ID_NICREV_SHIFT
= 4,
275 REV_ID_XGROLL_SHIFT
= 8,
276 REV_ID_XGREV_SHIFT
= 12,
277 REV_ID_CHIPREV_SHIFT
= 28,
281 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
284 FRC_ECC_ERR_VW
= (1 << 12),
285 FRC_ECC_ERR_VB
= (1 << 13),
286 FRC_ECC_ERR_NI
= (1 << 14),
287 FRC_ECC_ERR_NO
= (1 << 15),
288 FRC_ECC_PFE_SHIFT
= 16,
289 FRC_ECC_ERR_DO
= (1 << 18),
290 FRC_ECC_P14
= (1 << 19),
294 * Error Status Register (ERR_STS) bit definitions.
297 ERR_STS_NOF
= (1 << 0),
298 ERR_STS_NIF
= (1 << 1),
299 ERR_STS_DRP
= (1 << 2),
300 ERR_STS_XGP
= (1 << 3),
301 ERR_STS_FOU
= (1 << 4),
302 ERR_STS_FOC
= (1 << 5),
303 ERR_STS_FOF
= (1 << 6),
304 ERR_STS_FIU
= (1 << 7),
305 ERR_STS_FIC
= (1 << 8),
306 ERR_STS_FIF
= (1 << 9),
307 ERR_STS_MOF
= (1 << 10),
308 ERR_STS_TA
= (1 << 11),
309 ERR_STS_MA
= (1 << 12),
310 ERR_STS_MPE
= (1 << 13),
311 ERR_STS_SCE
= (1 << 14),
312 ERR_STS_STE
= (1 << 15),
313 ERR_STS_FOW
= (1 << 16),
314 ERR_STS_UE
= (1 << 17),
315 ERR_STS_MCH
= (1 << 26),
316 ERR_STS_LOC_SHIFT
= 27,
320 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
323 RAM_DBG_ADDR_FW
= (1 << 30),
324 RAM_DBG_ADDR_FR
= (1 << 31),
328 * Semaphore Register (SEM) bit definitions.
333 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
338 SEM_XGMAC0_SHIFT
= 0,
339 SEM_XGMAC1_SHIFT
= 2,
341 SEM_MAC_ADDR_SHIFT
= 6,
343 SEM_PROBE_SHIFT
= 10,
344 SEM_RT_IDX_SHIFT
= 12,
345 SEM_PROC_REG_SHIFT
= 14,
346 SEM_XGMAC0_MASK
= 0x00030000,
347 SEM_XGMAC1_MASK
= 0x000c0000,
348 SEM_ICB_MASK
= 0x00300000,
349 SEM_MAC_ADDR_MASK
= 0x00c00000,
350 SEM_FLASH_MASK
= 0x03000000,
351 SEM_PROBE_MASK
= 0x0c000000,
352 SEM_RT_IDX_MASK
= 0x30000000,
353 SEM_PROC_REG_MASK
= 0xc0000000,
357 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
360 XGMAC_ADDR_RDY
= (1 << 31),
361 XGMAC_ADDR_R
= (1 << 30),
362 XGMAC_ADDR_XME
= (1 << 29),
364 /* XGMAC control registers */
365 PAUSE_SRC_LO
= 0x00000100,
366 PAUSE_SRC_HI
= 0x00000104,
367 GLOBAL_CFG
= 0x00000108,
368 GLOBAL_CFG_RESET
= (1 << 0),
369 GLOBAL_CFG_JUMBO
= (1 << 6),
370 GLOBAL_CFG_TX_STAT_EN
= (1 << 10),
371 GLOBAL_CFG_RX_STAT_EN
= (1 << 11),
373 TX_CFG_RESET
= (1 << 0),
374 TX_CFG_EN
= (1 << 1),
375 TX_CFG_PREAM
= (1 << 2),
377 RX_CFG_RESET
= (1 << 0),
378 RX_CFG_EN
= (1 << 1),
379 RX_CFG_PREAM
= (1 << 2),
380 FLOW_CTL
= 0x0000011c,
381 PAUSE_OPCODE
= 0x00000120,
382 PAUSE_TIMER
= 0x00000124,
383 PAUSE_FRM_DEST_LO
= 0x00000128,
384 PAUSE_FRM_DEST_HI
= 0x0000012c,
385 MAC_TX_PARAMS
= 0x00000134,
386 MAC_TX_PARAMS_JUMBO
= (1 << 31),
387 MAC_TX_PARAMS_SIZE_SHIFT
= 16,
388 MAC_RX_PARAMS
= 0x00000138,
389 MAC_SYS_INT
= 0x00000144,
390 MAC_SYS_INT_MASK
= 0x00000148,
391 MAC_MGMT_INT
= 0x0000014c,
392 MAC_MGMT_IN_MASK
= 0x00000150,
393 EXT_ARB_MODE
= 0x000001fc,
395 /* XGMAC TX statistics registers */
396 TX_PKTS
= 0x00000200,
397 TX_BYTES
= 0x00000208,
398 TX_MCAST_PKTS
= 0x00000210,
399 TX_BCAST_PKTS
= 0x00000218,
400 TX_UCAST_PKTS
= 0x00000220,
401 TX_CTL_PKTS
= 0x00000228,
402 TX_PAUSE_PKTS
= 0x00000230,
403 TX_64_PKT
= 0x00000238,
404 TX_65_TO_127_PKT
= 0x00000240,
405 TX_128_TO_255_PKT
= 0x00000248,
406 TX_256_511_PKT
= 0x00000250,
407 TX_512_TO_1023_PKT
= 0x00000258,
408 TX_1024_TO_1518_PKT
= 0x00000260,
409 TX_1519_TO_MAX_PKT
= 0x00000268,
410 TX_UNDERSIZE_PKT
= 0x00000270,
411 TX_OVERSIZE_PKT
= 0x00000278,
413 /* XGMAC statistics control registers */
414 RX_HALF_FULL_DET
= 0x000002a0,
415 TX_HALF_FULL_DET
= 0x000002a4,
416 RX_OVERFLOW_DET
= 0x000002a8,
417 TX_OVERFLOW_DET
= 0x000002ac,
418 RX_HALF_FULL_MASK
= 0x000002b0,
419 TX_HALF_FULL_MASK
= 0x000002b4,
420 RX_OVERFLOW_MASK
= 0x000002b8,
421 TX_OVERFLOW_MASK
= 0x000002bc,
422 STAT_CNT_CTL
= 0x000002c0,
423 STAT_CNT_CTL_CLEAR_TX
= (1 << 0),
424 STAT_CNT_CTL_CLEAR_RX
= (1 << 1),
425 AUX_RX_HALF_FULL_DET
= 0x000002d0,
426 AUX_TX_HALF_FULL_DET
= 0x000002d4,
427 AUX_RX_OVERFLOW_DET
= 0x000002d8,
428 AUX_TX_OVERFLOW_DET
= 0x000002dc,
429 AUX_RX_HALF_FULL_MASK
= 0x000002f0,
430 AUX_TX_HALF_FULL_MASK
= 0x000002f4,
431 AUX_RX_OVERFLOW_MASK
= 0x000002f8,
432 AUX_TX_OVERFLOW_MASK
= 0x000002fc,
434 /* XGMAC RX statistics registers */
435 RX_BYTES
= 0x00000300,
436 RX_BYTES_OK
= 0x00000308,
437 RX_PKTS
= 0x00000310,
438 RX_PKTS_OK
= 0x00000318,
439 RX_BCAST_PKTS
= 0x00000320,
440 RX_MCAST_PKTS
= 0x00000328,
441 RX_UCAST_PKTS
= 0x00000330,
442 RX_UNDERSIZE_PKTS
= 0x00000338,
443 RX_OVERSIZE_PKTS
= 0x00000340,
444 RX_JABBER_PKTS
= 0x00000348,
445 RX_UNDERSIZE_FCERR_PKTS
= 0x00000350,
446 RX_DROP_EVENTS
= 0x00000358,
447 RX_FCERR_PKTS
= 0x00000360,
448 RX_ALIGN_ERR
= 0x00000368,
449 RX_SYMBOL_ERR
= 0x00000370,
450 RX_MAC_ERR
= 0x00000378,
451 RX_CTL_PKTS
= 0x00000380,
452 RX_PAUSE_PKTS
= 0x00000388,
453 RX_64_PKTS
= 0x00000390,
454 RX_65_TO_127_PKTS
= 0x00000398,
455 RX_128_255_PKTS
= 0x000003a0,
456 RX_256_511_PKTS
= 0x000003a8,
457 RX_512_TO_1023_PKTS
= 0x000003b0,
458 RX_1024_TO_1518_PKTS
= 0x000003b8,
459 RX_1519_TO_MAX_PKTS
= 0x000003c0,
460 RX_LEN_ERR_PKTS
= 0x000003c8,
462 /* XGMAC MDIO control registers */
463 MDIO_TX_DATA
= 0x00000400,
464 MDIO_RX_DATA
= 0x00000410,
465 MDIO_CMD
= 0x00000420,
466 MDIO_PHY_ADDR
= 0x00000430,
467 MDIO_PORT
= 0x00000440,
468 MDIO_STATUS
= 0x00000450,
470 /* XGMAC AUX statistics registers */
474 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
477 ETS_QUEUE_SHIFT
= 29,
481 ETS_FC_COS_SHIFT
= 23,
485 * Flash Address Register (FLASH_ADDR) bit definitions.
488 FLASH_ADDR_RDY
= (1 << 31),
489 FLASH_ADDR_R
= (1 << 30),
490 FLASH_ADDR_ERR
= (1 << 29),
494 * Stop CQ Processing Register (CQ_STOP) bit definitions.
497 CQ_STOP_QUEUE_MASK
= (0x007f0000),
498 CQ_STOP_TYPE_MASK
= (0x03000000),
499 CQ_STOP_TYPE_START
= 0x00000100,
500 CQ_STOP_TYPE_STOP
= 0x00000200,
501 CQ_STOP_TYPE_READ
= 0x00000300,
502 CQ_STOP_EN
= (1 << 15),
506 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
509 MAC_ADDR_IDX_SHIFT
= 4,
510 MAC_ADDR_TYPE_SHIFT
= 16,
511 MAC_ADDR_TYPE_MASK
= 0x000f0000,
512 MAC_ADDR_TYPE_CAM_MAC
= 0x00000000,
513 MAC_ADDR_TYPE_MULTI_MAC
= 0x00010000,
514 MAC_ADDR_TYPE_VLAN
= 0x00020000,
515 MAC_ADDR_TYPE_MULTI_FLTR
= 0x00030000,
516 MAC_ADDR_TYPE_FC_MAC
= 0x00040000,
517 MAC_ADDR_TYPE_MGMT_MAC
= 0x00050000,
518 MAC_ADDR_TYPE_MGMT_VLAN
= 0x00060000,
519 MAC_ADDR_TYPE_MGMT_V4
= 0x00070000,
520 MAC_ADDR_TYPE_MGMT_V6
= 0x00080000,
521 MAC_ADDR_TYPE_MGMT_TU_DP
= 0x00090000,
522 MAC_ADDR_ADR
= (1 << 25),
523 MAC_ADDR_RS
= (1 << 26),
524 MAC_ADDR_E
= (1 << 27),
525 MAC_ADDR_MR
= (1 << 30),
526 MAC_ADDR_MW
= (1 << 31),
527 MAX_MULTICAST_ENTRIES
= 32,
531 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
534 SPLT_HDR_EP
= (1 << 31),
538 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
541 FC_RCV_CFG_ECT
= (1 << 15),
542 FC_RCV_CFG_DFH
= (1 << 20),
543 FC_RCV_CFG_DVF
= (1 << 21),
544 FC_RCV_CFG_RCE
= (1 << 27),
545 FC_RCV_CFG_RFE
= (1 << 28),
546 FC_RCV_CFG_TEE
= (1 << 29),
547 FC_RCV_CFG_TCE
= (1 << 30),
548 FC_RCV_CFG_TFE
= (1 << 31),
552 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
555 NIC_RCV_CFG_PPE
= (1 << 0),
556 NIC_RCV_CFG_VLAN_MASK
= 0x00060000,
557 NIC_RCV_CFG_VLAN_ALL
= 0x00000000,
558 NIC_RCV_CFG_VLAN_MATCH_ONLY
= 0x00000002,
559 NIC_RCV_CFG_VLAN_MATCH_AND_NON
= 0x00000004,
560 NIC_RCV_CFG_VLAN_NONE_AND_NON
= 0x00000006,
561 NIC_RCV_CFG_RV
= (1 << 3),
562 NIC_RCV_CFG_DFQ_MASK
= (0x7f000000),
563 NIC_RCV_CFG_DFQ_SHIFT
= 8,
564 NIC_RCV_CFG_DFQ
= 0, /* HARDCODE default queue to 0. */
568 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
571 MGMT_RCV_CFG_ARP
= (1 << 0),
572 MGMT_RCV_CFG_DHC
= (1 << 1),
573 MGMT_RCV_CFG_DHS
= (1 << 2),
574 MGMT_RCV_CFG_NP
= (1 << 3),
575 MGMT_RCV_CFG_I6N
= (1 << 4),
576 MGMT_RCV_CFG_I6R
= (1 << 5),
577 MGMT_RCV_CFG_DH6
= (1 << 6),
578 MGMT_RCV_CFG_UD1
= (1 << 7),
579 MGMT_RCV_CFG_UD0
= (1 << 8),
580 MGMT_RCV_CFG_BCT
= (1 << 9),
581 MGMT_RCV_CFG_MCT
= (1 << 10),
582 MGMT_RCV_CFG_DM
= (1 << 11),
583 MGMT_RCV_CFG_RM
= (1 << 12),
584 MGMT_RCV_CFG_STL
= (1 << 13),
585 MGMT_RCV_CFG_VLAN_MASK
= 0xc0000000,
586 MGMT_RCV_CFG_VLAN_ALL
= 0x00000000,
587 MGMT_RCV_CFG_VLAN_MATCH_ONLY
= 0x00004000,
588 MGMT_RCV_CFG_VLAN_MATCH_AND_NON
= 0x00008000,
589 MGMT_RCV_CFG_VLAN_NONE_AND_NON
= 0x0000c000,
593 * Routing Index Register (RT_IDX) bit definitions.
596 RT_IDX_IDX_SHIFT
= 8,
597 RT_IDX_TYPE_MASK
= 0x000f0000,
598 RT_IDX_TYPE_RT
= 0x00000000,
599 RT_IDX_TYPE_RT_INV
= 0x00010000,
600 RT_IDX_TYPE_NICQ
= 0x00020000,
601 RT_IDX_TYPE_NICQ_INV
= 0x00030000,
602 RT_IDX_DST_MASK
= 0x00700000,
603 RT_IDX_DST_RSS
= 0x00000000,
604 RT_IDX_DST_CAM_Q
= 0x00100000,
605 RT_IDX_DST_COS_Q
= 0x00200000,
606 RT_IDX_DST_DFLT_Q
= 0x00300000,
607 RT_IDX_DST_DEST_Q
= 0x00400000,
608 RT_IDX_RS
= (1 << 26),
609 RT_IDX_E
= (1 << 27),
610 RT_IDX_MR
= (1 << 30),
611 RT_IDX_MW
= (1 << 31),
613 /* Nic Queue format - type 2 bits */
614 RT_IDX_BCAST
= (1 << 0),
615 RT_IDX_MCAST
= (1 << 1),
616 RT_IDX_MCAST_MATCH
= (1 << 2),
617 RT_IDX_MCAST_REG_MATCH
= (1 << 3),
618 RT_IDX_MCAST_HASH_MATCH
= (1 << 4),
619 RT_IDX_FC_MACH
= (1 << 5),
620 RT_IDX_ETH_FCOE
= (1 << 6),
621 RT_IDX_CAM_HIT
= (1 << 7),
622 RT_IDX_CAM_BIT0
= (1 << 8),
623 RT_IDX_CAM_BIT1
= (1 << 9),
624 RT_IDX_VLAN_TAG
= (1 << 10),
625 RT_IDX_VLAN_MATCH
= (1 << 11),
626 RT_IDX_VLAN_FILTER
= (1 << 12),
627 RT_IDX_ETH_SKIP1
= (1 << 13),
628 RT_IDX_ETH_SKIP2
= (1 << 14),
629 RT_IDX_BCAST_MCAST_MATCH
= (1 << 15),
630 RT_IDX_802_3
= (1 << 16),
631 RT_IDX_LLDP
= (1 << 17),
632 RT_IDX_UNUSED018
= (1 << 18),
633 RT_IDX_UNUSED019
= (1 << 19),
634 RT_IDX_UNUSED20
= (1 << 20),
635 RT_IDX_UNUSED21
= (1 << 21),
636 RT_IDX_ERR
= (1 << 22),
637 RT_IDX_VALID
= (1 << 23),
638 RT_IDX_TU_CSUM_ERR
= (1 << 24),
639 RT_IDX_IP_CSUM_ERR
= (1 << 25),
640 RT_IDX_MAC_ERR
= (1 << 26),
641 RT_IDX_RSS_TCP6
= (1 << 27),
642 RT_IDX_RSS_TCP4
= (1 << 28),
643 RT_IDX_RSS_IPV6
= (1 << 29),
644 RT_IDX_RSS_IPV4
= (1 << 30),
645 RT_IDX_RSS_MATCH
= (1 << 31),
647 /* Hierarchy for the NIC Queue Mask */
648 RT_IDX_ALL_ERR_SLOT
= 0,
649 RT_IDX_MAC_ERR_SLOT
= 0,
650 RT_IDX_IP_CSUM_ERR_SLOT
= 1,
651 RT_IDX_TCP_UDP_CSUM_ERR_SLOT
= 2,
652 RT_IDX_BCAST_SLOT
= 3,
653 RT_IDX_MCAST_MATCH_SLOT
= 4,
654 RT_IDX_ALLMULTI_SLOT
= 5,
655 RT_IDX_UNUSED6_SLOT
= 6,
656 RT_IDX_UNUSED7_SLOT
= 7,
657 RT_IDX_RSS_MATCH_SLOT
= 8,
658 RT_IDX_RSS_IPV4_SLOT
= 8,
659 RT_IDX_RSS_IPV6_SLOT
= 9,
660 RT_IDX_RSS_TCP4_SLOT
= 10,
661 RT_IDX_RSS_TCP6_SLOT
= 11,
662 RT_IDX_CAM_HIT_SLOT
= 12,
663 RT_IDX_UNUSED013
= 13,
664 RT_IDX_UNUSED014
= 14,
665 RT_IDX_PROMISCUOUS_SLOT
= 15,
666 RT_IDX_MAX_SLOTS
= 16,
670 * Control Register Set Map
673 PROC_ADDR
= 0, /* Use semaphore */
674 PROC_DATA
= 0x04, /* Use semaphore */
680 ICB_RID
= 0x1c, /* Use semaphore */
681 ICB_L
= 0x20, /* Use semaphore */
682 ICB_H
= 0x24, /* Use semaphore */
699 GPIO_1
= 0x68, /* Use semaphore */
700 GPIO_2
= 0x6c, /* Use semaphore */
701 GPIO_3
= 0x70, /* Use semaphore */
703 XGMAC_ADDR
= 0x78, /* Use semaphore */
704 XGMAC_DATA
= 0x7c, /* Use semaphore */
707 FLASH_ADDR
= 0x88, /* Use semaphore */
708 FLASH_DATA
= 0x8c, /* Use semaphore */
711 WQ_PAGE_TBL_LO
= 0x98,
712 WQ_PAGE_TBL_HI
= 0x9c,
713 CQ_PAGE_TBL_LO
= 0xa0,
714 CQ_PAGE_TBL_HI
= 0xa4,
715 MAC_ADDR_IDX
= 0xa8, /* Use semaphore */
716 MAC_ADDR_DATA
= 0xac, /* Use semaphore */
722 FC_PAUSE_THRES
= 0xc4,
723 NIC_PAUSE_THRES
= 0xc8,
733 XG_SERDES_ADDR
= 0xf0,
734 XG_SERDES_DATA
= 0xf4,
735 PRB_MX_ADDR
= 0xf8, /* Use semaphore */
736 PRB_MX_DATA
= 0xfc, /* Use semaphore */
743 CAM_OUT_ROUTE_FC
= 0,
744 CAM_OUT_ROUTE_NIC
= 1,
745 CAM_OUT_FUNC_SHIFT
= 2,
746 CAM_OUT_RV
= (1 << 4),
747 CAM_OUT_SH
= (1 << 15),
748 CAM_OUT_CQ_ID_SHIFT
= 5,
752 * Mailbox definitions
755 /* Asynchronous Event Notifications */
756 AEN_SYS_ERR
= 0x00008002,
757 AEN_LINK_UP
= 0x00008011,
758 AEN_LINK_DOWN
= 0x00008012,
759 AEN_IDC_CMPLT
= 0x00008100,
760 AEN_IDC_REQ
= 0x00008101,
761 AEN_IDC_EXT
= 0x00008102,
762 AEN_DCBX_CHG
= 0x00008110,
763 AEN_AEN_LOST
= 0x00008120,
764 AEN_AEN_SFP_IN
= 0x00008130,
765 AEN_AEN_SFP_OUT
= 0x00008131,
766 AEN_FW_INIT_DONE
= 0x00008400,
767 AEN_FW_INIT_FAIL
= 0x00008401,
769 /* Mailbox Command Opcodes. */
770 MB_CMD_NOP
= 0x00000000,
771 MB_CMD_EX_FW
= 0x00000002,
772 MB_CMD_MB_TEST
= 0x00000006,
773 MB_CMD_CSUM_TEST
= 0x00000007, /* Verify Checksum */
774 MB_CMD_ABOUT_FW
= 0x00000008,
775 MB_CMD_COPY_RISC_RAM
= 0x0000000a,
776 MB_CMD_LOAD_RISC_RAM
= 0x0000000b,
777 MB_CMD_DUMP_RISC_RAM
= 0x0000000c,
778 MB_CMD_WRITE_RAM
= 0x0000000d,
779 MB_CMD_INIT_RISC_RAM
= 0x0000000e,
780 MB_CMD_READ_RAM
= 0x0000000f,
781 MB_CMD_STOP_FW
= 0x00000014,
782 MB_CMD_MAKE_SYS_ERR
= 0x0000002a,
783 MB_CMD_WRITE_SFP
= 0x00000030,
784 MB_CMD_READ_SFP
= 0x00000031,
785 MB_CMD_INIT_FW
= 0x00000060,
786 MB_CMD_GET_IFCB
= 0x00000061,
787 MB_CMD_GET_FW_STATE
= 0x00000069,
788 MB_CMD_IDC_REQ
= 0x00000100, /* Inter-Driver Communication */
789 MB_CMD_IDC_ACK
= 0x00000101, /* Inter-Driver Communication */
790 MB_CMD_SET_WOL_MODE
= 0x00000110, /* Wake On Lan */
792 MB_WOL_MAGIC_PKT
= (1 << 1),
793 MB_WOL_FLTR
= (1 << 2),
794 MB_WOL_UCAST
= (1 << 3),
795 MB_WOL_MCAST
= (1 << 4),
796 MB_WOL_BCAST
= (1 << 5),
797 MB_WOL_LINK_UP
= (1 << 6),
798 MB_WOL_LINK_DOWN
= (1 << 7),
799 MB_WOL_MODE_ON
= (1 << 16), /* Wake on Lan Mode on */
800 MB_CMD_SET_WOL_FLTR
= 0x00000111, /* Wake On Lan Filter */
801 MB_CMD_CLEAR_WOL_FLTR
= 0x00000112, /* Wake On Lan Filter */
802 MB_CMD_SET_WOL_MAGIC
= 0x00000113, /* Wake On Lan Magic Packet */
803 MB_CMD_CLEAR_WOL_MAGIC
= 0x00000114,/* Wake On Lan Magic Packet */
804 MB_CMD_SET_WOL_IMMED
= 0x00000115,
805 MB_CMD_PORT_RESET
= 0x00000120,
806 MB_CMD_SET_PORT_CFG
= 0x00000122,
807 MB_CMD_GET_PORT_CFG
= 0x00000123,
808 MB_CMD_GET_LINK_STS
= 0x00000124,
809 MB_CMD_SET_LED_CFG
= 0x00000125, /* Set LED Configuration Register */
810 QL_LED_BLINK
= 0x03e803e8,
811 MB_CMD_GET_LED_CFG
= 0x00000126, /* Get LED Configuration Register */
812 MB_CMD_SET_MGMNT_TFK_CTL
= 0x00000160, /* Set Mgmnt Traffic Control */
813 MB_SET_MPI_TFK_STOP
= (1 << 0),
814 MB_SET_MPI_TFK_RESUME
= (1 << 1),
815 MB_CMD_GET_MGMNT_TFK_CTL
= 0x00000161, /* Get Mgmnt Traffic Control */
816 MB_GET_MPI_TFK_STOPPED
= (1 << 0),
817 MB_GET_MPI_TFK_FIFO_EMPTY
= (1 << 1),
819 /* Mailbox Command Status. */
820 MB_CMD_STS_GOOD
= 0x00004000, /* Success. */
821 MB_CMD_STS_INTRMDT
= 0x00001000, /* Intermediate Complete. */
822 MB_CMD_STS_INVLD_CMD
= 0x00004001, /* Invalid. */
823 MB_CMD_STS_XFC_ERR
= 0x00004002, /* Interface Error. */
824 MB_CMD_STS_CSUM_ERR
= 0x00004003, /* Csum Error. */
825 MB_CMD_STS_ERR
= 0x00004005, /* System Error. */
826 MB_CMD_STS_PARAM_ERR
= 0x00004006, /* Parameter Error. */
830 u32 mbox_in
[MAILBOX_COUNT
];
831 u32 mbox_out
[MAILBOX_COUNT
];
836 struct flash_params_8012
{
846 /* 8000 device's flash is a different structure
847 * at a different offset in flash.
849 #define FUNC0_FLASH_OFFSET 0x140200
850 #define FUNC1_FLASH_OFFSET 0x140600
852 /* Flash related data structures. */
853 struct flash_params_8000
{
854 u8 dev_id_str
[4]; /* "8000" */
874 __le16 subsys_ven_id
;
875 __le16 subsys_dev_id
;
880 struct flash_params_8012 flash_params_8012
;
881 struct flash_params_8000 flash_params_8000
;
885 * doorbell space for the rx ring context
887 struct rx_doorbell_context
{
888 u32 cnsmr_idx
; /* 0x00 */
889 u32 valid
; /* 0x04 */
890 u32 reserved
[4]; /* 0x08-0x14 */
891 u32 lbq_prod_idx
; /* 0x18 */
892 u32 sbq_prod_idx
; /* 0x1c */
896 * doorbell space for the tx ring context
898 struct tx_doorbell_context
{
899 u32 prod_idx
; /* 0x00 */
900 u32 valid
; /* 0x04 */
901 u32 reserved
[4]; /* 0x08-0x14 */
902 u32 lbq_prod_idx
; /* 0x18 */
903 u32 sbq_prod_idx
; /* 0x1c */
906 /* DATA STRUCTURES SHARED WITH HARDWARE. */
910 #define TX_DESC_LEN_MASK 0x000fffff
911 #define TX_DESC_C 0x40000000
912 #define TX_DESC_E 0x80000000
913 } __attribute((packed
));
916 * IOCB Definitions...
919 #define OPCODE_OB_MAC_IOCB 0x01
920 #define OPCODE_OB_MAC_TSO_IOCB 0x02
921 #define OPCODE_IB_MAC_IOCB 0x20
922 #define OPCODE_IB_MPI_IOCB 0x21
923 #define OPCODE_IB_AE_IOCB 0x3f
925 struct ob_mac_iocb_req
{
928 #define OB_MAC_IOCB_REQ_OI 0x01
929 #define OB_MAC_IOCB_REQ_I 0x02
930 #define OB_MAC_IOCB_REQ_D 0x08
931 #define OB_MAC_IOCB_REQ_F 0x10
934 #define OB_MAC_IOCB_DFP 0x02
935 #define OB_MAC_IOCB_V 0x04
938 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
945 struct tx_buf_desc tbd
[TX_DESC_PER_IOCB
];
946 } __attribute((packed
));
948 struct ob_mac_iocb_rsp
{
951 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
952 #define OB_MAC_IOCB_RSP_I 0x02 /* */
953 #define OB_MAC_IOCB_RSP_E 0x08 /* */
954 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
955 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
956 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
959 #define OB_MAC_IOCB_RSP_B 0x80 /* */
963 } __attribute((packed
));
965 struct ob_mac_tso_iocb_req
{
968 #define OB_MAC_TSO_IOCB_OI 0x01
969 #define OB_MAC_TSO_IOCB_I 0x02
970 #define OB_MAC_TSO_IOCB_D 0x08
971 #define OB_MAC_TSO_IOCB_IP4 0x40
972 #define OB_MAC_TSO_IOCB_IP6 0x80
974 #define OB_MAC_TSO_IOCB_LSO 0x20
975 #define OB_MAC_TSO_IOCB_UC 0x40
976 #define OB_MAC_TSO_IOCB_TC 0x80
978 #define OB_MAC_TSO_IOCB_IC 0x01
979 #define OB_MAC_TSO_IOCB_DFP 0x02
980 #define OB_MAC_TSO_IOCB_V 0x04
985 __le16 total_hdrs_len
;
986 __le16 net_trans_offset
;
987 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
990 struct tx_buf_desc tbd
[TX_DESC_PER_IOCB
];
991 } __attribute((packed
));
993 struct ob_mac_tso_iocb_rsp
{
996 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
997 #define OB_MAC_TSO_IOCB_RSP_I 0x02
998 #define OB_MAC_TSO_IOCB_RSP_E 0x08
999 #define OB_MAC_TSO_IOCB_RSP_S 0x10
1000 #define OB_MAC_TSO_IOCB_RSP_L 0x20
1001 #define OB_MAC_TSO_IOCB_RSP_P 0x40
1004 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
1007 __le32 reserved2
[13];
1008 } __attribute((packed
));
1010 struct ib_mac_iocb_rsp
{
1011 u8 opcode
; /* 0x20 */
1013 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1014 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
1015 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
1016 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1017 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1018 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1019 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1020 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1021 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1022 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1023 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1024 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1026 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1027 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1028 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1029 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1030 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1031 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1032 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1033 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1034 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1035 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1036 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1037 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1039 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1040 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1041 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1042 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1043 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1044 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1045 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1046 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1047 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1048 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1049 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1050 __le32 data_len
; /* */
1051 __le64 data_addr
; /* */
1053 __le16 vlan_id
; /* 12 bits */
1054 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1055 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1056 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1059 __le32 reserved2
[6];
1062 #define IB_MAC_IOCB_RSP_HV 0x20
1063 #define IB_MAC_IOCB_RSP_HS 0x40
1064 #define IB_MAC_IOCB_RSP_HL 0x80
1065 __le32 hdr_len
; /* */
1066 __le64 hdr_addr
; /* */
1067 } __attribute((packed
));
1069 struct ib_ae_iocb_rsp
{
1072 #define IB_AE_IOCB_RSP_OI 0x01
1073 #define IB_AE_IOCB_RSP_I 0x02
1075 #define LINK_UP_EVENT 0x00
1076 #define LINK_DOWN_EVENT 0x01
1077 #define CAM_LOOKUP_ERR_EVENT 0x06
1078 #define SOFT_ECC_ERROR_EVENT 0x07
1079 #define MGMT_ERR_EVENT 0x08
1080 #define TEN_GIG_MAC_EVENT 0x09
1081 #define GPI0_H2L_EVENT 0x10
1082 #define GPI0_L2H_EVENT 0x20
1083 #define GPI1_H2L_EVENT 0x11
1084 #define GPI1_L2H_EVENT 0x21
1085 #define PCI_ERR_ANON_BUF_RD 0x40
1087 __le32 reserved
[15];
1088 } __attribute((packed
));
1091 * These three structures are for generic
1092 * handling of ib and ob iocbs.
1094 struct ql_net_rsp_iocb
{
1099 __le32 reserved
[14];
1100 } __attribute((packed
));
1102 struct net_req_iocb
{
1107 __le32 reserved1
[30];
1108 } __attribute((packed
));
1111 * tx ring initialization control block for chip.
1113 * "Work Queue Initialization Control Block"
1117 #define Q_LEN_V (1 << 4)
1118 #define Q_LEN_CPP_CONT 0x0000
1119 #define Q_LEN_CPP_16 0x0001
1120 #define Q_LEN_CPP_32 0x0002
1121 #define Q_LEN_CPP_64 0x0003
1122 #define Q_LEN_CPP_512 0x0006
1124 #define Q_PRI_SHIFT 1
1125 #define Q_FLAGS_LC 0x1000
1126 #define Q_FLAGS_LB 0x2000
1127 #define Q_FLAGS_LI 0x4000
1128 #define Q_FLAGS_LO 0x8000
1130 #define Q_CQ_ID_RSS_RV 0x8000
1133 __le64 cnsmr_idx_addr
;
1134 } __attribute((packed
));
1137 * rx ring initialization control block for chip.
1139 * "Completion Queue Initialization Control Block"
1146 #define FLAGS_LV 0x08
1147 #define FLAGS_LS 0x10
1148 #define FLAGS_LL 0x20
1149 #define FLAGS_LI 0x40
1150 #define FLAGS_LC 0x80
1152 #define LEN_V (1 << 4)
1153 #define LEN_CPP_CONT 0x0000
1154 #define LEN_CPP_32 0x0001
1155 #define LEN_CPP_64 0x0002
1156 #define LEN_CPP_128 0x0003
1159 __le64 prod_idx_addr
;
1163 __le16 lbq_buf_size
;
1164 __le16 lbq_len
; /* entry count */
1166 __le16 sbq_buf_size
;
1167 __le16 sbq_len
; /* entry count */
1168 } __attribute((packed
));
1172 #define RSS_L4K 0x80
1174 #define RSS_L6K 0x01
1178 #define RSS_RI4 0x10
1179 #define RSS_RT4 0x20
1180 #define RSS_RI6 0x40
1181 #define RSS_RT6 0x80
1183 u8 hash_cq_id
[1024];
1184 __le32 ipv6_hash_key
[10];
1185 __le32 ipv4_hash_key
[4];
1186 } __attribute((packed
));
1188 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1191 struct tx_buf_desc oal
[TX_DESC_PER_OAL
];
1195 DECLARE_PCI_UNMAP_ADDR(mapaddr
);
1196 DECLARE_PCI_UNMAP_LEN(maplen
);
1199 struct tx_ring_desc
{
1200 struct sk_buff
*skb
;
1201 struct ob_mac_iocb_req
*queue_entry
;
1204 struct map_list map
[MAX_SKB_FRAGS
+ 1];
1206 struct tx_ring_desc
*next
;
1210 struct page
*page
; /* master page */
1211 char *va
; /* virt addr for this chunk */
1212 u64 map
; /* mapping for master */
1213 unsigned int offset
; /* offset for this chunk */
1214 unsigned int last_flag
; /* flag set for last chunk in page */
1219 struct page_chunk pg_chunk
;
1220 struct sk_buff
*skb
;
1224 DECLARE_PCI_UNMAP_ADDR(mapaddr
);
1225 DECLARE_PCI_UNMAP_LEN(maplen
);
1228 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1234 struct wqicb wqicb
; /* structure used to inform chip of new queue */
1235 void *wq_base
; /* pci_alloc:virtual addr for tx */
1236 dma_addr_t wq_base_dma
; /* pci_alloc:dma addr for tx */
1237 __le32
*cnsmr_idx_sh_reg
; /* shadow copy of consumer idx */
1238 dma_addr_t cnsmr_idx_sh_reg_dma
; /* dma-shadow copy of consumer */
1239 u32 wq_size
; /* size in bytes of queue area */
1240 u32 wq_len
; /* number of entries in queue */
1241 void __iomem
*prod_idx_db_reg
; /* doorbell area index reg at offset 0x00 */
1242 void __iomem
*valid_db_reg
; /* doorbell area valid reg at offset 0x04 */
1243 u16 prod_idx
; /* current value for prod idx */
1244 u16 cq_id
; /* completion (rx) queue for tx completions */
1245 u8 wq_id
; /* queue id for this entry */
1247 struct tx_ring_desc
*q
; /* descriptor list for the queue */
1249 atomic_t tx_count
; /* counts down for every outstanding IO */
1250 atomic_t queue_stopped
; /* Turns queue off when full. */
1251 struct delayed_work tx_work
;
1252 struct ql_adapter
*qdev
;
1256 * Type of inbound queue.
1259 DEFAULT_Q
= 2, /* Handles slow queue and chip/MPI events. */
1260 TX_Q
= 3, /* Handles outbound completions. */
1261 RX_Q
= 4, /* Handles inbound completions. */
1265 struct cqicb cqicb
; /* The chip's completion queue init control block. */
1267 /* Completion queue elements. */
1269 dma_addr_t cq_base_dma
;
1273 __le32
*prod_idx_sh_reg
; /* Shadowed producer register. */
1274 dma_addr_t prod_idx_sh_reg_dma
;
1275 void __iomem
*cnsmr_idx_db_reg
; /* PCI doorbell mem area + 0 */
1276 u32 cnsmr_idx
; /* current sw idx */
1277 struct ql_net_rsp_iocb
*curr_entry
; /* next entry on queue */
1278 void __iomem
*valid_db_reg
; /* PCI doorbell mem area + 0x04 */
1280 /* Large buffer queue elements. */
1281 u32 lbq_len
; /* entry count */
1282 u32 lbq_size
; /* size in bytes of queue */
1285 dma_addr_t lbq_base_dma
;
1286 void *lbq_base_indirect
;
1287 dma_addr_t lbq_base_indirect_dma
;
1288 struct page_chunk pg_chunk
; /* current page for chunks */
1289 struct bq_desc
*lbq
; /* array of control blocks */
1290 void __iomem
*lbq_prod_idx_db_reg
; /* PCI doorbell mem area + 0x18 */
1291 u32 lbq_prod_idx
; /* current sw prod idx */
1292 u32 lbq_curr_idx
; /* next entry we expect */
1293 u32 lbq_clean_idx
; /* beginning of new descs */
1294 u32 lbq_free_cnt
; /* free buffer desc cnt */
1296 /* Small buffer queue elements. */
1297 u32 sbq_len
; /* entry count */
1298 u32 sbq_size
; /* size in bytes of queue */
1301 dma_addr_t sbq_base_dma
;
1302 void *sbq_base_indirect
;
1303 dma_addr_t sbq_base_indirect_dma
;
1304 struct bq_desc
*sbq
; /* array of control blocks */
1305 void __iomem
*sbq_prod_idx_db_reg
; /* PCI doorbell mem area + 0x1c */
1306 u32 sbq_prod_idx
; /* current sw prod idx */
1307 u32 sbq_curr_idx
; /* next entry we expect */
1308 u32 sbq_clean_idx
; /* beginning of new descs */
1309 u32 sbq_free_cnt
; /* free buffer desc cnt */
1311 /* Misc. handler elements. */
1312 u32 type
; /* Type of queue, tx, rx. */
1313 u32 irq
; /* Which vector this ring is assigned. */
1314 u32 cpu
; /* Which CPU this should run on. */
1315 char name
[IFNAMSIZ
+ 5];
1316 struct napi_struct napi
;
1318 struct ql_adapter
*qdev
;
1322 * RSS Initialization Control Block
1330 * These stats come from offset 200h to 278h
1331 * in the XGMAC register.
1341 u64 tx_65_to_127_pkt
;
1342 u64 tx_128_to_255_pkt
;
1344 u64 tx_512_to_1023_pkt
;
1345 u64 tx_1024_to_1518_pkt
;
1346 u64 tx_1519_to_max_pkt
;
1347 u64 tx_undersize_pkt
;
1348 u64 tx_oversize_pkt
;
1351 * These stats come from offset 300h to 3C8h
1352 * in the XGMAC register.
1361 u64 rx_undersize_pkts
;
1362 u64 rx_oversize_pkts
;
1364 u64 rx_undersize_fcerr_pkts
;
1373 u64 rx_65_to_127_pkts
;
1374 u64 rx_128_255_pkts
;
1375 u64 rx_256_511_pkts
;
1376 u64 rx_512_to_1023_pkts
;
1377 u64 rx_1024_to_1518_pkts
;
1378 u64 rx_1519_to_max_pkts
;
1379 u64 rx_len_err_pkts
;
1381 * These stats come from offset 500h to 5C8h
1382 * in the XGMAC register.
1384 u64 tx_cbfc_pause_frames0
;
1385 u64 tx_cbfc_pause_frames1
;
1386 u64 tx_cbfc_pause_frames2
;
1387 u64 tx_cbfc_pause_frames3
;
1388 u64 tx_cbfc_pause_frames4
;
1389 u64 tx_cbfc_pause_frames5
;
1390 u64 tx_cbfc_pause_frames6
;
1391 u64 tx_cbfc_pause_frames7
;
1392 u64 rx_cbfc_pause_frames0
;
1393 u64 rx_cbfc_pause_frames1
;
1394 u64 rx_cbfc_pause_frames2
;
1395 u64 rx_cbfc_pause_frames3
;
1396 u64 rx_cbfc_pause_frames4
;
1397 u64 rx_cbfc_pause_frames5
;
1398 u64 rx_cbfc_pause_frames6
;
1399 u64 rx_cbfc_pause_frames7
;
1400 u64 rx_nic_fifo_drop
;
1404 * intr_context structure is used during initialization
1405 * to hook the interrupts. It is also used in a single
1406 * irq environment as a context to the ISR.
1408 struct intr_context
{
1409 struct ql_adapter
*qdev
;
1411 u32 irq_mask
; /* Mask of which rings the vector services. */
1413 u32 intr_en_mask
; /* value/mask used to enable this intr */
1414 u32 intr_dis_mask
; /* value/mask used to disable this intr */
1415 u32 intr_read_mask
; /* value/mask used to read this intr */
1416 char name
[IFNAMSIZ
* 2];
1417 atomic_t irq_cnt
; /* irq_cnt is used in single vector
1418 * environment. It's incremented for each
1419 * irq handler that is scheduled. When each
1420 * handler finishes it decrements irq_cnt and
1421 * enables interrupts if it's zero. */
1422 irq_handler_t handler
;
1425 /* adapter flags definitions. */
1427 QL_ADAPTER_UP
= 0, /* Adapter has been brought up. */
1428 QL_LEGACY_ENABLED
= 1,
1430 QL_MSIX_ENABLED
= 3,
1438 /* link_status bit definitions */
1440 STS_LOOPBACK_MASK
= 0x00000700,
1441 STS_LOOPBACK_PCS
= 0x00000100,
1442 STS_LOOPBACK_HSS
= 0x00000200,
1443 STS_LOOPBACK_EXT
= 0x00000300,
1444 STS_PAUSE_MASK
= 0x000000c0,
1445 STS_PAUSE_STD
= 0x00000040,
1446 STS_PAUSE_PRI
= 0x00000080,
1447 STS_SPEED_MASK
= 0x00000038,
1448 STS_SPEED_100Mb
= 0x00000000,
1449 STS_SPEED_1Gb
= 0x00000008,
1450 STS_SPEED_10Gb
= 0x00000010,
1451 STS_LINK_TYPE_MASK
= 0x00000007,
1452 STS_LINK_TYPE_XFI
= 0x00000001,
1453 STS_LINK_TYPE_XAUI
= 0x00000002,
1454 STS_LINK_TYPE_XFI_BP
= 0x00000003,
1455 STS_LINK_TYPE_XAUI_BP
= 0x00000004,
1456 STS_LINK_TYPE_10GBASET
= 0x00000005,
1459 /* link_config bit definitions */
1461 CFG_JUMBO_FRAME_SIZE
= 0x00010000,
1462 CFG_PAUSE_MASK
= 0x00000060,
1463 CFG_PAUSE_STD
= 0x00000020,
1464 CFG_PAUSE_PRI
= 0x00000040,
1465 CFG_DCBX
= 0x00000010,
1466 CFG_LOOPBACK_MASK
= 0x00000007,
1467 CFG_LOOPBACK_PCS
= 0x00000002,
1468 CFG_LOOPBACK_HSS
= 0x00000004,
1469 CFG_LOOPBACK_EXT
= 0x00000006,
1470 CFG_DEFAULT_MAX_FRAME_SIZE
= 0x00002580,
1473 struct nic_operations
{
1475 int (*get_flash
) (struct ql_adapter
*);
1476 int (*port_initialize
) (struct ql_adapter
*);
1480 * The main Adapter structure definition.
1481 * This structure has all fields relevant to the hardware.
1485 unsigned long flags
;
1488 struct nic_stats nic_stats
;
1490 struct vlan_group
*vlgrp
;
1492 /* PCI Configuration information for this device */
1493 struct pci_dev
*pdev
;
1494 struct net_device
*ndev
; /* Parent NET device */
1496 /* Hardware information */
1499 u32 func
; /* PCI function for this adapter */
1500 u32 alt_func
; /* PCI function for alternate adapter */
1501 u32 port
; /* Port number this adapter */
1503 spinlock_t adapter_lock
;
1505 spinlock_t stats_lock
;
1507 /* PCI Bus Relative Register Addresses */
1508 void __iomem
*reg_base
;
1509 void __iomem
*doorbell_area
;
1510 u32 doorbell_area_size
;
1514 /* Page for Shadow Registers */
1515 void *rx_ring_shadow_reg_area
;
1516 dma_addr_t rx_ring_shadow_reg_dma
;
1517 void *tx_ring_shadow_reg_area
;
1518 dma_addr_t tx_ring_shadow_reg_dma
;
1522 struct mbox_params idc_mbc
;
1527 struct msix_entry
*msi_x_entry
;
1528 struct intr_context intr_context
[MAX_RX_RINGS
];
1530 int tx_ring_count
; /* One per online CPU. */
1531 u32 rss_ring_count
; /* One per irq vector. */
1534 * (CPU count * outbound completion rx_ring) +
1535 * (irq_vector_cnt * inbound (RSS) completion rx_ring)
1541 struct rx_ring rx_ring
[MAX_RX_RINGS
];
1542 struct tx_ring tx_ring
[MAX_TX_RINGS
];
1543 unsigned int lbq_buf_order
;
1546 u32 default_rx_queue
;
1548 u16 rx_coalesce_usecs
; /* cqicb->int_delay */
1549 u16 rx_max_coalesced_frames
; /* cqicb->pkt_int_delay */
1550 u16 tx_coalesce_usecs
; /* cqicb->int_delay */
1551 u16 tx_max_coalesced_frames
; /* cqicb->pkt_int_delay */
1561 union flash_params flash
;
1563 struct workqueue_struct
*workqueue
;
1564 struct delayed_work asic_reset_work
;
1565 struct delayed_work mpi_reset_work
;
1566 struct delayed_work mpi_work
;
1567 struct delayed_work mpi_port_cfg_work
;
1568 struct delayed_work mpi_idc_work
;
1569 struct completion ide_completion
;
1570 struct nic_operations
*nic_ops
;
1575 * Typical Register accessor for memory mapped device.
1577 static inline u32
ql_read32(const struct ql_adapter
*qdev
, int reg
)
1579 return readl(qdev
->reg_base
+ reg
);
1583 * Typical Register accessor for memory mapped device.
1585 static inline void ql_write32(const struct ql_adapter
*qdev
, int reg
, u32 val
)
1587 writel(val
, qdev
->reg_base
+ reg
);
1591 * Doorbell Registers:
1592 * Doorbell registers are virtual registers in the PCI memory space.
1593 * The space is allocated by the chip during PCI initialization. The
1594 * device driver finds the doorbell address in BAR 3 in PCI config space.
1595 * The registers are used to control outbound and inbound queues. For
1596 * example, the producer index for an outbound queue. Each queue uses
1597 * 1 4k chunk of memory. The lower half of the space is for outbound
1598 * queues. The upper half is for inbound queues.
1600 static inline void ql_write_db_reg(u32 val
, void __iomem
*addr
)
1608 * Outbound queues have a consumer index that is maintained by the chip.
1609 * Inbound queues have a producer index that is maintained by the chip.
1610 * For lower overhead, these registers are "shadowed" to host memory
1611 * which allows the device driver to track the queue progress without
1612 * PCI reads. When an entry is placed on an inbound queue, the chip will
1613 * update the relevant index register and then copy the value to the
1614 * shadow register in host memory.
1616 static inline u32
ql_read_sh_reg(__le32
*addr
)
1619 reg
= le32_to_cpu(*addr
);
1624 extern char qlge_driver_name
[];
1625 extern const char qlge_driver_version
[];
1626 extern const struct ethtool_ops qlge_ethtool_ops
;
1628 extern int ql_sem_spinlock(struct ql_adapter
*qdev
, u32 sem_mask
);
1629 extern void ql_sem_unlock(struct ql_adapter
*qdev
, u32 sem_mask
);
1630 extern int ql_read_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32
*data
);
1631 extern int ql_get_mac_addr_reg(struct ql_adapter
*qdev
, u32 type
, u16 index
,
1633 extern int ql_get_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32
*value
);
1634 extern int ql_write_cfg(struct ql_adapter
*qdev
, void *ptr
, int size
, u32 bit
,
1636 void ql_queue_fw_error(struct ql_adapter
*qdev
);
1637 void ql_mpi_work(struct work_struct
*work
);
1638 void ql_mpi_reset_work(struct work_struct
*work
);
1639 int ql_wait_reg_rdy(struct ql_adapter
*qdev
, u32 reg
, u32 bit
, u32 ebit
);
1640 void ql_queue_asic_error(struct ql_adapter
*qdev
);
1641 u32
ql_enable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
);
1642 void ql_set_ethtool_ops(struct net_device
*ndev
);
1643 int ql_read_xgmac_reg64(struct ql_adapter
*qdev
, u32 reg
, u64
*data
);
1644 void ql_mpi_idc_work(struct work_struct
*work
);
1645 void ql_mpi_port_cfg_work(struct work_struct
*work
);
1646 int ql_mb_get_fw_state(struct ql_adapter
*qdev
);
1647 int ql_cam_route_initialize(struct ql_adapter
*qdev
);
1648 int ql_read_mpi_reg(struct ql_adapter
*qdev
, u32 reg
, u32
*data
);
1649 int ql_mb_about_fw(struct ql_adapter
*qdev
);
1650 int ql_wol(struct ql_adapter
*qdev
);
1651 int ql_mb_wol_set_magic(struct ql_adapter
*qdev
, u32 enable_wol
);
1652 int ql_mb_wol_mode(struct ql_adapter
*qdev
, u32 wol
);
1653 int ql_mb_set_led_cfg(struct ql_adapter
*qdev
, u32 led_config
);
1654 int ql_mb_get_led_cfg(struct ql_adapter
*qdev
);
1655 void ql_link_on(struct ql_adapter
*qdev
);
1656 void ql_link_off(struct ql_adapter
*qdev
);
1657 int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter
*qdev
, u32 control
);
1658 int ql_mb_get_port_cfg(struct ql_adapter
*qdev
);
1659 int ql_mb_set_port_cfg(struct ql_adapter
*qdev
);
1660 int ql_wait_fifo_empty(struct ql_adapter
*qdev
);
1667 /* #define QL_IB_DUMP */
1668 /* #define QL_OB_DUMP */
1672 extern void ql_dump_xgmac_control_regs(struct ql_adapter
*qdev
);
1673 extern void ql_dump_routing_entries(struct ql_adapter
*qdev
);
1674 extern void ql_dump_regs(struct ql_adapter
*qdev
);
1675 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1676 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1677 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1679 #define QL_DUMP_REGS(qdev)
1680 #define QL_DUMP_ROUTE(qdev)
1681 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1685 extern void ql_dump_stat(struct ql_adapter
*qdev
);
1686 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1688 #define QL_DUMP_STAT(qdev)
1692 extern void ql_dump_qdev(struct ql_adapter
*qdev
);
1693 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1695 #define QL_DUMP_QDEV(qdev)
1699 extern void ql_dump_wqicb(struct wqicb
*wqicb
);
1700 extern void ql_dump_tx_ring(struct tx_ring
*tx_ring
);
1701 extern void ql_dump_ricb(struct ricb
*ricb
);
1702 extern void ql_dump_cqicb(struct cqicb
*cqicb
);
1703 extern void ql_dump_rx_ring(struct rx_ring
*rx_ring
);
1704 extern void ql_dump_hw_cb(struct ql_adapter
*qdev
, int size
, u32 bit
, u16 q_id
);
1705 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1706 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1707 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1708 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1709 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1710 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1711 ql_dump_hw_cb(qdev, size, bit, q_id)
1713 #define QL_DUMP_RICB(ricb)
1714 #define QL_DUMP_WQICB(wqicb)
1715 #define QL_DUMP_TX_RING(tx_ring)
1716 #define QL_DUMP_CQICB(cqicb)
1717 #define QL_DUMP_RX_RING(rx_ring)
1718 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1722 extern void ql_dump_tx_desc(struct tx_buf_desc
*tbd
);
1723 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req
*ob_mac_iocb
);
1724 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp
*ob_mac_rsp
);
1725 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1726 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1728 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1729 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1733 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp
*ib_mac_rsp
);
1734 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1736 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1740 extern void ql_dump_all(struct ql_adapter
*qdev
);
1741 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1743 #define QL_DUMP_ALL(qdev)
1746 #endif /* _QLGE_H_ */