2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmapool.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/ioport.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/timer.h>
25 #include <linux/list.h>
26 #include <linux/interrupt.h>
27 #include <linux/moduleparam.h>
28 #include <linux/device.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/otg.h>
34 #include <linux/irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/mv_usb.h>
38 #include <asm/unaligned.h>
42 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
43 #define DRIVER_VERSION "8 Nov 2010"
45 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
46 ((ep)->udc->ep0_dir) : ((ep)->direction))
48 /* timeout value -- usec */
49 #define RESET_TIMEOUT 10000
50 #define FLUSH_TIMEOUT 10000
51 #define EPSTATUS_TIMEOUT 10000
52 #define PRIME_TIMEOUT 10000
53 #define READSAFE_TIMEOUT 1000
55 #define LOOPS_USEC_SHIFT 1
56 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
57 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
59 static DECLARE_COMPLETION(release_done
);
61 static const char driver_name
[] = "mv_udc";
62 static const char driver_desc
[] = DRIVER_DESC
;
64 static void nuke(struct mv_ep
*ep
, int status
);
65 static void stop_activity(struct mv_udc
*udc
, struct usb_gadget_driver
*driver
);
67 /* for endpoint 0 operations */
68 static const struct usb_endpoint_descriptor mv_ep0_desc
= {
69 .bLength
= USB_DT_ENDPOINT_SIZE
,
70 .bDescriptorType
= USB_DT_ENDPOINT
,
71 .bEndpointAddress
= 0,
72 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
73 .wMaxPacketSize
= EP0_MAX_PKT_SIZE
,
76 static void ep0_reset(struct mv_udc
*udc
)
83 for (i
= 0; i
< 2; i
++) {
88 ep
->dqh
= &udc
->ep_dqh
[i
];
90 /* configure ep0 endpoint capabilities in dQH */
91 ep
->dqh
->max_packet_length
=
92 (EP0_MAX_PKT_SIZE
<< EP_QUEUE_HEAD_MAX_PKT_LEN_POS
)
95 ep
->dqh
->next_dtd_ptr
= EP_QUEUE_HEAD_NEXT_TERMINATE
;
97 epctrlx
= readl(&udc
->op_regs
->epctrlx
[0]);
99 epctrlx
|= EPCTRL_TX_ENABLE
100 | (USB_ENDPOINT_XFER_CONTROL
101 << EPCTRL_TX_EP_TYPE_SHIFT
);
104 epctrlx
|= EPCTRL_RX_ENABLE
105 | (USB_ENDPOINT_XFER_CONTROL
106 << EPCTRL_RX_EP_TYPE_SHIFT
);
109 writel(epctrlx
, &udc
->op_regs
->epctrlx
[0]);
113 /* protocol ep0 stall, will automatically be cleared on new transaction */
114 static void ep0_stall(struct mv_udc
*udc
)
118 /* set TX and RX to stall */
119 epctrlx
= readl(&udc
->op_regs
->epctrlx
[0]);
120 epctrlx
|= EPCTRL_RX_EP_STALL
| EPCTRL_TX_EP_STALL
;
121 writel(epctrlx
, &udc
->op_regs
->epctrlx
[0]);
123 /* update ep0 state */
124 udc
->ep0_state
= WAIT_FOR_SETUP
;
125 udc
->ep0_dir
= EP_DIR_OUT
;
128 static int process_ep_req(struct mv_udc
*udc
, int index
,
129 struct mv_req
*curr_req
)
131 struct mv_dtd
*curr_dtd
;
132 struct mv_dqh
*curr_dqh
;
133 int td_complete
, actual
, remaining_length
;
139 curr_dqh
= &udc
->ep_dqh
[index
];
140 direction
= index
% 2;
142 curr_dtd
= curr_req
->head
;
144 actual
= curr_req
->req
.length
;
146 for (i
= 0; i
< curr_req
->dtd_count
; i
++) {
147 if (curr_dtd
->size_ioc_sts
& DTD_STATUS_ACTIVE
) {
148 dev_dbg(&udc
->dev
->dev
, "%s, dTD not completed\n",
149 udc
->eps
[index
].name
);
153 errors
= curr_dtd
->size_ioc_sts
& DTD_ERROR_MASK
;
156 (curr_dtd
->size_ioc_sts
& DTD_PACKET_SIZE
)
157 >> DTD_LENGTH_BIT_POS
;
158 actual
-= remaining_length
;
160 if (remaining_length
) {
162 dev_dbg(&udc
->dev
->dev
,
163 "TX dTD remains data\n");
170 dev_info(&udc
->dev
->dev
,
171 "complete_tr error: ep=%d %s: error = 0x%x\n",
172 index
>> 1, direction
? "SEND" : "RECV",
174 if (errors
& DTD_STATUS_HALTED
) {
175 /* Clear the errors and Halt condition */
176 curr_dqh
->size_ioc_int_sts
&= ~errors
;
178 } else if (errors
& DTD_STATUS_DATA_BUFF_ERR
) {
180 } else if (errors
& DTD_STATUS_TRANSACTION_ERR
) {
184 if (i
!= curr_req
->dtd_count
- 1)
185 curr_dtd
= (struct mv_dtd
*)curr_dtd
->next_dtd_virt
;
190 if (direction
== EP_DIR_OUT
)
191 bit_pos
= 1 << curr_req
->ep
->ep_num
;
193 bit_pos
= 1 << (16 + curr_req
->ep
->ep_num
);
195 while ((curr_dqh
->curr_dtd_ptr
== curr_dtd
->td_dma
)) {
196 if (curr_dtd
->dtd_next
== EP_QUEUE_HEAD_NEXT_TERMINATE
) {
197 while (readl(&udc
->op_regs
->epstatus
) & bit_pos
)
204 curr_req
->req
.actual
= actual
;
210 * done() - retire a request; caller blocked irqs
211 * @status : request status to be set, only works when
212 * request is still in progress.
214 static void done(struct mv_ep
*ep
, struct mv_req
*req
, int status
)
215 __releases(&ep
->udc
->lock
)
216 __acquires(&ep
->udc
->lock
)
218 struct mv_udc
*udc
= NULL
;
219 unsigned char stopped
= ep
->stopped
;
220 struct mv_dtd
*curr_td
, *next_td
;
223 udc
= (struct mv_udc
*)ep
->udc
;
224 /* Removed the req from fsl_ep->queue */
225 list_del_init(&req
->queue
);
227 /* req.status should be set as -EINPROGRESS in ep_queue() */
228 if (req
->req
.status
== -EINPROGRESS
)
229 req
->req
.status
= status
;
231 status
= req
->req
.status
;
233 /* Free dtd for the request */
235 for (j
= 0; j
< req
->dtd_count
; j
++) {
237 if (j
!= req
->dtd_count
- 1)
238 next_td
= curr_td
->next_dtd_virt
;
239 dma_pool_free(udc
->dtd_pool
, curr_td
, curr_td
->td_dma
);
242 usb_gadget_unmap_request(&udc
->gadget
, &req
->req
, ep_dir(ep
));
244 if (status
&& (status
!= -ESHUTDOWN
))
245 dev_info(&udc
->dev
->dev
, "complete %s req %p stat %d len %u/%u",
246 ep
->ep
.name
, &req
->req
, status
,
247 req
->req
.actual
, req
->req
.length
);
251 spin_unlock(&ep
->udc
->lock
);
253 * complete() is from gadget layer,
254 * eg fsg->bulk_in_complete()
256 if (req
->req
.complete
)
257 req
->req
.complete(&ep
->ep
, &req
->req
);
259 spin_lock(&ep
->udc
->lock
);
260 ep
->stopped
= stopped
;
263 static int queue_dtd(struct mv_ep
*ep
, struct mv_req
*req
)
267 u32 bit_pos
, direction
;
268 u32 usbcmd
, epstatus
;
273 direction
= ep_dir(ep
);
274 dqh
= &(udc
->ep_dqh
[ep
->ep_num
* 2 + direction
]);
275 bit_pos
= 1 << (((direction
== EP_DIR_OUT
) ? 0 : 16) + ep
->ep_num
);
277 /* check if the pipe is empty */
278 if (!(list_empty(&ep
->queue
))) {
279 struct mv_req
*lastreq
;
280 lastreq
= list_entry(ep
->queue
.prev
, struct mv_req
, queue
);
281 lastreq
->tail
->dtd_next
=
282 req
->head
->td_dma
& EP_QUEUE_HEAD_NEXT_POINTER_MASK
;
286 if (readl(&udc
->op_regs
->epprime
) & bit_pos
)
289 loops
= LOOPS(READSAFE_TIMEOUT
);
291 /* start with setting the semaphores */
292 usbcmd
= readl(&udc
->op_regs
->usbcmd
);
293 usbcmd
|= USBCMD_ATDTW_TRIPWIRE_SET
;
294 writel(usbcmd
, &udc
->op_regs
->usbcmd
);
296 /* read the endpoint status */
297 epstatus
= readl(&udc
->op_regs
->epstatus
) & bit_pos
;
300 * Reread the ATDTW semaphore bit to check if it is
301 * cleared. When hardware see a hazard, it will clear
302 * the bit or else we remain set to 1 and we can
303 * proceed with priming of endpoint if not already
306 if (readl(&udc
->op_regs
->usbcmd
)
307 & USBCMD_ATDTW_TRIPWIRE_SET
)
312 dev_err(&udc
->dev
->dev
,
313 "Timeout for ATDTW_TRIPWIRE...\n");
320 /* Clear the semaphore */
321 usbcmd
= readl(&udc
->op_regs
->usbcmd
);
322 usbcmd
&= USBCMD_ATDTW_TRIPWIRE_CLEAR
;
323 writel(usbcmd
, &udc
->op_regs
->usbcmd
);
329 /* Write dQH next pointer and terminate bit to 0 */
330 dqh
->next_dtd_ptr
= req
->head
->td_dma
331 & EP_QUEUE_HEAD_NEXT_POINTER_MASK
;
333 /* clear active and halt bit, in case set from a previous error */
334 dqh
->size_ioc_int_sts
&= ~(DTD_STATUS_ACTIVE
| DTD_STATUS_HALTED
);
336 /* Ensure that updates to the QH will occure before priming. */
339 /* Prime the Endpoint */
340 writel(bit_pos
, &udc
->op_regs
->epprime
);
346 static struct mv_dtd
*build_dtd(struct mv_req
*req
, unsigned *length
,
347 dma_addr_t
*dma
, int *is_last
)
354 /* how big will this transfer be? */
355 if (usb_endpoint_xfer_isoc(req
->ep
->ep
.desc
)) {
357 mult
= (dqh
->max_packet_length
>> EP_QUEUE_HEAD_MULT_POS
)
359 *length
= min(req
->req
.length
- req
->req
.actual
,
360 (unsigned)(mult
* req
->ep
->ep
.maxpacket
));
362 *length
= min(req
->req
.length
- req
->req
.actual
,
363 (unsigned)EP_MAX_LENGTH_TRANSFER
);
368 * Be careful that no _GFP_HIGHMEM is set,
369 * or we can not use dma_to_virt
371 dtd
= dma_pool_alloc(udc
->dtd_pool
, GFP_ATOMIC
, dma
);
376 /* initialize buffer page pointers */
377 temp
= (u32
)(req
->req
.dma
+ req
->req
.actual
);
378 dtd
->buff_ptr0
= cpu_to_le32(temp
);
380 dtd
->buff_ptr1
= cpu_to_le32(temp
+ 0x1000);
381 dtd
->buff_ptr2
= cpu_to_le32(temp
+ 0x2000);
382 dtd
->buff_ptr3
= cpu_to_le32(temp
+ 0x3000);
383 dtd
->buff_ptr4
= cpu_to_le32(temp
+ 0x4000);
385 req
->req
.actual
+= *length
;
387 /* zlp is needed if req->req.zero is set */
389 if (*length
== 0 || (*length
% req
->ep
->ep
.maxpacket
) != 0)
393 } else if (req
->req
.length
== req
->req
.actual
)
398 /* Fill in the transfer size; set active bit */
399 temp
= ((*length
<< DTD_LENGTH_BIT_POS
) | DTD_STATUS_ACTIVE
);
401 /* Enable interrupt for the last dtd of a request */
402 if (*is_last
&& !req
->req
.no_interrupt
)
407 dtd
->size_ioc_sts
= temp
;
414 /* generate dTD linked list for a request */
415 static int req_to_dtd(struct mv_req
*req
)
418 int is_last
, is_first
= 1;
419 struct mv_dtd
*dtd
, *last_dtd
= NULL
;
426 dtd
= build_dtd(req
, &count
, &dma
, &is_last
);
434 last_dtd
->dtd_next
= dma
;
435 last_dtd
->next_dtd_virt
= dtd
;
441 /* set terminate bit to 1 for the last dTD */
442 dtd
->dtd_next
= DTD_NEXT_TERMINATE
;
449 static int mv_ep_enable(struct usb_ep
*_ep
,
450 const struct usb_endpoint_descriptor
*desc
)
456 u32 bit_pos
, epctrlx
, direction
;
457 unsigned char zlt
= 0, ios
= 0, mult
= 0;
460 ep
= container_of(_ep
, struct mv_ep
, ep
);
464 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
)
467 if (!udc
->driver
|| udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)
470 direction
= ep_dir(ep
);
471 max
= usb_endpoint_maxp(desc
);
474 * disable HW zero length termination select
475 * driver handles zero length packet through req->req.zero
479 bit_pos
= 1 << ((direction
== EP_DIR_OUT
? 0 : 16) + ep
->ep_num
);
481 /* Check if the Endpoint is Primed */
482 if ((readl(&udc
->op_regs
->epprime
) & bit_pos
)
483 || (readl(&udc
->op_regs
->epstatus
) & bit_pos
)) {
484 dev_info(&udc
->dev
->dev
,
485 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
486 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
487 (unsigned)ep
->ep_num
, direction
? "SEND" : "RECV",
488 (unsigned)readl(&udc
->op_regs
->epprime
),
489 (unsigned)readl(&udc
->op_regs
->epstatus
),
493 /* Set the max packet length, interrupt on Setup and Mult fields */
494 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
495 case USB_ENDPOINT_XFER_BULK
:
499 case USB_ENDPOINT_XFER_CONTROL
:
501 case USB_ENDPOINT_XFER_INT
:
504 case USB_ENDPOINT_XFER_ISOC
:
505 /* Calculate transactions needed for high bandwidth iso */
506 mult
= (unsigned char)(1 + ((max
>> 11) & 0x03));
507 max
= max
& 0x7ff; /* bit 0~10 */
508 /* 3 transactions at most */
516 spin_lock_irqsave(&udc
->lock
, flags
);
517 /* Get the endpoint queue head address */
519 dqh
->max_packet_length
= (max
<< EP_QUEUE_HEAD_MAX_PKT_LEN_POS
)
520 | (mult
<< EP_QUEUE_HEAD_MULT_POS
)
521 | (zlt
? EP_QUEUE_HEAD_ZLT_SEL
: 0)
522 | (ios
? EP_QUEUE_HEAD_IOS
: 0);
523 dqh
->next_dtd_ptr
= 1;
524 dqh
->size_ioc_int_sts
= 0;
526 ep
->ep
.maxpacket
= max
;
530 /* Enable the endpoint for Rx or Tx and set the endpoint type */
531 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
532 if (direction
== EP_DIR_IN
) {
533 epctrlx
&= ~EPCTRL_TX_ALL_MASK
;
534 epctrlx
|= EPCTRL_TX_ENABLE
| EPCTRL_TX_DATA_TOGGLE_RST
535 | ((desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
)
536 << EPCTRL_TX_EP_TYPE_SHIFT
);
538 epctrlx
&= ~EPCTRL_RX_ALL_MASK
;
539 epctrlx
|= EPCTRL_RX_ENABLE
| EPCTRL_RX_DATA_TOGGLE_RST
540 | ((desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
)
541 << EPCTRL_RX_EP_TYPE_SHIFT
);
543 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
546 * Implement Guideline (GL# USB-7) The unused endpoint type must
547 * be programmed to bulk.
549 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
550 if ((epctrlx
& EPCTRL_RX_ENABLE
) == 0) {
551 epctrlx
|= (USB_ENDPOINT_XFER_BULK
552 << EPCTRL_RX_EP_TYPE_SHIFT
);
553 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
556 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
557 if ((epctrlx
& EPCTRL_TX_ENABLE
) == 0) {
558 epctrlx
|= (USB_ENDPOINT_XFER_BULK
559 << EPCTRL_TX_EP_TYPE_SHIFT
);
560 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
563 spin_unlock_irqrestore(&udc
->lock
, flags
);
570 static int mv_ep_disable(struct usb_ep
*_ep
)
575 u32 bit_pos
, epctrlx
, direction
;
578 ep
= container_of(_ep
, struct mv_ep
, ep
);
579 if ((_ep
== NULL
) || !ep
->ep
.desc
)
584 /* Get the endpoint queue head address */
587 spin_lock_irqsave(&udc
->lock
, flags
);
589 direction
= ep_dir(ep
);
590 bit_pos
= 1 << ((direction
== EP_DIR_OUT
? 0 : 16) + ep
->ep_num
);
592 /* Reset the max packet length and the interrupt on Setup */
593 dqh
->max_packet_length
= 0;
595 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
596 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
597 epctrlx
&= ~((direction
== EP_DIR_IN
)
598 ? (EPCTRL_TX_ENABLE
| EPCTRL_TX_TYPE
)
599 : (EPCTRL_RX_ENABLE
| EPCTRL_RX_TYPE
));
600 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
602 /* nuke all pending requests (does flush) */
603 nuke(ep
, -ESHUTDOWN
);
608 spin_unlock_irqrestore(&udc
->lock
, flags
);
613 static struct usb_request
*
614 mv_alloc_request(struct usb_ep
*_ep
, gfp_t gfp_flags
)
616 struct mv_req
*req
= NULL
;
618 req
= kzalloc(sizeof *req
, gfp_flags
);
622 req
->req
.dma
= DMA_ADDR_INVALID
;
623 INIT_LIST_HEAD(&req
->queue
);
628 static void mv_free_request(struct usb_ep
*_ep
, struct usb_request
*_req
)
630 struct mv_req
*req
= NULL
;
632 req
= container_of(_req
, struct mv_req
, req
);
638 static void mv_ep_fifo_flush(struct usb_ep
*_ep
)
641 u32 bit_pos
, direction
;
648 ep
= container_of(_ep
, struct mv_ep
, ep
);
653 direction
= ep_dir(ep
);
656 bit_pos
= (1 << 16) | 1;
657 else if (direction
== EP_DIR_OUT
)
658 bit_pos
= 1 << ep
->ep_num
;
660 bit_pos
= 1 << (16 + ep
->ep_num
);
662 loops
= LOOPS(EPSTATUS_TIMEOUT
);
664 unsigned int inter_loops
;
667 dev_err(&udc
->dev
->dev
,
668 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
669 (unsigned)readl(&udc
->op_regs
->epstatus
),
673 /* Write 1 to the Flush register */
674 writel(bit_pos
, &udc
->op_regs
->epflush
);
676 /* Wait until flushing completed */
677 inter_loops
= LOOPS(FLUSH_TIMEOUT
);
678 while (readl(&udc
->op_regs
->epflush
)) {
680 * ENDPTFLUSH bit should be cleared to indicate this
681 * operation is complete
683 if (inter_loops
== 0) {
684 dev_err(&udc
->dev
->dev
,
685 "TIMEOUT for ENDPTFLUSH=0x%x,"
687 (unsigned)readl(&udc
->op_regs
->epflush
),
695 } while (readl(&udc
->op_regs
->epstatus
) & bit_pos
);
698 /* queues (submits) an I/O request to an endpoint */
700 mv_ep_queue(struct usb_ep
*_ep
, struct usb_request
*_req
, gfp_t gfp_flags
)
702 struct mv_ep
*ep
= container_of(_ep
, struct mv_ep
, ep
);
703 struct mv_req
*req
= container_of(_req
, struct mv_req
, req
);
704 struct mv_udc
*udc
= ep
->udc
;
708 /* catch various bogus parameters */
709 if (!_req
|| !req
->req
.complete
|| !req
->req
.buf
710 || !list_empty(&req
->queue
)) {
711 dev_err(&udc
->dev
->dev
, "%s, bad params", __func__
);
714 if (unlikely(!_ep
|| !ep
->ep
.desc
)) {
715 dev_err(&udc
->dev
->dev
, "%s, bad ep", __func__
);
720 if (!udc
->driver
|| udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)
725 /* map virtual address to hardware */
726 retval
= usb_gadget_map_request(&udc
->gadget
, _req
, ep_dir(ep
));
730 req
->req
.status
= -EINPROGRESS
;
734 spin_lock_irqsave(&udc
->lock
, flags
);
736 /* build dtds and push them to device queue */
737 if (!req_to_dtd(req
)) {
738 retval
= queue_dtd(ep
, req
);
740 spin_unlock_irqrestore(&udc
->lock
, flags
);
741 dev_err(&udc
->dev
->dev
, "Failed to queue dtd\n");
745 spin_unlock_irqrestore(&udc
->lock
, flags
);
746 dev_err(&udc
->dev
->dev
, "Failed to dma_pool_alloc\n");
751 /* Update ep0 state */
753 udc
->ep0_state
= DATA_STATE_XMIT
;
755 /* irq handler advances the queue */
756 list_add_tail(&req
->queue
, &ep
->queue
);
757 spin_unlock_irqrestore(&udc
->lock
, flags
);
762 usb_gadget_unmap_request(&udc
->gadget
, _req
, ep_dir(ep
));
767 static void mv_prime_ep(struct mv_ep
*ep
, struct mv_req
*req
)
769 struct mv_dqh
*dqh
= ep
->dqh
;
772 /* Write dQH next pointer and terminate bit to 0 */
773 dqh
->next_dtd_ptr
= req
->head
->td_dma
774 & EP_QUEUE_HEAD_NEXT_POINTER_MASK
;
776 /* clear active and halt bit, in case set from a previous error */
777 dqh
->size_ioc_int_sts
&= ~(DTD_STATUS_ACTIVE
| DTD_STATUS_HALTED
);
779 /* Ensure that updates to the QH will occure before priming. */
782 bit_pos
= 1 << (((ep_dir(ep
) == EP_DIR_OUT
) ? 0 : 16) + ep
->ep_num
);
784 /* Prime the Endpoint */
785 writel(bit_pos
, &ep
->udc
->op_regs
->epprime
);
788 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
789 static int mv_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
791 struct mv_ep
*ep
= container_of(_ep
, struct mv_ep
, ep
);
793 struct mv_udc
*udc
= ep
->udc
;
795 int stopped
, ret
= 0;
801 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
802 stopped
= ep
->stopped
;
804 /* Stop the ep before we deal with the queue */
806 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
807 if (ep_dir(ep
) == EP_DIR_IN
)
808 epctrlx
&= ~EPCTRL_TX_ENABLE
;
810 epctrlx
&= ~EPCTRL_RX_ENABLE
;
811 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
813 /* make sure it's actually queued on this endpoint */
814 list_for_each_entry(req
, &ep
->queue
, queue
) {
815 if (&req
->req
== _req
)
818 if (&req
->req
!= _req
) {
823 /* The request is in progress, or completed but not dequeued */
824 if (ep
->queue
.next
== &req
->queue
) {
825 _req
->status
= -ECONNRESET
;
826 mv_ep_fifo_flush(_ep
); /* flush current transfer */
828 /* The request isn't the last request in this ep queue */
829 if (req
->queue
.next
!= &ep
->queue
) {
830 struct mv_req
*next_req
;
832 next_req
= list_entry(req
->queue
.next
,
833 struct mv_req
, queue
);
835 /* Point the QH to the first TD of next request */
836 mv_prime_ep(ep
, next_req
);
841 qh
->next_dtd_ptr
= 1;
842 qh
->size_ioc_int_sts
= 0;
845 /* The request hasn't been processed, patch up the TD chain */
847 struct mv_req
*prev_req
;
849 prev_req
= list_entry(req
->queue
.prev
, struct mv_req
, queue
);
850 writel(readl(&req
->tail
->dtd_next
),
851 &prev_req
->tail
->dtd_next
);
855 done(ep
, req
, -ECONNRESET
);
859 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
860 if (ep_dir(ep
) == EP_DIR_IN
)
861 epctrlx
|= EPCTRL_TX_ENABLE
;
863 epctrlx
|= EPCTRL_RX_ENABLE
;
864 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
865 ep
->stopped
= stopped
;
867 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
871 static void ep_set_stall(struct mv_udc
*udc
, u8 ep_num
, u8 direction
, int stall
)
875 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep_num
]);
878 if (direction
== EP_DIR_IN
)
879 epctrlx
|= EPCTRL_TX_EP_STALL
;
881 epctrlx
|= EPCTRL_RX_EP_STALL
;
883 if (direction
== EP_DIR_IN
) {
884 epctrlx
&= ~EPCTRL_TX_EP_STALL
;
885 epctrlx
|= EPCTRL_TX_DATA_TOGGLE_RST
;
887 epctrlx
&= ~EPCTRL_RX_EP_STALL
;
888 epctrlx
|= EPCTRL_RX_DATA_TOGGLE_RST
;
891 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep_num
]);
894 static int ep_is_stall(struct mv_udc
*udc
, u8 ep_num
, u8 direction
)
898 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep_num
]);
900 if (direction
== EP_DIR_OUT
)
901 return (epctrlx
& EPCTRL_RX_EP_STALL
) ? 1 : 0;
903 return (epctrlx
& EPCTRL_TX_EP_STALL
) ? 1 : 0;
906 static int mv_ep_set_halt_wedge(struct usb_ep
*_ep
, int halt
, int wedge
)
909 unsigned long flags
= 0;
913 ep
= container_of(_ep
, struct mv_ep
, ep
);
915 if (!_ep
|| !ep
->ep
.desc
) {
920 if (ep
->ep
.desc
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
921 status
= -EOPNOTSUPP
;
926 * Attempt to halt IN ep will fail if any transfer requests
929 if (halt
&& (ep_dir(ep
) == EP_DIR_IN
) && !list_empty(&ep
->queue
)) {
934 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
935 ep_set_stall(udc
, ep
->ep_num
, ep_dir(ep
), halt
);
940 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
942 if (ep
->ep_num
== 0) {
943 udc
->ep0_state
= WAIT_FOR_SETUP
;
944 udc
->ep0_dir
= EP_DIR_OUT
;
950 static int mv_ep_set_halt(struct usb_ep
*_ep
, int halt
)
952 return mv_ep_set_halt_wedge(_ep
, halt
, 0);
955 static int mv_ep_set_wedge(struct usb_ep
*_ep
)
957 return mv_ep_set_halt_wedge(_ep
, 1, 1);
960 static struct usb_ep_ops mv_ep_ops
= {
961 .enable
= mv_ep_enable
,
962 .disable
= mv_ep_disable
,
964 .alloc_request
= mv_alloc_request
,
965 .free_request
= mv_free_request
,
967 .queue
= mv_ep_queue
,
968 .dequeue
= mv_ep_dequeue
,
970 .set_wedge
= mv_ep_set_wedge
,
971 .set_halt
= mv_ep_set_halt
,
972 .fifo_flush
= mv_ep_fifo_flush
, /* flush fifo */
975 static void udc_clock_enable(struct mv_udc
*udc
)
977 clk_prepare_enable(udc
->clk
);
980 static void udc_clock_disable(struct mv_udc
*udc
)
982 clk_disable_unprepare(udc
->clk
);
985 static void udc_stop(struct mv_udc
*udc
)
989 /* Disable interrupts */
990 tmp
= readl(&udc
->op_regs
->usbintr
);
991 tmp
&= ~(USBINTR_INT_EN
| USBINTR_ERR_INT_EN
|
992 USBINTR_PORT_CHANGE_DETECT_EN
| USBINTR_RESET_EN
);
993 writel(tmp
, &udc
->op_regs
->usbintr
);
997 /* Reset the Run the bit in the command register to stop VUSB */
998 tmp
= readl(&udc
->op_regs
->usbcmd
);
999 tmp
&= ~USBCMD_RUN_STOP
;
1000 writel(tmp
, &udc
->op_regs
->usbcmd
);
1003 static void udc_start(struct mv_udc
*udc
)
1007 usbintr
= USBINTR_INT_EN
| USBINTR_ERR_INT_EN
1008 | USBINTR_PORT_CHANGE_DETECT_EN
1009 | USBINTR_RESET_EN
| USBINTR_DEVICE_SUSPEND
;
1010 /* Enable interrupts */
1011 writel(usbintr
, &udc
->op_regs
->usbintr
);
1015 /* Set the Run bit in the command register */
1016 writel(USBCMD_RUN_STOP
, &udc
->op_regs
->usbcmd
);
1019 static int udc_reset(struct mv_udc
*udc
)
1024 /* Stop the controller */
1025 tmp
= readl(&udc
->op_regs
->usbcmd
);
1026 tmp
&= ~USBCMD_RUN_STOP
;
1027 writel(tmp
, &udc
->op_regs
->usbcmd
);
1029 /* Reset the controller to get default values */
1030 writel(USBCMD_CTRL_RESET
, &udc
->op_regs
->usbcmd
);
1032 /* wait for reset to complete */
1033 loops
= LOOPS(RESET_TIMEOUT
);
1034 while (readl(&udc
->op_regs
->usbcmd
) & USBCMD_CTRL_RESET
) {
1036 dev_err(&udc
->dev
->dev
,
1037 "Wait for RESET completed TIMEOUT\n");
1044 /* set controller to device mode */
1045 tmp
= readl(&udc
->op_regs
->usbmode
);
1046 tmp
|= USBMODE_CTRL_MODE_DEVICE
;
1048 /* turn setup lockout off, require setup tripwire in usbcmd */
1049 tmp
|= USBMODE_SETUP_LOCK_OFF
;
1051 writel(tmp
, &udc
->op_regs
->usbmode
);
1053 writel(0x0, &udc
->op_regs
->epsetupstat
);
1055 /* Configure the Endpoint List Address */
1056 writel(udc
->ep_dqh_dma
& USB_EP_LIST_ADDRESS_MASK
,
1057 &udc
->op_regs
->eplistaddr
);
1059 portsc
= readl(&udc
->op_regs
->portsc
[0]);
1060 if (readl(&udc
->cap_regs
->hcsparams
) & HCSPARAMS_PPC
)
1061 portsc
&= (~PORTSCX_W1C_BITS
| ~PORTSCX_PORT_POWER
);
1064 portsc
|= PORTSCX_FORCE_FULL_SPEED_CONNECT
;
1066 portsc
&= (~PORTSCX_FORCE_FULL_SPEED_CONNECT
);
1068 writel(portsc
, &udc
->op_regs
->portsc
[0]);
1070 tmp
= readl(&udc
->op_regs
->epctrlx
[0]);
1071 tmp
&= ~(EPCTRL_TX_EP_STALL
| EPCTRL_RX_EP_STALL
);
1072 writel(tmp
, &udc
->op_regs
->epctrlx
[0]);
1077 static int mv_udc_enable_internal(struct mv_udc
*udc
)
1084 dev_dbg(&udc
->dev
->dev
, "enable udc\n");
1085 udc_clock_enable(udc
);
1086 if (udc
->pdata
->phy_init
) {
1087 retval
= udc
->pdata
->phy_init(udc
->phy_regs
);
1089 dev_err(&udc
->dev
->dev
,
1090 "init phy error %d\n", retval
);
1091 udc_clock_disable(udc
);
1100 static int mv_udc_enable(struct mv_udc
*udc
)
1102 if (udc
->clock_gating
)
1103 return mv_udc_enable_internal(udc
);
1108 static void mv_udc_disable_internal(struct mv_udc
*udc
)
1111 dev_dbg(&udc
->dev
->dev
, "disable udc\n");
1112 if (udc
->pdata
->phy_deinit
)
1113 udc
->pdata
->phy_deinit(udc
->phy_regs
);
1114 udc_clock_disable(udc
);
1119 static void mv_udc_disable(struct mv_udc
*udc
)
1121 if (udc
->clock_gating
)
1122 mv_udc_disable_internal(udc
);
1125 static int mv_udc_get_frame(struct usb_gadget
*gadget
)
1133 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1135 retval
= readl(&udc
->op_regs
->frindex
) & USB_FRINDEX_MASKS
;
1140 /* Tries to wake up the host connected to this gadget */
1141 static int mv_udc_wakeup(struct usb_gadget
*gadget
)
1143 struct mv_udc
*udc
= container_of(gadget
, struct mv_udc
, gadget
);
1146 /* Remote wakeup feature not enabled by host */
1147 if (!udc
->remote_wakeup
)
1150 portsc
= readl(&udc
->op_regs
->portsc
);
1151 /* not suspended? */
1152 if (!(portsc
& PORTSCX_PORT_SUSPEND
))
1154 /* trigger force resume */
1155 portsc
|= PORTSCX_PORT_FORCE_RESUME
;
1156 writel(portsc
, &udc
->op_regs
->portsc
[0]);
1160 static int mv_udc_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1163 unsigned long flags
;
1166 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1167 spin_lock_irqsave(&udc
->lock
, flags
);
1169 udc
->vbus_active
= (is_active
!= 0);
1171 dev_dbg(&udc
->dev
->dev
, "%s: softconnect %d, vbus_active %d\n",
1172 __func__
, udc
->softconnect
, udc
->vbus_active
);
1174 if (udc
->driver
&& udc
->softconnect
&& udc
->vbus_active
) {
1175 retval
= mv_udc_enable(udc
);
1177 /* Clock is disabled, need re-init registers */
1182 } else if (udc
->driver
&& udc
->softconnect
) {
1186 /* stop all the transfer in queue*/
1187 stop_activity(udc
, udc
->driver
);
1189 mv_udc_disable(udc
);
1193 spin_unlock_irqrestore(&udc
->lock
, flags
);
1197 static int mv_udc_pullup(struct usb_gadget
*gadget
, int is_on
)
1200 unsigned long flags
;
1203 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1204 spin_lock_irqsave(&udc
->lock
, flags
);
1206 udc
->softconnect
= (is_on
!= 0);
1208 dev_dbg(&udc
->dev
->dev
, "%s: softconnect %d, vbus_active %d\n",
1209 __func__
, udc
->softconnect
, udc
->vbus_active
);
1211 if (udc
->driver
&& udc
->softconnect
&& udc
->vbus_active
) {
1212 retval
= mv_udc_enable(udc
);
1214 /* Clock is disabled, need re-init registers */
1219 } else if (udc
->driver
&& udc
->vbus_active
) {
1220 /* stop all the transfer in queue*/
1221 stop_activity(udc
, udc
->driver
);
1223 mv_udc_disable(udc
);
1226 spin_unlock_irqrestore(&udc
->lock
, flags
);
1230 static int mv_udc_start(struct usb_gadget
*, struct usb_gadget_driver
*);
1231 static int mv_udc_stop(struct usb_gadget
*, struct usb_gadget_driver
*);
1232 /* device controller usb_gadget_ops structure */
1233 static const struct usb_gadget_ops mv_ops
= {
1235 /* returns the current frame number */
1236 .get_frame
= mv_udc_get_frame
,
1238 /* tries to wake up the host connected to this gadget */
1239 .wakeup
= mv_udc_wakeup
,
1241 /* notify controller that VBUS is powered or not */
1242 .vbus_session
= mv_udc_vbus_session
,
1244 /* D+ pullup, software-controlled connect/disconnect to USB host */
1245 .pullup
= mv_udc_pullup
,
1246 .udc_start
= mv_udc_start
,
1247 .udc_stop
= mv_udc_stop
,
1250 static int eps_init(struct mv_udc
*udc
)
1256 /* initialize ep0 */
1259 strncpy(ep
->name
, "ep0", sizeof(ep
->name
));
1260 ep
->ep
.name
= ep
->name
;
1261 ep
->ep
.ops
= &mv_ep_ops
;
1264 ep
->ep
.maxpacket
= EP0_MAX_PKT_SIZE
;
1266 ep
->ep
.desc
= &mv_ep0_desc
;
1267 INIT_LIST_HEAD(&ep
->queue
);
1269 ep
->ep_type
= USB_ENDPOINT_XFER_CONTROL
;
1271 /* initialize other endpoints */
1272 for (i
= 2; i
< udc
->max_eps
* 2; i
++) {
1275 snprintf(name
, sizeof(name
), "ep%din", i
/ 2);
1276 ep
->direction
= EP_DIR_IN
;
1278 snprintf(name
, sizeof(name
), "ep%dout", i
/ 2);
1279 ep
->direction
= EP_DIR_OUT
;
1282 strncpy(ep
->name
, name
, sizeof(ep
->name
));
1283 ep
->ep
.name
= ep
->name
;
1285 ep
->ep
.ops
= &mv_ep_ops
;
1287 ep
->ep
.maxpacket
= (unsigned short) ~0;
1290 INIT_LIST_HEAD(&ep
->queue
);
1291 list_add_tail(&ep
->ep
.ep_list
, &udc
->gadget
.ep_list
);
1293 ep
->dqh
= &udc
->ep_dqh
[i
];
1299 /* delete all endpoint requests, called with spinlock held */
1300 static void nuke(struct mv_ep
*ep
, int status
)
1302 /* called with spinlock held */
1305 /* endpoint fifo flush */
1306 mv_ep_fifo_flush(&ep
->ep
);
1308 while (!list_empty(&ep
->queue
)) {
1309 struct mv_req
*req
= NULL
;
1310 req
= list_entry(ep
->queue
.next
, struct mv_req
, queue
);
1311 done(ep
, req
, status
);
1315 /* stop all USB activities */
1316 static void stop_activity(struct mv_udc
*udc
, struct usb_gadget_driver
*driver
)
1320 nuke(&udc
->eps
[0], -ESHUTDOWN
);
1322 list_for_each_entry(ep
, &udc
->gadget
.ep_list
, ep
.ep_list
) {
1323 nuke(ep
, -ESHUTDOWN
);
1326 /* report disconnect; the driver is already quiesced */
1328 spin_unlock(&udc
->lock
);
1329 driver
->disconnect(&udc
->gadget
);
1330 spin_lock(&udc
->lock
);
1334 static int mv_udc_start(struct usb_gadget
*gadget
,
1335 struct usb_gadget_driver
*driver
)
1339 unsigned long flags
;
1341 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1346 spin_lock_irqsave(&udc
->lock
, flags
);
1348 /* hook up the driver ... */
1349 driver
->driver
.bus
= NULL
;
1350 udc
->driver
= driver
;
1352 udc
->usb_state
= USB_STATE_ATTACHED
;
1353 udc
->ep0_state
= WAIT_FOR_SETUP
;
1354 udc
->ep0_dir
= EP_DIR_OUT
;
1356 spin_unlock_irqrestore(&udc
->lock
, flags
);
1358 if (udc
->transceiver
) {
1359 retval
= otg_set_peripheral(udc
->transceiver
->otg
,
1362 dev_err(&udc
->dev
->dev
,
1363 "unable to register peripheral to otg\n");
1369 /* pullup is always on */
1370 mv_udc_pullup(&udc
->gadget
, 1);
1372 /* When boot with cable attached, there will be no vbus irq occurred */
1374 queue_work(udc
->qwork
, &udc
->vbus_work
);
1379 static int mv_udc_stop(struct usb_gadget
*gadget
,
1380 struct usb_gadget_driver
*driver
)
1383 unsigned long flags
;
1385 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1387 spin_lock_irqsave(&udc
->lock
, flags
);
1392 /* stop all usb activities */
1393 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1394 stop_activity(udc
, driver
);
1395 mv_udc_disable(udc
);
1397 spin_unlock_irqrestore(&udc
->lock
, flags
);
1399 /* unbind gadget driver */
1405 static void mv_set_ptc(struct mv_udc
*udc
, u32 mode
)
1409 portsc
= readl(&udc
->op_regs
->portsc
[0]);
1410 portsc
|= mode
<< 16;
1411 writel(portsc
, &udc
->op_regs
->portsc
[0]);
1414 static void prime_status_complete(struct usb_ep
*ep
, struct usb_request
*_req
)
1416 struct mv_ep
*mvep
= container_of(ep
, struct mv_ep
, ep
);
1417 struct mv_req
*req
= container_of(_req
, struct mv_req
, req
);
1419 unsigned long flags
;
1423 dev_info(&udc
->dev
->dev
, "switch to test mode %d\n", req
->test_mode
);
1425 spin_lock_irqsave(&udc
->lock
, flags
);
1426 if (req
->test_mode
) {
1427 mv_set_ptc(udc
, req
->test_mode
);
1430 spin_unlock_irqrestore(&udc
->lock
, flags
);
1434 udc_prime_status(struct mv_udc
*udc
, u8 direction
, u16 status
, bool empty
)
1441 udc
->ep0_dir
= direction
;
1442 udc
->ep0_state
= WAIT_FOR_OUT_STATUS
;
1444 req
= udc
->status_req
;
1446 /* fill in the reqest structure */
1447 if (empty
== false) {
1448 *((u16
*) req
->req
.buf
) = cpu_to_le16(status
);
1449 req
->req
.length
= 2;
1451 req
->req
.length
= 0;
1454 req
->req
.status
= -EINPROGRESS
;
1455 req
->req
.actual
= 0;
1456 if (udc
->test_mode
) {
1457 req
->req
.complete
= prime_status_complete
;
1458 req
->test_mode
= udc
->test_mode
;
1461 req
->req
.complete
= NULL
;
1464 if (req
->req
.dma
== DMA_ADDR_INVALID
) {
1465 req
->req
.dma
= dma_map_single(ep
->udc
->gadget
.dev
.parent
,
1466 req
->req
.buf
, req
->req
.length
,
1467 ep_dir(ep
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1471 /* prime the data phase */
1472 if (!req_to_dtd(req
)) {
1473 retval
= queue_dtd(ep
, req
);
1475 dev_err(&udc
->dev
->dev
,
1476 "Failed to queue dtd when prime status\n");
1479 } else{ /* no mem */
1481 dev_err(&udc
->dev
->dev
,
1482 "Failed to dma_pool_alloc when prime status\n");
1486 list_add_tail(&req
->queue
, &ep
->queue
);
1490 usb_gadget_unmap_request(&udc
->gadget
, &req
->req
, ep_dir(ep
));
1495 static void mv_udc_testmode(struct mv_udc
*udc
, u16 index
)
1497 if (index
<= TEST_FORCE_EN
) {
1498 udc
->test_mode
= index
;
1499 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1502 dev_err(&udc
->dev
->dev
,
1503 "This test mode(%d) is not supported\n", index
);
1506 static void ch9setaddress(struct mv_udc
*udc
, struct usb_ctrlrequest
*setup
)
1508 udc
->dev_addr
= (u8
)setup
->wValue
;
1510 /* update usb state */
1511 udc
->usb_state
= USB_STATE_ADDRESS
;
1513 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1517 static void ch9getstatus(struct mv_udc
*udc
, u8 ep_num
,
1518 struct usb_ctrlrequest
*setup
)
1523 if ((setup
->bRequestType
& (USB_DIR_IN
| USB_TYPE_MASK
))
1524 != (USB_DIR_IN
| USB_TYPE_STANDARD
))
1527 if ((setup
->bRequestType
& USB_RECIP_MASK
) == USB_RECIP_DEVICE
) {
1528 status
= 1 << USB_DEVICE_SELF_POWERED
;
1529 status
|= udc
->remote_wakeup
<< USB_DEVICE_REMOTE_WAKEUP
;
1530 } else if ((setup
->bRequestType
& USB_RECIP_MASK
)
1531 == USB_RECIP_INTERFACE
) {
1532 /* get interface status */
1534 } else if ((setup
->bRequestType
& USB_RECIP_MASK
)
1535 == USB_RECIP_ENDPOINT
) {
1536 u8 ep_num
, direction
;
1538 ep_num
= setup
->wIndex
& USB_ENDPOINT_NUMBER_MASK
;
1539 direction
= (setup
->wIndex
& USB_ENDPOINT_DIR_MASK
)
1540 ? EP_DIR_IN
: EP_DIR_OUT
;
1541 status
= ep_is_stall(udc
, ep_num
, direction
)
1542 << USB_ENDPOINT_HALT
;
1545 retval
= udc_prime_status(udc
, EP_DIR_IN
, status
, false);
1549 udc
->ep0_state
= DATA_STATE_XMIT
;
1552 static void ch9clearfeature(struct mv_udc
*udc
, struct usb_ctrlrequest
*setup
)
1558 if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1559 == ((USB_TYPE_STANDARD
| USB_RECIP_DEVICE
))) {
1560 switch (setup
->wValue
) {
1561 case USB_DEVICE_REMOTE_WAKEUP
:
1562 udc
->remote_wakeup
= 0;
1567 } else if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1568 == ((USB_TYPE_STANDARD
| USB_RECIP_ENDPOINT
))) {
1569 switch (setup
->wValue
) {
1570 case USB_ENDPOINT_HALT
:
1571 ep_num
= setup
->wIndex
& USB_ENDPOINT_NUMBER_MASK
;
1572 direction
= (setup
->wIndex
& USB_ENDPOINT_DIR_MASK
)
1573 ? EP_DIR_IN
: EP_DIR_OUT
;
1574 if (setup
->wValue
!= 0 || setup
->wLength
!= 0
1575 || ep_num
> udc
->max_eps
)
1577 ep
= &udc
->eps
[ep_num
* 2 + direction
];
1580 spin_unlock(&udc
->lock
);
1581 ep_set_stall(udc
, ep_num
, direction
, 0);
1582 spin_lock(&udc
->lock
);
1590 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1596 static void ch9setfeature(struct mv_udc
*udc
, struct usb_ctrlrequest
*setup
)
1601 if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1602 == ((USB_TYPE_STANDARD
| USB_RECIP_DEVICE
))) {
1603 switch (setup
->wValue
) {
1604 case USB_DEVICE_REMOTE_WAKEUP
:
1605 udc
->remote_wakeup
= 1;
1607 case USB_DEVICE_TEST_MODE
:
1608 if (setup
->wIndex
& 0xFF
1609 || udc
->gadget
.speed
!= USB_SPEED_HIGH
)
1612 if (udc
->usb_state
!= USB_STATE_CONFIGURED
1613 && udc
->usb_state
!= USB_STATE_ADDRESS
1614 && udc
->usb_state
!= USB_STATE_DEFAULT
)
1617 mv_udc_testmode(udc
, (setup
->wIndex
>> 8));
1622 } else if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1623 == ((USB_TYPE_STANDARD
| USB_RECIP_ENDPOINT
))) {
1624 switch (setup
->wValue
) {
1625 case USB_ENDPOINT_HALT
:
1626 ep_num
= setup
->wIndex
& USB_ENDPOINT_NUMBER_MASK
;
1627 direction
= (setup
->wIndex
& USB_ENDPOINT_DIR_MASK
)
1628 ? EP_DIR_IN
: EP_DIR_OUT
;
1629 if (setup
->wValue
!= 0 || setup
->wLength
!= 0
1630 || ep_num
> udc
->max_eps
)
1632 spin_unlock(&udc
->lock
);
1633 ep_set_stall(udc
, ep_num
, direction
, 1);
1634 spin_lock(&udc
->lock
);
1642 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1648 static void handle_setup_packet(struct mv_udc
*udc
, u8 ep_num
,
1649 struct usb_ctrlrequest
*setup
)
1650 __releases(&ep
->udc
->lock
)
1651 __acquires(&ep
->udc
->lock
)
1653 bool delegate
= false;
1655 nuke(&udc
->eps
[ep_num
* 2 + EP_DIR_OUT
], -ESHUTDOWN
);
1657 dev_dbg(&udc
->dev
->dev
, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1658 setup
->bRequestType
, setup
->bRequest
,
1659 setup
->wValue
, setup
->wIndex
, setup
->wLength
);
1660 /* We process some stardard setup requests here */
1661 if ((setup
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1662 switch (setup
->bRequest
) {
1663 case USB_REQ_GET_STATUS
:
1664 ch9getstatus(udc
, ep_num
, setup
);
1667 case USB_REQ_SET_ADDRESS
:
1668 ch9setaddress(udc
, setup
);
1671 case USB_REQ_CLEAR_FEATURE
:
1672 ch9clearfeature(udc
, setup
);
1675 case USB_REQ_SET_FEATURE
:
1676 ch9setfeature(udc
, setup
);
1685 /* delegate USB standard requests to the gadget driver */
1686 if (delegate
== true) {
1687 /* USB requests handled by gadget */
1688 if (setup
->wLength
) {
1689 /* DATA phase from gadget, STATUS phase from udc */
1690 udc
->ep0_dir
= (setup
->bRequestType
& USB_DIR_IN
)
1691 ? EP_DIR_IN
: EP_DIR_OUT
;
1692 spin_unlock(&udc
->lock
);
1693 if (udc
->driver
->setup(&udc
->gadget
,
1694 &udc
->local_setup_buff
) < 0)
1696 spin_lock(&udc
->lock
);
1697 udc
->ep0_state
= (setup
->bRequestType
& USB_DIR_IN
)
1698 ? DATA_STATE_XMIT
: DATA_STATE_RECV
;
1700 /* no DATA phase, IN STATUS phase from gadget */
1701 udc
->ep0_dir
= EP_DIR_IN
;
1702 spin_unlock(&udc
->lock
);
1703 if (udc
->driver
->setup(&udc
->gadget
,
1704 &udc
->local_setup_buff
) < 0)
1706 spin_lock(&udc
->lock
);
1707 udc
->ep0_state
= WAIT_FOR_OUT_STATUS
;
1712 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1713 static void ep0_req_complete(struct mv_udc
*udc
,
1714 struct mv_ep
*ep0
, struct mv_req
*req
)
1718 if (udc
->usb_state
== USB_STATE_ADDRESS
) {
1719 /* set the new address */
1720 new_addr
= (u32
)udc
->dev_addr
;
1721 writel(new_addr
<< USB_DEVICE_ADDRESS_BIT_SHIFT
,
1722 &udc
->op_regs
->deviceaddr
);
1727 switch (udc
->ep0_state
) {
1728 case DATA_STATE_XMIT
:
1729 /* receive status phase */
1730 if (udc_prime_status(udc
, EP_DIR_OUT
, 0, true))
1733 case DATA_STATE_RECV
:
1734 /* send status phase */
1735 if (udc_prime_status(udc
, EP_DIR_IN
, 0 , true))
1738 case WAIT_FOR_OUT_STATUS
:
1739 udc
->ep0_state
= WAIT_FOR_SETUP
;
1741 case WAIT_FOR_SETUP
:
1742 dev_err(&udc
->dev
->dev
, "unexpect ep0 packets\n");
1750 static void get_setup_data(struct mv_udc
*udc
, u8 ep_num
, u8
*buffer_ptr
)
1755 dqh
= &udc
->ep_dqh
[ep_num
* 2 + EP_DIR_OUT
];
1757 /* Clear bit in ENDPTSETUPSTAT */
1758 writel((1 << ep_num
), &udc
->op_regs
->epsetupstat
);
1760 /* while a hazard exists when setup package arrives */
1762 /* Set Setup Tripwire */
1763 temp
= readl(&udc
->op_regs
->usbcmd
);
1764 writel(temp
| USBCMD_SETUP_TRIPWIRE_SET
, &udc
->op_regs
->usbcmd
);
1766 /* Copy the setup packet to local buffer */
1767 memcpy(buffer_ptr
, (u8
*) dqh
->setup_buffer
, 8);
1768 } while (!(readl(&udc
->op_regs
->usbcmd
) & USBCMD_SETUP_TRIPWIRE_SET
));
1770 /* Clear Setup Tripwire */
1771 temp
= readl(&udc
->op_regs
->usbcmd
);
1772 writel(temp
& ~USBCMD_SETUP_TRIPWIRE_SET
, &udc
->op_regs
->usbcmd
);
1775 static void irq_process_tr_complete(struct mv_udc
*udc
)
1778 int i
, ep_num
= 0, direction
= 0;
1779 struct mv_ep
*curr_ep
;
1780 struct mv_req
*curr_req
, *temp_req
;
1784 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1785 * because the setup packets are to be read ASAP
1788 /* Process all Setup packet received interrupts */
1789 tmp
= readl(&udc
->op_regs
->epsetupstat
);
1792 for (i
= 0; i
< udc
->max_eps
; i
++) {
1793 if (tmp
& (1 << i
)) {
1794 get_setup_data(udc
, i
,
1795 (u8
*)(&udc
->local_setup_buff
));
1796 handle_setup_packet(udc
, i
,
1797 &udc
->local_setup_buff
);
1802 /* Don't clear the endpoint setup status register here.
1803 * It is cleared as a setup packet is read out of the buffer
1806 /* Process non-setup transaction complete interrupts */
1807 tmp
= readl(&udc
->op_regs
->epcomplete
);
1812 writel(tmp
, &udc
->op_regs
->epcomplete
);
1814 for (i
= 0; i
< udc
->max_eps
* 2; i
++) {
1818 bit_pos
= 1 << (ep_num
+ 16 * direction
);
1820 if (!(bit_pos
& tmp
))
1824 curr_ep
= &udc
->eps
[0];
1826 curr_ep
= &udc
->eps
[i
];
1827 /* process the req queue until an uncomplete request */
1828 list_for_each_entry_safe(curr_req
, temp_req
,
1829 &curr_ep
->queue
, queue
) {
1830 status
= process_ep_req(udc
, i
, curr_req
);
1834 /* write back status to req */
1835 curr_req
->req
.status
= status
;
1837 /* ep0 request completion */
1839 ep0_req_complete(udc
, curr_ep
, curr_req
);
1842 done(curr_ep
, curr_req
, status
);
1848 static void irq_process_reset(struct mv_udc
*udc
)
1853 udc
->ep0_dir
= EP_DIR_OUT
;
1854 udc
->ep0_state
= WAIT_FOR_SETUP
;
1855 udc
->remote_wakeup
= 0; /* default to 0 on reset */
1857 /* The address bits are past bit 25-31. Set the address */
1858 tmp
= readl(&udc
->op_regs
->deviceaddr
);
1859 tmp
&= ~(USB_DEVICE_ADDRESS_MASK
);
1860 writel(tmp
, &udc
->op_regs
->deviceaddr
);
1862 /* Clear all the setup token semaphores */
1863 tmp
= readl(&udc
->op_regs
->epsetupstat
);
1864 writel(tmp
, &udc
->op_regs
->epsetupstat
);
1866 /* Clear all the endpoint complete status bits */
1867 tmp
= readl(&udc
->op_regs
->epcomplete
);
1868 writel(tmp
, &udc
->op_regs
->epcomplete
);
1870 /* wait until all endptprime bits cleared */
1871 loops
= LOOPS(PRIME_TIMEOUT
);
1872 while (readl(&udc
->op_regs
->epprime
) & 0xFFFFFFFF) {
1874 dev_err(&udc
->dev
->dev
,
1875 "Timeout for ENDPTPRIME = 0x%x\n",
1876 readl(&udc
->op_regs
->epprime
));
1883 /* Write 1s to the Flush register */
1884 writel((u32
)~0, &udc
->op_regs
->epflush
);
1886 if (readl(&udc
->op_regs
->portsc
[0]) & PORTSCX_PORT_RESET
) {
1887 dev_info(&udc
->dev
->dev
, "usb bus reset\n");
1888 udc
->usb_state
= USB_STATE_DEFAULT
;
1889 /* reset all the queues, stop all USB activities */
1890 stop_activity(udc
, udc
->driver
);
1892 dev_info(&udc
->dev
->dev
, "USB reset portsc 0x%x\n",
1893 readl(&udc
->op_regs
->portsc
));
1901 /* reset all the queues, stop all USB activities */
1902 stop_activity(udc
, udc
->driver
);
1904 /* reset ep0 dQH and endptctrl */
1907 /* enable interrupt and set controller to run state */
1910 udc
->usb_state
= USB_STATE_ATTACHED
;
1914 static void handle_bus_resume(struct mv_udc
*udc
)
1916 udc
->usb_state
= udc
->resume_state
;
1917 udc
->resume_state
= 0;
1919 /* report resume to the driver */
1921 if (udc
->driver
->resume
) {
1922 spin_unlock(&udc
->lock
);
1923 udc
->driver
->resume(&udc
->gadget
);
1924 spin_lock(&udc
->lock
);
1929 static void irq_process_suspend(struct mv_udc
*udc
)
1931 udc
->resume_state
= udc
->usb_state
;
1932 udc
->usb_state
= USB_STATE_SUSPENDED
;
1934 if (udc
->driver
->suspend
) {
1935 spin_unlock(&udc
->lock
);
1936 udc
->driver
->suspend(&udc
->gadget
);
1937 spin_lock(&udc
->lock
);
1941 static void irq_process_port_change(struct mv_udc
*udc
)
1945 portsc
= readl(&udc
->op_regs
->portsc
[0]);
1946 if (!(portsc
& PORTSCX_PORT_RESET
)) {
1948 u32 speed
= portsc
& PORTSCX_PORT_SPEED_MASK
;
1950 case PORTSCX_PORT_SPEED_HIGH
:
1951 udc
->gadget
.speed
= USB_SPEED_HIGH
;
1953 case PORTSCX_PORT_SPEED_FULL
:
1954 udc
->gadget
.speed
= USB_SPEED_FULL
;
1956 case PORTSCX_PORT_SPEED_LOW
:
1957 udc
->gadget
.speed
= USB_SPEED_LOW
;
1960 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1965 if (portsc
& PORTSCX_PORT_SUSPEND
) {
1966 udc
->resume_state
= udc
->usb_state
;
1967 udc
->usb_state
= USB_STATE_SUSPENDED
;
1968 if (udc
->driver
->suspend
) {
1969 spin_unlock(&udc
->lock
);
1970 udc
->driver
->suspend(&udc
->gadget
);
1971 spin_lock(&udc
->lock
);
1975 if (!(portsc
& PORTSCX_PORT_SUSPEND
)
1976 && udc
->usb_state
== USB_STATE_SUSPENDED
) {
1977 handle_bus_resume(udc
);
1980 if (!udc
->resume_state
)
1981 udc
->usb_state
= USB_STATE_DEFAULT
;
1984 static void irq_process_error(struct mv_udc
*udc
)
1986 /* Increment the error count */
1990 static irqreturn_t
mv_udc_irq(int irq
, void *dev
)
1992 struct mv_udc
*udc
= (struct mv_udc
*)dev
;
1995 /* Disable ISR when stopped bit is set */
1999 spin_lock(&udc
->lock
);
2001 status
= readl(&udc
->op_regs
->usbsts
);
2002 intr
= readl(&udc
->op_regs
->usbintr
);
2006 spin_unlock(&udc
->lock
);
2010 /* Clear all the interrupts occurred */
2011 writel(status
, &udc
->op_regs
->usbsts
);
2013 if (status
& USBSTS_ERR
)
2014 irq_process_error(udc
);
2016 if (status
& USBSTS_RESET
)
2017 irq_process_reset(udc
);
2019 if (status
& USBSTS_PORT_CHANGE
)
2020 irq_process_port_change(udc
);
2022 if (status
& USBSTS_INT
)
2023 irq_process_tr_complete(udc
);
2025 if (status
& USBSTS_SUSPEND
)
2026 irq_process_suspend(udc
);
2028 spin_unlock(&udc
->lock
);
2033 static irqreturn_t
mv_udc_vbus_irq(int irq
, void *dev
)
2035 struct mv_udc
*udc
= (struct mv_udc
*)dev
;
2037 /* polling VBUS and init phy may cause too much time*/
2039 queue_work(udc
->qwork
, &udc
->vbus_work
);
2044 static void mv_udc_vbus_work(struct work_struct
*work
)
2049 udc
= container_of(work
, struct mv_udc
, vbus_work
);
2050 if (!udc
->pdata
->vbus
)
2053 vbus
= udc
->pdata
->vbus
->poll();
2054 dev_info(&udc
->dev
->dev
, "vbus is %d\n", vbus
);
2056 if (vbus
== VBUS_HIGH
)
2057 mv_udc_vbus_session(&udc
->gadget
, 1);
2058 else if (vbus
== VBUS_LOW
)
2059 mv_udc_vbus_session(&udc
->gadget
, 0);
2062 /* release device structure */
2063 static void gadget_release(struct device
*_dev
)
2067 udc
= dev_get_drvdata(_dev
);
2069 complete(udc
->done
);
2072 static int mv_udc_remove(struct platform_device
*pdev
)
2076 udc
= platform_get_drvdata(pdev
);
2078 usb_del_gadget_udc(&udc
->gadget
);
2081 flush_workqueue(udc
->qwork
);
2082 destroy_workqueue(udc
->qwork
);
2085 /* free memory allocated in probe */
2087 dma_pool_destroy(udc
->dtd_pool
);
2090 dma_free_coherent(&pdev
->dev
, udc
->ep_dqh_size
,
2091 udc
->ep_dqh
, udc
->ep_dqh_dma
);
2093 mv_udc_disable(udc
);
2095 /* free dev, wait for the release() finished */
2096 wait_for_completion(udc
->done
);
2101 static int mv_udc_probe(struct platform_device
*pdev
)
2103 struct mv_usb_platform_data
*pdata
= pdev
->dev
.platform_data
;
2109 if (pdata
== NULL
) {
2110 dev_err(&pdev
->dev
, "missing platform_data\n");
2114 udc
= devm_kzalloc(&pdev
->dev
, sizeof(*udc
), GFP_KERNEL
);
2116 dev_err(&pdev
->dev
, "failed to allocate memory for udc\n");
2120 udc
->done
= &release_done
;
2121 udc
->pdata
= pdev
->dev
.platform_data
;
2122 spin_lock_init(&udc
->lock
);
2126 if (pdata
->mode
== MV_USB_MODE_OTG
) {
2127 udc
->transceiver
= devm_usb_get_phy(&pdev
->dev
,
2129 if (IS_ERR(udc
->transceiver
)) {
2130 retval
= PTR_ERR(udc
->transceiver
);
2132 if (retval
== -ENXIO
)
2135 udc
->transceiver
= NULL
;
2136 return -EPROBE_DEFER
;
2140 /* udc only have one sysclk. */
2141 udc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
2142 if (IS_ERR(udc
->clk
))
2143 return PTR_ERR(udc
->clk
);
2145 r
= platform_get_resource_byname(udc
->dev
, IORESOURCE_MEM
, "capregs");
2147 dev_err(&pdev
->dev
, "no I/O memory resource defined\n");
2151 udc
->cap_regs
= (struct mv_cap_regs __iomem
*)
2152 devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
2153 if (udc
->cap_regs
== NULL
) {
2154 dev_err(&pdev
->dev
, "failed to map I/O memory\n");
2158 r
= platform_get_resource_byname(udc
->dev
, IORESOURCE_MEM
, "phyregs");
2160 dev_err(&pdev
->dev
, "no phy I/O memory resource defined\n");
2164 udc
->phy_regs
= ioremap(r
->start
, resource_size(r
));
2165 if (udc
->phy_regs
== NULL
) {
2166 dev_err(&pdev
->dev
, "failed to map phy I/O memory\n");
2170 /* we will acces controller register, so enable the clk */
2171 retval
= mv_udc_enable_internal(udc
);
2176 (struct mv_op_regs __iomem
*)((unsigned long)udc
->cap_regs
2177 + (readl(&udc
->cap_regs
->caplength_hciversion
)
2179 udc
->max_eps
= readl(&udc
->cap_regs
->dccparams
) & DCCPARAMS_DEN_MASK
;
2182 * some platform will use usb to download image, it may not disconnect
2183 * usb gadget before loading kernel. So first stop udc here.
2186 writel(0xFFFFFFFF, &udc
->op_regs
->usbsts
);
2188 size
= udc
->max_eps
* sizeof(struct mv_dqh
) *2;
2189 size
= (size
+ DQH_ALIGNMENT
- 1) & ~(DQH_ALIGNMENT
- 1);
2190 udc
->ep_dqh
= dma_alloc_coherent(&pdev
->dev
, size
,
2191 &udc
->ep_dqh_dma
, GFP_KERNEL
);
2193 if (udc
->ep_dqh
== NULL
) {
2194 dev_err(&pdev
->dev
, "allocate dQH memory failed\n");
2196 goto err_disable_clock
;
2198 udc
->ep_dqh_size
= size
;
2200 /* create dTD dma_pool resource */
2201 udc
->dtd_pool
= dma_pool_create("mv_dtd",
2203 sizeof(struct mv_dtd
),
2207 if (!udc
->dtd_pool
) {
2212 size
= udc
->max_eps
* sizeof(struct mv_ep
) *2;
2213 udc
->eps
= devm_kzalloc(&pdev
->dev
, size
, GFP_KERNEL
);
2214 if (udc
->eps
== NULL
) {
2215 dev_err(&pdev
->dev
, "allocate ep memory failed\n");
2217 goto err_destroy_dma
;
2220 /* initialize ep0 status request structure */
2221 udc
->status_req
= devm_kzalloc(&pdev
->dev
, sizeof(struct mv_req
),
2223 if (!udc
->status_req
) {
2224 dev_err(&pdev
->dev
, "allocate status_req memory failed\n");
2226 goto err_destroy_dma
;
2228 INIT_LIST_HEAD(&udc
->status_req
->queue
);
2230 /* allocate a small amount of memory to get valid address */
2231 udc
->status_req
->req
.buf
= kzalloc(8, GFP_KERNEL
);
2232 udc
->status_req
->req
.dma
= DMA_ADDR_INVALID
;
2234 udc
->resume_state
= USB_STATE_NOTATTACHED
;
2235 udc
->usb_state
= USB_STATE_POWERED
;
2236 udc
->ep0_dir
= EP_DIR_OUT
;
2237 udc
->remote_wakeup
= 0;
2239 r
= platform_get_resource(udc
->dev
, IORESOURCE_IRQ
, 0);
2241 dev_err(&pdev
->dev
, "no IRQ resource defined\n");
2243 goto err_destroy_dma
;
2245 udc
->irq
= r
->start
;
2246 if (devm_request_irq(&pdev
->dev
, udc
->irq
, mv_udc_irq
,
2247 IRQF_SHARED
, driver_name
, udc
)) {
2248 dev_err(&pdev
->dev
, "Request irq %d for UDC failed\n",
2251 goto err_destroy_dma
;
2254 /* initialize gadget structure */
2255 udc
->gadget
.ops
= &mv_ops
; /* usb_gadget_ops */
2256 udc
->gadget
.ep0
= &udc
->eps
[0].ep
; /* gadget ep0 */
2257 INIT_LIST_HEAD(&udc
->gadget
.ep_list
); /* ep_list */
2258 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
; /* speed */
2259 udc
->gadget
.max_speed
= USB_SPEED_HIGH
; /* support dual speed */
2261 /* the "gadget" abstracts/virtualizes the controller */
2262 udc
->gadget
.name
= driver_name
; /* gadget name */
2266 /* VBUS detect: we can disable/enable clock on demand.*/
2267 if (udc
->transceiver
)
2268 udc
->clock_gating
= 1;
2269 else if (pdata
->vbus
) {
2270 udc
->clock_gating
= 1;
2271 retval
= devm_request_threaded_irq(&pdev
->dev
,
2272 pdata
->vbus
->irq
, NULL
,
2273 mv_udc_vbus_irq
, IRQF_ONESHOT
, "vbus", udc
);
2275 dev_info(&pdev
->dev
,
2276 "Can not request irq for VBUS, "
2277 "disable clock gating\n");
2278 udc
->clock_gating
= 0;
2281 udc
->qwork
= create_singlethread_workqueue("mv_udc_queue");
2283 dev_err(&pdev
->dev
, "cannot create workqueue\n");
2285 goto err_destroy_dma
;
2288 INIT_WORK(&udc
->vbus_work
, mv_udc_vbus_work
);
2292 * When clock gating is supported, we can disable clk and phy.
2293 * If not, it means that VBUS detection is not supported, we
2294 * have to enable vbus active all the time to let controller work.
2296 if (udc
->clock_gating
)
2297 mv_udc_disable_internal(udc
);
2299 udc
->vbus_active
= 1;
2301 retval
= usb_add_gadget_udc_release(&pdev
->dev
, &udc
->gadget
,
2304 goto err_create_workqueue
;
2306 platform_set_drvdata(pdev
, udc
);
2307 dev_info(&pdev
->dev
, "successful probe UDC device %s clock gating.\n",
2308 udc
->clock_gating
? "with" : "without");
2312 err_create_workqueue
:
2313 destroy_workqueue(udc
->qwork
);
2315 dma_pool_destroy(udc
->dtd_pool
);
2317 dma_free_coherent(&pdev
->dev
, udc
->ep_dqh_size
,
2318 udc
->ep_dqh
, udc
->ep_dqh_dma
);
2320 mv_udc_disable_internal(udc
);
2326 static int mv_udc_suspend(struct device
*dev
)
2330 udc
= dev_get_drvdata(dev
);
2332 /* if OTG is enabled, the following will be done in OTG driver*/
2333 if (udc
->transceiver
)
2336 if (udc
->pdata
->vbus
&& udc
->pdata
->vbus
->poll
)
2337 if (udc
->pdata
->vbus
->poll() == VBUS_HIGH
) {
2338 dev_info(&udc
->dev
->dev
, "USB cable is connected!\n");
2343 * only cable is unplugged, udc can suspend.
2344 * So do not care about clock_gating == 1.
2346 if (!udc
->clock_gating
) {
2349 spin_lock_irq(&udc
->lock
);
2350 /* stop all usb activities */
2351 stop_activity(udc
, udc
->driver
);
2352 spin_unlock_irq(&udc
->lock
);
2354 mv_udc_disable_internal(udc
);
2360 static int mv_udc_resume(struct device
*dev
)
2365 udc
= dev_get_drvdata(dev
);
2367 /* if OTG is enabled, the following will be done in OTG driver*/
2368 if (udc
->transceiver
)
2371 if (!udc
->clock_gating
) {
2372 retval
= mv_udc_enable_internal(udc
);
2376 if (udc
->driver
&& udc
->softconnect
) {
2386 static const struct dev_pm_ops mv_udc_pm_ops
= {
2387 .suspend
= mv_udc_suspend
,
2388 .resume
= mv_udc_resume
,
2392 static void mv_udc_shutdown(struct platform_device
*pdev
)
2397 udc
= platform_get_drvdata(pdev
);
2398 /* reset controller mode to IDLE */
2400 mode
= readl(&udc
->op_regs
->usbmode
);
2402 writel(mode
, &udc
->op_regs
->usbmode
);
2403 mv_udc_disable(udc
);
2406 static struct platform_driver udc_driver
= {
2407 .probe
= mv_udc_probe
,
2408 .remove
= mv_udc_remove
,
2409 .shutdown
= mv_udc_shutdown
,
2411 .owner
= THIS_MODULE
,
2414 .pm
= &mv_udc_pm_ops
,
2419 module_platform_driver(udc_driver
);
2420 MODULE_ALIAS("platform:mv-udc");
2421 MODULE_DESCRIPTION(DRIVER_DESC
);
2422 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2423 MODULE_VERSION(DRIVER_VERSION
);
2424 MODULE_LICENSE("GPL");