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[SCTP]: Fix sctp_primitive_ABORT() call in sctp_close().
[linux-2.6.git] / arch / i386 / kernel / mpparse.c
bloba70b5fa0ef06fd3cf165349959d52f25fe151fed
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/bitops.h>
25
26 #include <asm/smp.h>
27 #include <asm/acpi.h>
28 #include <asm/mtrr.h>
29 #include <asm/mpspec.h>
30 #include <asm/io_apic.h>
31
32 #include <mach_apic.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __initdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 int apic_version [MAX_APICS];
45 int mp_bus_id_to_type [MAX_MP_BUSSES];
46 int mp_bus_id_to_node [MAX_MP_BUSSES];
47 int mp_bus_id_to_local [MAX_MP_BUSSES];
48 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
51
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
54
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
57
58 /* MP IRQ source entries */
59 int mp_irq_entries;
60
61 int nr_ioapics;
62
63 int pic_mode;
64 unsigned long mp_lapic_addr;
65
66 unsigned int def_to_bigsmp = 0;
67
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 static unsigned int __devinitdata num_processors;
72
73 /* Bitmask of physically existing CPUs */
74 physid_mask_t phys_cpu_present_map;
75
76 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
77
78 /*
79 * Intel MP BIOS table parsing routines:
80 */
81
82
83 /*
84 * Checksum an MP configuration block.
85 */
86
87 static int __init mpf_checksum(unsigned char *mp, int len)
88 {
89 int sum = 0;
90
91 while (len--)
92 sum += *mp++;
93
94 return sum & 0xFF;
95 }
96
97 /*
98 * Have to match translation table entries to main table entries by counter
99 * hence the mpc_record variable .... can't see a less disgusting way of
100 * doing this ....
101 */
102
103 static int mpc_record;
104 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
105
106 static void __devinit MP_processor_info (struct mpc_config_processor *m)
107 {
108 int ver, apicid;
109 physid_mask_t phys_cpu;
110
111 if (!(m->mpc_cpuflag & CPU_ENABLED))
112 return;
113
114 apicid = mpc_apic_id(m, translation_table[mpc_record]);
115
116 if (m->mpc_featureflag&(1<<0))
117 Dprintk(" Floating point unit present.\n");
118 if (m->mpc_featureflag&(1<<7))
119 Dprintk(" Machine Exception supported.\n");
120 if (m->mpc_featureflag&(1<<8))
121 Dprintk(" 64 bit compare & exchange supported.\n");
122 if (m->mpc_featureflag&(1<<9))
123 Dprintk(" Internal APIC present.\n");
124 if (m->mpc_featureflag&(1<<11))
125 Dprintk(" SEP present.\n");
126 if (m->mpc_featureflag&(1<<12))
127 Dprintk(" MTRR present.\n");
128 if (m->mpc_featureflag&(1<<13))
129 Dprintk(" PGE present.\n");
130 if (m->mpc_featureflag&(1<<14))
131 Dprintk(" MCA present.\n");
132 if (m->mpc_featureflag&(1<<15))
133 Dprintk(" CMOV present.\n");
134 if (m->mpc_featureflag&(1<<16))
135 Dprintk(" PAT present.\n");
136 if (m->mpc_featureflag&(1<<17))
137 Dprintk(" PSE present.\n");
138 if (m->mpc_featureflag&(1<<18))
139 Dprintk(" PSN present.\n");
140 if (m->mpc_featureflag&(1<<19))
141 Dprintk(" Cache Line Flush Instruction present.\n");
142 /* 20 Reserved */
143 if (m->mpc_featureflag&(1<<21))
144 Dprintk(" Debug Trace and EMON Store present.\n");
145 if (m->mpc_featureflag&(1<<22))
146 Dprintk(" ACPI Thermal Throttle Registers present.\n");
147 if (m->mpc_featureflag&(1<<23))
148 Dprintk(" MMX present.\n");
149 if (m->mpc_featureflag&(1<<24))
150 Dprintk(" FXSR present.\n");
151 if (m->mpc_featureflag&(1<<25))
152 Dprintk(" XMM present.\n");
153 if (m->mpc_featureflag&(1<<26))
154 Dprintk(" Willamette New Instructions present.\n");
155 if (m->mpc_featureflag&(1<<27))
156 Dprintk(" Self Snoop present.\n");
157 if (m->mpc_featureflag&(1<<28))
158 Dprintk(" HT present.\n");
159 if (m->mpc_featureflag&(1<<29))
160 Dprintk(" Thermal Monitor present.\n");
161 /* 30, 31 Reserved */
162
163
164 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
165 Dprintk(" Bootup CPU\n");
166 boot_cpu_physical_apicid = m->mpc_apicid;
167 }
168
169 ver = m->mpc_apicver;
170
171 /*
172 * Validate version
173 */
174 if (ver == 0x0) {
175 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
176 "fixing up to 0x10. (tell your hw vendor)\n",
177 m->mpc_apicid);
178 ver = 0x10;
179 }
180 apic_version[m->mpc_apicid] = ver;
181
182 phys_cpu = apicid_to_cpu_present(apicid);
183 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
184
185 if (num_processors >= NR_CPUS) {
186 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
187 " Processor ignored.\n", NR_CPUS);
188 return;
189 }
190
191 if (num_processors >= maxcpus) {
192 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
193 " Processor ignored.\n", maxcpus);
194 return;
195 }
196
197 cpu_set(num_processors, cpu_possible_map);
198 num_processors++;
199
200 /*
201 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
202 * but we need to work other dependencies like SMP_SUSPEND etc
203 * before this can be done without some confusion.
204 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
205 * - Ashok Raj <ashok.raj@intel.com>
206 */
207 if (num_processors > 8) {
208 switch (boot_cpu_data.x86_vendor) {
209 case X86_VENDOR_INTEL:
210 if (!APIC_XAPIC(ver)) {
211 def_to_bigsmp = 0;
212 break;
213 }
214 /* If P4 and above fall through */
215 case X86_VENDOR_AMD:
216 def_to_bigsmp = 1;
217 }
218 }
219 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
220 }
221
222 static void __init MP_bus_info (struct mpc_config_bus *m)
223 {
224 char str[7];
225
226 memcpy(str, m->mpc_bustype, 6);
227 str[6] = 0;
228
229 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
230
231 if (m->mpc_busid >= MAX_MP_BUSSES) {
232 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
233 " is too large, max. supported is %d\n",
234 m->mpc_busid, str, MAX_MP_BUSSES - 1);
235 return;
236 }
237
238 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
239 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
240 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
241 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
242 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
243 mpc_oem_pci_bus(m, translation_table[mpc_record]);
244 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
245 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
246 mp_current_pci_id++;
247 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
248 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
249 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
250 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
251 } else {
252 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
253 }
254 }
255
256 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
257 {
258 if (!(m->mpc_flags & MPC_APIC_USABLE))
259 return;
260
261 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
262 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
263 if (nr_ioapics >= MAX_IO_APICS) {
264 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
265 MAX_IO_APICS, nr_ioapics);
266 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
267 }
268 if (!m->mpc_apicaddr) {
269 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
270 " found in MP table, skipping!\n");
271 return;
272 }
273 mp_ioapics[nr_ioapics] = *m;
274 nr_ioapics++;
275 }
276
277 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
278 {
279 mp_irqs [mp_irq_entries] = *m;
280 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
281 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
282 m->mpc_irqtype, m->mpc_irqflag & 3,
283 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
284 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
285 if (++mp_irq_entries == MAX_IRQ_SOURCES)
286 panic("Max # of irq sources exceeded!!\n");
287 }
288
289 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
290 {
291 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
292 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
293 m->mpc_irqtype, m->mpc_irqflag & 3,
294 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
295 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
296 /*
297 * Well it seems all SMP boards in existence
298 * use ExtINT/LVT1 == LINT0 and
299 * NMI/LVT2 == LINT1 - the following check
300 * will show us if this assumptions is false.
301 * Until then we do not have to add baggage.
302 */
303 if ((m->mpc_irqtype == mp_ExtINT) &&
304 (m->mpc_destapiclint != 0))
305 BUG();
306 if ((m->mpc_irqtype == mp_NMI) &&
307 (m->mpc_destapiclint != 1))
308 BUG();
309 }
310
311 #ifdef CONFIG_X86_NUMAQ
312 static void __init MP_translation_info (struct mpc_config_translation *m)
313 {
314 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
315
316 if (mpc_record >= MAX_MPC_ENTRY)
317 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
318 else
319 translation_table[mpc_record] = m; /* stash this for later */
320 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
321 node_set_online(m->trans_quad);
322 }
323
324 /*
325 * Read/parse the MPC oem tables
326 */
327
328 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
329 unsigned short oemsize)
330 {
331 int count = sizeof (*oemtable); /* the header size */
332 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
333
334 mpc_record = 0;
335 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
336 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
337 {
338 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
339 oemtable->oem_signature[0],
340 oemtable->oem_signature[1],
341 oemtable->oem_signature[2],
342 oemtable->oem_signature[3]);
343 return;
344 }
345 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
346 {
347 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
348 return;
349 }
350 while (count < oemtable->oem_length) {
351 switch (*oemptr) {
352 case MP_TRANSLATION:
353 {
354 struct mpc_config_translation *m=
355 (struct mpc_config_translation *)oemptr;
356 MP_translation_info(m);
357 oemptr += sizeof(*m);
358 count += sizeof(*m);
359 ++mpc_record;
360 break;
361 }
362 default:
363 {
364 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
365 return;
366 }
367 }
368 }
369 }
370
371 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
372 char *productid)
373 {
374 if (strncmp(oem, "IBM NUMA", 8))
375 printk("Warning! May not be a NUMA-Q system!\n");
376 if (mpc->mpc_oemptr)
377 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
378 mpc->mpc_oemsize);
379 }
380 #endif /* CONFIG_X86_NUMAQ */
381
382 /*
383 * Read/parse the MPC
384 */
385
386 static int __init smp_read_mpc(struct mp_config_table *mpc)
387 {
388 char str[16];
389 char oem[10];
390 int count=sizeof(*mpc);
391 unsigned char *mpt=((unsigned char *)mpc)+count;
392
393 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
394 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
395 *(u32 *)mpc->mpc_signature);
396 return 0;
397 }
398 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
399 printk(KERN_ERR "SMP mptable: checksum error!\n");
400 return 0;
401 }
402 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
403 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
404 mpc->mpc_spec);
405 return 0;
406 }
407 if (!mpc->mpc_lapic) {
408 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
409 return 0;
410 }
411 memcpy(oem,mpc->mpc_oem,8);
412 oem[8]=0;
413 printk(KERN_INFO "OEM ID: %s ",oem);
414
415 memcpy(str,mpc->mpc_productid,12);
416 str[12]=0;
417 printk("Product ID: %s ",str);
418
419 mps_oem_check(mpc, oem, str);
420
421 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
422
423 /*
424 * Save the local APIC address (it might be non-default) -- but only
425 * if we're not using ACPI.
426 */
427 if (!acpi_lapic)
428 mp_lapic_addr = mpc->mpc_lapic;
429
430 /*
431 * Now process the configuration blocks.
432 */
433 mpc_record = 0;
434 while (count < mpc->mpc_length) {
435 switch(*mpt) {
436 case MP_PROCESSOR:
437 {
438 struct mpc_config_processor *m=
439 (struct mpc_config_processor *)mpt;
440 /* ACPI may have already provided this data */
441 if (!acpi_lapic)
442 MP_processor_info(m);
443 mpt += sizeof(*m);
444 count += sizeof(*m);
445 break;
446 }
447 case MP_BUS:
448 {
449 struct mpc_config_bus *m=
450 (struct mpc_config_bus *)mpt;
451 MP_bus_info(m);
452 mpt += sizeof(*m);
453 count += sizeof(*m);
454 break;
455 }
456 case MP_IOAPIC:
457 {
458 struct mpc_config_ioapic *m=
459 (struct mpc_config_ioapic *)mpt;
460 MP_ioapic_info(m);
461 mpt+=sizeof(*m);
462 count+=sizeof(*m);
463 break;
464 }
465 case MP_INTSRC:
466 {
467 struct mpc_config_intsrc *m=
468 (struct mpc_config_intsrc *)mpt;
469
470 MP_intsrc_info(m);
471 mpt+=sizeof(*m);
472 count+=sizeof(*m);
473 break;
474 }
475 case MP_LINTSRC:
476 {
477 struct mpc_config_lintsrc *m=
478 (struct mpc_config_lintsrc *)mpt;
479 MP_lintsrc_info(m);
480 mpt+=sizeof(*m);
481 count+=sizeof(*m);
482 break;
483 }
484 default:
485 {
486 count = mpc->mpc_length;
487 break;
488 }
489 }
490 ++mpc_record;
491 }
492 clustered_apic_check();
493 if (!num_processors)
494 printk(KERN_ERR "SMP mptable: no processors registered!\n");
495 return num_processors;
496 }
497
498 static int __init ELCR_trigger(unsigned int irq)
499 {
500 unsigned int port;
501
502 port = 0x4d0 + (irq >> 3);
503 return (inb(port) >> (irq & 7)) & 1;
504 }
505
506 static void __init construct_default_ioirq_mptable(int mpc_default_type)
507 {
508 struct mpc_config_intsrc intsrc;
509 int i;
510 int ELCR_fallback = 0;
511
512 intsrc.mpc_type = MP_INTSRC;
513 intsrc.mpc_irqflag = 0; /* conforming */
514 intsrc.mpc_srcbus = 0;
515 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
516
517 intsrc.mpc_irqtype = mp_INT;
518
519 /*
520 * If true, we have an ISA/PCI system with no IRQ entries
521 * in the MP table. To prevent the PCI interrupts from being set up
522 * incorrectly, we try to use the ELCR. The sanity check to see if
523 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
524 * never be level sensitive, so we simply see if the ELCR agrees.
525 * If it does, we assume it's valid.
526 */
527 if (mpc_default_type == 5) {
528 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
529
530 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
531 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
532 else {
533 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
534 ELCR_fallback = 1;
535 }
536 }
537
538 for (i = 0; i < 16; i++) {
539 switch (mpc_default_type) {
540 case 2:
541 if (i == 0 || i == 13)
542 continue; /* IRQ0 & IRQ13 not connected */
543 /* fall through */
544 default:
545 if (i == 2)
546 continue; /* IRQ2 is never connected */
547 }
548
549 if (ELCR_fallback) {
550 /*
551 * If the ELCR indicates a level-sensitive interrupt, we
552 * copy that information over to the MP table in the
553 * irqflag field (level sensitive, active high polarity).
554 */
555 if (ELCR_trigger(i))
556 intsrc.mpc_irqflag = 13;
557 else
558 intsrc.mpc_irqflag = 0;
559 }
560
561 intsrc.mpc_srcbusirq = i;
562 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
563 MP_intsrc_info(&intsrc);
564 }
565
566 intsrc.mpc_irqtype = mp_ExtINT;
567 intsrc.mpc_srcbusirq = 0;
568 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
569 MP_intsrc_info(&intsrc);
570 }
571
572 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
573 {
574 struct mpc_config_processor processor;
575 struct mpc_config_bus bus;
576 struct mpc_config_ioapic ioapic;
577 struct mpc_config_lintsrc lintsrc;
578 int linttypes[2] = { mp_ExtINT, mp_NMI };
579 int i;
580
581 /*
582 * local APIC has default address
583 */
584 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
585
586 /*
587 * 2 CPUs, numbered 0 & 1.
588 */
589 processor.mpc_type = MP_PROCESSOR;
590 /* Either an integrated APIC or a discrete 82489DX. */
591 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
592 processor.mpc_cpuflag = CPU_ENABLED;
593 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
594 (boot_cpu_data.x86_model << 4) |
595 boot_cpu_data.x86_mask;
596 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
597 processor.mpc_reserved[0] = 0;
598 processor.mpc_reserved[1] = 0;
599 for (i = 0; i < 2; i++) {
600 processor.mpc_apicid = i;
601 MP_processor_info(&processor);
602 }
603
604 bus.mpc_type = MP_BUS;
605 bus.mpc_busid = 0;
606 switch (mpc_default_type) {
607 default:
608 printk("???\n");
609 printk(KERN_ERR "Unknown standard configuration %d\n",
610 mpc_default_type);
611 /* fall through */
612 case 1:
613 case 5:
614 memcpy(bus.mpc_bustype, "ISA ", 6);
615 break;
616 case 2:
617 case 6:
618 case 3:
619 memcpy(bus.mpc_bustype, "EISA ", 6);
620 break;
621 case 4:
622 case 7:
623 memcpy(bus.mpc_bustype, "MCA ", 6);
624 }
625 MP_bus_info(&bus);
626 if (mpc_default_type > 4) {
627 bus.mpc_busid = 1;
628 memcpy(bus.mpc_bustype, "PCI ", 6);
629 MP_bus_info(&bus);
630 }
631
632 ioapic.mpc_type = MP_IOAPIC;
633 ioapic.mpc_apicid = 2;
634 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
635 ioapic.mpc_flags = MPC_APIC_USABLE;
636 ioapic.mpc_apicaddr = 0xFEC00000;
637 MP_ioapic_info(&ioapic);
638
639 /*
640 * We set up most of the low 16 IO-APIC pins according to MPS rules.
641 */
642 construct_default_ioirq_mptable(mpc_default_type);
643
644 lintsrc.mpc_type = MP_LINTSRC;
645 lintsrc.mpc_irqflag = 0; /* conforming */
646 lintsrc.mpc_srcbusid = 0;
647 lintsrc.mpc_srcbusirq = 0;
648 lintsrc.mpc_destapic = MP_APIC_ALL;
649 for (i = 0; i < 2; i++) {
650 lintsrc.mpc_irqtype = linttypes[i];
651 lintsrc.mpc_destapiclint = i;
652 MP_lintsrc_info(&lintsrc);
653 }
654 }
655
656 static struct intel_mp_floating *mpf_found;
657
658 /*
659 * Scan the memory blocks for an SMP configuration block.
660 */
661 void __init get_smp_config (void)
662 {
663 struct intel_mp_floating *mpf = mpf_found;
664
665 /*
666 * ACPI supports both logical (e.g. Hyper-Threading) and physical
667 * processors, where MPS only supports physical.
668 */
669 if (acpi_lapic && acpi_ioapic) {
670 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
671 return;
672 }
673 else if (acpi_lapic)
674 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
675
676 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
677 if (mpf->mpf_feature2 & (1<<7)) {
678 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
679 pic_mode = 1;
680 } else {
681 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
682 pic_mode = 0;
683 }
684
685 /*
686 * Now see if we need to read further.
687 */
688 if (mpf->mpf_feature1 != 0) {
689
690 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
691 construct_default_ISA_mptable(mpf->mpf_feature1);
692
693 } else if (mpf->mpf_physptr) {
694
695 /*
696 * Read the physical hardware table. Anything here will
697 * override the defaults.
698 */
699 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
700 smp_found_config = 0;
701 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
702 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
703 return;
704 }
705 /*
706 * If there are no explicit MP IRQ entries, then we are
707 * broken. We set up most of the low 16 IO-APIC pins to
708 * ISA defaults and hope it will work.
709 */
710 if (!mp_irq_entries) {
711 struct mpc_config_bus bus;
712
713 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
714
715 bus.mpc_type = MP_BUS;
716 bus.mpc_busid = 0;
717 memcpy(bus.mpc_bustype, "ISA ", 6);
718 MP_bus_info(&bus);
719
720 construct_default_ioirq_mptable(0);
721 }
722
723 } else
724 BUG();
725
726 printk(KERN_INFO "Processors: %d\n", num_processors);
727 /*
728 * Only use the first configuration found.
729 */
730 }
731
732 static int __init smp_scan_config (unsigned long base, unsigned long length)
733 {
734 unsigned long *bp = phys_to_virt(base);
735 struct intel_mp_floating *mpf;
736
737 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
738 if (sizeof(*mpf) != 16)
739 printk("Error: MPF size\n");
740
741 while (length > 0) {
742 mpf = (struct intel_mp_floating *)bp;
743 if ((*bp == SMP_MAGIC_IDENT) &&
744 (mpf->mpf_length == 1) &&
745 !mpf_checksum((unsigned char *)bp, 16) &&
746 ((mpf->mpf_specification == 1)
747 || (mpf->mpf_specification == 4)) ) {
748
749 smp_found_config = 1;
750 printk(KERN_INFO "found SMP MP-table at %08lx\n",
751 virt_to_phys(mpf));
752 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
753 if (mpf->mpf_physptr) {
754 /*
755 * We cannot access to MPC table to compute
756 * table size yet, as only few megabytes from
757 * the bottom is mapped now.
758 * PC-9800's MPC table places on the very last
759 * of physical memory; so that simply reserving
760 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
761 * in reserve_bootmem.
762 */
763 unsigned long size = PAGE_SIZE;
764 unsigned long end = max_low_pfn * PAGE_SIZE;
765 if (mpf->mpf_physptr + size > end)
766 size = end - mpf->mpf_physptr;
767 reserve_bootmem(mpf->mpf_physptr, size);
768 }
769
770 mpf_found = mpf;
771 return 1;
772 }
773 bp += 4;
774 length -= 16;
775 }
776 return 0;
777 }
778
779 void __init find_smp_config (void)
780 {
781 unsigned int address;
782
783 /*
784 * FIXME: Linux assumes you have 640K of base ram..
785 * this continues the error...
786 *
787 * 1) Scan the bottom 1K for a signature
788 * 2) Scan the top 1K of base RAM
789 * 3) Scan the 64K of bios
790 */
791 if (smp_scan_config(0x0,0x400) ||
792 smp_scan_config(639*0x400,0x400) ||
793 smp_scan_config(0xF0000,0x10000))
794 return;
795 /*
796 * If it is an SMP machine we should know now, unless the
797 * configuration is in an EISA/MCA bus machine with an
798 * extended bios data area.
799 *
800 * there is a real-mode segmented pointer pointing to the
801 * 4K EBDA area at 0x40E, calculate and scan it here.
802 *
803 * NOTE! There are Linux loaders that will corrupt the EBDA
804 * area, and as such this kind of SMP config may be less
805 * trustworthy, simply because the SMP table may have been
806 * stomped on during early boot. These loaders are buggy and
807 * should be fixed.
808 *
809 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
810 */
811
812 address = get_bios_ebda();
813 if (address)
814 smp_scan_config(address, 0x400);
815 }
816
817 int es7000_plat;
818
819 /* --------------------------------------------------------------------------
820 ACPI-based MP Configuration
821 -------------------------------------------------------------------------- */
822
823 #ifdef CONFIG_ACPI
824
825 void __init mp_register_lapic_address (
826 u64 address)
827 {
828 mp_lapic_addr = (unsigned long) address;
829
830 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
831
832 if (boot_cpu_physical_apicid == -1U)
833 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
834
835 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
836 }
837
838
839 void __devinit mp_register_lapic (
840 u8 id,
841 u8 enabled)
842 {
843 struct mpc_config_processor processor;
844 int boot_cpu = 0;
845
846 if (MAX_APICS - id <= 0) {
847 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
848 id, MAX_APICS);
849 return;
850 }
851
852 if (id == boot_cpu_physical_apicid)
853 boot_cpu = 1;
854
855 processor.mpc_type = MP_PROCESSOR;
856 processor.mpc_apicid = id;
857 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
858 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
859 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
860 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
861 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
862 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
863 processor.mpc_reserved[0] = 0;
864 processor.mpc_reserved[1] = 0;
865
866 MP_processor_info(&processor);
867 }
868
869 #ifdef CONFIG_X86_IO_APIC
870
871 #define MP_ISA_BUS 0
872 #define MP_MAX_IOAPIC_PIN 127
873
874 static struct mp_ioapic_routing {
875 int apic_id;
876 int gsi_base;
877 int gsi_end;
878 u32 pin_programmed[4];
879 } mp_ioapic_routing[MAX_IO_APICS];
880
881
882 static int mp_find_ioapic (
883 int gsi)
884 {
885 int i = 0;
886
887 /* Find the IOAPIC that manages this GSI. */
888 for (i = 0; i < nr_ioapics; i++) {
889 if ((gsi >= mp_ioapic_routing[i].gsi_base)
890 && (gsi <= mp_ioapic_routing[i].gsi_end))
891 return i;
892 }
893
894 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
895
896 return -1;
897 }
898
899
900 void __init mp_register_ioapic (
901 u8 id,
902 u32 address,
903 u32 gsi_base)
904 {
905 int idx = 0;
906 int tmpid;
907
908 if (nr_ioapics >= MAX_IO_APICS) {
909 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
910 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
911 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
912 }
913 if (!address) {
914 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
915 " found in MADT table, skipping!\n");
916 return;
917 }
918
919 idx = nr_ioapics++;
920
921 mp_ioapics[idx].mpc_type = MP_IOAPIC;
922 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
923 mp_ioapics[idx].mpc_apicaddr = address;
924
925 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
926 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
927 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
928 tmpid = io_apic_get_unique_id(idx, id);
929 else
930 tmpid = id;
931 if (tmpid == -1) {
932 nr_ioapics--;
933 return;
934 }
935 mp_ioapics[idx].mpc_apicid = tmpid;
936 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
937
938 /*
939 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
940 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
941 */
942 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
943 mp_ioapic_routing[idx].gsi_base = gsi_base;
944 mp_ioapic_routing[idx].gsi_end = gsi_base +
945 io_apic_get_redir_entries(idx);
946
947 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
948 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
949 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
950 mp_ioapic_routing[idx].gsi_base,
951 mp_ioapic_routing[idx].gsi_end);
952
953 return;
954 }
955
956
957 void __init mp_override_legacy_irq (
958 u8 bus_irq,
959 u8 polarity,
960 u8 trigger,
961 u32 gsi)
962 {
963 struct mpc_config_intsrc intsrc;
964 int ioapic = -1;
965 int pin = -1;
966
967 /*
968 * Convert 'gsi' to 'ioapic.pin'.
969 */
970 ioapic = mp_find_ioapic(gsi);
971 if (ioapic < 0)
972 return;
973 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
974
975 /*
976 * TBD: This check is for faulty timer entries, where the override
977 * erroneously sets the trigger to level, resulting in a HUGE
978 * increase of timer interrupts!
979 */
980 if ((bus_irq == 0) && (trigger == 3))
981 trigger = 1;
982
983 intsrc.mpc_type = MP_INTSRC;
984 intsrc.mpc_irqtype = mp_INT;
985 intsrc.mpc_irqflag = (trigger << 2) | polarity;
986 intsrc.mpc_srcbus = MP_ISA_BUS;
987 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
988 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
989 intsrc.mpc_dstirq = pin; /* INTIN# */
990
991 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
992 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
993 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
994 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
995
996 mp_irqs[mp_irq_entries] = intsrc;
997 if (++mp_irq_entries == MAX_IRQ_SOURCES)
998 panic("Max # of irq sources exceeded!\n");
999
1000 return;
1001 }
1002
1003 void __init mp_config_acpi_legacy_irqs (void)
1004 {
1005 struct mpc_config_intsrc intsrc;
1006 int i = 0;
1007 int ioapic = -1;
1008
1009 /*
1010 * Fabricate the legacy ISA bus (bus #31).
1011 */
1012 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1013 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1014
1015 /*
1016 * Older generations of ES7000 have no legacy identity mappings
1017 */
1018 if (es7000_plat == 1)
1019 return;
1020
1021 /*
1022 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1023 */
1024 ioapic = mp_find_ioapic(0);
1025 if (ioapic < 0)
1026 return;
1027
1028 intsrc.mpc_type = MP_INTSRC;
1029 intsrc.mpc_irqflag = 0; /* Conforming */
1030 intsrc.mpc_srcbus = MP_ISA_BUS;
1031 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1032
1033 /*
1034 * Use the default configuration for the IRQs 0-15. Unless
1035 * overriden by (MADT) interrupt source override entries.
1036 */
1037 for (i = 0; i < 16; i++) {
1038 int idx;
1039
1040 for (idx = 0; idx < mp_irq_entries; idx++) {
1041 struct mpc_config_intsrc *irq = mp_irqs + idx;
1042
1043 /* Do we already have a mapping for this ISA IRQ? */
1044 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1045 break;
1046
1047 /* Do we already have a mapping for this IOAPIC pin */
1048 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1049 (irq->mpc_dstirq == i))
1050 break;
1051 }
1052
1053 if (idx != mp_irq_entries) {
1054 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1055 continue; /* IRQ already used */
1056 }
1057
1058 intsrc.mpc_irqtype = mp_INT;
1059 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1060 intsrc.mpc_dstirq = i;
1061
1062 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1063 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1064 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1065 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1066 intsrc.mpc_dstirq);
1067
1068 mp_irqs[mp_irq_entries] = intsrc;
1069 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1070 panic("Max # of irq sources exceeded!\n");
1071 }
1072 }
1073
1074 #define MAX_GSI_NUM 4096
1075
1076 int mp_register_gsi (u32 gsi, int triggering, int polarity)
1077 {
1078 int ioapic = -1;
1079 int ioapic_pin = 0;
1080 int idx, bit = 0;
1081 static int pci_irq = 16;
1082 /*
1083 * Mapping between Global System Interrups, which
1084 * represent all possible interrupts, and IRQs
1085 * assigned to actual devices.
1086 */
1087 static int gsi_to_irq[MAX_GSI_NUM];
1088
1089 /* Don't set up the ACPI SCI because it's already set up */
1090 if (acpi_fadt.sci_int == gsi)
1091 return gsi;
1092
1093 ioapic = mp_find_ioapic(gsi);
1094 if (ioapic < 0) {
1095 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1096 return gsi;
1097 }
1098
1099 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1100
1101 if (ioapic_renumber_irq)
1102 gsi = ioapic_renumber_irq(ioapic, gsi);
1103
1104 /*
1105 * Avoid pin reprogramming. PRTs typically include entries
1106 * with redundant pin->gsi mappings (but unique PCI devices);
1107 * we only program the IOAPIC on the first.
1108 */
1109 bit = ioapic_pin % 32;
1110 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1111 if (idx > 3) {
1112 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1113 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1114 ioapic_pin);
1115 return gsi;
1116 }
1117 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1118 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1119 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1120 return gsi_to_irq[gsi];
1121 }
1122
1123 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1124
1125 if (triggering == ACPI_LEVEL_SENSITIVE) {
1126 /*
1127 * For PCI devices assign IRQs in order, avoiding gaps
1128 * due to unused I/O APIC pins.
1129 */
1130 int irq = gsi;
1131 if (gsi < MAX_GSI_NUM) {
1132 /*
1133 * Retain the VIA chipset work-around (gsi > 15), but
1134 * avoid a problem where the 8254 timer (IRQ0) is setup
1135 * via an override (so it's not on pin 0 of the ioapic),
1136 * and at the same time, the pin 0 interrupt is a PCI
1137 * type. The gsi > 15 test could cause these two pins
1138 * to be shared as IRQ0, and they are not shareable.
1139 * So test for this condition, and if necessary, avoid
1140 * the pin collision.
1141 */
1142 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1143 gsi = pci_irq++;
1144 /*
1145 * Don't assign IRQ used by ACPI SCI
1146 */
1147 if (gsi == acpi_fadt.sci_int)
1148 gsi = pci_irq++;
1149 gsi_to_irq[irq] = gsi;
1150 } else {
1151 printk(KERN_ERR "GSI %u is too high\n", gsi);
1152 return gsi;
1153 }
1154 }
1155
1156 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1157 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1158 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1159 return gsi;
1160 }
1161
1162 #endif /* CONFIG_X86_IO_APIC */
1163 #endif /* CONFIG_ACPI */
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