2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
37 void (*cpu_wait
)(void);
38 EXPORT_SYMBOL(cpu_wait
);
40 static void r3081_wait(void)
42 unsigned long cfg
= read_c0_conf();
43 write_c0_conf(cfg
| R30XX_CONF_HALT
);
46 static void r39xx_wait(void)
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
54 extern void r4k_wait(void);
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
63 void r4k_wait_irqoff(void)
67 __asm__(" .set push \n"
72 __asm__(" .globl __pastwait \n"
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
80 static void rm7k_wait_irqoff(void)
90 " mtc0 $1, $12 # stalls until W stage \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
102 static void au1k_wait(void)
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
115 : : "r" (au1k_wait
));
118 static int __initdata nowait
;
120 static int __init
wait_disable(char *s
)
127 __setup("nowait", wait_disable
);
129 static int __cpuinitdata mips_fpu_disabled
;
131 static int __init
fpu_disable(char *s
)
133 cpu_data
[0].options
&= ~MIPS_CPU_FPU
;
134 mips_fpu_disabled
= 1;
139 __setup("nofpu", fpu_disable
);
141 int __cpuinitdata mips_dsp_disabled
;
143 static int __init
dsp_disable(char *s
)
145 cpu_data
[0].ases
&= ~MIPS_ASE_DSP
;
146 mips_dsp_disabled
= 1;
151 __setup("nodsp", dsp_disable
);
153 void __init
check_wait(void)
155 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
158 printk("Wait instruction disabled.\n");
162 switch (c
->cputype
) {
165 cpu_wait
= r3081_wait
;
168 cpu_wait
= r39xx_wait
;
171 /* case CPU_R4300: */
189 case CPU_CAVIUM_OCTEON
:
190 case CPU_CAVIUM_OCTEON_PLUS
:
191 case CPU_CAVIUM_OCTEON2
:
199 cpu_wait
= rm7k_wait_irqoff
;
206 if (read_c0_config7() & MIPS_CONF7_WII
)
207 cpu_wait
= r4k_wait_irqoff
;
212 if ((c
->processor_id
& 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
213 cpu_wait
= r4k_wait_irqoff
;
217 cpu_wait
= r4k_wait_irqoff
;
220 cpu_wait
= au1k_wait
;
224 * WAIT on Rev1.0 has E1, E2, E3 and E16.
225 * WAIT on Rev2.0 and Rev3.0 has E16.
226 * Rev3.1 WAIT is nop, why bother
228 if ((c
->processor_id
& 0xff) <= 0x64)
232 * Another rev is incremeting c0_count at a reduced clock
233 * rate while in WAIT mode. So we basically have the choice
234 * between using the cp0 timer as clocksource or avoiding
235 * the WAIT instruction. Until more details are known,
236 * disable the use of WAIT for 20Kc entirely.
241 if ((c
->processor_id
& 0x00ff) >= 0x40)
249 static inline void check_errata(void)
251 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
253 switch (c
->cputype
) {
256 * Erratum "RPS May Cause Incorrect Instruction Execution"
257 * This code only handles VPE0, any SMP/SMTC/RTOS code
258 * making use of VPE1 will be responsable for that VPE.
260 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
261 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
268 void __init
check_bugs32(void)
274 * Probe whether cpu has config register by trying to play with
275 * alternate cache bit and see whether it matters.
276 * It's used by cpu_probe to distinguish between R3000A and R3081.
278 static inline int cpu_has_confreg(void)
280 #ifdef CONFIG_CPU_R3000
281 extern unsigned long r3k_cache_size(unsigned long);
282 unsigned long size1
, size2
;
283 unsigned long cfg
= read_c0_conf();
285 size1
= r3k_cache_size(ST0_ISC
);
286 write_c0_conf(cfg
^ R30XX_CONF_AC
);
287 size2
= r3k_cache_size(ST0_ISC
);
289 return size1
!= size2
;
295 static inline void set_elf_platform(int cpu
, const char *plat
)
298 __elf_platform
= plat
;
302 * Get the FPU Implementation/Revision.
304 static inline unsigned long cpu_get_fpu_id(void)
306 unsigned long tmp
, fpu_id
;
308 tmp
= read_c0_status();
310 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
311 write_c0_status(tmp
);
316 * Check the CPU has an FPU the official way.
318 static inline int __cpu_has_fpu(void)
320 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
323 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
325 #ifdef __NEED_VMBITS_PROBE
326 write_c0_entryhi(0x3fffffffffffe000ULL
);
327 back_to_back_c0_hazard();
328 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
332 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
335 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
337 switch (c
->processor_id
& 0xff00) {
339 c
->cputype
= CPU_R2000
;
340 __cpu_name
[cpu
] = "R2000";
341 c
->isa_level
= MIPS_CPU_ISA_I
;
342 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
345 c
->options
|= MIPS_CPU_FPU
;
349 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
) {
350 if (cpu_has_confreg()) {
351 c
->cputype
= CPU_R3081E
;
352 __cpu_name
[cpu
] = "R3081";
354 c
->cputype
= CPU_R3000A
;
355 __cpu_name
[cpu
] = "R3000A";
359 c
->cputype
= CPU_R3000
;
360 __cpu_name
[cpu
] = "R3000";
362 c
->isa_level
= MIPS_CPU_ISA_I
;
363 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
366 c
->options
|= MIPS_CPU_FPU
;
370 if (read_c0_config() & CONF_SC
) {
371 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
372 c
->cputype
= CPU_R4400PC
;
373 __cpu_name
[cpu
] = "R4400PC";
375 c
->cputype
= CPU_R4000PC
;
376 __cpu_name
[cpu
] = "R4000PC";
379 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
380 c
->cputype
= CPU_R4400SC
;
381 __cpu_name
[cpu
] = "R4400SC";
383 c
->cputype
= CPU_R4000SC
;
384 __cpu_name
[cpu
] = "R4000SC";
388 c
->isa_level
= MIPS_CPU_ISA_III
;
389 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
390 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
394 case PRID_IMP_VR41XX
:
395 switch (c
->processor_id
& 0xf0) {
396 case PRID_REV_VR4111
:
397 c
->cputype
= CPU_VR4111
;
398 __cpu_name
[cpu
] = "NEC VR4111";
400 case PRID_REV_VR4121
:
401 c
->cputype
= CPU_VR4121
;
402 __cpu_name
[cpu
] = "NEC VR4121";
404 case PRID_REV_VR4122
:
405 if ((c
->processor_id
& 0xf) < 0x3) {
406 c
->cputype
= CPU_VR4122
;
407 __cpu_name
[cpu
] = "NEC VR4122";
409 c
->cputype
= CPU_VR4181A
;
410 __cpu_name
[cpu
] = "NEC VR4181A";
413 case PRID_REV_VR4130
:
414 if ((c
->processor_id
& 0xf) < 0x4) {
415 c
->cputype
= CPU_VR4131
;
416 __cpu_name
[cpu
] = "NEC VR4131";
418 c
->cputype
= CPU_VR4133
;
419 __cpu_name
[cpu
] = "NEC VR4133";
423 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
424 c
->cputype
= CPU_VR41XX
;
425 __cpu_name
[cpu
] = "NEC Vr41xx";
428 c
->isa_level
= MIPS_CPU_ISA_III
;
429 c
->options
= R4K_OPTS
;
433 c
->cputype
= CPU_R4300
;
434 __cpu_name
[cpu
] = "R4300";
435 c
->isa_level
= MIPS_CPU_ISA_III
;
436 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
441 c
->cputype
= CPU_R4600
;
442 __cpu_name
[cpu
] = "R4600";
443 c
->isa_level
= MIPS_CPU_ISA_III
;
444 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
451 * This processor doesn't have an MMU, so it's not
452 * "real easy" to run Linux on it. It is left purely
453 * for documentation. Commented out because it shares
454 * it's c0_prid id number with the TX3900.
456 c
->cputype
= CPU_R4650
;
457 __cpu_name
[cpu
] = "R4650";
458 c
->isa_level
= MIPS_CPU_ISA_III
;
459 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
464 c
->isa_level
= MIPS_CPU_ISA_I
;
465 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
467 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
468 c
->cputype
= CPU_TX3927
;
469 __cpu_name
[cpu
] = "TX3927";
472 switch (c
->processor_id
& 0xff) {
473 case PRID_REV_TX3912
:
474 c
->cputype
= CPU_TX3912
;
475 __cpu_name
[cpu
] = "TX3912";
478 case PRID_REV_TX3922
:
479 c
->cputype
= CPU_TX3922
;
480 __cpu_name
[cpu
] = "TX3922";
487 c
->cputype
= CPU_R4700
;
488 __cpu_name
[cpu
] = "R4700";
489 c
->isa_level
= MIPS_CPU_ISA_III
;
490 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
495 c
->cputype
= CPU_TX49XX
;
496 __cpu_name
[cpu
] = "R49XX";
497 c
->isa_level
= MIPS_CPU_ISA_III
;
498 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
499 if (!(c
->processor_id
& 0x08))
500 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
504 c
->cputype
= CPU_R5000
;
505 __cpu_name
[cpu
] = "R5000";
506 c
->isa_level
= MIPS_CPU_ISA_IV
;
507 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
512 c
->cputype
= CPU_R5432
;
513 __cpu_name
[cpu
] = "R5432";
514 c
->isa_level
= MIPS_CPU_ISA_IV
;
515 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
516 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
520 c
->cputype
= CPU_R5500
;
521 __cpu_name
[cpu
] = "R5500";
522 c
->isa_level
= MIPS_CPU_ISA_IV
;
523 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
524 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
527 case PRID_IMP_NEVADA
:
528 c
->cputype
= CPU_NEVADA
;
529 __cpu_name
[cpu
] = "Nevada";
530 c
->isa_level
= MIPS_CPU_ISA_IV
;
531 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
532 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
536 c
->cputype
= CPU_R6000
;
537 __cpu_name
[cpu
] = "R6000";
538 c
->isa_level
= MIPS_CPU_ISA_II
;
539 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
543 case PRID_IMP_R6000A
:
544 c
->cputype
= CPU_R6000A
;
545 __cpu_name
[cpu
] = "R6000A";
546 c
->isa_level
= MIPS_CPU_ISA_II
;
547 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
551 case PRID_IMP_RM7000
:
552 c
->cputype
= CPU_RM7000
;
553 __cpu_name
[cpu
] = "RM7000";
554 c
->isa_level
= MIPS_CPU_ISA_IV
;
555 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
558 * Undocumented RM7000: Bit 29 in the info register of
559 * the RM7000 v2.0 indicates if the TLB has 48 or 64
562 * 29 1 => 64 entry JTLB
565 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
567 case PRID_IMP_RM9000
:
568 c
->cputype
= CPU_RM9000
;
569 __cpu_name
[cpu
] = "RM9000";
570 c
->isa_level
= MIPS_CPU_ISA_IV
;
571 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
574 * Bit 29 in the info register of the RM9000
575 * indicates if the TLB has 48 or 64 entries.
577 * 29 1 => 64 entry JTLB
580 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
583 c
->cputype
= CPU_R8000
;
584 __cpu_name
[cpu
] = "RM8000";
585 c
->isa_level
= MIPS_CPU_ISA_IV
;
586 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
587 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
589 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
591 case PRID_IMP_R10000
:
592 c
->cputype
= CPU_R10000
;
593 __cpu_name
[cpu
] = "R10000";
594 c
->isa_level
= MIPS_CPU_ISA_IV
;
595 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
596 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
597 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
601 case PRID_IMP_R12000
:
602 c
->cputype
= CPU_R12000
;
603 __cpu_name
[cpu
] = "R12000";
604 c
->isa_level
= MIPS_CPU_ISA_IV
;
605 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
606 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
607 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
611 case PRID_IMP_R14000
:
612 c
->cputype
= CPU_R14000
;
613 __cpu_name
[cpu
] = "R14000";
614 c
->isa_level
= MIPS_CPU_ISA_IV
;
615 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
616 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
617 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
621 case PRID_IMP_LOONGSON2
:
622 c
->cputype
= CPU_LOONGSON2
;
623 __cpu_name
[cpu
] = "ICT Loongson-2";
625 switch (c
->processor_id
& PRID_REV_MASK
) {
626 case PRID_REV_LOONGSON2E
:
627 set_elf_platform(cpu
, "loongson2e");
629 case PRID_REV_LOONGSON2F
:
630 set_elf_platform(cpu
, "loongson2f");
634 c
->isa_level
= MIPS_CPU_ISA_III
;
635 c
->options
= R4K_OPTS
|
636 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
643 static char unknown_isa
[] __cpuinitdata
= KERN_ERR \
644 "Unsupported ISA type, c0.config0: %d.";
646 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
648 unsigned int config0
;
651 config0
= read_c0_config();
653 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
654 c
->options
|= MIPS_CPU_TLB
;
655 isa
= (config0
& MIPS_CONF_AT
) >> 13;
658 switch ((config0
& MIPS_CONF_AR
) >> 10) {
660 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
663 c
->isa_level
= MIPS_CPU_ISA_M32R2
;
670 switch ((config0
& MIPS_CONF_AR
) >> 10) {
672 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
675 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
685 return config0
& MIPS_CONF_M
;
688 panic(unknown_isa
, config0
);
691 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
693 unsigned int config1
;
695 config1
= read_c0_config1();
697 if (config1
& MIPS_CONF1_MD
)
698 c
->ases
|= MIPS_ASE_MDMX
;
699 if (config1
& MIPS_CONF1_WR
)
700 c
->options
|= MIPS_CPU_WATCH
;
701 if (config1
& MIPS_CONF1_CA
)
702 c
->ases
|= MIPS_ASE_MIPS16
;
703 if (config1
& MIPS_CONF1_EP
)
704 c
->options
|= MIPS_CPU_EJTAG
;
705 if (config1
& MIPS_CONF1_FP
) {
706 c
->options
|= MIPS_CPU_FPU
;
707 c
->options
|= MIPS_CPU_32FPR
;
710 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
712 return config1
& MIPS_CONF_M
;
715 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
717 unsigned int config2
;
719 config2
= read_c0_config2();
721 if (config2
& MIPS_CONF2_SL
)
722 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
724 return config2
& MIPS_CONF_M
;
727 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
729 unsigned int config3
;
731 config3
= read_c0_config3();
733 if (config3
& MIPS_CONF3_SM
)
734 c
->ases
|= MIPS_ASE_SMARTMIPS
;
735 if (config3
& MIPS_CONF3_DSP
)
736 c
->ases
|= MIPS_ASE_DSP
;
737 if (config3
& MIPS_CONF3_VINT
)
738 c
->options
|= MIPS_CPU_VINT
;
739 if (config3
& MIPS_CONF3_VEIC
)
740 c
->options
|= MIPS_CPU_VEIC
;
741 if (config3
& MIPS_CONF3_MT
)
742 c
->ases
|= MIPS_ASE_MIPSMT
;
743 if (config3
& MIPS_CONF3_ULRI
)
744 c
->options
|= MIPS_CPU_ULRI
;
746 return config3
& MIPS_CONF_M
;
749 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
751 unsigned int config4
;
753 config4
= read_c0_config4();
755 if ((config4
& MIPS_CONF4_MMUEXTDEF
) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
757 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
759 c
->kscratch_mask
= (config4
>> 16) & 0xff;
761 return config4
& MIPS_CONF_M
;
764 static void __cpuinit
decode_configs(struct cpuinfo_mips
*c
)
768 /* MIPS32 or MIPS64 compliant CPU. */
769 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
770 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
772 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
774 ok
= decode_config0(c
); /* Read Config registers. */
775 BUG_ON(!ok
); /* Arch spec violation! */
777 ok
= decode_config1(c
);
779 ok
= decode_config2(c
);
781 ok
= decode_config3(c
);
783 ok
= decode_config4(c
);
785 mips_probe_watch_registers(c
);
788 c
->core
= read_c0_ebase() & 0x3ff;
791 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
794 switch (c
->processor_id
& 0xff00) {
796 c
->cputype
= CPU_4KC
;
797 __cpu_name
[cpu
] = "MIPS 4Kc";
800 case PRID_IMP_4KECR2
:
801 c
->cputype
= CPU_4KEC
;
802 __cpu_name
[cpu
] = "MIPS 4KEc";
806 c
->cputype
= CPU_4KSC
;
807 __cpu_name
[cpu
] = "MIPS 4KSc";
810 c
->cputype
= CPU_5KC
;
811 __cpu_name
[cpu
] = "MIPS 5Kc";
814 c
->cputype
= CPU_20KC
;
815 __cpu_name
[cpu
] = "MIPS 20Kc";
819 c
->cputype
= CPU_24K
;
820 __cpu_name
[cpu
] = "MIPS 24Kc";
823 c
->cputype
= CPU_25KF
;
824 __cpu_name
[cpu
] = "MIPS 25Kc";
827 c
->cputype
= CPU_34K
;
828 __cpu_name
[cpu
] = "MIPS 34Kc";
831 c
->cputype
= CPU_74K
;
832 __cpu_name
[cpu
] = "MIPS 74Kc";
835 c
->cputype
= CPU_1004K
;
836 __cpu_name
[cpu
] = "MIPS 1004Kc";
843 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
846 switch (c
->processor_id
& 0xff00) {
847 case PRID_IMP_AU1_REV1
:
848 case PRID_IMP_AU1_REV2
:
849 c
->cputype
= CPU_ALCHEMY
;
850 switch ((c
->processor_id
>> 24) & 0xff) {
852 __cpu_name
[cpu
] = "Au1000";
855 __cpu_name
[cpu
] = "Au1500";
858 __cpu_name
[cpu
] = "Au1100";
861 __cpu_name
[cpu
] = "Au1550";
864 __cpu_name
[cpu
] = "Au1200";
865 if ((c
->processor_id
& 0xff) == 2)
866 __cpu_name
[cpu
] = "Au1250";
869 __cpu_name
[cpu
] = "Au1210";
872 __cpu_name
[cpu
] = "Au1xxx";
879 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
883 switch (c
->processor_id
& 0xff00) {
885 c
->cputype
= CPU_SB1
;
886 __cpu_name
[cpu
] = "SiByte SB1";
887 /* FPU in pass1 is known to have issues. */
888 if ((c
->processor_id
& 0xff) < 0x02)
889 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
892 c
->cputype
= CPU_SB1A
;
893 __cpu_name
[cpu
] = "SiByte SB1A";
898 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
901 switch (c
->processor_id
& 0xff00) {
902 case PRID_IMP_SR71000
:
903 c
->cputype
= CPU_SR71000
;
904 __cpu_name
[cpu
] = "Sandcraft SR71000";
911 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
914 switch (c
->processor_id
& 0xff00) {
915 case PRID_IMP_PR4450
:
916 c
->cputype
= CPU_PR4450
;
917 __cpu_name
[cpu
] = "Philips PR4450";
918 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
923 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
926 switch (c
->processor_id
& 0xff00) {
927 case PRID_IMP_BMIPS32_REV4
:
928 case PRID_IMP_BMIPS32_REV8
:
929 c
->cputype
= CPU_BMIPS32
;
930 __cpu_name
[cpu
] = "Broadcom BMIPS32";
931 set_elf_platform(cpu
, "bmips32");
933 case PRID_IMP_BMIPS3300
:
934 case PRID_IMP_BMIPS3300_ALT
:
935 case PRID_IMP_BMIPS3300_BUG
:
936 c
->cputype
= CPU_BMIPS3300
;
937 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
938 set_elf_platform(cpu
, "bmips3300");
940 case PRID_IMP_BMIPS43XX
: {
941 int rev
= c
->processor_id
& 0xff;
943 if (rev
>= PRID_REV_BMIPS4380_LO
&&
944 rev
<= PRID_REV_BMIPS4380_HI
) {
945 c
->cputype
= CPU_BMIPS4380
;
946 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
947 set_elf_platform(cpu
, "bmips4380");
949 c
->cputype
= CPU_BMIPS4350
;
950 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
951 set_elf_platform(cpu
, "bmips4350");
955 case PRID_IMP_BMIPS5000
:
956 c
->cputype
= CPU_BMIPS5000
;
957 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
958 set_elf_platform(cpu
, "bmips5000");
959 c
->options
|= MIPS_CPU_ULRI
;
964 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
967 switch (c
->processor_id
& 0xff00) {
968 case PRID_IMP_CAVIUM_CN38XX
:
969 case PRID_IMP_CAVIUM_CN31XX
:
970 case PRID_IMP_CAVIUM_CN30XX
:
971 c
->cputype
= CPU_CAVIUM_OCTEON
;
972 __cpu_name
[cpu
] = "Cavium Octeon";
974 case PRID_IMP_CAVIUM_CN58XX
:
975 case PRID_IMP_CAVIUM_CN56XX
:
976 case PRID_IMP_CAVIUM_CN50XX
:
977 case PRID_IMP_CAVIUM_CN52XX
:
978 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
979 __cpu_name
[cpu
] = "Cavium Octeon+";
981 set_elf_platform(cpu
, "octeon");
983 case PRID_IMP_CAVIUM_CN61XX
:
984 case PRID_IMP_CAVIUM_CN63XX
:
985 case PRID_IMP_CAVIUM_CN66XX
:
986 case PRID_IMP_CAVIUM_CN68XX
:
987 c
->cputype
= CPU_CAVIUM_OCTEON2
;
988 __cpu_name
[cpu
] = "Cavium Octeon II";
989 set_elf_platform(cpu
, "octeon2");
992 printk(KERN_INFO
"Unknown Octeon chip!\n");
993 c
->cputype
= CPU_UNKNOWN
;
998 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
1001 /* JZRISC does not implement the CP0 counter. */
1002 c
->options
&= ~MIPS_CPU_COUNTER
;
1003 switch (c
->processor_id
& 0xff00) {
1004 case PRID_IMP_JZRISC
:
1005 c
->cputype
= CPU_JZRISC
;
1006 __cpu_name
[cpu
] = "Ingenic JZRISC";
1009 panic("Unknown Ingenic Processor ID!");
1014 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
1018 if ((c
->processor_id
& 0xff00) == PRID_IMP_NETLOGIC_AU13XX
) {
1019 c
->cputype
= CPU_ALCHEMY
;
1020 __cpu_name
[cpu
] = "Au1300";
1021 /* following stuff is not for Alchemy */
1025 c
->options
= (MIPS_CPU_TLB
|
1033 switch (c
->processor_id
& 0xff00) {
1034 case PRID_IMP_NETLOGIC_XLP8XX
:
1035 case PRID_IMP_NETLOGIC_XLP3XX
:
1036 c
->cputype
= CPU_XLP
;
1037 __cpu_name
[cpu
] = "Netlogic XLP";
1040 case PRID_IMP_NETLOGIC_XLR732
:
1041 case PRID_IMP_NETLOGIC_XLR716
:
1042 case PRID_IMP_NETLOGIC_XLR532
:
1043 case PRID_IMP_NETLOGIC_XLR308
:
1044 case PRID_IMP_NETLOGIC_XLR532C
:
1045 case PRID_IMP_NETLOGIC_XLR516C
:
1046 case PRID_IMP_NETLOGIC_XLR508C
:
1047 case PRID_IMP_NETLOGIC_XLR308C
:
1048 c
->cputype
= CPU_XLR
;
1049 __cpu_name
[cpu
] = "Netlogic XLR";
1052 case PRID_IMP_NETLOGIC_XLS608
:
1053 case PRID_IMP_NETLOGIC_XLS408
:
1054 case PRID_IMP_NETLOGIC_XLS404
:
1055 case PRID_IMP_NETLOGIC_XLS208
:
1056 case PRID_IMP_NETLOGIC_XLS204
:
1057 case PRID_IMP_NETLOGIC_XLS108
:
1058 case PRID_IMP_NETLOGIC_XLS104
:
1059 case PRID_IMP_NETLOGIC_XLS616B
:
1060 case PRID_IMP_NETLOGIC_XLS608B
:
1061 case PRID_IMP_NETLOGIC_XLS416B
:
1062 case PRID_IMP_NETLOGIC_XLS412B
:
1063 case PRID_IMP_NETLOGIC_XLS408B
:
1064 case PRID_IMP_NETLOGIC_XLS404B
:
1065 c
->cputype
= CPU_XLR
;
1066 __cpu_name
[cpu
] = "Netlogic XLS";
1070 pr_info("Unknown Netlogic chip id [%02x]!\n",
1072 c
->cputype
= CPU_XLR
;
1076 if (c
->cputype
== CPU_XLP
) {
1077 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
1078 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
1079 /* This will be updated again after all threads are woken up */
1080 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
1082 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
1083 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
1088 /* For use by uaccess.h */
1090 EXPORT_SYMBOL(__ua_limit
);
1093 const char *__cpu_name
[NR_CPUS
];
1094 const char *__elf_platform
;
1096 __cpuinit
void cpu_probe(void)
1098 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1099 unsigned int cpu
= smp_processor_id();
1101 c
->processor_id
= PRID_IMP_UNKNOWN
;
1102 c
->fpu_id
= FPIR_IMP_NONE
;
1103 c
->cputype
= CPU_UNKNOWN
;
1105 c
->processor_id
= read_c0_prid();
1106 switch (c
->processor_id
& 0xff0000) {
1107 case PRID_COMP_LEGACY
:
1108 cpu_probe_legacy(c
, cpu
);
1110 case PRID_COMP_MIPS
:
1111 cpu_probe_mips(c
, cpu
);
1113 case PRID_COMP_ALCHEMY
:
1114 cpu_probe_alchemy(c
, cpu
);
1116 case PRID_COMP_SIBYTE
:
1117 cpu_probe_sibyte(c
, cpu
);
1119 case PRID_COMP_BROADCOM
:
1120 cpu_probe_broadcom(c
, cpu
);
1122 case PRID_COMP_SANDCRAFT
:
1123 cpu_probe_sandcraft(c
, cpu
);
1126 cpu_probe_nxp(c
, cpu
);
1128 case PRID_COMP_CAVIUM
:
1129 cpu_probe_cavium(c
, cpu
);
1131 case PRID_COMP_INGENIC
:
1132 cpu_probe_ingenic(c
, cpu
);
1134 case PRID_COMP_NETLOGIC
:
1135 cpu_probe_netlogic(c
, cpu
);
1139 BUG_ON(!__cpu_name
[cpu
]);
1140 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1143 * Platform code can force the cpu type to optimize code
1144 * generation. In that case be sure the cpu type is correctly
1145 * manually setup otherwise it could trigger some nasty bugs.
1147 BUG_ON(current_cpu_type() != c
->cputype
);
1149 if (mips_fpu_disabled
)
1150 c
->options
&= ~MIPS_CPU_FPU
;
1152 if (mips_dsp_disabled
)
1153 c
->ases
&= ~MIPS_ASE_DSP
;
1155 if (c
->options
& MIPS_CPU_FPU
) {
1156 c
->fpu_id
= cpu_get_fpu_id();
1158 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1159 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
1160 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
1161 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
1162 if (c
->fpu_id
& MIPS_FPIR_3D
)
1163 c
->ases
|= MIPS_ASE_MIPS3D
;
1167 if (cpu_has_mips_r2
)
1168 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1172 cpu_probe_vmbits(c
);
1176 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
1180 __cpuinit
void cpu_report(void)
1182 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1184 printk(KERN_INFO
"CPU revision is: %08x (%s)\n",
1185 c
->processor_id
, cpu_name_string());
1186 if (c
->options
& MIPS_CPU_FPU
)
1187 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);