| blob | 338d5f67ef0d88dafe9d562bc37f36afd8eca0b6 |
1 /*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/delay.h>
26 #include <plat/common.h>
27 #include <plat/prcm.h>
28 #include <plat/irqs.h>
29 #include <plat/control.h>
41 #define MAX_MODULE_ENABLE_WAIT 100000
44 u32 control_padconf_sys_nirq;
45 u32 iva2_cm_clksel1;
46 u32 iva2_cm_clksel2;
47 u32 cm_sysconfig;
48 u32 sgx_cm_clksel;
49 u32 dss_cm_clksel;
50 u32 cam_cm_clksel;
51 u32 per_cm_clksel;
52 u32 emu_cm_clksel;
53 u32 emu_cm_clkstctrl;
54 u32 pll_cm_autoidle2;
55 u32 pll_cm_clksel4;
56 u32 pll_cm_clksel5;
57 u32 pll_cm_clken2;
58 u32 cm_polctrl;
59 u32 iva2_cm_fclken;
60 u32 iva2_cm_clken_pll;
61 u32 core_cm_fclken1;
62 u32 core_cm_fclken3;
63 u32 sgx_cm_fclken;
64 u32 wkup_cm_fclken;
65 u32 dss_cm_fclken;
66 u32 cam_cm_fclken;
67 u32 per_cm_fclken;
68 u32 usbhost_cm_fclken;
69 u32 core_cm_iclken1;
70 u32 core_cm_iclken2;
71 u32 core_cm_iclken3;
72 u32 sgx_cm_iclken;
73 u32 wkup_cm_iclken;
74 u32 dss_cm_iclken;
75 u32 cam_cm_iclken;
76 u32 per_cm_iclken;
77 u32 usbhost_cm_iclken;
78 u32 iva2_cm_autiidle2;
79 u32 mpu_cm_autoidle2;
80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119 };
124 {
125 /* XXX This presumably needs modification for 34XX */
130 }
133 /* Resets clock rates and reboots the system. Only called from system.h */
135 {
136 s16 prcm_offs;
143 u32 l;
147 /* Reserve the first word in scratchpad for communicating
148 * with the boot ROM. A pointer to a data structure
149 * describing the boot process can be stored there,
150 * cf. OMAP34xx TRM, Initialization / Software Booting
151 * Configuration. */
155 else
160 OMAP2_RM_RSTCTRL);
163 OMAP4_RM_RSTCTRL);
164 }
167 {
170 }
174 {
177 }
179 /* Read a register in a PRM module */
181 {
183 }
185 /* Write into a register in a PRM module */
187 {
189 }
191 /* Read-modify-write a register in a PRM module. Caller must lock */
193 {
194 u32 v;
202 }
204 /* Read a PRM register, AND it, and shift the result down to bit 0 */
206 {
207 u32 v;
214 }
216 /* Read a register in a CM module */
218 {
220 }
222 /* Write into a register in a CM module */
224 {
226 }
228 /* Read-modify-write a register in a CM module. Caller must lock */
230 {
231 u32 v;
239 }
241 /**
242 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
243 * @reg: physical address of module IDLEST register
244 * @mask: value to mask against to determine if the module is active
245 * @name: name of the clock (for printk)
246 *
247 * Returns 1 if the module indicated readiness in time, or 0 if it
248 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
249 */
251 {
255 /*
256 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
257 * 34xx reverses this, just to keep us on our toes
258 */
263 else
266 /* Wait for lock */
273 else
278 };
281 {
282 /* Static mapping, never released */
286 }
290 }
294 }
295 }
297 #ifdef CONFIG_ARCH_OMAP3
299 {
331 OMAP3430_CM_CLKEN_PLL);
378 OMAP2_CM_CLKSTCTRL);
389 OMAP2_CM_CLKSTCTRL);
417 OMAP3_CM_CLKOUT_CTRL_OFFSET);
419 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
450 }
453 {
455 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
457 CM_CLKSEL1);
459 CM_CLKSEL2);
462 CM_CLKSEL);
464 CM_CLKSEL);
466 CM_CLKSEL);
468 CM_CLKSEL);
470 CM_CLKSEL1);
472 OMAP2_CM_CLKSTCTRL);
474 CM_AUTOIDLE2);
476 OMAP3430ES2_CM_CLKSEL4);
478 OMAP3430ES2_CM_CLKSEL5);
480 OMAP3430ES2_CM_CLKEN2);
483 CM_FCLKEN);
485 OMAP3430_CM_CLKEN_PLL);
488 OMAP3430ES2_CM_FCLKEN3);
490 CM_FCLKEN);
493 CM_FCLKEN);
495 CM_FCLKEN);
497 CM_FCLKEN);
504 CM_ICLKEN);
507 CM_ICLKEN);
509 CM_ICLKEN);
511 CM_ICLKEN);
515 CM_AUTOIDLE2);
518 OMAP2_CM_CLKSTCTRL);
520 OMAP2_CM_CLKSTCTRL);
522 OMAP2_CM_CLKSTCTRL);
524 OMAP2_CM_CLKSTCTRL);
526 OMAP2_CM_CLKSTCTRL);
528 OMAP2_CM_CLKSTCTRL);
530 OMAP2_CM_CLKSTCTRL);
532 OMAP2_CM_CLKSTCTRL);
536 CM_AUTOIDLE1);
538 CM_AUTOIDLE2);
540 CM_AUTOIDLE3);
543 CM_AUTOIDLE);
545 CM_AUTOIDLE);
547 CM_AUTOIDLE);
551 OMAP3430_CM_SLEEPDEP);
553 OMAP3430_CM_SLEEPDEP);
555 OMAP3430_CM_SLEEPDEP);
557 OMAP3430_CM_SLEEPDEP);
561 OMAP3_CM_CLKOUT_CTRL_OFFSET);
563 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
565 PM_WKDEP);
567 PM_WKDEP);
569 PM_WKDEP);
571 PM_WKDEP);
573 PM_WKDEP);
577 OMAP3430_PM_MPUGRPSEL1);
579 OMAP3430_PM_IVAGRPSEL1);
581 OMAP3430ES2_PM_MPUGRPSEL3);
583 OMAP3430ES2_PM_IVAGRPSEL3);
585 OMAP3430_PM_MPUGRPSEL);
587 OMAP3430_PM_IVAGRPSEL);
589 OMAP3430_PM_MPUGRPSEL);
591 OMAP3430_PM_IVAGRPSEL);
594 }
595 #endif