arch/sh/include/asm/pgtable.h

   1 /*
   2  * This file contains the functions and defines necessary to modify and
   3  * use the SuperH page table tree.
   4  *
   5  * Copyright (C) 1999 Niibe Yutaka
   6  * Copyright (C) 2002 - 2007 Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General
   9  * Public License.  See the file "COPYING" in the main directory of this
  10  * archive for more details.
  11  */
  12 #ifndef __ASM_SH_PGTABLE_H
  13 #define __ASM_SH_PGTABLE_H
  14
  15 #include <asm/pgtable_nopmd.h>
  16 #include <asm/page.h>
  17
  18 #ifndef __ASSEMBLY__
  19 #include <asm/addrspace.h>
  20 #include <asm/fixmap.h>
  21
  22 /*
  23  * ZERO_PAGE is a global shared page that is always zero: used
  24  * for zero-mapped memory areas etc..
  25  */
  26 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
  27 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
  28
  29 #endif /* !__ASSEMBLY__ */
  30
  31 /*
  32  * Effective and physical address definitions, to aid with sign
  33  * extension.
  34  */
  35 #define NEFF            32
  36 #define NEFF_SIGN       (1LL << (NEFF - 1))
  37 #define NEFF_MASK       (-1LL << NEFF)
  38
  39 static inline unsigned long long neff_sign_extend(unsigned long val)
  40 {
  41         unsigned long long extended = val;
  42         return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
  43 }
  44
  45 #ifdef CONFIG_29BIT
  46 #define NPHYS           29
  47 #else
  48 #define NPHYS           32
  49 #endif
  50
  51 #define NPHYS_SIGN      (1LL << (NPHYS - 1))
  52 #define NPHYS_MASK      (-1LL << NPHYS)
  53
  54 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  55 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  56
  57 /* Entries per level */
  58 #define PTRS_PER_PTE    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
  59
  60 #define FIRST_USER_ADDRESS      0
  61
  62 #define PHYS_ADDR_MASK29                0x1fffffff
  63 #define PHYS_ADDR_MASK32                0xffffffff
  64
  65 #ifdef CONFIG_PMB
  66 static inline unsigned long phys_addr_mask(void)
  67 {
  68         /* Is the MMU in 29bit mode? */
  69         if (__in_29bit_mode())
  70                 return PHYS_ADDR_MASK29;
  71
  72         return PHYS_ADDR_MASK32;
  73 }
  74 #elif defined(CONFIG_32BIT)
  75 static inline unsigned long phys_addr_mask(void)
  76 {
  77         return PHYS_ADDR_MASK32;
  78 }
  79 #else
  80 static inline unsigned long phys_addr_mask(void)
  81 {
  82         return PHYS_ADDR_MASK29;
  83 }
  84 #endif
  85
  86 #define PTE_PHYS_MASK           (phys_addr_mask() & PAGE_MASK)
  87 #define PTE_FLAGS_MASK          (~(PTE_PHYS_MASK) << PAGE_SHIFT)
  88
  89 #ifdef CONFIG_SUPERH32
  90 #define VMALLOC_START   (P3SEG)
  91 #else
  92 #define VMALLOC_START   (0xf0000000)
  93 #endif
  94 #define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
  95
  96 #if defined(CONFIG_SUPERH32)
  97 #include <asm/pgtable_32.h>
  98 #else
  99 #include <asm/pgtable_64.h>
 100 #endif
 101
 102 /*
 103  * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
 104  * protection for execute, and considers it the same as a read. Also, write
 105  * permission implies read permission. This is the closest we can get..
 106  *
 107  * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
 108  * not only supporting separate execute, read, and write bits, but having
 109  * completely separate permission bits for user and kernel space.
 110  */
 111          /*xwr*/
 112 #define __P000  PAGE_NONE
 113 #define __P001  PAGE_READONLY
 114 #define __P010  PAGE_COPY
 115 #define __P011  PAGE_COPY
 116 #define __P100  PAGE_EXECREAD
 117 #define __P101  PAGE_EXECREAD
 118 #define __P110  PAGE_COPY
 119 #define __P111  PAGE_COPY
 120
 121 #define __S000  PAGE_NONE
 122 #define __S001  PAGE_READONLY
 123 #define __S010  PAGE_WRITEONLY
 124 #define __S011  PAGE_SHARED
 125 #define __S100  PAGE_EXECREAD
 126 #define __S101  PAGE_EXECREAD
 127 #define __S110  PAGE_RWX
 128 #define __S111  PAGE_RWX
 129
 130 typedef pte_t *pte_addr_t;
 131
 132 #define kern_addr_valid(addr)   (1)
 133
 134 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 135                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 136
 137 #define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
 138
 139 /*
 140  * No page table caches to initialise
 141  */
 142 #define pgtable_cache_init()    do { } while (0)
 143
 144 struct vm_area_struct;
 145
 146 extern void __update_cache(struct vm_area_struct *vma,
 147                            unsigned long address, pte_t pte);
 148 extern void __update_tlb(struct vm_area_struct *vma,
 149                          unsigned long address, pte_t pte);
 150
 151 static inline void
 152 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 153 {
 154         __update_cache(vma, address, pte);
 155         __update_tlb(vma, address, pte);
 156 }
 157
 158 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 159 extern void paging_init(void);
 160 extern void page_table_range_init(unsigned long start, unsigned long end,
 161                                   pgd_t *pgd);
 162
 163 /* arch/sh/mm/mmap.c */
 164 #define HAVE_ARCH_UNMAPPED_AREA
 165 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 166
 167 #include <asm-generic/pgtable.h>
 168
 169 #endif /* __ASM_SH_PGTABLE_H */