arch/arm/mach-shmobile/clock-sh7372.c

   1 /*
   2  * SH7372 clock framework support
   3  *
   4  * Copyright (C) 2010 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/io.h>
  22 #include <linux/sh_clk.h>
  23 #include <mach/common.h>
  24 #include <asm/clkdev.h>
  25
  26 /* SH7372 registers */
  27 #define FRQCRA          0xe6150000
  28 #define FRQCRB          0xe6150004
  29 #define FRQCRC          0xe61500e0
  30 #define FRQCRD          0xe61500e4
  31 #define VCLKCR1         0xe6150008
  32 #define VCLKCR2         0xe615000c
  33 #define VCLKCR3         0xe615001c
  34 #define FMSICKCR        0xe6150010
  35 #define FMSOCKCR        0xe6150014
  36 #define FSIACKCR        0xe6150018
  37 #define FSIBCKCR        0xe6150090
  38 #define SUBCKCR         0xe6150080
  39 #define SPUCKCR         0xe6150084
  40 #define VOUCKCR         0xe6150088
  41 #define HDMICKCR        0xe6150094
  42 #define DSITCKCR        0xe6150060
  43 #define DSI0PCKCR       0xe6150064
  44 #define DSI1PCKCR       0xe6150098
  45 #define PLLC01CR        0xe6150028
  46 #define PLLC2CR         0xe615002c
  47 #define SMSTPCR0        0xe6150130
  48 #define SMSTPCR1        0xe6150134
  49 #define SMSTPCR2        0xe6150138
  50 #define SMSTPCR3        0xe615013c
  51 #define SMSTPCR4        0xe6150140
  52
  53 #define FSIDIVA         0xFE1F8000
  54 #define FSIDIVB         0xFE1F8008
  55
  56 /* Platforms must set frequency on their DV_CLKI pin */
  57 struct clk sh7372_dv_clki_clk = {
  58 };
  59
  60 /* Fixed 32 KHz root clock from EXTALR pin */
  61 static struct clk r_clk = {
  62         .rate           = 32768,
  63 };
  64
  65 /*
  66  * 26MHz default rate for the EXTAL1 root input clock.
  67  * If needed, reset this with clk_set_rate() from the platform code.
  68  */
  69 struct clk sh7372_extal1_clk = {
  70         .rate           = 26000000,
  71 };
  72
  73 /*
  74  * 48MHz default rate for the EXTAL2 root input clock.
  75  * If needed, reset this with clk_set_rate() from the platform code.
  76  */
  77 struct clk sh7372_extal2_clk = {
  78         .rate           = 48000000,
  79 };
  80
  81 /* A fixed divide-by-2 block */
  82 static unsigned long div2_recalc(struct clk *clk)
  83 {
  84         return clk->parent->rate / 2;
  85 }
  86
  87 static struct clk_ops div2_clk_ops = {
  88         .recalc         = div2_recalc,
  89 };
  90
  91 /* Divide dv_clki by two */
  92 struct clk sh7372_dv_clki_div2_clk = {
  93         .ops            = &div2_clk_ops,
  94         .parent         = &sh7372_dv_clki_clk,
  95 };
  96
  97 /* Divide extal1 by two */
  98 static struct clk extal1_div2_clk = {
  99         .ops            = &div2_clk_ops,
 100         .parent         = &sh7372_extal1_clk,
 101 };
 102
 103 /* Divide extal2 by two */
 104 static struct clk extal2_div2_clk = {
 105         .ops            = &div2_clk_ops,
 106         .parent         = &sh7372_extal2_clk,
 107 };
 108
 109 /* Divide extal2 by four */
 110 static struct clk extal2_div4_clk = {
 111         .ops            = &div2_clk_ops,
 112         .parent         = &extal2_div2_clk,
 113 };
 114
 115 /* PLLC0 and PLLC1 */
 116 static unsigned long pllc01_recalc(struct clk *clk)
 117 {
 118         unsigned long mult = 1;
 119
 120         if (__raw_readl(PLLC01CR) & (1 << 14))
 121                 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
 122
 123         return clk->parent->rate * mult;
 124 }
 125
 126 static struct clk_ops pllc01_clk_ops = {
 127         .recalc         = pllc01_recalc,
 128 };
 129
 130 static struct clk pllc0_clk = {
 131         .ops            = &pllc01_clk_ops,
 132         .flags          = CLK_ENABLE_ON_INIT,
 133         .parent         = &extal1_div2_clk,
 134         .enable_reg     = (void __iomem *)FRQCRC,
 135 };
 136
 137 static struct clk pllc1_clk = {
 138         .ops            = &pllc01_clk_ops,
 139         .flags          = CLK_ENABLE_ON_INIT,
 140         .parent         = &extal1_div2_clk,
 141         .enable_reg     = (void __iomem *)FRQCRA,
 142 };
 143
 144 /* Divide PLLC1 by two */
 145 static struct clk pllc1_div2_clk = {
 146         .ops            = &div2_clk_ops,
 147         .parent         = &pllc1_clk,
 148 };
 149
 150 /* PLLC2 */
 151
 152 /* Indices are important - they are the actual src selecting values */
 153 static struct clk *pllc2_parent[] = {
 154         [0] = &extal1_div2_clk,
 155         [1] = &extal2_div2_clk,
 156         [2] = &sh7372_dv_clki_div2_clk,
 157 };
 158
 159 /* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
 160 static struct cpufreq_frequency_table pllc2_freq_table[29];
 161
 162 static void pllc2_table_rebuild(struct clk *clk)
 163 {
 164         int i;
 165
 166         /* Initialise PLLC2 frequency table */
 167         for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
 168                 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
 169                 pllc2_freq_table[i].index = i;
 170         }
 171
 172         /* This is a special entry - switching PLL off makes it a repeater */
 173         pllc2_freq_table[i].frequency = clk->parent->rate;
 174         pllc2_freq_table[i].index = i;
 175
 176         pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
 177         pllc2_freq_table[i].index = i;
 178 }
 179
 180 static unsigned long pllc2_recalc(struct clk *clk)
 181 {
 182         unsigned long mult = 1;
 183
 184         pllc2_table_rebuild(clk);
 185
 186         /*
 187          * If the PLL is off, mult == 1, clk->rate will be updated in
 188          * pllc2_enable().
 189          */
 190         if (__raw_readl(PLLC2CR) & (1 << 31))
 191                 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
 192
 193         return clk->parent->rate * mult;
 194 }
 195
 196 static long pllc2_round_rate(struct clk *clk, unsigned long rate)
 197 {
 198         return clk_rate_table_round(clk, clk->freq_table, rate);
 199 }
 200
 201 static int pllc2_enable(struct clk *clk)
 202 {
 203         int i;
 204
 205         __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
 206
 207         for (i = 0; i < 100; i++)
 208                 if (__raw_readl(PLLC2CR) & 0x80000000) {
 209                         clk->rate = pllc2_recalc(clk);
 210                         return 0;
 211                 }
 212
 213         pr_err("%s(): timeout!\n", __func__);
 214
 215         return -ETIMEDOUT;
 216 }
 217
 218 static void pllc2_disable(struct clk *clk)
 219 {
 220         __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
 221 }
 222
 223 static int pllc2_set_rate(struct clk *clk,
 224                           unsigned long rate, int algo_id)
 225 {
 226         unsigned long value;
 227         int idx;
 228
 229         idx = clk_rate_table_find(clk, clk->freq_table, rate);
 230         if (idx < 0)
 231                 return idx;
 232
 233         if (rate == clk->parent->rate) {
 234                 pllc2_disable(clk);
 235                 return 0;
 236         }
 237
 238         value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
 239
 240         if (value & 0x80000000)
 241                 pllc2_disable(clk);
 242
 243         __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
 244
 245         if (value & 0x80000000)
 246                 return pllc2_enable(clk);
 247
 248         return 0;
 249 }
 250
 251 static int pllc2_set_parent(struct clk *clk, struct clk *parent)
 252 {
 253         u32 value;
 254         int ret, i;
 255
 256         if (!clk->parent_table || !clk->parent_num)
 257                 return -EINVAL;
 258
 259         /* Search the parent */
 260         for (i = 0; i < clk->parent_num; i++)
 261                 if (clk->parent_table[i] == parent)
 262                         break;
 263
 264         if (i == clk->parent_num)
 265                 return -ENODEV;
 266
 267         ret = clk_reparent(clk, parent);
 268         if (ret < 0)
 269                 return ret;
 270
 271         value = __raw_readl(PLLC2CR) & ~(3 << 6);
 272
 273         __raw_writel(value | (i << 6), PLLC2CR);
 274
 275         /* Rebiuld the frequency table */
 276         pllc2_table_rebuild(clk);
 277
 278         return 0;
 279 }
 280
 281 static struct clk_ops pllc2_clk_ops = {
 282         .recalc         = pllc2_recalc,
 283         .round_rate     = pllc2_round_rate,
 284         .set_rate       = pllc2_set_rate,
 285         .enable         = pllc2_enable,
 286         .disable        = pllc2_disable,
 287         .set_parent     = pllc2_set_parent,
 288 };
 289
 290 struct clk sh7372_pllc2_clk = {
 291         .ops            = &pllc2_clk_ops,
 292         .parent         = &extal1_div2_clk,
 293         .freq_table     = pllc2_freq_table,
 294         .nr_freqs       = ARRAY_SIZE(pllc2_freq_table) - 1,
 295         .parent_table   = pllc2_parent,
 296         .parent_num     = ARRAY_SIZE(pllc2_parent),
 297 };
 298
 299 /* External input clock (pin name: FSIACK/FSIBCK ) */
 300 struct clk sh7372_fsiack_clk = {
 301 };
 302
 303 struct clk sh7372_fsibck_clk = {
 304 };
 305
 306 static struct clk *main_clks[] = {
 307         &sh7372_dv_clki_clk,
 308         &r_clk,
 309         &sh7372_extal1_clk,
 310         &sh7372_extal2_clk,
 311         &sh7372_dv_clki_div2_clk,
 312         &extal1_div2_clk,
 313         &extal2_div2_clk,
 314         &extal2_div4_clk,
 315         &pllc0_clk,
 316         &pllc1_clk,
 317         &pllc1_div2_clk,
 318         &sh7372_pllc2_clk,
 319         &sh7372_fsiack_clk,
 320         &sh7372_fsibck_clk,
 321 };
 322
 323 static void div4_kick(struct clk *clk)
 324 {
 325         unsigned long value;
 326
 327         /* set KICK bit in FRQCRB to update hardware setting */
 328         value = __raw_readl(FRQCRB);
 329         value |= (1 << 31);
 330         __raw_writel(value, FRQCRB);
 331 }
 332
 333 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
 334                           24, 32, 36, 48, 0, 72, 96, 0 };
 335
 336 static struct clk_div_mult_table div4_div_mult_table = {
 337         .divisors = divisors,
 338         .nr_divisors = ARRAY_SIZE(divisors),
 339 };
 340
 341 static struct clk_div4_table div4_table = {
 342         .div_mult_table = &div4_div_mult_table,
 343         .kick = div4_kick,
 344 };
 345
 346 enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
 347        DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
 348        DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
 349        DIV4_DDRP, DIV4_NR };
 350
 351 #define DIV4(_reg, _bit, _mask, _flags) \
 352   SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
 353
 354 static struct clk div4_clks[DIV4_NR] = {
 355         [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
 356         [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
 357         [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
 358         [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
 359         [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
 360         [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
 361         [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
 362         [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
 363         [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
 364         [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
 365         [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
 366         [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
 367         [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
 368         [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
 369         [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
 370 };
 371
 372 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
 373        DIV6_SUB, DIV6_SPU,
 374        DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
 375        DIV6_NR };
 376
 377 static struct clk div6_clks[DIV6_NR] = {
 378         [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
 379         [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
 380         [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
 381         [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
 382         [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
 383         [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
 384         [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
 385         [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
 386         [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
 387         [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
 388         [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
 389 };
 390
 391 enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
 392
 393 /* Indices are important - they are the actual src selecting values */
 394 static struct clk *hdmi_parent[] = {
 395         [0] = &pllc1_div2_clk,
 396         [1] = &sh7372_pllc2_clk,
 397         [2] = &sh7372_dv_clki_clk,
 398         [3] = NULL,     /* pllc2_div4 not implemented yet */
 399 };
 400
 401 static struct clk *fsiackcr_parent[] = {
 402         [0] = &pllc1_div2_clk,
 403         [1] = &sh7372_pllc2_clk,
 404         [2] = &sh7372_fsiack_clk, /* external input for FSI A */
 405         [3] = NULL,     /* setting prohibited */
 406 };
 407
 408 static struct clk *fsibckcr_parent[] = {
 409         [0] = &pllc1_div2_clk,
 410         [1] = &sh7372_pllc2_clk,
 411         [2] = &sh7372_fsibck_clk, /* external input for FSI B */
 412         [3] = NULL,     /* setting prohibited */
 413 };
 414
 415 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 416         [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
 417                                       hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
 418         [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
 419                                       fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
 420         [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
 421                                       fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
 422 };
 423
 424 /* FSI DIV */
 425 static unsigned long fsidiv_recalc(struct clk *clk)
 426 {
 427         unsigned long value;
 428
 429         value = __raw_readl(clk->mapping->base);
 430
 431         if ((value & 0x3) != 0x3)
 432                 return 0;
 433
 434         value >>= 16;
 435         if (value < 2)
 436                 return 0;
 437
 438         return clk->parent->rate / value;
 439 }
 440
 441 static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
 442 {
 443         return clk_rate_div_range_round(clk, 2, 0xffff, rate);
 444 }
 445
 446 static void fsidiv_disable(struct clk *clk)
 447 {
 448         __raw_writel(0, clk->mapping->base);
 449 }
 450
 451 static int fsidiv_enable(struct clk *clk)
 452 {
 453         unsigned long value;
 454
 455         value  = __raw_readl(clk->mapping->base) >> 16;
 456         if (value < 2) {
 457                 fsidiv_disable(clk);
 458                 return -ENOENT;
 459         }
 460
 461         __raw_writel((value << 16) | 0x3, clk->mapping->base);
 462
 463         return 0;
 464 }
 465
 466 static int fsidiv_set_rate(struct clk *clk,
 467                            unsigned long rate, int algo_id)
 468 {
 469         int idx;
 470
 471         if (clk->parent->rate == rate) {
 472                 fsidiv_disable(clk);
 473                 return 0;
 474         }
 475
 476         idx = (clk->parent->rate / rate) & 0xffff;
 477         if (idx < 2)
 478                 return -ENOENT;
 479
 480         __raw_writel(idx << 16, clk->mapping->base);
 481         return fsidiv_enable(clk);
 482 }
 483
 484 static struct clk_ops fsidiv_clk_ops = {
 485         .recalc         = fsidiv_recalc,
 486         .round_rate     = fsidiv_round_rate,
 487         .set_rate       = fsidiv_set_rate,
 488         .enable         = fsidiv_enable,
 489         .disable        = fsidiv_disable,
 490 };
 491
 492 static struct clk_mapping sh7372_fsidiva_clk_mapping = {
 493         .phys   = FSIDIVA,
 494         .len    = 8,
 495 };
 496
 497 struct clk sh7372_fsidiva_clk = {
 498         .ops            = &fsidiv_clk_ops,
 499         .parent         = &div6_reparent_clks[DIV6_FSIA], /* late install */
 500         .mapping        = &sh7372_fsidiva_clk_mapping,
 501 };
 502
 503 static struct clk_mapping sh7372_fsidivb_clk_mapping = {
 504         .phys   = FSIDIVB,
 505         .len    = 8,
 506 };
 507
 508 struct clk sh7372_fsidivb_clk = {
 509         .ops            = &fsidiv_clk_ops,
 510         .parent         = &div6_reparent_clks[DIV6_FSIB],  /* late install */
 511         .mapping        = &sh7372_fsidivb_clk_mapping,
 512 };
 513
 514 static struct clk *late_main_clks[] = {
 515         &sh7372_fsidiva_clk,
 516         &sh7372_fsidivb_clk,
 517 };
 518
 519 enum { MSTP001,
 520        MSTP131, MSTP130,
 521        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
 522        MSTP118, MSTP117, MSTP116,
 523        MSTP106, MSTP101, MSTP100,
 524        MSTP223,
 525        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
 526        MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
 527        MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
 528        MSTP_NR };
 529
 530 #define MSTP(_parent, _reg, _bit, _flags) \
 531   SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
 532
 533 static struct clk mstp_clks[MSTP_NR] = {
 534         [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
 535         [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
 536         [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
 537         [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
 538         [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
 539         [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
 540         [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
 541         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
 542         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
 543         [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
 544         [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
 545         [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
 546         [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
 547         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
 548         [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
 549         [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
 550         [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
 551         [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
 552         [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
 553         [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
 554         [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
 555         [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
 556         [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
 557         [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
 558         [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
 559         [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
 560         [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
 561         [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
 562         [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
 563         [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
 564         [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
 565         [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
 566         [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
 567         [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
 568         [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
 569 };
 570
 571 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 572 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
 573 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
 574
 575 static struct clk_lookup lookups[] = {
 576         /* main clocks */
 577         CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
 578         CLKDEV_CON_ID("r_clk", &r_clk),
 579         CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
 580         CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
 581         CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
 582         CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
 583         CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
 584         CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
 585         CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
 586         CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
 587         CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
 588
 589         /* DIV4 clocks */
 590         CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
 591         CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
 592         CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
 593         CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
 594         CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
 595         CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
 596         CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
 597         CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
 598         CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
 599         CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
 600         CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
 601         CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
 602         CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
 603         CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
 604         CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
 605
 606         /* DIV6 clocks */
 607         CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
 608         CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
 609         CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
 610         CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
 611         CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
 612         CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FSIA]),
 613         CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FSIB]),
 614         CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
 615         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
 616         CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
 617         CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
 618         CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
 619         CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
 620         CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
 621
 622         /* MSTP32 clocks */
 623         CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
 624         CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
 625         CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
 626         CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
 627         CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
 628         CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
 629         CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
 630         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
 631         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
 632         CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
 633         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
 634         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
 635         CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
 636         CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
 637         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
 638         CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
 639         CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
 640         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
 641         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
 642         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
 643         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
 644         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
 645         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
 646         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
 647         CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
 648         CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
 649         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
 650         CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
 651         CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */
 652         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
 653         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
 654         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
 655         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
 656         CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
 657         CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
 658         CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
 659         CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
 660         CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
 661         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
 662
 663         CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
 664         CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
 665         CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
 666 };
 667
 668 void __init sh7372_clock_init(void)
 669 {
 670         int k, ret = 0;
 671
 672         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 673                 ret = clk_register(main_clks[k]);
 674
 675         if (!ret)
 676                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 677
 678         if (!ret)
 679                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 680
 681         if (!ret)
 682                 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
 683
 684         if (!ret)
 685                 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 686
 687         for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
 688                 ret = clk_register(late_main_clks[k]);
 689
 690         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 691
 692         if (!ret)
 693                 clk_init();
 694         else
 695                 panic("failed to setup sh7372 clocks\n");
 696
 697 }