2 * OMAP3 powerdomain definitions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
16 #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
19 * N.B. If powerdomains are added or removed from this file, update
20 * the array in mach-omap2/powerdomains.h.
23 #include <plat/powerdomain.h>
25 #include "prcm-common.h"
27 #include "prm-regbits-34xx.h"
29 #include "cm-regbits-34xx.h"
32 * 34XX-specific powerdomains, dependencies
35 #ifdef CONFIG_ARCH_OMAP3
41 static struct powerdomain iva2_pwrdm
= {
43 .prcm_offs
= OMAP3430_IVA2_MOD
,
44 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
45 .pwrsts
= PWRSTS_OFF_RET_ON
,
46 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
62 static struct powerdomain mpu_3xxx_pwrdm
= {
65 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
66 .pwrsts
= PWRSTS_OFF_RET_ON
,
67 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
68 .flags
= PWRDM_HAS_MPU_QUIRK
,
79 * The USBTLL Save-and-Restore mechanism is broken on
80 * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
81 * needs to be disabled on these chips.
82 * Refer: 3430 errata ID i459 and 3630 errata ID i579
84 static struct powerdomain core_3xxx_pre_es3_1_pwrdm
= {
86 .prcm_offs
= CORE_MOD
,
87 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
89 CHIP_IS_OMAP3430ES3_0
|
91 .pwrsts
= PWRSTS_OFF_RET_ON
,
92 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
95 [0] = PWRSTS_OFF_RET
, /* MEM1RETSTATE */
96 [1] = PWRSTS_OFF_RET
, /* MEM2RETSTATE */
99 [0] = PWRSTS_OFF_RET_ON
, /* MEM1ONSTATE */
100 [1] = PWRSTS_OFF_RET_ON
, /* MEM2ONSTATE */
104 static struct powerdomain core_3xxx_es3_1_pwrdm
= {
105 .name
= "core_pwrdm",
106 .prcm_offs
= CORE_MOD
,
107 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1
|
108 CHIP_GE_OMAP3630ES1_1
),
109 .pwrsts
= PWRSTS_OFF_RET_ON
,
110 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
111 .flags
= PWRDM_HAS_HDWR_SAR
, /* for USBTLL only */
114 [0] = PWRSTS_OFF_RET
, /* MEM1RETSTATE */
115 [1] = PWRSTS_OFF_RET
, /* MEM2RETSTATE */
118 [0] = PWRSTS_OFF_RET_ON
, /* MEM1ONSTATE */
119 [1] = PWRSTS_OFF_RET_ON
, /* MEM2ONSTATE */
123 static struct powerdomain dss_pwrdm
= {
125 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
126 .prcm_offs
= OMAP3430_DSS_MOD
,
127 .pwrsts
= PWRSTS_OFF_RET_ON
,
128 .pwrsts_logic_ret
= PWRDM_POWER_RET
,
131 [0] = PWRDM_POWER_RET
, /* MEMRETSTATE */
134 [0] = PWRDM_POWER_ON
, /* MEMONSTATE */
139 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
140 * possible SGX powerstate, the SGX device itself does not support
143 static struct powerdomain sgx_pwrdm
= {
145 .prcm_offs
= OMAP3430ES2_SGX_MOD
,
146 .omap_chip
= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2
),
147 /* XXX This is accurate for 3430 SGX, but what about GFX? */
148 .pwrsts
= PWRSTS_OFF_ON
,
149 .pwrsts_logic_ret
= PWRDM_POWER_RET
,
152 [0] = PWRDM_POWER_RET
, /* MEMRETSTATE */
155 [0] = PWRDM_POWER_ON
, /* MEMONSTATE */
159 static struct powerdomain cam_pwrdm
= {
161 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
162 .prcm_offs
= OMAP3430_CAM_MOD
,
163 .pwrsts
= PWRSTS_OFF_RET_ON
,
164 .pwrsts_logic_ret
= PWRDM_POWER_RET
,
167 [0] = PWRDM_POWER_RET
, /* MEMRETSTATE */
170 [0] = PWRDM_POWER_ON
, /* MEMONSTATE */
174 static struct powerdomain per_pwrdm
= {
176 .prcm_offs
= OMAP3430_PER_MOD
,
177 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
178 .pwrsts
= PWRSTS_OFF_RET_ON
,
179 .pwrsts_logic_ret
= PWRSTS_OFF_RET
,
182 [0] = PWRDM_POWER_RET
, /* MEMRETSTATE */
185 [0] = PWRDM_POWER_ON
, /* MEMONSTATE */
189 static struct powerdomain emu_pwrdm
= {
191 .prcm_offs
= OMAP3430_EMU_MOD
,
192 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
195 static struct powerdomain neon_pwrdm
= {
196 .name
= "neon_pwrdm",
197 .prcm_offs
= OMAP3430_NEON_MOD
,
198 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
199 .pwrsts
= PWRSTS_OFF_RET_ON
,
200 .pwrsts_logic_ret
= PWRDM_POWER_RET
,
203 static struct powerdomain usbhost_pwrdm
= {
204 .name
= "usbhost_pwrdm",
205 .prcm_offs
= OMAP3430ES2_USBHOST_MOD
,
206 .omap_chip
= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2
),
207 .pwrsts
= PWRSTS_OFF_RET_ON
,
208 .pwrsts_logic_ret
= PWRDM_POWER_RET
,
210 * REVISIT: Enabling usb host save and restore mechanism seems to
211 * leave the usb host domain permanently in ACTIVE mode after
212 * changing the usb host power domain state from OFF to active once.
215 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
218 [0] = PWRDM_POWER_RET
, /* MEMRETSTATE */
221 [0] = PWRDM_POWER_ON
, /* MEMONSTATE */
225 static struct powerdomain dpll1_pwrdm
= {
226 .name
= "dpll1_pwrdm",
227 .prcm_offs
= MPU_MOD
,
228 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
231 static struct powerdomain dpll2_pwrdm
= {
232 .name
= "dpll2_pwrdm",
233 .prcm_offs
= OMAP3430_IVA2_MOD
,
234 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
237 static struct powerdomain dpll3_pwrdm
= {
238 .name
= "dpll3_pwrdm",
239 .prcm_offs
= PLL_MOD
,
240 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
243 static struct powerdomain dpll4_pwrdm
= {
244 .name
= "dpll4_pwrdm",
245 .prcm_offs
= PLL_MOD
,
246 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
249 static struct powerdomain dpll5_pwrdm
= {
250 .name
= "dpll5_pwrdm",
251 .prcm_offs
= PLL_MOD
,
252 .omap_chip
= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2
),
256 #endif /* CONFIG_ARCH_OMAP3 */