2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
29 #include "intel_drv.h"
33 #include "drm_crtc_helper.h"
35 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
58 #define INTEL_P2_NUM 2
61 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
65 #define I8XX_DOT_MIN 25000
66 #define I8XX_DOT_MAX 350000
67 #define I8XX_VCO_MIN 930000
68 #define I8XX_VCO_MAX 1400000
72 #define I8XX_M_MAX 140
73 #define I8XX_M1_MIN 18
74 #define I8XX_M1_MAX 26
76 #define I8XX_M2_MAX 16
78 #define I8XX_P_MAX 128
80 #define I8XX_P1_MAX 33
81 #define I8XX_P1_LVDS_MIN 1
82 #define I8XX_P1_LVDS_MAX 6
83 #define I8XX_P2_SLOW 4
84 #define I8XX_P2_FAST 2
85 #define I8XX_P2_LVDS_SLOW 14
86 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
87 #define I8XX_P2_SLOW_LIMIT 165000
89 #define I9XX_DOT_MIN 20000
90 #define I9XX_DOT_MAX 400000
91 #define I9XX_VCO_MIN 1400000
92 #define I9XX_VCO_MAX 2800000
96 #define I9XX_M_MAX 120
97 #define I9XX_M1_MIN 10
98 #define I9XX_M1_MAX 20
100 #define I9XX_M2_MAX 9
101 #define I9XX_P_SDVO_DAC_MIN 5
102 #define I9XX_P_SDVO_DAC_MAX 80
103 #define I9XX_P_LVDS_MIN 7
104 #define I9XX_P_LVDS_MAX 98
105 #define I9XX_P1_MIN 1
106 #define I9XX_P1_MAX 8
107 #define I9XX_P2_SDVO_DAC_SLOW 10
108 #define I9XX_P2_SDVO_DAC_FAST 5
109 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
110 #define I9XX_P2_LVDS_SLOW 14
111 #define I9XX_P2_LVDS_FAST 7
112 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
114 #define INTEL_LIMIT_I8XX_DVO_DAC 0
115 #define INTEL_LIMIT_I8XX_LVDS 1
116 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
117 #define INTEL_LIMIT_I9XX_LVDS 3
119 static const intel_limit_t intel_limits
[] = {
120 { /* INTEL_LIMIT_I8XX_DVO_DAC */
121 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
122 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
123 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
124 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
125 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
126 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
127 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
128 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
129 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
130 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
132 { /* INTEL_LIMIT_I8XX_LVDS */
133 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
134 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
135 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
136 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
137 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
138 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
139 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
140 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
141 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
142 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
144 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
145 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
146 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
147 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
148 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
149 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
150 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
151 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
152 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
153 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
154 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
156 { /* INTEL_LIMIT_I9XX_LVDS */
157 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
158 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
159 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
160 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
161 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
162 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
163 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
164 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
165 /* The single-channel range is 25-112Mhz, and dual-channel
166 * is 80-224Mhz. Prefer single channel as much as possible.
168 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
169 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
173 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
175 struct drm_device
*dev
= crtc
->dev
;
176 const intel_limit_t
*limit
;
179 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
180 limit
= &intel_limits
[INTEL_LIMIT_I9XX_LVDS
];
182 limit
= &intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
184 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
185 limit
= &intel_limits
[INTEL_LIMIT_I8XX_LVDS
];
187 limit
= &intel_limits
[INTEL_LIMIT_I8XX_DVO_DAC
];
192 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
194 static void i8xx_clock(int refclk
, intel_clock_t
*clock
)
196 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
197 clock
->p
= clock
->p1
* clock
->p2
;
198 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
199 clock
->dot
= clock
->vco
/ clock
->p
;
202 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
204 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
206 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
207 clock
->p
= clock
->p1
* clock
->p2
;
208 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
209 clock
->dot
= clock
->vco
/ clock
->p
;
212 static void intel_clock(struct drm_device
*dev
, int refclk
,
213 intel_clock_t
*clock
)
216 return i9xx_clock (refclk
, clock
);
218 return i8xx_clock (refclk
, clock
);
222 * Returns whether any output on the specified pipe is of the specified type
224 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
226 struct drm_device
*dev
= crtc
->dev
;
227 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
228 struct drm_connector
*l_entry
;
230 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
231 if (l_entry
->encoder
&&
232 l_entry
->encoder
->crtc
== crtc
) {
233 struct intel_output
*intel_output
= to_intel_output(l_entry
);
234 if (intel_output
->type
== type
)
241 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
243 * Returns whether the given set of divisors are valid for a given refclk with
244 * the given connectors.
247 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
249 const intel_limit_t
*limit
= intel_limit (crtc
);
251 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
252 INTELPllInvalid ("p1 out of range\n");
253 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
254 INTELPllInvalid ("p out of range\n");
255 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
256 INTELPllInvalid ("m2 out of range\n");
257 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
258 INTELPllInvalid ("m1 out of range\n");
259 if (clock
->m1
<= clock
->m2
)
260 INTELPllInvalid ("m1 <= m2\n");
261 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
262 INTELPllInvalid ("m out of range\n");
263 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
264 INTELPllInvalid ("n out of range\n");
265 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
266 INTELPllInvalid ("vco out of range\n");
267 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
268 * connector, etc., rather than just a single range.
270 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
271 INTELPllInvalid ("dot out of range\n");
277 * Returns a set of divisors for the desired target clock with the given
278 * refclk, or FALSE. The returned values represent the clock equation:
279 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
281 static bool intel_find_best_PLL(struct drm_crtc
*crtc
, int target
,
282 int refclk
, intel_clock_t
*best_clock
)
284 struct drm_device
*dev
= crtc
->dev
;
285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
287 const intel_limit_t
*limit
= intel_limit(crtc
);
290 if (IS_I9XX(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
291 (I915_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
293 * For LVDS, if the panel is on, just rely on its current
294 * settings for dual-channel. We haven't figured out how to
295 * reliably set up different single/dual channel state, if we
298 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
300 clock
.p2
= limit
->p2
.p2_fast
;
302 clock
.p2
= limit
->p2
.p2_slow
;
304 if (target
< limit
->p2
.dot_limit
)
305 clock
.p2
= limit
->p2
.p2_slow
;
307 clock
.p2
= limit
->p2
.p2_fast
;
310 memset (best_clock
, 0, sizeof (*best_clock
));
312 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
313 for (clock
.m2
= limit
->m2
.min
; clock
.m2
< clock
.m1
&&
314 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
315 for (clock
.n
= limit
->n
.min
; clock
.n
<= limit
->n
.max
;
317 for (clock
.p1
= limit
->p1
.min
;
318 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
321 intel_clock(dev
, refclk
, &clock
);
323 if (!intel_PLL_is_valid(crtc
, &clock
))
326 this_err
= abs(clock
.dot
- target
);
327 if (this_err
< err
) {
336 return (err
!= target
);
340 intel_wait_for_vblank(struct drm_device
*dev
)
342 /* Wait for 20ms, i.e. one cycle at 50hz. */
347 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
)
349 struct drm_device
*dev
= crtc
->dev
;
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 struct drm_i915_master_private
*master_priv
;
352 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
353 struct intel_framebuffer
*intel_fb
;
354 struct drm_i915_gem_object
*obj_priv
;
355 struct drm_gem_object
*obj
;
356 int pipe
= intel_crtc
->pipe
;
357 unsigned long Start
, Offset
;
358 int dspbase
= (pipe
== 0 ? DSPAADDR
: DSPBADDR
);
359 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
360 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
361 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
366 DRM_DEBUG("No FB bound\n");
370 intel_fb
= to_intel_framebuffer(crtc
->fb
);
373 obj_priv
= obj
->driver_private
;
375 Start
= obj_priv
->gtt_offset
;
376 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
378 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
380 dspcntr
= I915_READ(dspcntr_reg
);
381 switch (crtc
->fb
->bits_per_pixel
) {
383 dspcntr
|= DISPPLANE_8BPP
;
386 if (crtc
->fb
->depth
== 15)
387 dspcntr
|= DISPPLANE_15_16BPP
;
389 dspcntr
|= DISPPLANE_16BPP
;
393 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
396 DRM_ERROR("Unknown color depth\n");
399 I915_WRITE(dspcntr_reg
, dspcntr
);
401 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
403 I915_WRITE(dspbase
, Offset
);
405 I915_WRITE(dspsurf
, Start
);
408 I915_WRITE(dspbase
, Start
+ Offset
);
413 if (!dev
->primary
->master
)
416 master_priv
= dev
->primary
->master
->driver_priv
;
417 if (!master_priv
->sarea_priv
)
422 master_priv
->sarea_priv
->pipeA_x
= x
;
423 master_priv
->sarea_priv
->pipeA_y
= y
;
426 master_priv
->sarea_priv
->pipeB_x
= x
;
427 master_priv
->sarea_priv
->pipeB_y
= y
;
430 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
438 * Sets the power management mode of the pipe and plane.
440 * This code should probably grow support for turning the cursor off and back
441 * on appropriately at the same time as we're turning the pipe off/on.
443 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
445 struct drm_device
*dev
= crtc
->dev
;
446 struct drm_i915_master_private
*master_priv
;
447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
448 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
449 int pipe
= intel_crtc
->pipe
;
450 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
451 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
452 int dspbase_reg
= (pipe
== 0) ? DSPAADDR
: DSPBADDR
;
453 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
457 /* XXX: When our outputs are all unaware of DPMS modes other than off
458 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
461 case DRM_MODE_DPMS_ON
:
462 case DRM_MODE_DPMS_STANDBY
:
463 case DRM_MODE_DPMS_SUSPEND
:
464 /* Enable the DPLL */
465 temp
= I915_READ(dpll_reg
);
466 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
467 I915_WRITE(dpll_reg
, temp
);
469 /* Wait for the clocks to stabilize. */
471 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
473 /* Wait for the clocks to stabilize. */
475 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
477 /* Wait for the clocks to stabilize. */
481 /* Enable the pipe */
482 temp
= I915_READ(pipeconf_reg
);
483 if ((temp
& PIPEACONF_ENABLE
) == 0)
484 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
486 /* Enable the plane */
487 temp
= I915_READ(dspcntr_reg
);
488 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
489 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
490 /* Flush the plane changes */
491 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
494 intel_crtc_load_lut(crtc
);
496 /* Give the overlay scaler a chance to enable if it's on this pipe */
497 //intel_crtc_dpms_video(crtc, true); TODO
499 case DRM_MODE_DPMS_OFF
:
500 /* Give the overlay scaler a chance to disable if it's on this pipe */
501 //intel_crtc_dpms_video(crtc, FALSE); TODO
503 /* Disable the VGA plane that we never use */
504 I915_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
506 /* Disable display plane */
507 temp
= I915_READ(dspcntr_reg
);
508 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
509 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
510 /* Flush the plane changes */
511 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
512 I915_READ(dspbase_reg
);
516 /* Wait for vblank for the disable to take effect */
517 intel_wait_for_vblank(dev
);
520 /* Next, disable display pipes */
521 temp
= I915_READ(pipeconf_reg
);
522 if ((temp
& PIPEACONF_ENABLE
) != 0) {
523 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
524 I915_READ(pipeconf_reg
);
527 /* Wait for vblank for the disable to take effect. */
528 intel_wait_for_vblank(dev
);
530 temp
= I915_READ(dpll_reg
);
531 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
532 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
536 /* Wait for the clocks to turn off. */
541 if (!dev
->primary
->master
)
544 master_priv
= dev
->primary
->master
->driver_priv
;
545 if (!master_priv
->sarea_priv
)
548 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
552 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
553 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
556 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
557 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
560 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
564 intel_crtc
->dpms_mode
= mode
;
567 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
569 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
570 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
573 static void intel_crtc_commit (struct drm_crtc
*crtc
)
575 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
576 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
579 void intel_encoder_prepare (struct drm_encoder
*encoder
)
581 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
582 /* lvds has its own version of prepare see intel_lvds_prepare */
583 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
586 void intel_encoder_commit (struct drm_encoder
*encoder
)
588 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
589 /* lvds has its own version of commit see intel_lvds_commit */
590 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
593 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
594 struct drm_display_mode
*mode
,
595 struct drm_display_mode
*adjusted_mode
)
601 /** Returns the core display clock speed for i830 - i945 */
602 static int intel_get_core_clock_speed(struct drm_device
*dev
)
605 /* Core clock values taken from the published datasheets.
606 * The 830 may go up to 166 Mhz, which we should check.
610 else if (IS_I915G(dev
))
612 else if (IS_I945GM(dev
) || IS_845G(dev
))
614 else if (IS_I915GM(dev
)) {
617 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
619 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
622 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
623 case GC_DISPLAY_CLOCK_333_MHZ
:
626 case GC_DISPLAY_CLOCK_190_200_MHZ
:
630 } else if (IS_I865G(dev
))
632 else if (IS_I855(dev
)) {
634 /* Assume that the hardware is in the high speed state. This
635 * should be the default.
637 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
638 case GC_CLOCK_133_200
:
639 case GC_CLOCK_100_200
:
641 case GC_CLOCK_166_250
:
643 case GC_CLOCK_100_133
:
646 } else /* 852, 830 */
649 return 0; /* Silence gcc warning */
654 * Return the pipe currently connected to the panel fitter,
655 * or -1 if the panel fitter is not present or not in use
657 static int intel_panel_fitter_pipe (struct drm_device
*dev
)
659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
662 /* i830 doesn't have a panel fitter */
666 pfit_control
= I915_READ(PFIT_CONTROL
);
668 /* See if the panel fitter is in use */
669 if ((pfit_control
& PFIT_ENABLE
) == 0)
672 /* 965 can place panel fitter on either pipe */
674 return (pfit_control
>> 29) & 0x3;
676 /* older chips can only use pipe 1 */
680 static void intel_crtc_mode_set(struct drm_crtc
*crtc
,
681 struct drm_display_mode
*mode
,
682 struct drm_display_mode
*adjusted_mode
,
685 struct drm_device
*dev
= crtc
->dev
;
686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
687 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
688 int pipe
= intel_crtc
->pipe
;
689 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
690 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
691 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
692 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
693 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
694 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
695 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
696 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
697 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
698 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
699 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
700 int dspsize_reg
= (pipe
== 0) ? DSPASIZE
: DSPBSIZE
;
701 int dsppos_reg
= (pipe
== 0) ? DSPAPOS
: DSPBPOS
;
702 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
705 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
706 bool ok
, is_sdvo
= false, is_dvo
= false;
707 bool is_crt
= false, is_lvds
= false, is_tv
= false;
708 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
709 struct drm_connector
*connector
;
711 drm_vblank_pre_modeset(dev
, pipe
);
713 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
714 struct intel_output
*intel_output
= to_intel_output(connector
);
716 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
719 switch (intel_output
->type
) {
720 case INTEL_OUTPUT_LVDS
:
723 case INTEL_OUTPUT_SDVO
:
726 case INTEL_OUTPUT_DVO
:
729 case INTEL_OUTPUT_TVOUT
:
732 case INTEL_OUTPUT_ANALOG
:
744 ok
= intel_find_best_PLL(crtc
, adjusted_mode
->clock
, refclk
, &clock
);
746 DRM_ERROR("Couldn't find PLL settings for mode!\n");
750 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
752 dpll
= DPLL_VGA_MODE_DIS
;
755 dpll
|= DPLLB_MODE_LVDS
;
757 dpll
|= DPLLB_MODE_DAC_SERIAL
;
759 dpll
|= DPLL_DVO_HIGH_SPEED
;
760 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
761 int sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
762 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
766 /* compute bitmask from p1 value */
767 dpll
|= (1 << (clock
.p1
- 1)) << 16;
770 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
773 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
776 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
779 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
783 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
786 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
789 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
791 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
793 dpll
|= PLL_P2_DIVIDE_BY_4
;
798 /* XXX: just matching BIOS for now */
799 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
803 dpll
|= PLL_REF_INPUT_DREFCLK
;
806 pipeconf
= I915_READ(pipeconf_reg
);
808 /* Set up the display plane register */
809 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
812 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
814 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
816 if (pipe
== 0 && !IS_I965G(dev
)) {
817 /* Enable pixel doubling when the dot clock is > 90% of the (display)
820 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
823 if (mode
->clock
> intel_get_core_clock_speed(dev
) * 9 / 10)
824 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
826 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
829 dspcntr
|= DISPLAY_PLANE_ENABLE
;
830 pipeconf
|= PIPEACONF_ENABLE
;
831 dpll
|= DPLL_VCO_ENABLE
;
834 /* Disable the panel fitter if it was on our pipe */
835 if (intel_panel_fitter_pipe(dev
) == pipe
)
836 I915_WRITE(PFIT_CONTROL
, 0);
838 DRM_DEBUG("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
839 drm_mode_debug_printmodeline(mode
);
842 if (dpll
& DPLL_VCO_ENABLE
) {
843 I915_WRITE(fp_reg
, fp
);
844 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
849 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
850 * This is an exception to the general rule that mode_set doesn't turn
854 u32 lvds
= I915_READ(LVDS
);
856 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
| LVDS_PIPEB_SELECT
;
857 /* Set the B0-B3 data pairs corresponding to whether we're going to
858 * set the DPLLs for dual-channel mode or not.
861 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
863 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
865 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
866 * appropriately here, but we need to look more thoroughly into how
867 * panels behave in the two modes.
870 I915_WRITE(LVDS
, lvds
);
874 I915_WRITE(fp_reg
, fp
);
875 I915_WRITE(dpll_reg
, dpll
);
877 /* Wait for the clocks to stabilize. */
881 int sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
882 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
883 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
885 /* write it again -- the BIOS does, after all */
886 I915_WRITE(dpll_reg
, dpll
);
889 /* Wait for the clocks to stabilize. */
892 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
893 ((adjusted_mode
->crtc_htotal
- 1) << 16));
894 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
895 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
896 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
897 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
898 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
899 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
900 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
901 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
902 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
903 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
904 /* pipesrc and dspsize control the size that is scaled from, which should
905 * always be the user's requested size.
907 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
908 I915_WRITE(dsppos_reg
, 0);
909 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
910 I915_WRITE(pipeconf_reg
, pipeconf
);
911 I915_READ(pipeconf_reg
);
913 intel_wait_for_vblank(dev
);
915 I915_WRITE(dspcntr_reg
, dspcntr
);
917 /* Flush the plane changes */
918 intel_pipe_set_base(crtc
, x
, y
);
920 intel_wait_for_vblank(dev
);
922 drm_vblank_post_modeset(dev
, pipe
);
925 /** Loads the palette/gamma unit for the CRTC with the prepared values */
926 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
928 struct drm_device
*dev
= crtc
->dev
;
929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
930 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
931 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
934 /* The clocks have to be on to load the palette. */
938 for (i
= 0; i
< 256; i
++) {
939 I915_WRITE(palreg
+ 4 * i
,
940 (intel_crtc
->lut_r
[i
] << 16) |
941 (intel_crtc
->lut_g
[i
] << 8) |
942 intel_crtc
->lut_b
[i
]);
946 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
947 struct drm_file
*file_priv
,
949 uint32_t width
, uint32_t height
)
951 struct drm_device
*dev
= crtc
->dev
;
952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
953 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
954 struct drm_gem_object
*bo
;
955 struct drm_i915_gem_object
*obj_priv
;
956 int pipe
= intel_crtc
->pipe
;
957 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
958 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
964 /* if we want to turn off the cursor ignore width and height */
966 DRM_DEBUG("cursor off\n");
967 /* turn of the cursor */
969 temp
|= CURSOR_MODE_DISABLE
;
971 I915_WRITE(control
, temp
);
976 /* Currently we only support 64x64 cursors */
977 if (width
!= 64 || height
!= 64) {
978 DRM_ERROR("we currently only support 64x64 cursors\n");
982 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
986 obj_priv
= bo
->driver_private
;
988 if (bo
->size
< width
* height
* 4) {
989 DRM_ERROR("buffer is to small\n");
990 drm_gem_object_unreference(bo
);
994 if (dev_priv
->cursor_needs_physical
) {
995 addr
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
997 addr
= obj_priv
->gtt_offset
;
1000 intel_crtc
->cursor_addr
= addr
;
1002 /* set the pipe for the cursor */
1003 temp
|= (pipe
<< 28);
1004 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
1006 I915_WRITE(control
, temp
);
1007 I915_WRITE(base
, addr
);
1012 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1014 struct drm_device
*dev
= crtc
->dev
;
1015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1016 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1017 int pipe
= intel_crtc
->pipe
;
1022 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
1026 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
1030 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
1031 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1033 adder
= intel_crtc
->cursor_addr
;
1034 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
1035 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
1040 /** Sets the color ramps on behalf of RandR */
1041 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
1042 u16 blue
, int regno
)
1044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1046 intel_crtc
->lut_r
[regno
] = red
>> 8;
1047 intel_crtc
->lut_g
[regno
] = green
>> 8;
1048 intel_crtc
->lut_b
[regno
] = blue
>> 8;
1051 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
1052 u16
*blue
, uint32_t size
)
1054 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1060 for (i
= 0; i
< 256; i
++) {
1061 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
1062 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
1063 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1066 intel_crtc_load_lut(crtc
);
1070 * Get a pipe with a simple mode set on it for doing load-based monitor
1073 * It will be up to the load-detect code to adjust the pipe as appropriate for
1074 * its requirements. The pipe will be connected to no other outputs.
1076 * Currently this code will only succeed if there is a pipe with no outputs
1077 * configured for it. In the future, it could choose to temporarily disable
1078 * some outputs to free up a pipe for its use.
1080 * \return crtc, or NULL if no pipes are available.
1083 /* VESA 640x480x72Hz mode to set on the pipe */
1084 static struct drm_display_mode load_detect_mode
= {
1085 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
1086 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
1089 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_output
*intel_output
,
1090 struct drm_display_mode
*mode
,
1093 struct intel_crtc
*intel_crtc
;
1094 struct drm_crtc
*possible_crtc
;
1095 struct drm_crtc
*supported_crtc
=NULL
;
1096 struct drm_encoder
*encoder
= &intel_output
->enc
;
1097 struct drm_crtc
*crtc
= NULL
;
1098 struct drm_device
*dev
= encoder
->dev
;
1099 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1100 struct drm_crtc_helper_funcs
*crtc_funcs
;
1104 * Algorithm gets a little messy:
1105 * - if the connector already has an assigned crtc, use it (but make
1106 * sure it's on first)
1107 * - try to find the first unused crtc that can drive this connector,
1108 * and use that if we find one
1109 * - if there are no unused crtcs available, try to use the first
1110 * one we found that supports the connector
1113 /* See if we already have a CRTC for this connector */
1114 if (encoder
->crtc
) {
1115 crtc
= encoder
->crtc
;
1116 /* Make sure the crtc and connector are running */
1117 intel_crtc
= to_intel_crtc(crtc
);
1118 *dpms_mode
= intel_crtc
->dpms_mode
;
1119 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
1120 crtc_funcs
= crtc
->helper_private
;
1121 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1122 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
1127 /* Find an unused one (if possible) */
1128 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1130 if (!(encoder
->possible_crtcs
& (1 << i
)))
1132 if (!possible_crtc
->enabled
) {
1133 crtc
= possible_crtc
;
1136 if (!supported_crtc
)
1137 supported_crtc
= possible_crtc
;
1141 * If we didn't find an unused CRTC, don't use any.
1147 encoder
->crtc
= crtc
;
1148 intel_output
->load_detect_temp
= true;
1150 intel_crtc
= to_intel_crtc(crtc
);
1151 *dpms_mode
= intel_crtc
->dpms_mode
;
1153 if (!crtc
->enabled
) {
1155 mode
= &load_detect_mode
;
1156 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0);
1158 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
1159 crtc_funcs
= crtc
->helper_private
;
1160 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1163 /* Add this connector to the crtc */
1164 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
1165 encoder_funcs
->commit(encoder
);
1167 /* let the connector get through one full cycle before testing */
1168 intel_wait_for_vblank(dev
);
1173 void intel_release_load_detect_pipe(struct intel_output
*intel_output
, int dpms_mode
)
1175 struct drm_encoder
*encoder
= &intel_output
->enc
;
1176 struct drm_device
*dev
= encoder
->dev
;
1177 struct drm_crtc
*crtc
= encoder
->crtc
;
1178 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1179 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1181 if (intel_output
->load_detect_temp
) {
1182 encoder
->crtc
= NULL
;
1183 intel_output
->load_detect_temp
= false;
1184 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
1185 drm_helper_disable_unused_functions(dev
);
1188 /* Switch crtc and output back off if necessary */
1189 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
1190 if (encoder
->crtc
== crtc
)
1191 encoder_funcs
->dpms(encoder
, dpms_mode
);
1192 crtc_funcs
->dpms(crtc
, dpms_mode
);
1196 /* Returns the clock of the currently programmed mode of the given pipe. */
1197 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
1199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1201 int pipe
= intel_crtc
->pipe
;
1202 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
1204 intel_clock_t clock
;
1206 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1207 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
1209 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
1211 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
1212 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
1213 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
1215 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
1216 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1218 switch (dpll
& DPLL_MODE_MASK
) {
1219 case DPLLB_MODE_DAC_SERIAL
:
1220 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
1223 case DPLLB_MODE_LVDS
:
1224 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
1228 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1229 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
1233 /* XXX: Handle the 100Mhz refclk */
1234 i9xx_clock(96000, &clock
);
1236 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
1239 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
1240 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1243 if ((dpll
& PLL_REF_INPUT_MASK
) ==
1244 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
1245 /* XXX: might not be 66MHz */
1246 i8xx_clock(66000, &clock
);
1248 i8xx_clock(48000, &clock
);
1250 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
1253 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
1254 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
1256 if (dpll
& PLL_P2_DIVIDE_BY_4
)
1261 i8xx_clock(48000, &clock
);
1265 /* XXX: It would be nice to validate the clocks, but we can't reuse
1266 * i830PllIsValid() because it relies on the xf86_config connector
1267 * configuration being accurate, which it isn't necessarily.
1273 /** Returns the currently programmed mode of the given pipe. */
1274 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1275 struct drm_crtc
*crtc
)
1277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1278 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1279 int pipe
= intel_crtc
->pipe
;
1280 struct drm_display_mode
*mode
;
1281 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
1282 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
1283 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
1284 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
1286 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
1290 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
1291 mode
->hdisplay
= (htot
& 0xffff) + 1;
1292 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
1293 mode
->hsync_start
= (hsync
& 0xffff) + 1;
1294 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
1295 mode
->vdisplay
= (vtot
& 0xffff) + 1;
1296 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
1297 mode
->vsync_start
= (vsync
& 0xffff) + 1;
1298 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
1300 drm_mode_set_name(mode
);
1301 drm_mode_set_crtcinfo(mode
, 0);
1306 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
1308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1310 drm_crtc_cleanup(crtc
);
1314 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
1315 .dpms
= intel_crtc_dpms
,
1316 .mode_fixup
= intel_crtc_mode_fixup
,
1317 .mode_set
= intel_crtc_mode_set
,
1318 .mode_set_base
= intel_pipe_set_base
,
1319 .prepare
= intel_crtc_prepare
,
1320 .commit
= intel_crtc_commit
,
1323 static const struct drm_crtc_funcs intel_crtc_funcs
= {
1324 .cursor_set
= intel_crtc_cursor_set
,
1325 .cursor_move
= intel_crtc_cursor_move
,
1326 .gamma_set
= intel_crtc_gamma_set
,
1327 .set_config
= drm_crtc_helper_set_config
,
1328 .destroy
= intel_crtc_destroy
,
1332 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
1334 struct intel_crtc
*intel_crtc
;
1337 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
1338 if (intel_crtc
== NULL
)
1341 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
1343 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
1344 intel_crtc
->pipe
= pipe
;
1345 for (i
= 0; i
< 256; i
++) {
1346 intel_crtc
->lut_r
[i
] = i
;
1347 intel_crtc
->lut_g
[i
] = i
;
1348 intel_crtc
->lut_b
[i
] = i
;
1351 intel_crtc
->cursor_addr
= 0;
1352 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
1353 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
1355 intel_crtc
->mode_set
.crtc
= &intel_crtc
->base
;
1356 intel_crtc
->mode_set
.connectors
= (struct drm_connector
**)(intel_crtc
+ 1);
1357 intel_crtc
->mode_set
.num_connectors
= 0;
1359 if (i915_fbpercrtc
) {
1366 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
1368 struct drm_crtc
*crtc
= NULL
;
1370 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1372 if (intel_crtc
->pipe
== pipe
)
1378 static int intel_connector_clones(struct drm_device
*dev
, int type_mask
)
1381 struct drm_connector
*connector
;
1384 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1385 struct intel_output
*intel_output
= to_intel_output(connector
);
1386 if (type_mask
& (1 << intel_output
->type
))
1387 index_mask
|= (1 << entry
);
1394 static void intel_setup_outputs(struct drm_device
*dev
)
1396 struct drm_connector
*connector
;
1398 intel_crt_init(dev
);
1400 /* Set up integrated LVDS */
1401 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1402 intel_lvds_init(dev
);
1405 intel_sdvo_init(dev
, SDVOB
);
1406 intel_sdvo_init(dev
, SDVOC
);
1408 intel_dvo_init(dev
);
1410 if (IS_I9XX(dev
) && !IS_I915G(dev
))
1413 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1414 struct intel_output
*intel_output
= to_intel_output(connector
);
1415 struct drm_encoder
*encoder
= &intel_output
->enc
;
1416 int crtc_mask
= 0, clone_mask
= 0;
1419 switch(intel_output
->type
) {
1420 case INTEL_OUTPUT_DVO
:
1421 case INTEL_OUTPUT_SDVO
:
1422 crtc_mask
= ((1 << 0)|
1424 clone_mask
= ((1 << INTEL_OUTPUT_ANALOG
) |
1425 (1 << INTEL_OUTPUT_DVO
) |
1426 (1 << INTEL_OUTPUT_SDVO
));
1428 case INTEL_OUTPUT_ANALOG
:
1429 crtc_mask
= ((1 << 0)|
1431 clone_mask
= ((1 << INTEL_OUTPUT_ANALOG
) |
1432 (1 << INTEL_OUTPUT_DVO
) |
1433 (1 << INTEL_OUTPUT_SDVO
));
1435 case INTEL_OUTPUT_LVDS
:
1436 crtc_mask
= (1 << 1);
1437 clone_mask
= (1 << INTEL_OUTPUT_LVDS
);
1439 case INTEL_OUTPUT_TVOUT
:
1440 crtc_mask
= ((1 << 0) |
1442 clone_mask
= (1 << INTEL_OUTPUT_TVOUT
);
1445 encoder
->possible_crtcs
= crtc_mask
;
1446 encoder
->possible_clones
= intel_connector_clones(dev
, clone_mask
);
1450 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
1452 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1453 struct drm_device
*dev
= fb
->dev
;
1456 intelfb_remove(dev
, fb
);
1458 drm_framebuffer_cleanup(fb
);
1459 mutex_lock(&dev
->struct_mutex
);
1460 drm_gem_object_unreference(intel_fb
->obj
);
1461 mutex_unlock(&dev
->struct_mutex
);
1466 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
1467 struct drm_file
*file_priv
,
1468 unsigned int *handle
)
1470 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1471 struct drm_gem_object
*object
= intel_fb
->obj
;
1473 return drm_gem_handle_create(file_priv
, object
, handle
);
1476 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
1477 .destroy
= intel_user_framebuffer_destroy
,
1478 .create_handle
= intel_user_framebuffer_create_handle
,
1481 int intel_framebuffer_create(struct drm_device
*dev
,
1482 struct drm_mode_fb_cmd
*mode_cmd
,
1483 struct drm_framebuffer
**fb
,
1484 struct drm_gem_object
*obj
)
1486 struct intel_framebuffer
*intel_fb
;
1489 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
1493 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
1495 DRM_ERROR("framebuffer init failed %d\n", ret
);
1499 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
1501 intel_fb
->obj
= obj
;
1503 *fb
= &intel_fb
->base
;
1509 static struct drm_framebuffer
*
1510 intel_user_framebuffer_create(struct drm_device
*dev
,
1511 struct drm_file
*filp
,
1512 struct drm_mode_fb_cmd
*mode_cmd
)
1514 struct drm_gem_object
*obj
;
1515 struct drm_framebuffer
*fb
;
1518 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
1522 ret
= intel_framebuffer_create(dev
, mode_cmd
, &fb
, obj
);
1524 drm_gem_object_unreference(obj
);
1531 static const struct drm_mode_config_funcs intel_mode_funcs
= {
1532 .fb_create
= intel_user_framebuffer_create
,
1533 .fb_changed
= intelfb_probe
,
1536 void intel_modeset_init(struct drm_device
*dev
)
1541 drm_mode_config_init(dev
);
1543 dev
->mode_config
.min_width
= 0;
1544 dev
->mode_config
.min_height
= 0;
1546 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
1548 if (IS_I965G(dev
)) {
1549 dev
->mode_config
.max_width
= 8192;
1550 dev
->mode_config
.max_height
= 8192;
1552 dev
->mode_config
.max_width
= 2048;
1553 dev
->mode_config
.max_height
= 2048;
1556 /* set memory base */
1558 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
1560 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
1562 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
1566 DRM_DEBUG("%d display pipe%s available.\n",
1567 num_pipe
, num_pipe
> 1 ? "s" : "");
1569 for (i
= 0; i
< num_pipe
; i
++) {
1570 intel_crtc_init(dev
, i
);
1573 intel_setup_outputs(dev
);
1576 void intel_modeset_cleanup(struct drm_device
*dev
)
1578 drm_mode_config_cleanup(dev
);
1582 /* current intel driver doesn't take advantage of encoders
1583 always give back the encoder for the connector
1585 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
1587 struct intel_output
*intel_output
= to_intel_output(connector
);
1589 return &intel_output
->enc
;