2 * srmmu.c: SRMMU specific routines for memory management.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
11 #include <linux/kernel.h>
13 #include <linux/vmalloc.h>
14 #include <linux/pagemap.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/kdebug.h>
21 #include <linux/log2.h>
22 #include <linux/gfp.h>
24 #include <asm/bitext.h>
26 #include <asm/pgalloc.h>
27 #include <asm/pgtable.h>
29 #include <asm/vaddrs.h>
30 #include <asm/traps.h>
33 #include <asm/cache.h>
34 #include <asm/oplib.h>
37 #include <asm/mmu_context.h>
38 #include <asm/io-unit.h>
39 #include <asm/cacheflush.h>
40 #include <asm/tlbflush.h>
42 /* Now the cpu specific definitions. */
43 #include <asm/viking.h>
46 #include <asm/tsunami.h>
47 #include <asm/swift.h>
48 #include <asm/turbosparc.h>
51 #include <asm/btfixup.h>
53 enum mbus_module srmmu_modtype
;
54 static unsigned int hwbug_bitmask
;
58 struct ctx_list
*ctx_list_pool
;
59 struct ctx_list ctx_free
;
60 struct ctx_list ctx_used
;
62 extern struct resource sparc_iomap
;
64 extern unsigned long last_valid_pfn
;
66 static pgd_t
*srmmu_swapper_pg_dir
;
69 #define FLUSH_BEGIN(mm)
72 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
76 BTFIXUPDEF_CALL(void, flush_page_for_dma
, unsigned long)
77 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
79 int flush_page_for_dma_global
= 1;
82 BTFIXUPDEF_CALL(void, local_flush_page_for_dma
, unsigned long)
83 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
88 ctxd_t
*srmmu_ctx_table_phys
;
89 static ctxd_t
*srmmu_context_table
;
91 int viking_mxcc_present
;
92 static DEFINE_SPINLOCK(srmmu_context_spinlock
);
94 static int is_hypersparc
;
96 static int srmmu_cache_pagetables
;
98 /* these will be initialized in srmmu_nocache_calcsize() */
99 static unsigned long srmmu_nocache_size
;
100 static unsigned long srmmu_nocache_end
;
102 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
103 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
105 /* The context table is a nocache user with the biggest alignment needs. */
106 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
108 void *srmmu_nocache_pool
;
109 void *srmmu_nocache_bitmap
;
110 static struct bit_map srmmu_nocache_map
;
112 static inline int srmmu_pte_none(pte_t pte
)
113 { return !(pte_val(pte
) & 0xFFFFFFF); }
115 static inline int srmmu_pmd_none(pmd_t pmd
)
116 { return !(pmd_val(pmd
) & 0xFFFFFFF); }
118 static inline pte_t
srmmu_pte_wrprotect(pte_t pte
)
119 { return __pte(pte_val(pte
) & ~SRMMU_WRITE
);}
121 static inline pte_t
srmmu_pte_mkclean(pte_t pte
)
122 { return __pte(pte_val(pte
) & ~SRMMU_DIRTY
);}
124 static inline pte_t
srmmu_pte_mkold(pte_t pte
)
125 { return __pte(pte_val(pte
) & ~SRMMU_REF
);}
127 /* XXX should we hyper_flush_whole_icache here - Anton */
128 static inline void srmmu_ctxd_set(ctxd_t
*ctxp
, pgd_t
*pgdp
)
129 { set_pte((pte_t
*)ctxp
, (SRMMU_ET_PTD
| (__nocache_pa((unsigned long) pgdp
) >> 4))); }
131 void pmd_set(pmd_t
*pmdp
, pte_t
*ptep
)
133 unsigned long ptp
; /* Physical address, shifted right by 4 */
136 ptp
= __nocache_pa((unsigned long) ptep
) >> 4;
137 for (i
= 0; i
< PTRS_PER_PTE
/SRMMU_REAL_PTRS_PER_PTE
; i
++) {
138 set_pte((pte_t
*)&pmdp
->pmdv
[i
], SRMMU_ET_PTD
| ptp
);
139 ptp
+= (SRMMU_REAL_PTRS_PER_PTE
*sizeof(pte_t
) >> 4);
143 void pmd_populate(struct mm_struct
*mm
, pmd_t
*pmdp
, struct page
*ptep
)
145 unsigned long ptp
; /* Physical address, shifted right by 4 */
148 ptp
= page_to_pfn(ptep
) << (PAGE_SHIFT
-4); /* watch for overflow */
149 for (i
= 0; i
< PTRS_PER_PTE
/SRMMU_REAL_PTRS_PER_PTE
; i
++) {
150 set_pte((pte_t
*)&pmdp
->pmdv
[i
], SRMMU_ET_PTD
| ptp
);
151 ptp
+= (SRMMU_REAL_PTRS_PER_PTE
*sizeof(pte_t
) >> 4);
155 static inline pte_t
srmmu_pte_modify(pte_t pte
, pgprot_t newprot
)
156 { return __pte((pte_val(pte
) & SRMMU_CHG_MASK
) | pgprot_val(newprot
)); }
158 /* to find an entry in a top-level page table... */
159 static inline pgd_t
*srmmu_pgd_offset(struct mm_struct
* mm
, unsigned long address
)
160 { return mm
->pgd
+ (address
>> SRMMU_PGDIR_SHIFT
); }
162 /* Find an entry in the third-level page table.. */
163 pte_t
*pte_offset_kernel(pmd_t
* dir
, unsigned long address
)
167 pte
= __nocache_va((dir
->pmdv
[0] & SRMMU_PTD_PMASK
) << 4);
168 return (pte_t
*) pte
+
169 ((address
>> PAGE_SHIFT
) & (PTRS_PER_PTE
- 1));
173 * size: bytes to allocate in the nocache area.
174 * align: bytes, number to align at.
175 * Returns the virtual address of the allocated area.
177 static unsigned long __srmmu_get_nocache(int size
, int align
)
181 if (size
< SRMMU_NOCACHE_BITMAP_SHIFT
) {
182 printk("Size 0x%x too small for nocache request\n", size
);
183 size
= SRMMU_NOCACHE_BITMAP_SHIFT
;
185 if (size
& (SRMMU_NOCACHE_BITMAP_SHIFT
-1)) {
186 printk("Size 0x%x unaligned int nocache request\n", size
);
187 size
+= SRMMU_NOCACHE_BITMAP_SHIFT
-1;
189 BUG_ON(align
> SRMMU_NOCACHE_ALIGN_MAX
);
191 offset
= bit_map_string_get(&srmmu_nocache_map
,
192 size
>> SRMMU_NOCACHE_BITMAP_SHIFT
,
193 align
>> SRMMU_NOCACHE_BITMAP_SHIFT
);
195 printk("srmmu: out of nocache %d: %d/%d\n",
196 size
, (int) srmmu_nocache_size
,
197 srmmu_nocache_map
.used
<< SRMMU_NOCACHE_BITMAP_SHIFT
);
201 return (SRMMU_NOCACHE_VADDR
+ (offset
<< SRMMU_NOCACHE_BITMAP_SHIFT
));
204 unsigned long srmmu_get_nocache(int size
, int align
)
208 tmp
= __srmmu_get_nocache(size
, align
);
211 memset((void *)tmp
, 0, size
);
216 void srmmu_free_nocache(unsigned long vaddr
, int size
)
220 if (vaddr
< SRMMU_NOCACHE_VADDR
) {
221 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
222 vaddr
, (unsigned long)SRMMU_NOCACHE_VADDR
);
225 if (vaddr
+size
> srmmu_nocache_end
) {
226 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
227 vaddr
, srmmu_nocache_end
);
230 if (!is_power_of_2(size
)) {
231 printk("Size 0x%x is not a power of 2\n", size
);
234 if (size
< SRMMU_NOCACHE_BITMAP_SHIFT
) {
235 printk("Size 0x%x is too small\n", size
);
238 if (vaddr
& (size
-1)) {
239 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr
, size
);
243 offset
= (vaddr
- SRMMU_NOCACHE_VADDR
) >> SRMMU_NOCACHE_BITMAP_SHIFT
;
244 size
= size
>> SRMMU_NOCACHE_BITMAP_SHIFT
;
246 bit_map_clear(&srmmu_nocache_map
, offset
, size
);
249 static void srmmu_early_allocate_ptable_skeleton(unsigned long start
,
252 extern unsigned long probe_memory(void); /* in fault.c */
255 * Reserve nocache dynamically proportionally to the amount of
256 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
258 static void srmmu_nocache_calcsize(void)
260 unsigned long sysmemavail
= probe_memory() / 1024;
261 int srmmu_nocache_npages
;
263 srmmu_nocache_npages
=
264 sysmemavail
/ SRMMU_NOCACHE_ALCRATIO
/ 1024 * 256;
266 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
267 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
268 if (srmmu_nocache_npages
< SRMMU_MIN_NOCACHE_PAGES
)
269 srmmu_nocache_npages
= SRMMU_MIN_NOCACHE_PAGES
;
271 /* anything above 1280 blows up */
272 if (srmmu_nocache_npages
> SRMMU_MAX_NOCACHE_PAGES
)
273 srmmu_nocache_npages
= SRMMU_MAX_NOCACHE_PAGES
;
275 srmmu_nocache_size
= srmmu_nocache_npages
* PAGE_SIZE
;
276 srmmu_nocache_end
= SRMMU_NOCACHE_VADDR
+ srmmu_nocache_size
;
279 static void __init
srmmu_nocache_init(void)
281 unsigned int bitmap_bits
;
285 unsigned long paddr
, vaddr
;
286 unsigned long pteval
;
288 bitmap_bits
= srmmu_nocache_size
>> SRMMU_NOCACHE_BITMAP_SHIFT
;
290 srmmu_nocache_pool
= __alloc_bootmem(srmmu_nocache_size
,
291 SRMMU_NOCACHE_ALIGN_MAX
, 0UL);
292 memset(srmmu_nocache_pool
, 0, srmmu_nocache_size
);
294 srmmu_nocache_bitmap
= __alloc_bootmem(bitmap_bits
>> 3, SMP_CACHE_BYTES
, 0UL);
295 bit_map_init(&srmmu_nocache_map
, srmmu_nocache_bitmap
, bitmap_bits
);
297 srmmu_swapper_pg_dir
= (pgd_t
*)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE
, SRMMU_PGD_TABLE_SIZE
);
298 memset(__nocache_fix(srmmu_swapper_pg_dir
), 0, SRMMU_PGD_TABLE_SIZE
);
299 init_mm
.pgd
= srmmu_swapper_pg_dir
;
301 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR
, srmmu_nocache_end
);
303 paddr
= __pa((unsigned long)srmmu_nocache_pool
);
304 vaddr
= SRMMU_NOCACHE_VADDR
;
306 while (vaddr
< srmmu_nocache_end
) {
307 pgd
= pgd_offset_k(vaddr
);
308 pmd
= pmd_offset(__nocache_fix(pgd
), vaddr
);
309 pte
= pte_offset_kernel(__nocache_fix(pmd
), vaddr
);
311 pteval
= ((paddr
>> 4) | SRMMU_ET_PTE
| SRMMU_PRIV
);
313 if (srmmu_cache_pagetables
)
314 pteval
|= SRMMU_CACHE
;
316 set_pte(__nocache_fix(pte
), __pte(pteval
));
326 pgd_t
*get_pgd_fast(void)
330 pgd
= (pgd_t
*)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE
, SRMMU_PGD_TABLE_SIZE
);
332 pgd_t
*init
= pgd_offset_k(0);
333 memset(pgd
, 0, USER_PTRS_PER_PGD
* sizeof(pgd_t
));
334 memcpy(pgd
+ USER_PTRS_PER_PGD
, init
+ USER_PTRS_PER_PGD
,
335 (PTRS_PER_PGD
- USER_PTRS_PER_PGD
) * sizeof(pgd_t
));
342 * Hardware needs alignment to 256 only, but we align to whole page size
343 * to reduce fragmentation problems due to the buddy principle.
344 * XXX Provide actual fragmentation statistics in /proc.
346 * Alignments up to the page size are the same for physical and virtual
347 * addresses of the nocache area.
349 pgtable_t
pte_alloc_one(struct mm_struct
*mm
, unsigned long address
)
354 if ((pte
= (unsigned long)pte_alloc_one_kernel(mm
, address
)) == 0)
356 page
= pfn_to_page( __nocache_pa(pte
) >> PAGE_SHIFT
);
357 pgtable_page_ctor(page
);
361 void pte_free(struct mm_struct
*mm
, pgtable_t pte
)
365 pgtable_page_dtor(pte
);
366 p
= (unsigned long)page_address(pte
); /* Cached address (for test) */
369 p
= page_to_pfn(pte
) << PAGE_SHIFT
; /* Physical address */
370 p
= (unsigned long) __nocache_va(p
); /* Nocached virtual */
371 srmmu_free_nocache(p
, PTE_SIZE
);
376 static inline void alloc_context(struct mm_struct
*old_mm
, struct mm_struct
*mm
)
378 struct ctx_list
*ctxp
;
380 ctxp
= ctx_free
.next
;
381 if(ctxp
!= &ctx_free
) {
382 remove_from_ctx_list(ctxp
);
383 add_to_used_ctxlist(ctxp
);
384 mm
->context
= ctxp
->ctx_number
;
388 ctxp
= ctx_used
.next
;
389 if(ctxp
->ctx_mm
== old_mm
)
391 if(ctxp
== &ctx_used
)
392 panic("out of mmu contexts");
393 flush_cache_mm(ctxp
->ctx_mm
);
394 flush_tlb_mm(ctxp
->ctx_mm
);
395 remove_from_ctx_list(ctxp
);
396 add_to_used_ctxlist(ctxp
);
397 ctxp
->ctx_mm
->context
= NO_CONTEXT
;
399 mm
->context
= ctxp
->ctx_number
;
402 static inline void free_context(int context
)
404 struct ctx_list
*ctx_old
;
406 ctx_old
= ctx_list_pool
+ context
;
407 remove_from_ctx_list(ctx_old
);
408 add_to_free_ctxlist(ctx_old
);
412 void switch_mm(struct mm_struct
*old_mm
, struct mm_struct
*mm
,
413 struct task_struct
*tsk
)
415 if(mm
->context
== NO_CONTEXT
) {
416 spin_lock(&srmmu_context_spinlock
);
417 alloc_context(old_mm
, mm
);
418 spin_unlock(&srmmu_context_spinlock
);
419 srmmu_ctxd_set(&srmmu_context_table
[mm
->context
], mm
->pgd
);
422 if (sparc_cpu_model
== sparc_leon
)
426 hyper_flush_whole_icache();
428 srmmu_set_context(mm
->context
);
431 /* Low level IO area allocation on the SRMMU. */
432 static inline void srmmu_mapioaddr(unsigned long physaddr
,
433 unsigned long virt_addr
, int bus_type
)
440 physaddr
&= PAGE_MASK
;
441 pgdp
= pgd_offset_k(virt_addr
);
442 pmdp
= pmd_offset(pgdp
, virt_addr
);
443 ptep
= pte_offset_kernel(pmdp
, virt_addr
);
444 tmp
= (physaddr
>> 4) | SRMMU_ET_PTE
;
447 * I need to test whether this is consistent over all
448 * sun4m's. The bus_type represents the upper 4 bits of
449 * 36-bit physical address on the I/O space lines...
451 tmp
|= (bus_type
<< 28);
453 __flush_page_to_ram(virt_addr
);
454 set_pte(ptep
, __pte(tmp
));
457 void srmmu_mapiorange(unsigned int bus
, unsigned long xpa
,
458 unsigned long xva
, unsigned int len
)
462 srmmu_mapioaddr(xpa
, xva
, bus
);
469 static inline void srmmu_unmapioaddr(unsigned long virt_addr
)
475 pgdp
= pgd_offset_k(virt_addr
);
476 pmdp
= pmd_offset(pgdp
, virt_addr
);
477 ptep
= pte_offset_kernel(pmdp
, virt_addr
);
479 /* No need to flush uncacheable page. */
483 void srmmu_unmapiorange(unsigned long virt_addr
, unsigned int len
)
487 srmmu_unmapioaddr(virt_addr
);
488 virt_addr
+= PAGE_SIZE
;
494 * On the SRMMU we do not have the problems with limited tlb entries
495 * for mapping kernel pages, so we just take things from the free page
496 * pool. As a side effect we are putting a little too much pressure
497 * on the gfp() subsystem. This setup also makes the logic of the
498 * iommu mapping code a lot easier as we can transparently handle
499 * mappings on the kernel stack without any special code.
501 struct thread_info
*alloc_thread_info_node(struct task_struct
*tsk
, int node
)
503 struct thread_info
*ret
;
505 ret
= (struct thread_info
*)__get_free_pages(GFP_KERNEL
,
507 #ifdef CONFIG_DEBUG_STACK_USAGE
509 memset(ret
, 0, PAGE_SIZE
<< THREAD_INFO_ORDER
);
510 #endif /* DEBUG_STACK_USAGE */
515 void free_thread_info(struct thread_info
*ti
)
517 free_pages((unsigned long)ti
, THREAD_INFO_ORDER
);
521 extern void tsunami_flush_cache_all(void);
522 extern void tsunami_flush_cache_mm(struct mm_struct
*mm
);
523 extern void tsunami_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
524 extern void tsunami_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
525 extern void tsunami_flush_page_to_ram(unsigned long page
);
526 extern void tsunami_flush_page_for_dma(unsigned long page
);
527 extern void tsunami_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
528 extern void tsunami_flush_tlb_all(void);
529 extern void tsunami_flush_tlb_mm(struct mm_struct
*mm
);
530 extern void tsunami_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
531 extern void tsunami_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
532 extern void tsunami_setup_blockops(void);
535 extern void swift_flush_cache_all(void);
536 extern void swift_flush_cache_mm(struct mm_struct
*mm
);
537 extern void swift_flush_cache_range(struct vm_area_struct
*vma
,
538 unsigned long start
, unsigned long end
);
539 extern void swift_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
540 extern void swift_flush_page_to_ram(unsigned long page
);
541 extern void swift_flush_page_for_dma(unsigned long page
);
542 extern void swift_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
543 extern void swift_flush_tlb_all(void);
544 extern void swift_flush_tlb_mm(struct mm_struct
*mm
);
545 extern void swift_flush_tlb_range(struct vm_area_struct
*vma
,
546 unsigned long start
, unsigned long end
);
547 extern void swift_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
549 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
550 void swift_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
555 if ((ctx1
= vma
->vm_mm
->context
) != -1) {
556 cctx
= srmmu_get_context();
557 /* Is context # ever different from current context? P3 */
559 printk("flush ctx %02x curr %02x\n", ctx1
, cctx
);
560 srmmu_set_context(ctx1
);
561 swift_flush_page(page
);
562 __asm__
__volatile__("sta %%g0, [%0] %1\n\t" : :
563 "r" (page
), "i" (ASI_M_FLUSH_PROBE
));
564 srmmu_set_context(cctx
);
566 /* Rm. prot. bits from virt. c. */
567 /* swift_flush_cache_all(); */
568 /* swift_flush_cache_page(vma, page); */
569 swift_flush_page(page
);
571 __asm__
__volatile__("sta %%g0, [%0] %1\n\t" : :
572 "r" (page
), "i" (ASI_M_FLUSH_PROBE
));
573 /* same as above: srmmu_flush_tlb_page() */
580 * The following are all MBUS based SRMMU modules, and therefore could
581 * be found in a multiprocessor configuration. On the whole, these
582 * chips seems to be much more touchy about DVMA and page tables
583 * with respect to cache coherency.
586 /* Cypress flushes. */
587 static void cypress_flush_cache_all(void)
589 volatile unsigned long cypress_sucks
;
590 unsigned long faddr
, tagval
;
592 flush_user_windows();
593 for(faddr
= 0; faddr
< 0x10000; faddr
+= 0x20) {
594 __asm__
__volatile__("lda [%1 + %2] %3, %0\n\t" :
596 "r" (faddr
), "r" (0x40000),
597 "i" (ASI_M_DATAC_TAG
));
599 /* If modified and valid, kick it. */
600 if((tagval
& 0x60) == 0x60)
601 cypress_sucks
= *(unsigned long *)(0xf0020000 + faddr
);
605 static void cypress_flush_cache_mm(struct mm_struct
*mm
)
607 register unsigned long a
, b
, c
, d
, e
, f
, g
;
608 unsigned long flags
, faddr
;
612 flush_user_windows();
613 local_irq_save(flags
);
614 octx
= srmmu_get_context();
615 srmmu_set_context(mm
->context
);
616 a
= 0x20; b
= 0x40; c
= 0x60;
617 d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
619 faddr
= (0x10000 - 0x100);
624 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
625 "sta %%g0, [%0 + %2] %1\n\t"
626 "sta %%g0, [%0 + %3] %1\n\t"
627 "sta %%g0, [%0 + %4] %1\n\t"
628 "sta %%g0, [%0 + %5] %1\n\t"
629 "sta %%g0, [%0 + %6] %1\n\t"
630 "sta %%g0, [%0 + %7] %1\n\t"
631 "sta %%g0, [%0 + %8] %1\n\t" : :
632 "r" (faddr
), "i" (ASI_M_FLUSH_CTX
),
633 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
634 "r" (e
), "r" (f
), "r" (g
));
636 srmmu_set_context(octx
);
637 local_irq_restore(flags
);
641 static void cypress_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
643 struct mm_struct
*mm
= vma
->vm_mm
;
644 register unsigned long a
, b
, c
, d
, e
, f
, g
;
645 unsigned long flags
, faddr
;
649 flush_user_windows();
650 local_irq_save(flags
);
651 octx
= srmmu_get_context();
652 srmmu_set_context(mm
->context
);
653 a
= 0x20; b
= 0x40; c
= 0x60;
654 d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
656 start
&= SRMMU_REAL_PMD_MASK
;
658 faddr
= (start
+ (0x10000 - 0x100));
663 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
664 "sta %%g0, [%0 + %2] %1\n\t"
665 "sta %%g0, [%0 + %3] %1\n\t"
666 "sta %%g0, [%0 + %4] %1\n\t"
667 "sta %%g0, [%0 + %5] %1\n\t"
668 "sta %%g0, [%0 + %6] %1\n\t"
669 "sta %%g0, [%0 + %7] %1\n\t"
670 "sta %%g0, [%0 + %8] %1\n\t" : :
672 "i" (ASI_M_FLUSH_SEG
),
673 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
674 "r" (e
), "r" (f
), "r" (g
));
675 } while (faddr
!= start
);
676 start
+= SRMMU_REAL_PMD_SIZE
;
678 srmmu_set_context(octx
);
679 local_irq_restore(flags
);
683 static void cypress_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
)
685 register unsigned long a
, b
, c
, d
, e
, f
, g
;
686 struct mm_struct
*mm
= vma
->vm_mm
;
687 unsigned long flags
, line
;
691 flush_user_windows();
692 local_irq_save(flags
);
693 octx
= srmmu_get_context();
694 srmmu_set_context(mm
->context
);
695 a
= 0x20; b
= 0x40; c
= 0x60;
696 d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
699 line
= (page
+ PAGE_SIZE
) - 0x100;
704 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
705 "sta %%g0, [%0 + %2] %1\n\t"
706 "sta %%g0, [%0 + %3] %1\n\t"
707 "sta %%g0, [%0 + %4] %1\n\t"
708 "sta %%g0, [%0 + %5] %1\n\t"
709 "sta %%g0, [%0 + %6] %1\n\t"
710 "sta %%g0, [%0 + %7] %1\n\t"
711 "sta %%g0, [%0 + %8] %1\n\t" : :
713 "i" (ASI_M_FLUSH_PAGE
),
714 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
715 "r" (e
), "r" (f
), "r" (g
));
716 } while(line
!= page
);
717 srmmu_set_context(octx
);
718 local_irq_restore(flags
);
722 /* Cypress is copy-back, at least that is how we configure it. */
723 static void cypress_flush_page_to_ram(unsigned long page
)
725 register unsigned long a
, b
, c
, d
, e
, f
, g
;
728 a
= 0x20; b
= 0x40; c
= 0x60; d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
730 line
= (page
+ PAGE_SIZE
) - 0x100;
735 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
736 "sta %%g0, [%0 + %2] %1\n\t"
737 "sta %%g0, [%0 + %3] %1\n\t"
738 "sta %%g0, [%0 + %4] %1\n\t"
739 "sta %%g0, [%0 + %5] %1\n\t"
740 "sta %%g0, [%0 + %6] %1\n\t"
741 "sta %%g0, [%0 + %7] %1\n\t"
742 "sta %%g0, [%0 + %8] %1\n\t" : :
744 "i" (ASI_M_FLUSH_PAGE
),
745 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
746 "r" (e
), "r" (f
), "r" (g
));
747 } while(line
!= page
);
750 /* Cypress is also IO cache coherent. */
751 static void cypress_flush_page_for_dma(unsigned long page
)
755 /* Cypress has unified L2 VIPT, from which both instructions and data
756 * are stored. It does not have an onboard icache of any sort, therefore
757 * no flush is necessary.
759 static void cypress_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
)
763 static void cypress_flush_tlb_all(void)
765 srmmu_flush_whole_tlb();
768 static void cypress_flush_tlb_mm(struct mm_struct
*mm
)
771 __asm__
__volatile__(
772 "lda [%0] %3, %%g5\n\t"
773 "sta %2, [%0] %3\n\t"
774 "sta %%g0, [%1] %4\n\t"
775 "sta %%g5, [%0] %3\n"
777 : "r" (SRMMU_CTX_REG
), "r" (0x300), "r" (mm
->context
),
778 "i" (ASI_M_MMUREGS
), "i" (ASI_M_FLUSH_PROBE
)
783 static void cypress_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
785 struct mm_struct
*mm
= vma
->vm_mm
;
789 start
&= SRMMU_PGDIR_MASK
;
790 size
= SRMMU_PGDIR_ALIGN(end
) - start
;
791 __asm__
__volatile__(
792 "lda [%0] %5, %%g5\n\t"
795 "subcc %3, %4, %3\n\t"
797 " sta %%g0, [%2 + %3] %6\n\t"
798 "sta %%g5, [%0] %5\n"
800 : "r" (SRMMU_CTX_REG
), "r" (mm
->context
), "r" (start
| 0x200),
801 "r" (size
), "r" (SRMMU_PGDIR_SIZE
), "i" (ASI_M_MMUREGS
),
802 "i" (ASI_M_FLUSH_PROBE
)
807 static void cypress_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
809 struct mm_struct
*mm
= vma
->vm_mm
;
812 __asm__
__volatile__(
813 "lda [%0] %3, %%g5\n\t"
814 "sta %1, [%0] %3\n\t"
815 "sta %%g0, [%2] %4\n\t"
816 "sta %%g5, [%0] %3\n"
818 : "r" (SRMMU_CTX_REG
), "r" (mm
->context
), "r" (page
& PAGE_MASK
),
819 "i" (ASI_M_MMUREGS
), "i" (ASI_M_FLUSH_PROBE
)
825 extern void viking_flush_cache_all(void);
826 extern void viking_flush_cache_mm(struct mm_struct
*mm
);
827 extern void viking_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
,
829 extern void viking_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
830 extern void viking_flush_page_to_ram(unsigned long page
);
831 extern void viking_flush_page_for_dma(unsigned long page
);
832 extern void viking_flush_sig_insns(struct mm_struct
*mm
, unsigned long addr
);
833 extern void viking_flush_page(unsigned long page
);
834 extern void viking_mxcc_flush_page(unsigned long page
);
835 extern void viking_flush_tlb_all(void);
836 extern void viking_flush_tlb_mm(struct mm_struct
*mm
);
837 extern void viking_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
839 extern void viking_flush_tlb_page(struct vm_area_struct
*vma
,
841 extern void sun4dsmp_flush_tlb_all(void);
842 extern void sun4dsmp_flush_tlb_mm(struct mm_struct
*mm
);
843 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
845 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct
*vma
,
849 extern void hypersparc_flush_cache_all(void);
850 extern void hypersparc_flush_cache_mm(struct mm_struct
*mm
);
851 extern void hypersparc_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
852 extern void hypersparc_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
853 extern void hypersparc_flush_page_to_ram(unsigned long page
);
854 extern void hypersparc_flush_page_for_dma(unsigned long page
);
855 extern void hypersparc_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
856 extern void hypersparc_flush_tlb_all(void);
857 extern void hypersparc_flush_tlb_mm(struct mm_struct
*mm
);
858 extern void hypersparc_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
859 extern void hypersparc_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
860 extern void hypersparc_setup_blockops(void);
863 * NOTE: All of this startup code assumes the low 16mb (approx.) of
864 * kernel mappings are done with one single contiguous chunk of
865 * ram. On small ram machines (classics mainly) we only get
866 * around 8mb mapped for us.
869 static void __init
early_pgtable_allocfail(char *type
)
871 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type
);
875 static void __init
srmmu_early_allocate_ptable_skeleton(unsigned long start
,
883 pgdp
= pgd_offset_k(start
);
884 if (pgd_none(*(pgd_t
*)__nocache_fix(pgdp
))) {
885 pmdp
= (pmd_t
*) __srmmu_get_nocache(
886 SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
888 early_pgtable_allocfail("pmd");
889 memset(__nocache_fix(pmdp
), 0, SRMMU_PMD_TABLE_SIZE
);
890 pgd_set(__nocache_fix(pgdp
), pmdp
);
892 pmdp
= pmd_offset(__nocache_fix(pgdp
), start
);
893 if(srmmu_pmd_none(*(pmd_t
*)__nocache_fix(pmdp
))) {
894 ptep
= (pte_t
*)__srmmu_get_nocache(PTE_SIZE
, PTE_SIZE
);
896 early_pgtable_allocfail("pte");
897 memset(__nocache_fix(ptep
), 0, PTE_SIZE
);
898 pmd_set(__nocache_fix(pmdp
), ptep
);
900 if (start
> (0xffffffffUL
- PMD_SIZE
))
902 start
= (start
+ PMD_SIZE
) & PMD_MASK
;
906 static void __init
srmmu_allocate_ptable_skeleton(unsigned long start
,
914 pgdp
= pgd_offset_k(start
);
915 if (pgd_none(*pgdp
)) {
916 pmdp
= (pmd_t
*)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
918 early_pgtable_allocfail("pmd");
919 memset(pmdp
, 0, SRMMU_PMD_TABLE_SIZE
);
922 pmdp
= pmd_offset(pgdp
, start
);
923 if(srmmu_pmd_none(*pmdp
)) {
924 ptep
= (pte_t
*) __srmmu_get_nocache(PTE_SIZE
,
927 early_pgtable_allocfail("pte");
928 memset(ptep
, 0, PTE_SIZE
);
931 if (start
> (0xffffffffUL
- PMD_SIZE
))
933 start
= (start
+ PMD_SIZE
) & PMD_MASK
;
938 * This is much cleaner than poking around physical address space
939 * looking at the prom's page table directly which is what most
940 * other OS's do. Yuck... this is much better.
942 static void __init
srmmu_inherit_prom_mappings(unsigned long start
,
948 int what
= 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
949 unsigned long prompte
;
951 while(start
<= end
) {
953 break; /* probably wrap around */
954 if(start
== 0xfef00000)
955 start
= KADB_DEBUGGER_BEGVM
;
956 if(!(prompte
= srmmu_hwprobe(start
))) {
961 /* A red snapper, see what it really is. */
964 if(!(start
& ~(SRMMU_REAL_PMD_MASK
))) {
965 if(srmmu_hwprobe((start
-PAGE_SIZE
) + SRMMU_REAL_PMD_SIZE
) == prompte
)
969 if(!(start
& ~(SRMMU_PGDIR_MASK
))) {
970 if(srmmu_hwprobe((start
-PAGE_SIZE
) + SRMMU_PGDIR_SIZE
) ==
975 pgdp
= pgd_offset_k(start
);
977 *(pgd_t
*)__nocache_fix(pgdp
) = __pgd(prompte
);
978 start
+= SRMMU_PGDIR_SIZE
;
981 if (pgd_none(*(pgd_t
*)__nocache_fix(pgdp
))) {
982 pmdp
= (pmd_t
*)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
984 early_pgtable_allocfail("pmd");
985 memset(__nocache_fix(pmdp
), 0, SRMMU_PMD_TABLE_SIZE
);
986 pgd_set(__nocache_fix(pgdp
), pmdp
);
988 pmdp
= pmd_offset(__nocache_fix(pgdp
), start
);
989 if(srmmu_pmd_none(*(pmd_t
*)__nocache_fix(pmdp
))) {
990 ptep
= (pte_t
*) __srmmu_get_nocache(PTE_SIZE
,
993 early_pgtable_allocfail("pte");
994 memset(__nocache_fix(ptep
), 0, PTE_SIZE
);
995 pmd_set(__nocache_fix(pmdp
), ptep
);
999 * We bend the rule where all 16 PTPs in a pmd_t point
1000 * inside the same PTE page, and we leak a perfectly
1001 * good hardware PTE piece. Alternatives seem worse.
1003 unsigned int x
; /* Index of HW PMD in soft cluster */
1004 x
= (start
>> PMD_SHIFT
) & 15;
1005 *(unsigned long *)__nocache_fix(&pmdp
->pmdv
[x
]) = prompte
;
1006 start
+= SRMMU_REAL_PMD_SIZE
;
1009 ptep
= pte_offset_kernel(__nocache_fix(pmdp
), start
);
1010 *(pte_t
*)__nocache_fix(ptep
) = __pte(prompte
);
1015 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1017 /* Create a third-level SRMMU 16MB page mapping. */
1018 static void __init
do_large_mapping(unsigned long vaddr
, unsigned long phys_base
)
1020 pgd_t
*pgdp
= pgd_offset_k(vaddr
);
1021 unsigned long big_pte
;
1023 big_pte
= KERNEL_PTE(phys_base
>> 4);
1024 *(pgd_t
*)__nocache_fix(pgdp
) = __pgd(big_pte
);
1027 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1028 static unsigned long __init
map_spbank(unsigned long vbase
, int sp_entry
)
1030 unsigned long pstart
= (sp_banks
[sp_entry
].base_addr
& SRMMU_PGDIR_MASK
);
1031 unsigned long vstart
= (vbase
& SRMMU_PGDIR_MASK
);
1032 unsigned long vend
= SRMMU_PGDIR_ALIGN(vbase
+ sp_banks
[sp_entry
].num_bytes
);
1033 /* Map "low" memory only */
1034 const unsigned long min_vaddr
= PAGE_OFFSET
;
1035 const unsigned long max_vaddr
= PAGE_OFFSET
+ SRMMU_MAXMEM
;
1037 if (vstart
< min_vaddr
|| vstart
>= max_vaddr
)
1040 if (vend
> max_vaddr
|| vend
< min_vaddr
)
1043 while(vstart
< vend
) {
1044 do_large_mapping(vstart
, pstart
);
1045 vstart
+= SRMMU_PGDIR_SIZE
; pstart
+= SRMMU_PGDIR_SIZE
;
1050 static inline void memprobe_error(char *msg
)
1053 prom_printf("Halting now...\n");
1057 static inline void map_kernel(void)
1061 if (phys_base
> 0) {
1062 do_large_mapping(PAGE_OFFSET
, phys_base
);
1065 for (i
= 0; sp_banks
[i
].num_bytes
!= 0; i
++) {
1066 map_spbank((unsigned long)__va(sp_banks
[i
].base_addr
), i
);
1070 /* Paging initialization on the Sparc Reference MMU. */
1071 extern void sparc_context_init(int);
1073 void (*poke_srmmu
)(void) __cpuinitdata
= NULL
;
1075 extern unsigned long bootmem_init(unsigned long *pages_avail
);
1077 void __init
srmmu_paging_init(void)
1085 unsigned long pages_avail
;
1087 sparc_iomap
.start
= SUN4M_IOBASE_VADDR
; /* 16MB of IOSPACE on all sun4m's. */
1089 if (sparc_cpu_model
== sun4d
)
1090 num_contexts
= 65536; /* We know it is Viking */
1092 /* Find the number of contexts on the srmmu. */
1093 cpunode
= prom_getchild(prom_root_node
);
1095 while(cpunode
!= 0) {
1096 prom_getstring(cpunode
, "device_type", node_str
, sizeof(node_str
));
1097 if(!strcmp(node_str
, "cpu")) {
1098 num_contexts
= prom_getintdefault(cpunode
, "mmu-nctx", 0x8);
1101 cpunode
= prom_getsibling(cpunode
);
1106 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1111 last_valid_pfn
= bootmem_init(&pages_avail
);
1113 srmmu_nocache_calcsize();
1114 srmmu_nocache_init();
1115 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM
-PAGE_SIZE
));
1118 /* ctx table has to be physically aligned to its size */
1119 srmmu_context_table
= (ctxd_t
*)__srmmu_get_nocache(num_contexts
*sizeof(ctxd_t
), num_contexts
*sizeof(ctxd_t
));
1120 srmmu_ctx_table_phys
= (ctxd_t
*)__nocache_pa((unsigned long)srmmu_context_table
);
1122 for(i
= 0; i
< num_contexts
; i
++)
1123 srmmu_ctxd_set((ctxd_t
*)__nocache_fix(&srmmu_context_table
[i
]), srmmu_swapper_pg_dir
);
1126 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys
);
1128 /* Stop from hanging here... */
1129 local_flush_tlb_all();
1135 srmmu_allocate_ptable_skeleton(sparc_iomap
.start
, IOBASE_END
);
1136 srmmu_allocate_ptable_skeleton(DVMA_VADDR
, DVMA_END
);
1138 srmmu_allocate_ptable_skeleton(
1139 __fix_to_virt(__end_of_fixed_addresses
- 1), FIXADDR_TOP
);
1140 srmmu_allocate_ptable_skeleton(PKMAP_BASE
, PKMAP_END
);
1142 pgd
= pgd_offset_k(PKMAP_BASE
);
1143 pmd
= pmd_offset(pgd
, PKMAP_BASE
);
1144 pte
= pte_offset_kernel(pmd
, PKMAP_BASE
);
1145 pkmap_page_table
= pte
;
1150 sparc_context_init(num_contexts
);
1155 unsigned long zones_size
[MAX_NR_ZONES
];
1156 unsigned long zholes_size
[MAX_NR_ZONES
];
1157 unsigned long npages
;
1160 for (znum
= 0; znum
< MAX_NR_ZONES
; znum
++)
1161 zones_size
[znum
] = zholes_size
[znum
] = 0;
1163 npages
= max_low_pfn
- pfn_base
;
1165 zones_size
[ZONE_DMA
] = npages
;
1166 zholes_size
[ZONE_DMA
] = npages
- pages_avail
;
1168 npages
= highend_pfn
- max_low_pfn
;
1169 zones_size
[ZONE_HIGHMEM
] = npages
;
1170 zholes_size
[ZONE_HIGHMEM
] = npages
- calc_highpages();
1172 free_area_init_node(0, zones_size
, pfn_base
, zholes_size
);
1176 void mmu_info(struct seq_file
*m
)
1181 "nocache total\t: %ld\n"
1182 "nocache used\t: %d\n",
1186 srmmu_nocache_map
.used
<< SRMMU_NOCACHE_BITMAP_SHIFT
);
1189 void destroy_context(struct mm_struct
*mm
)
1192 if(mm
->context
!= NO_CONTEXT
) {
1194 srmmu_ctxd_set(&srmmu_context_table
[mm
->context
], srmmu_swapper_pg_dir
);
1196 spin_lock(&srmmu_context_spinlock
);
1197 free_context(mm
->context
);
1198 spin_unlock(&srmmu_context_spinlock
);
1199 mm
->context
= NO_CONTEXT
;
1203 /* Init various srmmu chip types. */
1204 static void __init
srmmu_is_bad(void)
1206 prom_printf("Could not determine SRMMU chip type.\n");
1210 static void __init
init_vac_layout(void)
1217 unsigned long max_size
= 0;
1218 unsigned long min_line_size
= 0x10000000;
1221 nd
= prom_getchild(prom_root_node
);
1222 while((nd
= prom_getsibling(nd
)) != 0) {
1223 prom_getstring(nd
, "device_type", node_str
, sizeof(node_str
));
1224 if(!strcmp(node_str
, "cpu")) {
1225 vac_line_size
= prom_getint(nd
, "cache-line-size");
1226 if (vac_line_size
== -1) {
1227 prom_printf("can't determine cache-line-size, "
1231 cache_lines
= prom_getint(nd
, "cache-nlines");
1232 if (cache_lines
== -1) {
1233 prom_printf("can't determine cache-nlines, halting.\n");
1237 vac_cache_size
= cache_lines
* vac_line_size
;
1239 if(vac_cache_size
> max_size
)
1240 max_size
= vac_cache_size
;
1241 if(vac_line_size
< min_line_size
)
1242 min_line_size
= vac_line_size
;
1243 //FIXME: cpus not contiguous!!
1245 if (cpu
>= nr_cpu_ids
|| !cpu_online(cpu
))
1253 prom_printf("No CPU nodes found, halting.\n");
1257 vac_cache_size
= max_size
;
1258 vac_line_size
= min_line_size
;
1260 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1261 (int)vac_cache_size
, (int)vac_line_size
);
1264 static void __cpuinit
poke_hypersparc(void)
1266 volatile unsigned long clear
;
1267 unsigned long mreg
= srmmu_get_mmureg();
1269 hyper_flush_unconditional_combined();
1271 mreg
&= ~(HYPERSPARC_CWENABLE
);
1272 mreg
|= (HYPERSPARC_CENABLE
| HYPERSPARC_WBENABLE
);
1273 mreg
|= (HYPERSPARC_CMODE
);
1275 srmmu_set_mmureg(mreg
);
1277 #if 0 /* XXX I think this is bad news... -DaveM */
1278 hyper_clear_all_tags();
1281 put_ross_icr(HYPERSPARC_ICCR_FTD
| HYPERSPARC_ICCR_ICE
);
1282 hyper_flush_whole_icache();
1283 clear
= srmmu_get_faddr();
1284 clear
= srmmu_get_fstatus();
1287 static void __init
init_hypersparc(void)
1289 srmmu_name
= "ROSS HyperSparc";
1290 srmmu_modtype
= HyperSparc
;
1296 BTFIXUPSET_CALL(flush_cache_all
, hypersparc_flush_cache_all
, BTFIXUPCALL_NORM
);
1297 BTFIXUPSET_CALL(flush_cache_mm
, hypersparc_flush_cache_mm
, BTFIXUPCALL_NORM
);
1298 BTFIXUPSET_CALL(flush_cache_range
, hypersparc_flush_cache_range
, BTFIXUPCALL_NORM
);
1299 BTFIXUPSET_CALL(flush_cache_page
, hypersparc_flush_cache_page
, BTFIXUPCALL_NORM
);
1301 BTFIXUPSET_CALL(flush_tlb_all
, hypersparc_flush_tlb_all
, BTFIXUPCALL_NORM
);
1302 BTFIXUPSET_CALL(flush_tlb_mm
, hypersparc_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1303 BTFIXUPSET_CALL(flush_tlb_range
, hypersparc_flush_tlb_range
, BTFIXUPCALL_NORM
);
1304 BTFIXUPSET_CALL(flush_tlb_page
, hypersparc_flush_tlb_page
, BTFIXUPCALL_NORM
);
1306 BTFIXUPSET_CALL(__flush_page_to_ram
, hypersparc_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1307 BTFIXUPSET_CALL(flush_sig_insns
, hypersparc_flush_sig_insns
, BTFIXUPCALL_NORM
);
1308 BTFIXUPSET_CALL(flush_page_for_dma
, hypersparc_flush_page_for_dma
, BTFIXUPCALL_NOP
);
1311 poke_srmmu
= poke_hypersparc
;
1313 hypersparc_setup_blockops();
1316 static void __cpuinit
poke_cypress(void)
1318 unsigned long mreg
= srmmu_get_mmureg();
1319 unsigned long faddr
, tagval
;
1320 volatile unsigned long cypress_sucks
;
1321 volatile unsigned long clear
;
1323 clear
= srmmu_get_faddr();
1324 clear
= srmmu_get_fstatus();
1326 if (!(mreg
& CYPRESS_CENABLE
)) {
1327 for(faddr
= 0x0; faddr
< 0x10000; faddr
+= 20) {
1328 __asm__
__volatile__("sta %%g0, [%0 + %1] %2\n\t"
1329 "sta %%g0, [%0] %2\n\t" : :
1330 "r" (faddr
), "r" (0x40000),
1331 "i" (ASI_M_DATAC_TAG
));
1334 for(faddr
= 0; faddr
< 0x10000; faddr
+= 0x20) {
1335 __asm__
__volatile__("lda [%1 + %2] %3, %0\n\t" :
1337 "r" (faddr
), "r" (0x40000),
1338 "i" (ASI_M_DATAC_TAG
));
1340 /* If modified and valid, kick it. */
1341 if((tagval
& 0x60) == 0x60)
1342 cypress_sucks
= *(unsigned long *)
1343 (0xf0020000 + faddr
);
1347 /* And one more, for our good neighbor, Mr. Broken Cypress. */
1348 clear
= srmmu_get_faddr();
1349 clear
= srmmu_get_fstatus();
1351 mreg
|= (CYPRESS_CENABLE
| CYPRESS_CMODE
);
1352 srmmu_set_mmureg(mreg
);
1355 static void __init
init_cypress_common(void)
1359 BTFIXUPSET_CALL(flush_cache_all
, cypress_flush_cache_all
, BTFIXUPCALL_NORM
);
1360 BTFIXUPSET_CALL(flush_cache_mm
, cypress_flush_cache_mm
, BTFIXUPCALL_NORM
);
1361 BTFIXUPSET_CALL(flush_cache_range
, cypress_flush_cache_range
, BTFIXUPCALL_NORM
);
1362 BTFIXUPSET_CALL(flush_cache_page
, cypress_flush_cache_page
, BTFIXUPCALL_NORM
);
1364 BTFIXUPSET_CALL(flush_tlb_all
, cypress_flush_tlb_all
, BTFIXUPCALL_NORM
);
1365 BTFIXUPSET_CALL(flush_tlb_mm
, cypress_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1366 BTFIXUPSET_CALL(flush_tlb_page
, cypress_flush_tlb_page
, BTFIXUPCALL_NORM
);
1367 BTFIXUPSET_CALL(flush_tlb_range
, cypress_flush_tlb_range
, BTFIXUPCALL_NORM
);
1370 BTFIXUPSET_CALL(__flush_page_to_ram
, cypress_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1371 BTFIXUPSET_CALL(flush_sig_insns
, cypress_flush_sig_insns
, BTFIXUPCALL_NOP
);
1372 BTFIXUPSET_CALL(flush_page_for_dma
, cypress_flush_page_for_dma
, BTFIXUPCALL_NOP
);
1374 poke_srmmu
= poke_cypress
;
1377 static void __init
init_cypress_604(void)
1379 srmmu_name
= "ROSS Cypress-604(UP)";
1380 srmmu_modtype
= Cypress
;
1381 init_cypress_common();
1384 static void __init
init_cypress_605(unsigned long mrev
)
1386 srmmu_name
= "ROSS Cypress-605(MP)";
1388 srmmu_modtype
= Cypress_vE
;
1389 hwbug_bitmask
|= HWBUG_COPYBACK_BROKEN
;
1392 srmmu_modtype
= Cypress_vD
;
1393 hwbug_bitmask
|= HWBUG_ASIFLUSH_BROKEN
;
1395 srmmu_modtype
= Cypress
;
1398 init_cypress_common();
1401 static void __cpuinit
poke_swift(void)
1405 /* Clear any crap from the cache or else... */
1406 swift_flush_cache_all();
1408 /* Enable I & D caches */
1409 mreg
= srmmu_get_mmureg();
1410 mreg
|= (SWIFT_IE
| SWIFT_DE
);
1412 * The Swift branch folding logic is completely broken. At
1413 * trap time, if things are just right, if can mistakenly
1414 * think that a trap is coming from kernel mode when in fact
1415 * it is coming from user mode (it mis-executes the branch in
1416 * the trap code). So you see things like crashme completely
1417 * hosing your machine which is completely unacceptable. Turn
1418 * this shit off... nice job Fujitsu.
1420 mreg
&= ~(SWIFT_BF
);
1421 srmmu_set_mmureg(mreg
);
1424 #define SWIFT_MASKID_ADDR 0x10003018
1425 static void __init
init_swift(void)
1427 unsigned long swift_rev
;
1429 __asm__
__volatile__("lda [%1] %2, %0\n\t"
1430 "srl %0, 0x18, %0\n\t" :
1432 "r" (SWIFT_MASKID_ADDR
), "i" (ASI_M_BYPASS
));
1433 srmmu_name
= "Fujitsu Swift";
1439 srmmu_modtype
= Swift_lots_o_bugs
;
1440 hwbug_bitmask
|= (HWBUG_KERN_ACCBROKEN
| HWBUG_KERN_CBITBROKEN
);
1442 * Gee george, I wonder why Sun is so hush hush about
1443 * this hardware bug... really braindamage stuff going
1444 * on here. However I think we can find a way to avoid
1445 * all of the workaround overhead under Linux. Basically,
1446 * any page fault can cause kernel pages to become user
1447 * accessible (the mmu gets confused and clears some of
1448 * the ACC bits in kernel ptes). Aha, sounds pretty
1449 * horrible eh? But wait, after extensive testing it appears
1450 * that if you use pgd_t level large kernel pte's (like the
1451 * 4MB pages on the Pentium) the bug does not get tripped
1452 * at all. This avoids almost all of the major overhead.
1453 * Welcome to a world where your vendor tells you to,
1454 * "apply this kernel patch" instead of "sorry for the
1455 * broken hardware, send it back and we'll give you
1456 * properly functioning parts"
1461 srmmu_modtype
= Swift_bad_c
;
1462 hwbug_bitmask
|= HWBUG_KERN_CBITBROKEN
;
1464 * You see Sun allude to this hardware bug but never
1465 * admit things directly, they'll say things like,
1466 * "the Swift chip cache problems" or similar.
1470 srmmu_modtype
= Swift_ok
;
1474 BTFIXUPSET_CALL(flush_cache_all
, swift_flush_cache_all
, BTFIXUPCALL_NORM
);
1475 BTFIXUPSET_CALL(flush_cache_mm
, swift_flush_cache_mm
, BTFIXUPCALL_NORM
);
1476 BTFIXUPSET_CALL(flush_cache_page
, swift_flush_cache_page
, BTFIXUPCALL_NORM
);
1477 BTFIXUPSET_CALL(flush_cache_range
, swift_flush_cache_range
, BTFIXUPCALL_NORM
);
1480 BTFIXUPSET_CALL(flush_tlb_all
, swift_flush_tlb_all
, BTFIXUPCALL_NORM
);
1481 BTFIXUPSET_CALL(flush_tlb_mm
, swift_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1482 BTFIXUPSET_CALL(flush_tlb_page
, swift_flush_tlb_page
, BTFIXUPCALL_NORM
);
1483 BTFIXUPSET_CALL(flush_tlb_range
, swift_flush_tlb_range
, BTFIXUPCALL_NORM
);
1485 BTFIXUPSET_CALL(__flush_page_to_ram
, swift_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1486 BTFIXUPSET_CALL(flush_sig_insns
, swift_flush_sig_insns
, BTFIXUPCALL_NORM
);
1487 BTFIXUPSET_CALL(flush_page_for_dma
, swift_flush_page_for_dma
, BTFIXUPCALL_NORM
);
1489 flush_page_for_dma_global
= 0;
1492 * Are you now convinced that the Swift is one of the
1493 * biggest VLSI abortions of all time? Bravo Fujitsu!
1494 * Fujitsu, the !#?!%$'d up processor people. I bet if
1495 * you examined the microcode of the Swift you'd find
1496 * XXX's all over the place.
1498 poke_srmmu
= poke_swift
;
1501 static void turbosparc_flush_cache_all(void)
1503 flush_user_windows();
1504 turbosparc_idflash_clear();
1507 static void turbosparc_flush_cache_mm(struct mm_struct
*mm
)
1510 flush_user_windows();
1511 turbosparc_idflash_clear();
1515 static void turbosparc_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
1517 FLUSH_BEGIN(vma
->vm_mm
)
1518 flush_user_windows();
1519 turbosparc_idflash_clear();
1523 static void turbosparc_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
)
1525 FLUSH_BEGIN(vma
->vm_mm
)
1526 flush_user_windows();
1527 if (vma
->vm_flags
& VM_EXEC
)
1528 turbosparc_flush_icache();
1529 turbosparc_flush_dcache();
1533 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1534 static void turbosparc_flush_page_to_ram(unsigned long page
)
1536 #ifdef TURBOSPARC_WRITEBACK
1537 volatile unsigned long clear
;
1539 if (srmmu_hwprobe(page
))
1540 turbosparc_flush_page_cache(page
);
1541 clear
= srmmu_get_fstatus();
1545 static void turbosparc_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
)
1549 static void turbosparc_flush_page_for_dma(unsigned long page
)
1551 turbosparc_flush_dcache();
1554 static void turbosparc_flush_tlb_all(void)
1556 srmmu_flush_whole_tlb();
1559 static void turbosparc_flush_tlb_mm(struct mm_struct
*mm
)
1562 srmmu_flush_whole_tlb();
1566 static void turbosparc_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
1568 FLUSH_BEGIN(vma
->vm_mm
)
1569 srmmu_flush_whole_tlb();
1573 static void turbosparc_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
1575 FLUSH_BEGIN(vma
->vm_mm
)
1576 srmmu_flush_whole_tlb();
1581 static void __cpuinit
poke_turbosparc(void)
1583 unsigned long mreg
= srmmu_get_mmureg();
1584 unsigned long ccreg
;
1586 /* Clear any crap from the cache or else... */
1587 turbosparc_flush_cache_all();
1588 mreg
&= ~(TURBOSPARC_ICENABLE
| TURBOSPARC_DCENABLE
); /* Temporarily disable I & D caches */
1589 mreg
&= ~(TURBOSPARC_PCENABLE
); /* Don't check parity */
1590 srmmu_set_mmureg(mreg
);
1592 ccreg
= turbosparc_get_ccreg();
1594 #ifdef TURBOSPARC_WRITEBACK
1595 ccreg
|= (TURBOSPARC_SNENABLE
); /* Do DVMA snooping in Dcache */
1596 ccreg
&= ~(TURBOSPARC_uS2
| TURBOSPARC_WTENABLE
);
1597 /* Write-back D-cache, emulate VLSI
1598 * abortion number three, not number one */
1600 /* For now let's play safe, optimize later */
1601 ccreg
|= (TURBOSPARC_SNENABLE
| TURBOSPARC_WTENABLE
);
1602 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1603 ccreg
&= ~(TURBOSPARC_uS2
);
1604 /* Emulate VLSI abortion number three, not number one */
1607 switch (ccreg
& 7) {
1608 case 0: /* No SE cache */
1609 case 7: /* Test mode */
1612 ccreg
|= (TURBOSPARC_SCENABLE
);
1614 turbosparc_set_ccreg (ccreg
);
1616 mreg
|= (TURBOSPARC_ICENABLE
| TURBOSPARC_DCENABLE
); /* I & D caches on */
1617 mreg
|= (TURBOSPARC_ICSNOOP
); /* Icache snooping on */
1618 srmmu_set_mmureg(mreg
);
1621 static void __init
init_turbosparc(void)
1623 srmmu_name
= "Fujitsu TurboSparc";
1624 srmmu_modtype
= TurboSparc
;
1626 BTFIXUPSET_CALL(flush_cache_all
, turbosparc_flush_cache_all
, BTFIXUPCALL_NORM
);
1627 BTFIXUPSET_CALL(flush_cache_mm
, turbosparc_flush_cache_mm
, BTFIXUPCALL_NORM
);
1628 BTFIXUPSET_CALL(flush_cache_page
, turbosparc_flush_cache_page
, BTFIXUPCALL_NORM
);
1629 BTFIXUPSET_CALL(flush_cache_range
, turbosparc_flush_cache_range
, BTFIXUPCALL_NORM
);
1631 BTFIXUPSET_CALL(flush_tlb_all
, turbosparc_flush_tlb_all
, BTFIXUPCALL_NORM
);
1632 BTFIXUPSET_CALL(flush_tlb_mm
, turbosparc_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1633 BTFIXUPSET_CALL(flush_tlb_page
, turbosparc_flush_tlb_page
, BTFIXUPCALL_NORM
);
1634 BTFIXUPSET_CALL(flush_tlb_range
, turbosparc_flush_tlb_range
, BTFIXUPCALL_NORM
);
1636 BTFIXUPSET_CALL(__flush_page_to_ram
, turbosparc_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1638 BTFIXUPSET_CALL(flush_sig_insns
, turbosparc_flush_sig_insns
, BTFIXUPCALL_NOP
);
1639 BTFIXUPSET_CALL(flush_page_for_dma
, turbosparc_flush_page_for_dma
, BTFIXUPCALL_NORM
);
1641 poke_srmmu
= poke_turbosparc
;
1644 static void __cpuinit
poke_tsunami(void)
1646 unsigned long mreg
= srmmu_get_mmureg();
1648 tsunami_flush_icache();
1649 tsunami_flush_dcache();
1650 mreg
&= ~TSUNAMI_ITD
;
1651 mreg
|= (TSUNAMI_IENAB
| TSUNAMI_DENAB
);
1652 srmmu_set_mmureg(mreg
);
1655 static void __init
init_tsunami(void)
1658 * Tsunami's pretty sane, Sun and TI actually got it
1659 * somewhat right this time. Fujitsu should have
1660 * taken some lessons from them.
1663 srmmu_name
= "TI Tsunami";
1664 srmmu_modtype
= Tsunami
;
1666 BTFIXUPSET_CALL(flush_cache_all
, tsunami_flush_cache_all
, BTFIXUPCALL_NORM
);
1667 BTFIXUPSET_CALL(flush_cache_mm
, tsunami_flush_cache_mm
, BTFIXUPCALL_NORM
);
1668 BTFIXUPSET_CALL(flush_cache_page
, tsunami_flush_cache_page
, BTFIXUPCALL_NORM
);
1669 BTFIXUPSET_CALL(flush_cache_range
, tsunami_flush_cache_range
, BTFIXUPCALL_NORM
);
1672 BTFIXUPSET_CALL(flush_tlb_all
, tsunami_flush_tlb_all
, BTFIXUPCALL_NORM
);
1673 BTFIXUPSET_CALL(flush_tlb_mm
, tsunami_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1674 BTFIXUPSET_CALL(flush_tlb_page
, tsunami_flush_tlb_page
, BTFIXUPCALL_NORM
);
1675 BTFIXUPSET_CALL(flush_tlb_range
, tsunami_flush_tlb_range
, BTFIXUPCALL_NORM
);
1677 BTFIXUPSET_CALL(__flush_page_to_ram
, tsunami_flush_page_to_ram
, BTFIXUPCALL_NOP
);
1678 BTFIXUPSET_CALL(flush_sig_insns
, tsunami_flush_sig_insns
, BTFIXUPCALL_NORM
);
1679 BTFIXUPSET_CALL(flush_page_for_dma
, tsunami_flush_page_for_dma
, BTFIXUPCALL_NORM
);
1681 poke_srmmu
= poke_tsunami
;
1683 tsunami_setup_blockops();
1686 static void __cpuinit
poke_viking(void)
1688 unsigned long mreg
= srmmu_get_mmureg();
1689 static int smp_catch
;
1691 if(viking_mxcc_present
) {
1692 unsigned long mxcc_control
= mxcc_get_creg();
1694 mxcc_control
|= (MXCC_CTL_ECE
| MXCC_CTL_PRE
| MXCC_CTL_MCE
);
1695 mxcc_control
&= ~(MXCC_CTL_RRC
);
1696 mxcc_set_creg(mxcc_control
);
1699 * We don't need memory parity checks.
1700 * XXX This is a mess, have to dig out later. ecd.
1701 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1704 /* We do cache ptables on MXCC. */
1705 mreg
|= VIKING_TCENABLE
;
1707 unsigned long bpreg
;
1709 mreg
&= ~(VIKING_TCENABLE
);
1711 /* Must disable mixed-cmd mode here for other cpu's. */
1712 bpreg
= viking_get_bpreg();
1713 bpreg
&= ~(VIKING_ACTION_MIX
);
1714 viking_set_bpreg(bpreg
);
1716 /* Just in case PROM does something funny. */
1721 mreg
|= VIKING_SPENABLE
;
1722 mreg
|= (VIKING_ICENABLE
| VIKING_DCENABLE
);
1723 mreg
|= VIKING_SBENABLE
;
1724 mreg
&= ~(VIKING_ACENABLE
);
1725 srmmu_set_mmureg(mreg
);
1728 static void __init
init_viking(void)
1730 unsigned long mreg
= srmmu_get_mmureg();
1732 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1733 if(mreg
& VIKING_MMODE
) {
1734 srmmu_name
= "TI Viking";
1735 viking_mxcc_present
= 0;
1739 * We need this to make sure old viking takes no hits
1740 * on it's cache for dma snoops to workaround the
1741 * "load from non-cacheable memory" interrupt bug.
1742 * This is only necessary because of the new way in
1743 * which we use the IOMMU.
1745 BTFIXUPSET_CALL(flush_page_for_dma
, viking_flush_page
, BTFIXUPCALL_NORM
);
1747 flush_page_for_dma_global
= 0;
1749 srmmu_name
= "TI Viking/MXCC";
1750 viking_mxcc_present
= 1;
1752 srmmu_cache_pagetables
= 1;
1754 /* MXCC vikings lack the DMA snooping bug. */
1755 BTFIXUPSET_CALL(flush_page_for_dma
, viking_flush_page_for_dma
, BTFIXUPCALL_NOP
);
1758 BTFIXUPSET_CALL(flush_cache_all
, viking_flush_cache_all
, BTFIXUPCALL_NORM
);
1759 BTFIXUPSET_CALL(flush_cache_mm
, viking_flush_cache_mm
, BTFIXUPCALL_NORM
);
1760 BTFIXUPSET_CALL(flush_cache_page
, viking_flush_cache_page
, BTFIXUPCALL_NORM
);
1761 BTFIXUPSET_CALL(flush_cache_range
, viking_flush_cache_range
, BTFIXUPCALL_NORM
);
1764 if (sparc_cpu_model
== sun4d
) {
1765 BTFIXUPSET_CALL(flush_tlb_all
, sun4dsmp_flush_tlb_all
, BTFIXUPCALL_NORM
);
1766 BTFIXUPSET_CALL(flush_tlb_mm
, sun4dsmp_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1767 BTFIXUPSET_CALL(flush_tlb_page
, sun4dsmp_flush_tlb_page
, BTFIXUPCALL_NORM
);
1768 BTFIXUPSET_CALL(flush_tlb_range
, sun4dsmp_flush_tlb_range
, BTFIXUPCALL_NORM
);
1772 BTFIXUPSET_CALL(flush_tlb_all
, viking_flush_tlb_all
, BTFIXUPCALL_NORM
);
1773 BTFIXUPSET_CALL(flush_tlb_mm
, viking_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1774 BTFIXUPSET_CALL(flush_tlb_page
, viking_flush_tlb_page
, BTFIXUPCALL_NORM
);
1775 BTFIXUPSET_CALL(flush_tlb_range
, viking_flush_tlb_range
, BTFIXUPCALL_NORM
);
1778 BTFIXUPSET_CALL(__flush_page_to_ram
, viking_flush_page_to_ram
, BTFIXUPCALL_NOP
);
1779 BTFIXUPSET_CALL(flush_sig_insns
, viking_flush_sig_insns
, BTFIXUPCALL_NOP
);
1781 poke_srmmu
= poke_viking
;
1784 #ifdef CONFIG_SPARC_LEON
1786 void __init
poke_leonsparc(void)
1790 void __init
init_leon(void)
1793 srmmu_name
= "LEON";
1795 BTFIXUPSET_CALL(flush_cache_all
, leon_flush_cache_all
,
1797 BTFIXUPSET_CALL(flush_cache_mm
, leon_flush_cache_all
,
1799 BTFIXUPSET_CALL(flush_cache_page
, leon_flush_pcache_all
,
1801 BTFIXUPSET_CALL(flush_cache_range
, leon_flush_cache_all
,
1803 BTFIXUPSET_CALL(flush_page_for_dma
, leon_flush_dcache_all
,
1806 BTFIXUPSET_CALL(flush_tlb_all
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
1807 BTFIXUPSET_CALL(flush_tlb_mm
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
1808 BTFIXUPSET_CALL(flush_tlb_page
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
1809 BTFIXUPSET_CALL(flush_tlb_range
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
1811 BTFIXUPSET_CALL(__flush_page_to_ram
, leon_flush_cache_all
,
1813 BTFIXUPSET_CALL(flush_sig_insns
, leon_flush_cache_all
, BTFIXUPCALL_NOP
);
1815 poke_srmmu
= poke_leonsparc
;
1817 srmmu_cache_pagetables
= 0;
1819 leon_flush_during_switch
= leon_flush_needed();
1823 /* Probe for the srmmu chip version. */
1824 static void __init
get_srmmu_type(void)
1826 unsigned long mreg
, psr
;
1827 unsigned long mod_typ
, mod_rev
, psr_typ
, psr_vers
;
1829 srmmu_modtype
= SRMMU_INVAL_MOD
;
1832 mreg
= srmmu_get_mmureg(); psr
= get_psr();
1833 mod_typ
= (mreg
& 0xf0000000) >> 28;
1834 mod_rev
= (mreg
& 0x0f000000) >> 24;
1835 psr_typ
= (psr
>> 28) & 0xf;
1836 psr_vers
= (psr
>> 24) & 0xf;
1838 /* First, check for sparc-leon. */
1839 if (sparc_cpu_model
== sparc_leon
) {
1844 /* Second, check for HyperSparc or Cypress. */
1848 /* UP or MP Hypersparc */
1853 /* Uniprocessor Cypress */
1859 /* _REALLY OLD_ Cypress MP chips... */
1863 /* MP Cypress mmu/cache-controller */
1864 init_cypress_605(mod_rev
);
1867 /* Some other Cypress revision, assume a 605. */
1868 init_cypress_605(mod_rev
);
1875 * Now Fujitsu TurboSparc. It might happen that it is
1876 * in Swift emulation mode, so we will check later...
1878 if (psr_typ
== 0 && psr_vers
== 5) {
1883 /* Next check for Fujitsu Swift. */
1884 if(psr_typ
== 0 && psr_vers
== 4) {
1888 /* Look if it is not a TurboSparc emulating Swift... */
1889 cpunode
= prom_getchild(prom_root_node
);
1890 while((cpunode
= prom_getsibling(cpunode
)) != 0) {
1891 prom_getstring(cpunode
, "device_type", node_str
, sizeof(node_str
));
1892 if(!strcmp(node_str
, "cpu")) {
1893 if (!prom_getintdefault(cpunode
, "psr-implementation", 1) &&
1894 prom_getintdefault(cpunode
, "psr-version", 1) == 5) {
1906 /* Now the Viking family of srmmu. */
1909 ((psr_vers
== 1) && (mod_typ
== 0) && (mod_rev
== 0)))) {
1914 /* Finally the Tsunami. */
1915 if(psr_typ
== 4 && psr_vers
== 1 && (mod_typ
|| mod_rev
)) {
1925 /* Local cross-calls. */
1926 static void smp_flush_page_for_dma(unsigned long page
)
1928 xc1((smpfunc_t
) BTFIXUP_CALL(local_flush_page_for_dma
), page
);
1929 local_flush_page_for_dma(page
);
1934 /* Load up routines and constants for sun4m and sun4d mmu */
1935 void __init
load_mmu(void)
1937 extern void ld_mmu_iommu(void);
1938 extern void ld_mmu_iounit(void);
1944 /* El switcheroo... */
1946 BTFIXUPCOPY_CALL(local_flush_cache_all
, flush_cache_all
);
1947 BTFIXUPCOPY_CALL(local_flush_cache_mm
, flush_cache_mm
);
1948 BTFIXUPCOPY_CALL(local_flush_cache_range
, flush_cache_range
);
1949 BTFIXUPCOPY_CALL(local_flush_cache_page
, flush_cache_page
);
1950 BTFIXUPCOPY_CALL(local_flush_tlb_all
, flush_tlb_all
);
1951 BTFIXUPCOPY_CALL(local_flush_tlb_mm
, flush_tlb_mm
);
1952 BTFIXUPCOPY_CALL(local_flush_tlb_range
, flush_tlb_range
);
1953 BTFIXUPCOPY_CALL(local_flush_tlb_page
, flush_tlb_page
);
1954 BTFIXUPCOPY_CALL(local_flush_page_to_ram
, __flush_page_to_ram
);
1955 BTFIXUPCOPY_CALL(local_flush_sig_insns
, flush_sig_insns
);
1956 BTFIXUPCOPY_CALL(local_flush_page_for_dma
, flush_page_for_dma
);
1958 BTFIXUPSET_CALL(flush_cache_all
, smp_flush_cache_all
, BTFIXUPCALL_NORM
);
1959 BTFIXUPSET_CALL(flush_cache_mm
, smp_flush_cache_mm
, BTFIXUPCALL_NORM
);
1960 BTFIXUPSET_CALL(flush_cache_range
, smp_flush_cache_range
, BTFIXUPCALL_NORM
);
1961 BTFIXUPSET_CALL(flush_cache_page
, smp_flush_cache_page
, BTFIXUPCALL_NORM
);
1962 if (sparc_cpu_model
!= sun4d
&&
1963 sparc_cpu_model
!= sparc_leon
) {
1964 BTFIXUPSET_CALL(flush_tlb_all
, smp_flush_tlb_all
, BTFIXUPCALL_NORM
);
1965 BTFIXUPSET_CALL(flush_tlb_mm
, smp_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1966 BTFIXUPSET_CALL(flush_tlb_range
, smp_flush_tlb_range
, BTFIXUPCALL_NORM
);
1967 BTFIXUPSET_CALL(flush_tlb_page
, smp_flush_tlb_page
, BTFIXUPCALL_NORM
);
1969 BTFIXUPSET_CALL(__flush_page_to_ram
, smp_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1970 BTFIXUPSET_CALL(flush_sig_insns
, smp_flush_sig_insns
, BTFIXUPCALL_NORM
);
1971 BTFIXUPSET_CALL(flush_page_for_dma
, smp_flush_page_for_dma
, BTFIXUPCALL_NORM
);
1973 if (poke_srmmu
== poke_viking
) {
1974 /* Avoid unnecessary cross calls. */
1975 BTFIXUPCOPY_CALL(flush_cache_all
, local_flush_cache_all
);
1976 BTFIXUPCOPY_CALL(flush_cache_mm
, local_flush_cache_mm
);
1977 BTFIXUPCOPY_CALL(flush_cache_range
, local_flush_cache_range
);
1978 BTFIXUPCOPY_CALL(flush_cache_page
, local_flush_cache_page
);
1979 BTFIXUPCOPY_CALL(__flush_page_to_ram
, local_flush_page_to_ram
);
1980 BTFIXUPCOPY_CALL(flush_sig_insns
, local_flush_sig_insns
);
1981 BTFIXUPCOPY_CALL(flush_page_for_dma
, local_flush_page_for_dma
);
1985 if (sparc_cpu_model
== sun4d
)
1990 if (sparc_cpu_model
== sun4d
)
1992 else if (sparc_cpu_model
== sparc_leon
)