2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cmd.h>
36 #include <linux/cache.h>
42 MLX4_COMMAND_INTERFACE_MIN_REV
= 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV
= 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS
= 3,
47 extern void __buggy_use_of_MLX4_GET(void);
48 extern void __buggy_use_of_MLX4_PUT(void);
50 static int enable_qos
;
51 module_param(enable_qos
, bool, 0444);
52 MODULE_PARM_DESC(enable_qos
, "Enable Quality of Service support in the HCA (default: off)");
54 #define MLX4_GET(dest, source, offset) \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
66 #define MLX4_PUT(dest, source, offset) \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
78 static void dump_dev_cap_flags(struct mlx4_dev
*dev
, u32 flags
)
80 static const char *fname
[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
84 [ 3] = "XRC transport",
85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
93 [15] = "Big LSO headers",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
101 [25] = "Router support",
102 [30] = "IBoE support"
106 mlx4_dbg(dev
, "DEV_CAP flags:\n");
107 for (i
= 0; i
< ARRAY_SIZE(fname
); ++i
)
108 if (fname
[i
] && (flags
& (1 << i
)))
109 mlx4_dbg(dev
, " %s\n", fname
[i
]);
112 int mlx4_MOD_STAT_CFG(struct mlx4_dev
*dev
, struct mlx4_mod_stat_cfg
*cfg
)
114 struct mlx4_cmd_mailbox
*mailbox
;
118 #define MOD_STAT_CFG_IN_SIZE 0x100
120 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
121 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
123 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
125 return PTR_ERR(mailbox
);
126 inbox
= mailbox
->buf
;
128 memset(inbox
, 0, MOD_STAT_CFG_IN_SIZE
);
130 MLX4_PUT(inbox
, cfg
->log_pg_sz
, MOD_STAT_CFG_PG_SZ_OFFSET
);
131 MLX4_PUT(inbox
, cfg
->log_pg_sz_m
, MOD_STAT_CFG_PG_SZ_M_OFFSET
);
133 err
= mlx4_cmd(dev
, mailbox
->dma
, 0, 0, MLX4_CMD_MOD_STAT_CFG
,
134 MLX4_CMD_TIME_CLASS_A
);
136 mlx4_free_cmd_mailbox(dev
, mailbox
);
140 int mlx4_QUERY_DEV_CAP(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
142 struct mlx4_cmd_mailbox
*mailbox
;
151 #define QUERY_DEV_CAP_OUT_SIZE 0x100
152 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
153 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
154 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
155 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
156 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
157 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
158 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
159 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
160 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
161 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
162 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
163 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
164 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
165 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
166 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
167 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
168 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
169 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
170 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
171 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
172 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
173 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
174 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
175 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
176 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
177 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
178 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
179 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
180 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
181 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
182 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
183 #define QUERY_DEV_CAP_UDP_RSS_OFFSET 0x42
184 #define QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET 0x43
185 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
186 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
187 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
188 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
189 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
190 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
191 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
192 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
193 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
194 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
195 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
196 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
197 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
198 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
199 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
200 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
201 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
202 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
203 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
204 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
205 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
206 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
207 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
208 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
209 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
210 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
211 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
212 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
213 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
214 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
216 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
218 return PTR_ERR(mailbox
);
219 outbox
= mailbox
->buf
;
221 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_DEV_CAP
,
222 MLX4_CMD_TIME_CLASS_A
);
226 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_QP_OFFSET
);
227 dev_cap
->reserved_qps
= 1 << (field
& 0xf);
228 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_OFFSET
);
229 dev_cap
->max_qps
= 1 << (field
& 0x1f);
230 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_SRQ_OFFSET
);
231 dev_cap
->reserved_srqs
= 1 << (field
>> 4);
232 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SRQ_OFFSET
);
233 dev_cap
->max_srqs
= 1 << (field
& 0x1f);
234 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET
);
235 dev_cap
->max_cq_sz
= 1 << field
;
236 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_CQ_OFFSET
);
237 dev_cap
->reserved_cqs
= 1 << (field
& 0xf);
238 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_CQ_OFFSET
);
239 dev_cap
->max_cqs
= 1 << (field
& 0x1f);
240 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MPT_OFFSET
);
241 dev_cap
->max_mpts
= 1 << (field
& 0x3f);
242 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_EQ_OFFSET
);
243 dev_cap
->reserved_eqs
= field
& 0xf;
244 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_EQ_OFFSET
);
245 dev_cap
->max_eqs
= 1 << (field
& 0xf);
246 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MTT_OFFSET
);
247 dev_cap
->reserved_mtts
= 1 << (field
>> 4);
248 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET
);
249 dev_cap
->max_mrw_sz
= 1 << field
;
250 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MRW_OFFSET
);
251 dev_cap
->reserved_mrws
= 1 << (field
& 0xf);
252 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET
);
253 dev_cap
->max_mtt_seg
= 1 << (field
& 0x3f);
254 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET
);
255 dev_cap
->max_requester_per_qp
= 1 << (field
& 0x3f);
256 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_RES_QP_OFFSET
);
257 dev_cap
->max_responder_per_qp
= 1 << (field
& 0x3f);
258 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_GSO_OFFSET
);
261 dev_cap
->max_gso_sz
= 0;
263 dev_cap
->max_gso_sz
= 1 << field
;
265 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_RDMA_OFFSET
);
266 dev_cap
->max_rdma_global
= 1 << (field
& 0x3f);
267 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_ACK_DELAY_OFFSET
);
268 dev_cap
->local_ca_ack_delay
= field
& 0x1f;
269 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
270 dev_cap
->num_ports
= field
& 0xf;
271 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET
);
272 dev_cap
->max_msg_sz
= 1 << (field
& 0x1f);
273 MLX4_GET(stat_rate
, outbox
, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET
);
274 dev_cap
->stat_rate_support
= stat_rate
;
275 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_UDP_RSS_OFFSET
);
276 dev_cap
->udp_rss
= field
& 0x1;
277 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET
);
278 dev_cap
->loopback_support
= field
& 0x1;
279 MLX4_GET(dev_cap
->flags
, outbox
, QUERY_DEV_CAP_FLAGS_OFFSET
);
280 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_UAR_OFFSET
);
281 dev_cap
->reserved_uars
= field
>> 4;
282 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_UAR_SZ_OFFSET
);
283 dev_cap
->uar_size
= 1 << ((field
& 0x3f) + 20);
284 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_PAGE_SZ_OFFSET
);
285 dev_cap
->min_page_sz
= 1 << field
;
287 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_BF_OFFSET
);
289 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET
);
290 dev_cap
->bf_reg_size
= 1 << (field
& 0x1f);
291 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET
);
292 dev_cap
->bf_regs_per_page
= 1 << (field
& 0x3f);
293 mlx4_dbg(dev
, "BlueFlame available (reg size %d, regs/page %d)\n",
294 dev_cap
->bf_reg_size
, dev_cap
->bf_regs_per_page
);
296 dev_cap
->bf_reg_size
= 0;
297 mlx4_dbg(dev
, "BlueFlame not available\n");
300 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET
);
301 dev_cap
->max_sq_sg
= field
;
302 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET
);
303 dev_cap
->max_sq_desc_sz
= size
;
305 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET
);
306 dev_cap
->max_qp_per_mcg
= 1 << field
;
307 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MCG_OFFSET
);
308 dev_cap
->reserved_mgms
= field
& 0xf;
309 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MCG_OFFSET
);
310 dev_cap
->max_mcgs
= 1 << field
;
311 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_PD_OFFSET
);
312 dev_cap
->reserved_pds
= field
>> 4;
313 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_PD_OFFSET
);
314 dev_cap
->max_pds
= 1 << (field
& 0x3f);
316 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET
);
317 dev_cap
->rdmarc_entry_sz
= size
;
318 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET
);
319 dev_cap
->qpc_entry_sz
= size
;
320 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET
);
321 dev_cap
->aux_entry_sz
= size
;
322 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET
);
323 dev_cap
->altc_entry_sz
= size
;
324 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET
);
325 dev_cap
->eqc_entry_sz
= size
;
326 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET
);
327 dev_cap
->cqc_entry_sz
= size
;
328 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET
);
329 dev_cap
->srq_entry_sz
= size
;
330 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET
);
331 dev_cap
->cmpt_entry_sz
= size
;
332 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET
);
333 dev_cap
->mtt_entry_sz
= size
;
334 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET
);
335 dev_cap
->dmpt_entry_sz
= size
;
337 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET
);
338 dev_cap
->max_srq_sz
= 1 << field
;
339 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET
);
340 dev_cap
->max_qp_sz
= 1 << field
;
341 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSZ_SRQ_OFFSET
);
342 dev_cap
->resize_srq
= field
& 1;
343 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET
);
344 dev_cap
->max_rq_sg
= field
;
345 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET
);
346 dev_cap
->max_rq_desc_sz
= size
;
348 MLX4_GET(dev_cap
->bmme_flags
, outbox
,
349 QUERY_DEV_CAP_BMME_FLAGS_OFFSET
);
350 MLX4_GET(dev_cap
->reserved_lkey
, outbox
,
351 QUERY_DEV_CAP_RSVD_LKEY_OFFSET
);
352 MLX4_GET(dev_cap
->max_icm_sz
, outbox
,
353 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET
);
355 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
356 for (i
= 1; i
<= dev_cap
->num_ports
; ++i
) {
357 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
358 dev_cap
->max_vl
[i
] = field
>> 4;
359 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MTU_WIDTH_OFFSET
);
360 dev_cap
->ib_mtu
[i
] = field
>> 4;
361 dev_cap
->max_port_width
[i
] = field
& 0xf;
362 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_GID_OFFSET
);
363 dev_cap
->max_gids
[i
] = 1 << (field
& 0xf);
364 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_PKEY_OFFSET
);
365 dev_cap
->max_pkeys
[i
] = 1 << (field
& 0xf);
368 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
369 #define QUERY_PORT_MTU_OFFSET 0x01
370 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
371 #define QUERY_PORT_WIDTH_OFFSET 0x06
372 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
373 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
374 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
375 #define QUERY_PORT_MAC_OFFSET 0x10
376 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
377 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
378 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
380 for (i
= 1; i
<= dev_cap
->num_ports
; ++i
) {
381 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, i
, 0, MLX4_CMD_QUERY_PORT
,
382 MLX4_CMD_TIME_CLASS_B
);
386 MLX4_GET(field
, outbox
, QUERY_PORT_SUPPORTED_TYPE_OFFSET
);
387 dev_cap
->supported_port_types
[i
] = field
& 3;
388 MLX4_GET(field
, outbox
, QUERY_PORT_MTU_OFFSET
);
389 dev_cap
->ib_mtu
[i
] = field
& 0xf;
390 MLX4_GET(field
, outbox
, QUERY_PORT_WIDTH_OFFSET
);
391 dev_cap
->max_port_width
[i
] = field
& 0xf;
392 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_GID_PKEY_OFFSET
);
393 dev_cap
->max_gids
[i
] = 1 << (field
>> 4);
394 dev_cap
->max_pkeys
[i
] = 1 << (field
& 0xf);
395 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_VL_OFFSET
);
396 dev_cap
->max_vl
[i
] = field
& 0xf;
397 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_MACVLAN_OFFSET
);
398 dev_cap
->log_max_macs
[i
] = field
& 0xf;
399 dev_cap
->log_max_vlans
[i
] = field
>> 4;
400 MLX4_GET(dev_cap
->eth_mtu
[i
], outbox
, QUERY_PORT_ETH_MTU_OFFSET
);
401 MLX4_GET(dev_cap
->def_mac
[i
], outbox
, QUERY_PORT_MAC_OFFSET
);
402 MLX4_GET(field32
, outbox
, QUERY_PORT_TRANS_VENDOR_OFFSET
);
403 dev_cap
->trans_type
[i
] = field32
>> 24;
404 dev_cap
->vendor_oui
[i
] = field32
& 0xffffff;
405 MLX4_GET(dev_cap
->wavelength
[i
], outbox
, QUERY_PORT_WAVELENGTH_OFFSET
);
406 MLX4_GET(dev_cap
->trans_code
[i
], outbox
, QUERY_PORT_TRANS_CODE_OFFSET
);
410 mlx4_dbg(dev
, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
411 dev_cap
->bmme_flags
, dev_cap
->reserved_lkey
);
414 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
415 * we can't use any EQs whose doorbell falls on that page,
416 * even if the EQ itself isn't reserved.
418 dev_cap
->reserved_eqs
= max(dev_cap
->reserved_uars
* 4,
419 dev_cap
->reserved_eqs
);
421 mlx4_dbg(dev
, "Max ICM size %lld MB\n",
422 (unsigned long long) dev_cap
->max_icm_sz
>> 20);
423 mlx4_dbg(dev
, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
424 dev_cap
->max_qps
, dev_cap
->reserved_qps
, dev_cap
->qpc_entry_sz
);
425 mlx4_dbg(dev
, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
426 dev_cap
->max_srqs
, dev_cap
->reserved_srqs
, dev_cap
->srq_entry_sz
);
427 mlx4_dbg(dev
, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
428 dev_cap
->max_cqs
, dev_cap
->reserved_cqs
, dev_cap
->cqc_entry_sz
);
429 mlx4_dbg(dev
, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
430 dev_cap
->max_eqs
, dev_cap
->reserved_eqs
, dev_cap
->eqc_entry_sz
);
431 mlx4_dbg(dev
, "reserved MPTs: %d, reserved MTTs: %d\n",
432 dev_cap
->reserved_mrws
, dev_cap
->reserved_mtts
);
433 mlx4_dbg(dev
, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
434 dev_cap
->max_pds
, dev_cap
->reserved_pds
, dev_cap
->reserved_uars
);
435 mlx4_dbg(dev
, "Max QP/MCG: %d, reserved MGMs: %d\n",
436 dev_cap
->max_pds
, dev_cap
->reserved_mgms
);
437 mlx4_dbg(dev
, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
438 dev_cap
->max_cq_sz
, dev_cap
->max_qp_sz
, dev_cap
->max_srq_sz
);
439 mlx4_dbg(dev
, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
440 dev_cap
->local_ca_ack_delay
, 128 << dev_cap
->ib_mtu
[1],
441 dev_cap
->max_port_width
[1]);
442 mlx4_dbg(dev
, "Max SQ desc size: %d, max SQ S/G: %d\n",
443 dev_cap
->max_sq_desc_sz
, dev_cap
->max_sq_sg
);
444 mlx4_dbg(dev
, "Max RQ desc size: %d, max RQ S/G: %d\n",
445 dev_cap
->max_rq_desc_sz
, dev_cap
->max_rq_sg
);
446 mlx4_dbg(dev
, "Max GSO size: %d\n", dev_cap
->max_gso_sz
);
448 dump_dev_cap_flags(dev
, dev_cap
->flags
);
451 mlx4_free_cmd_mailbox(dev
, mailbox
);
455 int mlx4_map_cmd(struct mlx4_dev
*dev
, u16 op
, struct mlx4_icm
*icm
, u64 virt
)
457 struct mlx4_cmd_mailbox
*mailbox
;
458 struct mlx4_icm_iter iter
;
466 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
468 return PTR_ERR(mailbox
);
469 memset(mailbox
->buf
, 0, MLX4_MAILBOX_SIZE
);
470 pages
= mailbox
->buf
;
472 for (mlx4_icm_first(icm
, &iter
);
473 !mlx4_icm_last(&iter
);
474 mlx4_icm_next(&iter
)) {
476 * We have to pass pages that are aligned to their
477 * size, so find the least significant 1 in the
478 * address or size and use that as our log2 size.
480 lg
= ffs(mlx4_icm_addr(&iter
) | mlx4_icm_size(&iter
)) - 1;
481 if (lg
< MLX4_ICM_PAGE_SHIFT
) {
482 mlx4_warn(dev
, "Got FW area not aligned to %d (%llx/%lx).\n",
484 (unsigned long long) mlx4_icm_addr(&iter
),
485 mlx4_icm_size(&iter
));
490 for (i
= 0; i
< mlx4_icm_size(&iter
) >> lg
; ++i
) {
492 pages
[nent
* 2] = cpu_to_be64(virt
);
496 pages
[nent
* 2 + 1] =
497 cpu_to_be64((mlx4_icm_addr(&iter
) + (i
<< lg
)) |
498 (lg
- MLX4_ICM_PAGE_SHIFT
));
499 ts
+= 1 << (lg
- 10);
502 if (++nent
== MLX4_MAILBOX_SIZE
/ 16) {
503 err
= mlx4_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
504 MLX4_CMD_TIME_CLASS_B
);
513 err
= mlx4_cmd(dev
, mailbox
->dma
, nent
, 0, op
, MLX4_CMD_TIME_CLASS_B
);
518 case MLX4_CMD_MAP_FA
:
519 mlx4_dbg(dev
, "Mapped %d chunks/%d KB for FW.\n", tc
, ts
);
521 case MLX4_CMD_MAP_ICM_AUX
:
522 mlx4_dbg(dev
, "Mapped %d chunks/%d KB for ICM aux.\n", tc
, ts
);
524 case MLX4_CMD_MAP_ICM
:
525 mlx4_dbg(dev
, "Mapped %d chunks/%d KB at %llx for ICM.\n",
526 tc
, ts
, (unsigned long long) virt
- (ts
<< 10));
531 mlx4_free_cmd_mailbox(dev
, mailbox
);
535 int mlx4_MAP_FA(struct mlx4_dev
*dev
, struct mlx4_icm
*icm
)
537 return mlx4_map_cmd(dev
, MLX4_CMD_MAP_FA
, icm
, -1);
540 int mlx4_UNMAP_FA(struct mlx4_dev
*dev
)
542 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_UNMAP_FA
, MLX4_CMD_TIME_CLASS_B
);
546 int mlx4_RUN_FW(struct mlx4_dev
*dev
)
548 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_RUN_FW
, MLX4_CMD_TIME_CLASS_A
);
551 int mlx4_QUERY_FW(struct mlx4_dev
*dev
)
553 struct mlx4_fw
*fw
= &mlx4_priv(dev
)->fw
;
554 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
555 struct mlx4_cmd_mailbox
*mailbox
;
562 #define QUERY_FW_OUT_SIZE 0x100
563 #define QUERY_FW_VER_OFFSET 0x00
564 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
565 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
566 #define QUERY_FW_ERR_START_OFFSET 0x30
567 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
568 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
570 #define QUERY_FW_SIZE_OFFSET 0x00
571 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
572 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
574 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
576 return PTR_ERR(mailbox
);
577 outbox
= mailbox
->buf
;
579 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_FW
,
580 MLX4_CMD_TIME_CLASS_A
);
584 MLX4_GET(fw_ver
, outbox
, QUERY_FW_VER_OFFSET
);
586 * FW subminor version is at more significant bits than minor
587 * version, so swap here.
589 dev
->caps
.fw_ver
= (fw_ver
& 0xffff00000000ull
) |
590 ((fw_ver
& 0xffff0000ull
) >> 16) |
591 ((fw_ver
& 0x0000ffffull
) << 16);
593 MLX4_GET(cmd_if_rev
, outbox
, QUERY_FW_CMD_IF_REV_OFFSET
);
594 if (cmd_if_rev
< MLX4_COMMAND_INTERFACE_MIN_REV
||
595 cmd_if_rev
> MLX4_COMMAND_INTERFACE_MAX_REV
) {
596 mlx4_err(dev
, "Installed FW has unsupported "
597 "command interface revision %d.\n",
599 mlx4_err(dev
, "(Installed FW version is %d.%d.%03d)\n",
600 (int) (dev
->caps
.fw_ver
>> 32),
601 (int) (dev
->caps
.fw_ver
>> 16) & 0xffff,
602 (int) dev
->caps
.fw_ver
& 0xffff);
603 mlx4_err(dev
, "This driver version supports only revisions %d to %d.\n",
604 MLX4_COMMAND_INTERFACE_MIN_REV
, MLX4_COMMAND_INTERFACE_MAX_REV
);
609 if (cmd_if_rev
< MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS
)
610 dev
->flags
|= MLX4_FLAG_OLD_PORT_CMDS
;
612 MLX4_GET(lg
, outbox
, QUERY_FW_MAX_CMD_OFFSET
);
613 cmd
->max_cmds
= 1 << lg
;
615 mlx4_dbg(dev
, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
616 (int) (dev
->caps
.fw_ver
>> 32),
617 (int) (dev
->caps
.fw_ver
>> 16) & 0xffff,
618 (int) dev
->caps
.fw_ver
& 0xffff,
619 cmd_if_rev
, cmd
->max_cmds
);
621 MLX4_GET(fw
->catas_offset
, outbox
, QUERY_FW_ERR_START_OFFSET
);
622 MLX4_GET(fw
->catas_size
, outbox
, QUERY_FW_ERR_SIZE_OFFSET
);
623 MLX4_GET(fw
->catas_bar
, outbox
, QUERY_FW_ERR_BAR_OFFSET
);
624 fw
->catas_bar
= (fw
->catas_bar
>> 6) * 2;
626 mlx4_dbg(dev
, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
627 (unsigned long long) fw
->catas_offset
, fw
->catas_size
, fw
->catas_bar
);
629 MLX4_GET(fw
->fw_pages
, outbox
, QUERY_FW_SIZE_OFFSET
);
630 MLX4_GET(fw
->clr_int_base
, outbox
, QUERY_FW_CLR_INT_BASE_OFFSET
);
631 MLX4_GET(fw
->clr_int_bar
, outbox
, QUERY_FW_CLR_INT_BAR_OFFSET
);
632 fw
->clr_int_bar
= (fw
->clr_int_bar
>> 6) * 2;
634 mlx4_dbg(dev
, "FW size %d KB\n", fw
->fw_pages
>> 2);
637 * Round up number of system pages needed in case
638 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
641 ALIGN(fw
->fw_pages
, PAGE_SIZE
/ MLX4_ICM_PAGE_SIZE
) >>
642 (PAGE_SHIFT
- MLX4_ICM_PAGE_SHIFT
);
644 mlx4_dbg(dev
, "Clear int @ %llx, BAR %d\n",
645 (unsigned long long) fw
->clr_int_base
, fw
->clr_int_bar
);
648 mlx4_free_cmd_mailbox(dev
, mailbox
);
652 static void get_board_id(void *vsd
, char *board_id
)
656 #define VSD_OFFSET_SIG1 0x00
657 #define VSD_OFFSET_SIG2 0xde
658 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
659 #define VSD_OFFSET_TS_BOARD_ID 0x20
661 #define VSD_SIGNATURE_TOPSPIN 0x5ad
663 memset(board_id
, 0, MLX4_BOARD_ID_LEN
);
665 if (be16_to_cpup(vsd
+ VSD_OFFSET_SIG1
) == VSD_SIGNATURE_TOPSPIN
&&
666 be16_to_cpup(vsd
+ VSD_OFFSET_SIG2
) == VSD_SIGNATURE_TOPSPIN
) {
667 strlcpy(board_id
, vsd
+ VSD_OFFSET_TS_BOARD_ID
, MLX4_BOARD_ID_LEN
);
670 * The board ID is a string but the firmware byte
671 * swaps each 4-byte word before passing it back to
672 * us. Therefore we need to swab it before printing.
674 for (i
= 0; i
< 4; ++i
)
675 ((u32
*) board_id
)[i
] =
676 swab32(*(u32
*) (vsd
+ VSD_OFFSET_MLX_BOARD_ID
+ i
* 4));
680 int mlx4_QUERY_ADAPTER(struct mlx4_dev
*dev
, struct mlx4_adapter
*adapter
)
682 struct mlx4_cmd_mailbox
*mailbox
;
686 #define QUERY_ADAPTER_OUT_SIZE 0x100
687 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
688 #define QUERY_ADAPTER_VSD_OFFSET 0x20
690 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
692 return PTR_ERR(mailbox
);
693 outbox
= mailbox
->buf
;
695 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_ADAPTER
,
696 MLX4_CMD_TIME_CLASS_A
);
700 MLX4_GET(adapter
->inta_pin
, outbox
, QUERY_ADAPTER_INTA_PIN_OFFSET
);
702 get_board_id(outbox
+ QUERY_ADAPTER_VSD_OFFSET
/ 4,
706 mlx4_free_cmd_mailbox(dev
, mailbox
);
710 int mlx4_INIT_HCA(struct mlx4_dev
*dev
, struct mlx4_init_hca_param
*param
)
712 struct mlx4_cmd_mailbox
*mailbox
;
716 #define INIT_HCA_IN_SIZE 0x200
717 #define INIT_HCA_VERSION_OFFSET 0x000
718 #define INIT_HCA_VERSION 2
719 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
720 #define INIT_HCA_FLAGS_OFFSET 0x014
721 #define INIT_HCA_QPC_OFFSET 0x020
722 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
723 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
724 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
725 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
726 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
727 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
728 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
729 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
730 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
731 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
732 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
733 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
734 #define INIT_HCA_MCAST_OFFSET 0x0c0
735 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
736 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
737 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
738 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
739 #define INIT_HCA_TPT_OFFSET 0x0f0
740 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
741 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
742 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
743 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
744 #define INIT_HCA_UAR_OFFSET 0x120
745 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
746 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
748 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
750 return PTR_ERR(mailbox
);
751 inbox
= mailbox
->buf
;
753 memset(inbox
, 0, INIT_HCA_IN_SIZE
);
755 *((u8
*) mailbox
->buf
+ INIT_HCA_VERSION_OFFSET
) = INIT_HCA_VERSION
;
757 *((u8
*) mailbox
->buf
+ INIT_HCA_CACHELINE_SZ_OFFSET
) =
758 (ilog2(cache_line_size()) - 4) << 5;
760 #if defined(__LITTLE_ENDIAN)
761 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) &= ~cpu_to_be32(1 << 1);
762 #elif defined(__BIG_ENDIAN)
763 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 1);
765 #error Host endianness not defined
767 /* Check port for UD address vector: */
768 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1);
770 /* Enable IPoIB checksumming if we can: */
771 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IPOIB_CSUM
)
772 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 3);
774 /* Enable QoS support if module parameter set */
776 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 2);
778 /* QPC/EEC/CQC/EQC/RDMARC attributes */
780 MLX4_PUT(inbox
, param
->qpc_base
, INIT_HCA_QPC_BASE_OFFSET
);
781 MLX4_PUT(inbox
, param
->log_num_qps
, INIT_HCA_LOG_QP_OFFSET
);
782 MLX4_PUT(inbox
, param
->srqc_base
, INIT_HCA_SRQC_BASE_OFFSET
);
783 MLX4_PUT(inbox
, param
->log_num_srqs
, INIT_HCA_LOG_SRQ_OFFSET
);
784 MLX4_PUT(inbox
, param
->cqc_base
, INIT_HCA_CQC_BASE_OFFSET
);
785 MLX4_PUT(inbox
, param
->log_num_cqs
, INIT_HCA_LOG_CQ_OFFSET
);
786 MLX4_PUT(inbox
, param
->altc_base
, INIT_HCA_ALTC_BASE_OFFSET
);
787 MLX4_PUT(inbox
, param
->auxc_base
, INIT_HCA_AUXC_BASE_OFFSET
);
788 MLX4_PUT(inbox
, param
->eqc_base
, INIT_HCA_EQC_BASE_OFFSET
);
789 MLX4_PUT(inbox
, param
->log_num_eqs
, INIT_HCA_LOG_EQ_OFFSET
);
790 MLX4_PUT(inbox
, param
->rdmarc_base
, INIT_HCA_RDMARC_BASE_OFFSET
);
791 MLX4_PUT(inbox
, param
->log_rd_per_qp
, INIT_HCA_LOG_RD_OFFSET
);
793 /* multicast attributes */
795 MLX4_PUT(inbox
, param
->mc_base
, INIT_HCA_MC_BASE_OFFSET
);
796 MLX4_PUT(inbox
, param
->log_mc_entry_sz
, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
);
797 MLX4_PUT(inbox
, param
->log_mc_hash_sz
, INIT_HCA_LOG_MC_HASH_SZ_OFFSET
);
798 MLX4_PUT(inbox
, param
->log_mc_table_sz
, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
);
802 MLX4_PUT(inbox
, param
->dmpt_base
, INIT_HCA_DMPT_BASE_OFFSET
);
803 MLX4_PUT(inbox
, param
->log_mpt_sz
, INIT_HCA_LOG_MPT_SZ_OFFSET
);
804 MLX4_PUT(inbox
, param
->mtt_base
, INIT_HCA_MTT_BASE_OFFSET
);
805 MLX4_PUT(inbox
, param
->cmpt_base
, INIT_HCA_CMPT_BASE_OFFSET
);
809 MLX4_PUT(inbox
, (u8
) (PAGE_SHIFT
- 12), INIT_HCA_UAR_PAGE_SZ_OFFSET
);
810 MLX4_PUT(inbox
, param
->log_uar_sz
, INIT_HCA_LOG_UAR_SZ_OFFSET
);
812 err
= mlx4_cmd(dev
, mailbox
->dma
, 0, 0, MLX4_CMD_INIT_HCA
, 10000);
815 mlx4_err(dev
, "INIT_HCA returns %d\n", err
);
817 mlx4_free_cmd_mailbox(dev
, mailbox
);
821 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
)
823 struct mlx4_cmd_mailbox
*mailbox
;
829 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
830 #define INIT_PORT_IN_SIZE 256
831 #define INIT_PORT_FLAGS_OFFSET 0x00
832 #define INIT_PORT_FLAG_SIG (1 << 18)
833 #define INIT_PORT_FLAG_NG (1 << 17)
834 #define INIT_PORT_FLAG_G0 (1 << 16)
835 #define INIT_PORT_VL_SHIFT 4
836 #define INIT_PORT_PORT_WIDTH_SHIFT 8
837 #define INIT_PORT_MTU_OFFSET 0x04
838 #define INIT_PORT_MAX_GID_OFFSET 0x06
839 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
840 #define INIT_PORT_GUID0_OFFSET 0x10
841 #define INIT_PORT_NODE_GUID_OFFSET 0x18
842 #define INIT_PORT_SI_GUID_OFFSET 0x20
844 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
846 return PTR_ERR(mailbox
);
847 inbox
= mailbox
->buf
;
849 memset(inbox
, 0, INIT_PORT_IN_SIZE
);
852 flags
|= (dev
->caps
.vl_cap
[port
] & 0xf) << INIT_PORT_VL_SHIFT
;
853 flags
|= (dev
->caps
.port_width_cap
[port
] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT
;
854 MLX4_PUT(inbox
, flags
, INIT_PORT_FLAGS_OFFSET
);
856 field
= 128 << dev
->caps
.ib_mtu_cap
[port
];
857 MLX4_PUT(inbox
, field
, INIT_PORT_MTU_OFFSET
);
858 field
= dev
->caps
.gid_table_len
[port
];
859 MLX4_PUT(inbox
, field
, INIT_PORT_MAX_GID_OFFSET
);
860 field
= dev
->caps
.pkey_table_len
[port
];
861 MLX4_PUT(inbox
, field
, INIT_PORT_MAX_PKEY_OFFSET
);
863 err
= mlx4_cmd(dev
, mailbox
->dma
, port
, 0, MLX4_CMD_INIT_PORT
,
864 MLX4_CMD_TIME_CLASS_A
);
866 mlx4_free_cmd_mailbox(dev
, mailbox
);
868 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_INIT_PORT
,
869 MLX4_CMD_TIME_CLASS_A
);
873 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT
);
875 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
)
877 return mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_CLOSE_PORT
, 1000);
879 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT
);
881 int mlx4_CLOSE_HCA(struct mlx4_dev
*dev
, int panic
)
883 return mlx4_cmd(dev
, 0, 0, panic
, MLX4_CMD_CLOSE_HCA
, 1000);
886 int mlx4_SET_ICM_SIZE(struct mlx4_dev
*dev
, u64 icm_size
, u64
*aux_pages
)
888 int ret
= mlx4_cmd_imm(dev
, icm_size
, aux_pages
, 0, 0,
889 MLX4_CMD_SET_ICM_SIZE
,
890 MLX4_CMD_TIME_CLASS_A
);
895 * Round up number of system pages needed in case
896 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
898 *aux_pages
= ALIGN(*aux_pages
, PAGE_SIZE
/ MLX4_ICM_PAGE_SIZE
) >>
899 (PAGE_SHIFT
- MLX4_ICM_PAGE_SHIFT
);
904 int mlx4_NOP(struct mlx4_dev
*dev
)
906 /* Input modifier of 0x1f means "finish as soon as possible." */
907 return mlx4_cmd(dev
, 0, 0x1f, 0, MLX4_CMD_NOP
, 100);