1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
26 #include <asm/system.h>
28 #include <asm/pgalloc.h>
29 #include <asm/pgtable.h>
30 #include <asm/oplib.h>
31 #include <asm/iommu.h>
33 #include <asm/uaccess.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
37 #include <asm/starfire.h>
39 #include <asm/spitfire.h>
40 #include <asm/sections.h>
42 extern void device_scan(void);
44 struct sparc_phys_banks sp_banks
[SPARC_PHYS_BANKS
];
46 unsigned long *sparc64_valid_addr_bitmap
;
48 /* Ugly, but necessary... -DaveM */
49 unsigned long phys_base __read_mostly
;
50 unsigned long kern_base __read_mostly
;
51 unsigned long kern_size __read_mostly
;
52 unsigned long pfn_base __read_mostly
;
54 /* This is even uglier. We have a problem where the kernel may not be
55 * located at phys_base. However, initial __alloc_bootmem() calls need to
56 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
57 * those page mappings wont work. Things are ok after inherit_prom_mappings
58 * is called though. Dave says he'll clean this up some other time.
61 static unsigned long bootmap_base
;
63 /* get_new_mmu_context() uses "cache + 1". */
64 DEFINE_SPINLOCK(ctx_alloc_lock
);
65 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
66 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
67 unsigned long mmu_context_bmap
[CTX_BMAP_SLOTS
];
69 /* References to special section boundaries */
70 extern char _start
[], _end
[];
72 /* Initial ramdisk setup */
73 extern unsigned long sparc_ramdisk_image64
;
74 extern unsigned int sparc_ramdisk_image
;
75 extern unsigned int sparc_ramdisk_size
;
77 struct page
*mem_map_zero __read_mostly
;
81 /* XXX Tune this... */
82 #define PGT_CACHE_LOW 25
83 #define PGT_CACHE_HIGH 50
85 void check_pgt_cache(void)
88 if (pgtable_cache_size
> PGT_CACHE_HIGH
) {
91 free_pgd_slow(get_pgd_fast());
93 free_pte_slow(pte_alloc_one_fast(NULL
, 0));
95 free_pte_slow(pte_alloc_one_fast(NULL
, 1 << (PAGE_SHIFT
+ 10)));
96 } while (pgtable_cache_size
> PGT_CACHE_LOW
);
101 #ifdef CONFIG_DEBUG_DCFLUSH
102 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
104 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
108 __inline__
void flush_dcache_page_impl(struct page
*page
)
110 #ifdef CONFIG_DEBUG_DCFLUSH
111 atomic_inc(&dcpage_flushes
);
114 #ifdef DCACHE_ALIASING_POSSIBLE
115 __flush_dcache_page(page_address(page
),
116 ((tlb_type
== spitfire
) &&
117 page_mapping(page
) != NULL
));
119 if (page_mapping(page
) != NULL
&&
120 tlb_type
== spitfire
)
121 __flush_icache_page(__pa(page_address(page
)));
125 #define PG_dcache_dirty PG_arch_1
126 #define PG_dcache_cpu_shift 24
127 #define PG_dcache_cpu_mask (256 - 1)
130 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
133 #define dcache_dirty_cpu(page) \
134 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
136 static __inline__
void set_dcache_dirty(struct page
*page
, int this_cpu
)
138 unsigned long mask
= this_cpu
;
139 unsigned long non_cpu_bits
;
141 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
142 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
144 __asm__
__volatile__("1:\n\t"
146 "and %%g7, %1, %%g1\n\t"
147 "or %%g1, %0, %%g1\n\t"
148 "casx [%2], %%g7, %%g1\n\t"
150 "membar #StoreLoad | #StoreStore\n\t"
151 "bne,pn %%xcc, 1b\n\t"
154 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
158 static __inline__
void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
160 unsigned long mask
= (1UL << PG_dcache_dirty
);
162 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
165 "srlx %%g7, %4, %%g1\n\t"
166 "and %%g1, %3, %%g1\n\t"
168 "bne,pn %%icc, 2f\n\t"
169 " andn %%g7, %1, %%g1\n\t"
170 "casx [%2], %%g7, %%g1\n\t"
172 "membar #StoreLoad | #StoreStore\n\t"
173 "bne,pn %%xcc, 1b\n\t"
177 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
178 "i" (PG_dcache_cpu_mask
),
179 "i" (PG_dcache_cpu_shift
)
183 extern void __update_mmu_cache(unsigned long mmu_context_hw
, unsigned long address
, pte_t pte
, int code
);
185 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
189 unsigned long pg_flags
;
192 if (pfn_valid(pfn
) &&
193 (page
= pfn_to_page(pfn
), page_mapping(page
)) &&
194 ((pg_flags
= page
->flags
) & (1UL << PG_dcache_dirty
))) {
195 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
197 int this_cpu
= get_cpu();
199 /* This is just to optimize away some function calls
203 flush_dcache_page_impl(page
);
205 smp_flush_dcache_page_impl(page
, cpu
);
207 clear_dcache_dirty_cpu(page
, cpu
);
212 if (get_thread_fault_code())
213 __update_mmu_cache(CTX_NRBITS(vma
->vm_mm
->context
),
214 address
, pte
, get_thread_fault_code());
217 void flush_dcache_page(struct page
*page
)
219 struct address_space
*mapping
;
222 /* Do not bother with the expensive D-cache flush if it
223 * is merely the zero page. The 'bigcore' testcase in GDB
224 * causes this case to run millions of times.
226 if (page
== ZERO_PAGE(0))
229 this_cpu
= get_cpu();
231 mapping
= page_mapping(page
);
232 if (mapping
&& !mapping_mapped(mapping
)) {
233 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
235 int dirty_cpu
= dcache_dirty_cpu(page
);
237 if (dirty_cpu
== this_cpu
)
239 smp_flush_dcache_page_impl(page
, dirty_cpu
);
241 set_dcache_dirty(page
, this_cpu
);
243 /* We could delay the flush for the !page_mapping
244 * case too. But that case is for exec env/arg
245 * pages and those are %99 certainly going to get
246 * faulted into the tlb (and thus flushed) anyways.
248 flush_dcache_page_impl(page
);
255 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
257 /* Cheetah has coherent I-cache. */
258 if (tlb_type
== spitfire
) {
261 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
)
262 __flush_icache_page(__get_phys(kaddr
));
266 unsigned long page_to_pfn(struct page
*page
)
268 return (unsigned long) ((page
- mem_map
) + pfn_base
);
271 struct page
*pfn_to_page(unsigned long pfn
)
273 return (mem_map
+ (pfn
- pfn_base
));
278 printk("Mem-info:\n");
280 printk("Free swap: %6ldkB\n",
281 nr_swap_pages
<< (PAGE_SHIFT
-10));
282 printk("%ld pages of RAM\n", num_physpages
);
283 printk("%d free pages\n", nr_free_pages());
284 printk("%d pages in page table cache\n",pgtable_cache_size
);
287 void mmu_info(struct seq_file
*m
)
289 if (tlb_type
== cheetah
)
290 seq_printf(m
, "MMU Type\t: Cheetah\n");
291 else if (tlb_type
== cheetah_plus
)
292 seq_printf(m
, "MMU Type\t: Cheetah+\n");
293 else if (tlb_type
== spitfire
)
294 seq_printf(m
, "MMU Type\t: Spitfire\n");
296 seq_printf(m
, "MMU Type\t: ???\n");
298 #ifdef CONFIG_DEBUG_DCFLUSH
299 seq_printf(m
, "DCPageFlushes\t: %d\n",
300 atomic_read(&dcpage_flushes
));
302 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
303 atomic_read(&dcpage_flushes_xcall
));
304 #endif /* CONFIG_SMP */
305 #endif /* CONFIG_DEBUG_DCFLUSH */
308 struct linux_prom_translation
{
313 static struct linux_prom_translation prom_trans
[512] __initdata
;
315 extern unsigned long prom_boot_page
;
316 extern void prom_remap(unsigned long physpage
, unsigned long virtpage
, int mmu_ihandle
);
317 extern int prom_get_mmu_ihandle(void);
318 extern void register_prom_callbacks(void);
320 /* Exported for SMP bootup purposes. */
321 unsigned long kern_locked_tte_data
;
323 /* Exported for kernel TLB miss handling in ktlb.S */
324 unsigned long prom_pmd_phys __read_mostly
;
325 unsigned int swapper_pgd_zero __read_mostly
;
327 void __init
early_pgtable_allocfail(char *type
)
329 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type
);
333 #define BASE_PAGE_SIZE 8192
334 static pmd_t
*prompmd
;
337 * Translate PROM's mapping we capture at boot time into physical address.
338 * The second parameter is only set from prom_callback() invocations.
340 unsigned long prom_virt_to_phys(unsigned long promva
, int *error
)
342 pmd_t
*pmdp
= prompmd
+ ((promva
>> 23) & 0x7ff);
346 if (pmd_none(*pmdp
)) {
351 ptep
= (pte_t
*)__pmd_page(*pmdp
) + ((promva
>> 13) & 0x3ff);
352 if (!pte_present(*ptep
)) {
359 return(pte_val(*ptep
));
361 base
= pte_val(*ptep
) & _PAGE_PADDR
;
362 return(base
+ (promva
& (BASE_PAGE_SIZE
- 1)));
365 static void inherit_prom_mappings(void)
367 unsigned long phys_page
, tte_vaddr
, tte_data
;
368 void (*remap_func
)(unsigned long, unsigned long, int);
373 node
= prom_finddevice("/virtual-memory");
374 n
= prom_getproplen(node
, "translations");
375 if (n
== 0 || n
== -1) {
376 prom_printf("prom_mappings: Couldn't get size.\n");
379 n
+= 24 * sizeof(struct linux_prom_translation
);
380 if (n
> sizeof(prom_trans
)) {
381 prom_printf("prom_mappings: prom_trans too small, "
382 "need %Zd bytes\n", n
);
386 if ((n
= prom_getproperty(node
, "translations",
387 (char *)&prom_trans
[0], tsz
)) == -1) {
388 prom_printf("prom_mappings: Couldn't get property.\n");
391 n
= n
/ sizeof(struct linux_prom_translation
);
393 /* The obp translations are saved based on 8k pagesize, since obp
394 * can use a mixture of pagesizes. Misses to the 0xf0000000 ->
395 * 0x100000000, ie obp range, are handled in entry.S and do not
396 * use the vpte scheme (see rant: inherit_locked_prom_mappings).
398 #define OBP_PMD_SIZE 2048
399 prompmd
= __alloc_bootmem(OBP_PMD_SIZE
, OBP_PMD_SIZE
, bootmap_base
);
401 early_pgtable_allocfail("pmd");
402 memset(prompmd
, 0, OBP_PMD_SIZE
);
403 for (i
= 0; i
< n
; i
++) {
406 if (prom_trans
[i
].virt
>= LOW_OBP_ADDRESS
&& prom_trans
[i
].virt
< HI_OBP_ADDRESS
) {
407 for (vaddr
= prom_trans
[i
].virt
;
408 ((vaddr
< prom_trans
[i
].virt
+ prom_trans
[i
].size
) &&
409 (vaddr
< HI_OBP_ADDRESS
));
410 vaddr
+= BASE_PAGE_SIZE
) {
413 pmdp
= prompmd
+ ((vaddr
>> 23) & 0x7ff);
414 if (pmd_none(*pmdp
)) {
415 ptep
= __alloc_bootmem(BASE_PAGE_SIZE
,
419 early_pgtable_allocfail("pte");
420 memset(ptep
, 0, BASE_PAGE_SIZE
);
423 ptep
= (pte_t
*)__pmd_page(*pmdp
) +
424 ((vaddr
>> 13) & 0x3ff);
426 val
= prom_trans
[i
].data
;
428 /* Clear diag TTE bits. */
429 if (tlb_type
== spitfire
)
430 val
&= ~0x0003fe0000000000UL
;
432 set_pte_at(&init_mm
, vaddr
,
433 ptep
, __pte(val
| _PAGE_MODIFIED
));
434 prom_trans
[i
].data
+= BASE_PAGE_SIZE
;
438 prom_pmd_phys
= __pa(prompmd
);
440 /* Now fixup OBP's idea about where we really are mapped. */
441 prom_printf("Remapping the kernel... ");
443 /* Spitfire Errata #32 workaround */
444 /* NOTE: Using plain zero for the context value is
445 * correct here, we are not using the Linux trap
446 * tables yet so we should not use the special
447 * UltraSPARC-III+ page size encodings yet.
449 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
452 : "r" (0), "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
457 phys_page
= spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
462 phys_page
= cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
466 phys_page
&= _PAGE_PADDR
;
467 phys_page
+= ((unsigned long)&prom_boot_page
-
468 (unsigned long)KERNBASE
);
470 if (tlb_type
== spitfire
) {
471 /* Lock this into i/d tlb entry 59 */
472 __asm__
__volatile__(
473 "stxa %%g0, [%2] %3\n\t"
474 "stxa %0, [%1] %4\n\t"
477 "stxa %%g0, [%2] %5\n\t"
478 "stxa %0, [%1] %6\n\t"
481 : : "r" (phys_page
| _PAGE_VALID
| _PAGE_SZ8K
| _PAGE_CP
|
482 _PAGE_CV
| _PAGE_P
| _PAGE_L
| _PAGE_W
),
483 "r" (59 << 3), "r" (TLB_TAG_ACCESS
),
484 "i" (ASI_DMMU
), "i" (ASI_DTLB_DATA_ACCESS
),
485 "i" (ASI_IMMU
), "i" (ASI_ITLB_DATA_ACCESS
)
487 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
488 /* Lock this into i/d tlb-0 entry 11 */
489 __asm__
__volatile__(
490 "stxa %%g0, [%2] %3\n\t"
491 "stxa %0, [%1] %4\n\t"
494 "stxa %%g0, [%2] %5\n\t"
495 "stxa %0, [%1] %6\n\t"
498 : : "r" (phys_page
| _PAGE_VALID
| _PAGE_SZ8K
| _PAGE_CP
|
499 _PAGE_CV
| _PAGE_P
| _PAGE_L
| _PAGE_W
),
500 "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS
),
501 "i" (ASI_DMMU
), "i" (ASI_DTLB_DATA_ACCESS
),
502 "i" (ASI_IMMU
), "i" (ASI_ITLB_DATA_ACCESS
)
505 /* Implement me :-) */
509 tte_vaddr
= (unsigned long) KERNBASE
;
511 /* Spitfire Errata #32 workaround */
512 /* NOTE: Using plain zero for the context value is
513 * correct here, we are not using the Linux trap
514 * tables yet so we should not use the special
515 * UltraSPARC-III+ page size encodings yet.
517 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
521 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
523 if (tlb_type
== spitfire
)
524 tte_data
= spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
526 tte_data
= cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
528 kern_locked_tte_data
= tte_data
;
530 remap_func
= (void *) ((unsigned long) &prom_remap
-
531 (unsigned long) &prom_boot_page
);
534 /* Spitfire Errata #32 workaround */
535 /* NOTE: Using plain zero for the context value is
536 * correct here, we are not using the Linux trap
537 * tables yet so we should not use the special
538 * UltraSPARC-III+ page size encodings yet.
540 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
544 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
546 remap_func((tlb_type
== spitfire
?
547 (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR
) :
548 (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR
)),
549 (unsigned long) KERNBASE
,
550 prom_get_mmu_ihandle());
553 remap_func(((tte_data
+ 0x400000) & _PAGE_PADDR
),
554 (unsigned long) KERNBASE
+ 0x400000, prom_get_mmu_ihandle());
556 /* Flush out that temporary mapping. */
557 spitfire_flush_dtlb_nucleus_page(0x0);
558 spitfire_flush_itlb_nucleus_page(0x0);
560 /* Now lock us back into the TLBs via OBP. */
561 prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data
, tte_vaddr
);
562 prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data
, tte_vaddr
);
564 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data
+ 0x400000,
565 tte_vaddr
+ 0x400000);
566 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data
+ 0x400000,
567 tte_vaddr
+ 0x400000);
570 /* Re-read translations property. */
571 if ((n
= prom_getproperty(node
, "translations",
572 (char *)&prom_trans
[0], tsz
)) == -1) {
573 prom_printf("prom_mappings: Can't reread prom_trans.\n");
576 n
= n
/ sizeof(struct linux_prom_translation
);
578 for (i
= 0; i
< n
; i
++) {
579 unsigned long vaddr
= prom_trans
[i
].virt
;
580 unsigned long size
= prom_trans
[i
].size
;
582 if (vaddr
< 0xf0000000UL
) {
583 unsigned long avoid_start
= (unsigned long) KERNBASE
;
584 unsigned long avoid_end
= avoid_start
+ (4 * 1024 * 1024);
587 avoid_end
+= (4 * 1024 * 1024);
588 if (vaddr
< avoid_start
) {
589 unsigned long top
= vaddr
+ size
;
591 if (top
> avoid_start
)
593 prom_unmap(top
- vaddr
, vaddr
);
595 if ((vaddr
+ size
) > avoid_end
) {
596 unsigned long bottom
= vaddr
;
598 if (bottom
< avoid_end
)
600 prom_unmap((vaddr
+ size
) - bottom
, bottom
);
605 prom_printf("done.\n");
607 register_prom_callbacks();
610 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
611 * upwards as reserved for use by the firmware (I wonder if this
612 * will be the same on Cheetah...). We use this virtual address
613 * range for the VPTE table mappings of the nucleus so we need
614 * to zap them when we enter the PROM. -DaveM
616 static void __flush_nucleus_vptes(void)
618 unsigned long prom_reserved_base
= 0xfffffffc00000000UL
;
621 /* Only DTLB must be checked for VPTE entries. */
622 if (tlb_type
== spitfire
) {
623 for (i
= 0; i
< 63; i
++) {
626 /* Spitfire Errata #32 workaround */
627 /* NOTE: Always runs on spitfire, so no cheetah+
628 * page size encodings.
630 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
634 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
636 tag
= spitfire_get_dtlb_tag(i
);
637 if (((tag
& ~(PAGE_MASK
)) == 0) &&
638 ((tag
& (PAGE_MASK
)) >= prom_reserved_base
)) {
639 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
642 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
643 spitfire_put_dtlb_data(i
, 0x0UL
);
646 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
647 for (i
= 0; i
< 512; i
++) {
648 unsigned long tag
= cheetah_get_dtlb_tag(i
, 2);
650 if ((tag
& ~PAGE_MASK
) == 0 &&
651 (tag
& PAGE_MASK
) >= prom_reserved_base
) {
652 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
655 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
656 cheetah_put_dtlb_data(i
, 0x0UL
, 2);
659 if (tlb_type
!= cheetah_plus
)
662 tag
= cheetah_get_dtlb_tag(i
, 3);
664 if ((tag
& ~PAGE_MASK
) == 0 &&
665 (tag
& PAGE_MASK
) >= prom_reserved_base
) {
666 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
669 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
670 cheetah_put_dtlb_data(i
, 0x0UL
, 3);
674 /* Implement me :-) */
679 static int prom_ditlb_set
;
680 struct prom_tlb_entry
{
682 unsigned long tlb_tag
;
683 unsigned long tlb_data
;
685 struct prom_tlb_entry prom_itlb
[16], prom_dtlb
[16];
687 void prom_world(int enter
)
689 unsigned long pstate
;
693 set_fs((mm_segment_t
) { get_thread_current_ds() });
698 /* Make sure the following runs atomically. */
699 __asm__
__volatile__("flushw\n\t"
700 "rdpr %%pstate, %0\n\t"
701 "wrpr %0, %1, %%pstate"
706 /* Kick out nucleus VPTEs. */
707 __flush_nucleus_vptes();
709 /* Install PROM world. */
710 for (i
= 0; i
< 16; i
++) {
711 if (prom_dtlb
[i
].tlb_ent
!= -1) {
712 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
714 : : "r" (prom_dtlb
[i
].tlb_tag
), "r" (TLB_TAG_ACCESS
),
716 if (tlb_type
== spitfire
)
717 spitfire_put_dtlb_data(prom_dtlb
[i
].tlb_ent
,
718 prom_dtlb
[i
].tlb_data
);
719 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
720 cheetah_put_ldtlb_data(prom_dtlb
[i
].tlb_ent
,
721 prom_dtlb
[i
].tlb_data
);
723 if (prom_itlb
[i
].tlb_ent
!= -1) {
724 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
726 : : "r" (prom_itlb
[i
].tlb_tag
),
727 "r" (TLB_TAG_ACCESS
),
729 if (tlb_type
== spitfire
)
730 spitfire_put_itlb_data(prom_itlb
[i
].tlb_ent
,
731 prom_itlb
[i
].tlb_data
);
732 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
733 cheetah_put_litlb_data(prom_itlb
[i
].tlb_ent
,
734 prom_itlb
[i
].tlb_data
);
738 for (i
= 0; i
< 16; i
++) {
739 if (prom_dtlb
[i
].tlb_ent
!= -1) {
740 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
742 : : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
743 if (tlb_type
== spitfire
)
744 spitfire_put_dtlb_data(prom_dtlb
[i
].tlb_ent
, 0x0UL
);
746 cheetah_put_ldtlb_data(prom_dtlb
[i
].tlb_ent
, 0x0UL
);
748 if (prom_itlb
[i
].tlb_ent
!= -1) {
749 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
751 : : "r" (TLB_TAG_ACCESS
),
753 if (tlb_type
== spitfire
)
754 spitfire_put_itlb_data(prom_itlb
[i
].tlb_ent
, 0x0UL
);
756 cheetah_put_litlb_data(prom_itlb
[i
].tlb_ent
, 0x0UL
);
760 __asm__
__volatile__("wrpr %0, 0, %%pstate"
764 void inherit_locked_prom_mappings(int save_p
)
770 /* Fucking losing PROM has more mappings in the TLB, but
771 * it (conveniently) fails to mention any of these in the
772 * translations property. The only ones that matter are
773 * the locked PROM tlb entries, so we impose the following
774 * irrecovable rule on the PROM, it is allowed 8 locked
775 * entries in the ITLB and 8 in the DTLB.
777 * Supposedly the upper 16GB of the address space is
778 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
779 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
780 * used between the client program and the firmware on sun5
781 * systems to coordinate mmu mappings is also COMPLETELY
782 * UNDOCUMENTED!!!!!! Thanks S(t)un!
785 for (i
= 0; i
< 16; i
++) {
786 prom_itlb
[i
].tlb_ent
= -1;
787 prom_dtlb
[i
].tlb_ent
= -1;
790 if (tlb_type
== spitfire
) {
791 int high
= SPITFIRE_HIGHEST_LOCKED_TLBENT
- bigkernel
;
792 for (i
= 0; i
< high
; i
++) {
795 /* Spitfire Errata #32 workaround */
796 /* NOTE: Always runs on spitfire, so no cheetah+
797 * page size encodings.
799 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
803 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
805 data
= spitfire_get_dtlb_data(i
);
806 if ((data
& (_PAGE_L
|_PAGE_VALID
)) == (_PAGE_L
|_PAGE_VALID
)) {
809 /* Spitfire Errata #32 workaround */
810 /* NOTE: Always runs on spitfire, so no
811 * cheetah+ page size encodings.
813 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
817 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
819 tag
= spitfire_get_dtlb_tag(i
);
821 prom_dtlb
[dtlb_seen
].tlb_ent
= i
;
822 prom_dtlb
[dtlb_seen
].tlb_tag
= tag
;
823 prom_dtlb
[dtlb_seen
].tlb_data
= data
;
825 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
827 : : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
828 spitfire_put_dtlb_data(i
, 0x0UL
);
836 for (i
= 0; i
< high
; i
++) {
839 /* Spitfire Errata #32 workaround */
840 /* NOTE: Always runs on spitfire, so no
841 * cheetah+ page size encodings.
843 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
847 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
849 data
= spitfire_get_itlb_data(i
);
850 if ((data
& (_PAGE_L
|_PAGE_VALID
)) == (_PAGE_L
|_PAGE_VALID
)) {
853 /* Spitfire Errata #32 workaround */
854 /* NOTE: Always runs on spitfire, so no
855 * cheetah+ page size encodings.
857 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
861 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
863 tag
= spitfire_get_itlb_tag(i
);
865 prom_itlb
[itlb_seen
].tlb_ent
= i
;
866 prom_itlb
[itlb_seen
].tlb_tag
= tag
;
867 prom_itlb
[itlb_seen
].tlb_data
= data
;
869 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
871 : : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
872 spitfire_put_itlb_data(i
, 0x0UL
);
879 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
880 int high
= CHEETAH_HIGHEST_LOCKED_TLBENT
- bigkernel
;
882 for (i
= 0; i
< high
; i
++) {
885 data
= cheetah_get_ldtlb_data(i
);
886 if ((data
& (_PAGE_L
|_PAGE_VALID
)) == (_PAGE_L
|_PAGE_VALID
)) {
889 tag
= cheetah_get_ldtlb_tag(i
);
891 prom_dtlb
[dtlb_seen
].tlb_ent
= i
;
892 prom_dtlb
[dtlb_seen
].tlb_tag
= tag
;
893 prom_dtlb
[dtlb_seen
].tlb_data
= data
;
895 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
897 : : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
898 cheetah_put_ldtlb_data(i
, 0x0UL
);
906 for (i
= 0; i
< high
; i
++) {
909 data
= cheetah_get_litlb_data(i
);
910 if ((data
& (_PAGE_L
|_PAGE_VALID
)) == (_PAGE_L
|_PAGE_VALID
)) {
913 tag
= cheetah_get_litlb_tag(i
);
915 prom_itlb
[itlb_seen
].tlb_ent
= i
;
916 prom_itlb
[itlb_seen
].tlb_tag
= tag
;
917 prom_itlb
[itlb_seen
].tlb_data
= data
;
919 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
921 : : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
922 cheetah_put_litlb_data(i
, 0x0UL
);
930 /* Implement me :-) */
937 /* Give PROM back his world, done during reboots... */
938 void prom_reload_locked(void)
942 for (i
= 0; i
< 16; i
++) {
943 if (prom_dtlb
[i
].tlb_ent
!= -1) {
944 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
946 : : "r" (prom_dtlb
[i
].tlb_tag
), "r" (TLB_TAG_ACCESS
),
948 if (tlb_type
== spitfire
)
949 spitfire_put_dtlb_data(prom_dtlb
[i
].tlb_ent
,
950 prom_dtlb
[i
].tlb_data
);
951 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
952 cheetah_put_ldtlb_data(prom_dtlb
[i
].tlb_ent
,
953 prom_dtlb
[i
].tlb_data
);
956 if (prom_itlb
[i
].tlb_ent
!= -1) {
957 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
959 : : "r" (prom_itlb
[i
].tlb_tag
),
960 "r" (TLB_TAG_ACCESS
),
962 if (tlb_type
== spitfire
)
963 spitfire_put_itlb_data(prom_itlb
[i
].tlb_ent
,
964 prom_itlb
[i
].tlb_data
);
966 cheetah_put_litlb_data(prom_itlb
[i
].tlb_ent
,
967 prom_itlb
[i
].tlb_data
);
972 #ifdef DCACHE_ALIASING_POSSIBLE
973 void __flush_dcache_range(unsigned long start
, unsigned long end
)
977 if (tlb_type
== spitfire
) {
980 for (va
= start
; va
< end
; va
+= 32) {
981 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
988 for (va
= start
; va
< end
; va
+= 32)
989 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
993 "i" (ASI_DCACHE_INVALIDATE
));
996 #endif /* DCACHE_ALIASING_POSSIBLE */
998 /* If not locked, zap it. */
999 void __flush_tlb_all(void)
1001 unsigned long pstate
;
1004 __asm__
__volatile__("flushw\n\t"
1005 "rdpr %%pstate, %0\n\t"
1006 "wrpr %0, %1, %%pstate"
1009 if (tlb_type
== spitfire
) {
1010 for (i
= 0; i
< 64; i
++) {
1011 /* Spitfire Errata #32 workaround */
1012 /* NOTE: Always runs on spitfire, so no
1013 * cheetah+ page size encodings.
1015 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1019 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1021 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L
)) {
1022 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1025 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
1026 spitfire_put_dtlb_data(i
, 0x0UL
);
1029 /* Spitfire Errata #32 workaround */
1030 /* NOTE: Always runs on spitfire, so no
1031 * cheetah+ page size encodings.
1033 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1037 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1039 if (!(spitfire_get_itlb_data(i
) & _PAGE_L
)) {
1040 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1043 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
1044 spitfire_put_itlb_data(i
, 0x0UL
);
1047 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1048 cheetah_flush_dtlb_all();
1049 cheetah_flush_itlb_all();
1051 __asm__
__volatile__("wrpr %0, 0, %%pstate"
1055 /* Caller does TLB context flushing on local CPU if necessary.
1056 * The caller also ensures that CTX_VALID(mm->context) is false.
1058 * We must be careful about boundary cases so that we never
1059 * let the user have CTX 0 (nucleus) or we ever use a CTX
1060 * version of zero (and thus NO_CONTEXT would not be caught
1061 * by version mis-match tests in mmu_context.h).
1063 void get_new_mmu_context(struct mm_struct
*mm
)
1065 unsigned long ctx
, new_ctx
;
1066 unsigned long orig_pgsz_bits
;
1069 spin_lock(&ctx_alloc_lock
);
1070 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
1071 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
1072 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
1073 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
1074 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
1075 if (new_ctx
>= ctx
) {
1077 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
1080 new_ctx
= CTX_FIRST_VERSION
;
1082 /* Don't call memset, for 16 entries that's just
1085 mmu_context_bmap
[0] = 3;
1086 mmu_context_bmap
[1] = 0;
1087 mmu_context_bmap
[2] = 0;
1088 mmu_context_bmap
[3] = 0;
1089 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
1090 mmu_context_bmap
[i
+ 0] = 0;
1091 mmu_context_bmap
[i
+ 1] = 0;
1092 mmu_context_bmap
[i
+ 2] = 0;
1093 mmu_context_bmap
[i
+ 3] = 0;
1098 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
1099 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
1101 tlb_context_cache
= new_ctx
;
1102 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
1103 spin_unlock(&ctx_alloc_lock
);
1107 struct pgtable_cache_struct pgt_quicklists
;
1110 /* OK, we have to color these pages. The page tables are accessed
1111 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1112 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1113 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1114 * fast handlers do not get data from old/garbage dcache lines that
1115 * correspond to an old/stale virtual address (user/kernel) that
1116 * previously mapped the pagetable page while accessing vpte range
1117 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1118 * color is the same, then when the kernel initializes the pagetable
1119 * using the later address range, accesses with the first address
1120 * range will see the newly initialized data rather than the garbage.
1122 #ifdef DCACHE_ALIASING_POSSIBLE
1123 #define DC_ALIAS_SHIFT 1
1125 #define DC_ALIAS_SHIFT 0
1127 pte_t
*pte_alloc_one_kernel(struct mm_struct
*mm
, unsigned long address
)
1130 unsigned long color
;
1133 pte_t
*ptep
= pte_alloc_one_fast(mm
, address
);
1139 color
= VPTE_COLOR(address
);
1140 page
= alloc_pages(GFP_KERNEL
|__GFP_REPEAT
, DC_ALIAS_SHIFT
);
1142 unsigned long *to_free
;
1143 unsigned long paddr
;
1146 #ifdef DCACHE_ALIASING_POSSIBLE
1147 set_page_count(page
, 1);
1148 ClearPageCompound(page
);
1150 set_page_count((page
+ 1), 1);
1151 ClearPageCompound(page
+ 1);
1153 paddr
= (unsigned long) page_address(page
);
1154 memset((char *)paddr
, 0, (PAGE_SIZE
<< DC_ALIAS_SHIFT
));
1157 pte
= (pte_t
*) paddr
;
1158 to_free
= (unsigned long *) (paddr
+ PAGE_SIZE
);
1160 pte
= (pte_t
*) (paddr
+ PAGE_SIZE
);
1161 to_free
= (unsigned long *) paddr
;
1164 #ifdef DCACHE_ALIASING_POSSIBLE
1165 /* Now free the other one up, adjust cache size. */
1167 *to_free
= (unsigned long) pte_quicklist
[color
^ 0x1];
1168 pte_quicklist
[color
^ 0x1] = to_free
;
1169 pgtable_cache_size
++;
1178 void sparc_ultra_dump_itlb(void)
1182 if (tlb_type
== spitfire
) {
1183 printk ("Contents of itlb: ");
1184 for (slot
= 0; slot
< 14; slot
++) printk (" ");
1185 printk ("%2x:%016lx,%016lx\n",
1187 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1188 for (slot
= 1; slot
< 64; slot
+=3) {
1189 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1191 spitfire_get_itlb_tag(slot
), spitfire_get_itlb_data(slot
),
1193 spitfire_get_itlb_tag(slot
+1), spitfire_get_itlb_data(slot
+1),
1195 spitfire_get_itlb_tag(slot
+2), spitfire_get_itlb_data(slot
+2));
1197 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1198 printk ("Contents of itlb0:\n");
1199 for (slot
= 0; slot
< 16; slot
+=2) {
1200 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1202 cheetah_get_litlb_tag(slot
), cheetah_get_litlb_data(slot
),
1204 cheetah_get_litlb_tag(slot
+1), cheetah_get_litlb_data(slot
+1));
1206 printk ("Contents of itlb2:\n");
1207 for (slot
= 0; slot
< 128; slot
+=2) {
1208 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1210 cheetah_get_itlb_tag(slot
), cheetah_get_itlb_data(slot
),
1212 cheetah_get_itlb_tag(slot
+1), cheetah_get_itlb_data(slot
+1));
1217 void sparc_ultra_dump_dtlb(void)
1221 if (tlb_type
== spitfire
) {
1222 printk ("Contents of dtlb: ");
1223 for (slot
= 0; slot
< 14; slot
++) printk (" ");
1224 printk ("%2x:%016lx,%016lx\n", 0,
1225 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1226 for (slot
= 1; slot
< 64; slot
+=3) {
1227 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1229 spitfire_get_dtlb_tag(slot
), spitfire_get_dtlb_data(slot
),
1231 spitfire_get_dtlb_tag(slot
+1), spitfire_get_dtlb_data(slot
+1),
1233 spitfire_get_dtlb_tag(slot
+2), spitfire_get_dtlb_data(slot
+2));
1235 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1236 printk ("Contents of dtlb0:\n");
1237 for (slot
= 0; slot
< 16; slot
+=2) {
1238 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1240 cheetah_get_ldtlb_tag(slot
), cheetah_get_ldtlb_data(slot
),
1242 cheetah_get_ldtlb_tag(slot
+1), cheetah_get_ldtlb_data(slot
+1));
1244 printk ("Contents of dtlb2:\n");
1245 for (slot
= 0; slot
< 512; slot
+=2) {
1246 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1248 cheetah_get_dtlb_tag(slot
, 2), cheetah_get_dtlb_data(slot
, 2),
1250 cheetah_get_dtlb_tag(slot
+1, 2), cheetah_get_dtlb_data(slot
+1, 2));
1252 if (tlb_type
== cheetah_plus
) {
1253 printk ("Contents of dtlb3:\n");
1254 for (slot
= 0; slot
< 512; slot
+=2) {
1255 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1257 cheetah_get_dtlb_tag(slot
, 3), cheetah_get_dtlb_data(slot
, 3),
1259 cheetah_get_dtlb_tag(slot
+1, 3), cheetah_get_dtlb_data(slot
+1, 3));
1265 extern unsigned long cmdline_memory_size
;
1267 unsigned long __init
bootmem_init(unsigned long *pages_avail
)
1269 unsigned long bootmap_size
, start_pfn
, end_pfn
;
1270 unsigned long end_of_phys_memory
= 0UL;
1271 unsigned long bootmap_pfn
, bytes_avail
, size
;
1274 #ifdef CONFIG_DEBUG_BOOTMEM
1275 prom_printf("bootmem_init: Scan sp_banks, ");
1279 for (i
= 0; sp_banks
[i
].num_bytes
!= 0; i
++) {
1280 end_of_phys_memory
= sp_banks
[i
].base_addr
+
1281 sp_banks
[i
].num_bytes
;
1282 bytes_avail
+= sp_banks
[i
].num_bytes
;
1283 if (cmdline_memory_size
) {
1284 if (bytes_avail
> cmdline_memory_size
) {
1285 unsigned long slack
= bytes_avail
- cmdline_memory_size
;
1287 bytes_avail
-= slack
;
1288 end_of_phys_memory
-= slack
;
1290 sp_banks
[i
].num_bytes
-= slack
;
1291 if (sp_banks
[i
].num_bytes
== 0) {
1292 sp_banks
[i
].base_addr
= 0xdeadbeef;
1294 sp_banks
[i
+1].num_bytes
= 0;
1295 sp_banks
[i
+1].base_addr
= 0xdeadbeef;
1302 *pages_avail
= bytes_avail
>> PAGE_SHIFT
;
1304 /* Start with page aligned address of last symbol in kernel
1305 * image. The kernel is hard mapped below PAGE_OFFSET in a
1306 * 4MB locked TLB translation.
1308 start_pfn
= PAGE_ALIGN(kern_base
+ kern_size
) >> PAGE_SHIFT
;
1310 bootmap_pfn
= start_pfn
;
1312 end_pfn
= end_of_phys_memory
>> PAGE_SHIFT
;
1314 #ifdef CONFIG_BLK_DEV_INITRD
1315 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1316 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
1317 unsigned long ramdisk_image
= sparc_ramdisk_image
?
1318 sparc_ramdisk_image
: sparc_ramdisk_image64
;
1319 if (ramdisk_image
>= (unsigned long)_end
- 2 * PAGE_SIZE
)
1320 ramdisk_image
-= KERNBASE
;
1321 initrd_start
= ramdisk_image
+ phys_base
;
1322 initrd_end
= initrd_start
+ sparc_ramdisk_size
;
1323 if (initrd_end
> end_of_phys_memory
) {
1324 printk(KERN_CRIT
"initrd extends beyond end of memory "
1325 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1326 initrd_end
, end_of_phys_memory
);
1330 if (initrd_start
>= (start_pfn
<< PAGE_SHIFT
) &&
1331 initrd_start
< (start_pfn
<< PAGE_SHIFT
) + 2 * PAGE_SIZE
)
1332 bootmap_pfn
= PAGE_ALIGN (initrd_end
) >> PAGE_SHIFT
;
1336 /* Initialize the boot-time allocator. */
1337 max_pfn
= max_low_pfn
= end_pfn
;
1338 min_low_pfn
= pfn_base
;
1340 #ifdef CONFIG_DEBUG_BOOTMEM
1341 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1342 min_low_pfn
, bootmap_pfn
, max_low_pfn
);
1344 bootmap_size
= init_bootmem_node(NODE_DATA(0), bootmap_pfn
, pfn_base
, end_pfn
);
1346 bootmap_base
= bootmap_pfn
<< PAGE_SHIFT
;
1348 /* Now register the available physical memory with the
1351 for (i
= 0; sp_banks
[i
].num_bytes
!= 0; i
++) {
1352 #ifdef CONFIG_DEBUG_BOOTMEM
1353 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1354 i
, sp_banks
[i
].base_addr
, sp_banks
[i
].num_bytes
);
1356 free_bootmem(sp_banks
[i
].base_addr
, sp_banks
[i
].num_bytes
);
1359 #ifdef CONFIG_BLK_DEV_INITRD
1361 size
= initrd_end
- initrd_start
;
1363 /* Resert the initrd image area. */
1364 #ifdef CONFIG_DEBUG_BOOTMEM
1365 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1366 initrd_start
, initrd_end
);
1368 reserve_bootmem(initrd_start
, size
);
1369 *pages_avail
-= PAGE_ALIGN(size
) >> PAGE_SHIFT
;
1371 initrd_start
+= PAGE_OFFSET
;
1372 initrd_end
+= PAGE_OFFSET
;
1375 /* Reserve the kernel text/data/bss. */
1376 #ifdef CONFIG_DEBUG_BOOTMEM
1377 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base
, kern_size
);
1379 reserve_bootmem(kern_base
, kern_size
);
1380 *pages_avail
-= PAGE_ALIGN(kern_size
) >> PAGE_SHIFT
;
1382 /* Reserve the bootmem map. We do not account for it
1383 * in pages_avail because we will release that memory
1384 * in free_all_bootmem.
1386 size
= bootmap_size
;
1387 #ifdef CONFIG_DEBUG_BOOTMEM
1388 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1389 (bootmap_pfn
<< PAGE_SHIFT
), size
);
1391 reserve_bootmem((bootmap_pfn
<< PAGE_SHIFT
), size
);
1392 *pages_avail
-= PAGE_ALIGN(size
) >> PAGE_SHIFT
;
1397 /* paging_init() sets up the page tables */
1399 extern void cheetah_ecache_flush_init(void);
1401 static unsigned long last_valid_pfn
;
1403 void __init
paging_init(void)
1405 extern pmd_t swapper_pmd_dir
[1024];
1406 unsigned long alias_base
= kern_base
+ PAGE_OFFSET
;
1407 unsigned long second_alias_page
= 0;
1408 unsigned long pt
, flags
, end_pfn
, pages_avail
;
1409 unsigned long shift
= alias_base
- ((unsigned long)KERNBASE
);
1410 unsigned long real_end
;
1412 set_bit(0, mmu_context_bmap
);
1414 real_end
= (unsigned long)_end
;
1415 if ((real_end
> ((unsigned long)KERNBASE
+ 0x400000)))
1417 #ifdef CONFIG_BLK_DEV_INITRD
1418 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
)
1419 real_end
= (PAGE_ALIGN(real_end
) + PAGE_ALIGN(sparc_ramdisk_size
));
1422 /* We assume physical memory starts at some 4mb multiple,
1423 * if this were not true we wouldn't boot up to this point
1426 pt
= kern_base
| _PAGE_VALID
| _PAGE_SZ4MB
;
1427 pt
|= _PAGE_CP
| _PAGE_CV
| _PAGE_P
| _PAGE_L
| _PAGE_W
;
1428 local_irq_save(flags
);
1429 if (tlb_type
== spitfire
) {
1430 __asm__
__volatile__(
1431 " stxa %1, [%0] %3\n"
1432 " stxa %2, [%5] %4\n"
1439 : "r" (TLB_TAG_ACCESS
), "r" (alias_base
), "r" (pt
),
1440 "i" (ASI_DMMU
), "i" (ASI_DTLB_DATA_ACCESS
), "r" (61 << 3)
1442 if (real_end
>= KERNBASE
+ 0x340000) {
1443 second_alias_page
= alias_base
+ 0x400000;
1444 __asm__
__volatile__(
1445 " stxa %1, [%0] %3\n"
1446 " stxa %2, [%5] %4\n"
1453 : "r" (TLB_TAG_ACCESS
), "r" (second_alias_page
), "r" (pt
+ 0x400000),
1454 "i" (ASI_DMMU
), "i" (ASI_DTLB_DATA_ACCESS
), "r" (60 << 3)
1457 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1458 __asm__
__volatile__(
1459 " stxa %1, [%0] %3\n"
1460 " stxa %2, [%5] %4\n"
1467 : "r" (TLB_TAG_ACCESS
), "r" (alias_base
), "r" (pt
),
1468 "i" (ASI_DMMU
), "i" (ASI_DTLB_DATA_ACCESS
), "r" ((0<<16) | (13<<3))
1470 if (real_end
>= KERNBASE
+ 0x340000) {
1471 second_alias_page
= alias_base
+ 0x400000;
1472 __asm__
__volatile__(
1473 " stxa %1, [%0] %3\n"
1474 " stxa %2, [%5] %4\n"
1481 : "r" (TLB_TAG_ACCESS
), "r" (second_alias_page
), "r" (pt
+ 0x400000),
1482 "i" (ASI_DMMU
), "i" (ASI_DTLB_DATA_ACCESS
), "r" ((0<<16) | (12<<3))
1486 local_irq_restore(flags
);
1488 /* Now set kernel pgd to upper alias so physical page computations
1491 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
1493 memset(swapper_pmd_dir
, 0, sizeof(swapper_pmd_dir
));
1495 /* Now can init the kernel/bad page tables. */
1496 pud_set(pud_offset(&swapper_pg_dir
[0], 0),
1497 swapper_pmd_dir
+ (shift
/ sizeof(pgd_t
)));
1499 swapper_pgd_zero
= pgd_val(init_mm
.pgd
[0]);
1501 /* Setup bootmem... */
1503 last_valid_pfn
= end_pfn
= bootmem_init(&pages_avail
);
1505 /* Inherit non-locked OBP mappings. */
1506 inherit_prom_mappings();
1508 /* Ok, we can use our TLB miss and window trap handlers safely.
1509 * We need to do a quick peek here to see if we are on StarFire
1510 * or not, so setup_tba can setup the IRQ globals correctly (it
1511 * needs to get the hard smp processor id correctly).
1514 extern void setup_tba(int);
1515 setup_tba(this_is_starfire
);
1518 inherit_locked_prom_mappings(1);
1520 /* We only created DTLB mapping of this stuff. */
1521 spitfire_flush_dtlb_nucleus_page(alias_base
);
1522 if (second_alias_page
)
1523 spitfire_flush_dtlb_nucleus_page(second_alias_page
);
1528 unsigned long zones_size
[MAX_NR_ZONES
];
1529 unsigned long zholes_size
[MAX_NR_ZONES
];
1530 unsigned long npages
;
1533 for (znum
= 0; znum
< MAX_NR_ZONES
; znum
++)
1534 zones_size
[znum
] = zholes_size
[znum
] = 0;
1536 npages
= end_pfn
- pfn_base
;
1537 zones_size
[ZONE_DMA
] = npages
;
1538 zholes_size
[ZONE_DMA
] = npages
- pages_avail
;
1540 free_area_init_node(0, &contig_page_data
, zones_size
,
1541 phys_base
>> PAGE_SHIFT
, zholes_size
);
1547 /* Ok, it seems that the prom can allocate some more memory chunks
1548 * as a side effect of some prom calls we perform during the
1549 * boot sequence. My most likely theory is that it is from the
1550 * prom_set_traptable() call, and OBP is allocating a scratchpad
1551 * for saving client program register state etc.
1553 static void __init
sort_memlist(struct linux_mlist_p1275
*thislist
)
1557 unsigned long tmpaddr
, tmpsize
;
1558 unsigned long lowest
;
1560 for (i
= 0; thislist
[i
].theres_more
!= 0; i
++) {
1561 lowest
= thislist
[i
].start_adr
;
1562 for (mitr
= i
+1; thislist
[mitr
-1].theres_more
!= 0; mitr
++)
1563 if (thislist
[mitr
].start_adr
< lowest
) {
1564 lowest
= thislist
[mitr
].start_adr
;
1567 if (lowest
== thislist
[i
].start_adr
)
1569 tmpaddr
= thislist
[swapi
].start_adr
;
1570 tmpsize
= thislist
[swapi
].num_bytes
;
1571 for (mitr
= swapi
; mitr
> i
; mitr
--) {
1572 thislist
[mitr
].start_adr
= thislist
[mitr
-1].start_adr
;
1573 thislist
[mitr
].num_bytes
= thislist
[mitr
-1].num_bytes
;
1575 thislist
[i
].start_adr
= tmpaddr
;
1576 thislist
[i
].num_bytes
= tmpsize
;
1580 void __init
rescan_sp_banks(void)
1582 struct linux_prom64_registers memlist
[64];
1583 struct linux_mlist_p1275 avail
[64], *mlist
;
1584 unsigned long bytes
, base_paddr
;
1585 int num_regs
, node
= prom_finddevice("/memory");
1588 num_regs
= prom_getproperty(node
, "available",
1589 (char *) memlist
, sizeof(memlist
));
1590 num_regs
= (num_regs
/ sizeof(struct linux_prom64_registers
));
1591 for (i
= 0; i
< num_regs
; i
++) {
1592 avail
[i
].start_adr
= memlist
[i
].phys_addr
;
1593 avail
[i
].num_bytes
= memlist
[i
].reg_size
;
1594 avail
[i
].theres_more
= &avail
[i
+ 1];
1596 avail
[i
- 1].theres_more
= NULL
;
1597 sort_memlist(avail
);
1601 bytes
= mlist
->num_bytes
;
1602 base_paddr
= mlist
->start_adr
;
1604 sp_banks
[0].base_addr
= base_paddr
;
1605 sp_banks
[0].num_bytes
= bytes
;
1607 while (mlist
->theres_more
!= NULL
){
1609 mlist
= mlist
->theres_more
;
1610 bytes
= mlist
->num_bytes
;
1611 if (i
>= SPARC_PHYS_BANKS
-1) {
1612 printk ("The machine has more banks than "
1613 "this kernel can support\n"
1614 "Increase the SPARC_PHYS_BANKS "
1615 "setting (currently %d)\n",
1617 i
= SPARC_PHYS_BANKS
-1;
1621 sp_banks
[i
].base_addr
= mlist
->start_adr
;
1622 sp_banks
[i
].num_bytes
= mlist
->num_bytes
;
1626 sp_banks
[i
].base_addr
= 0xdeadbeefbeefdeadUL
;
1627 sp_banks
[i
].num_bytes
= 0;
1629 for (i
= 0; sp_banks
[i
].num_bytes
!= 0; i
++)
1630 sp_banks
[i
].num_bytes
&= PAGE_MASK
;
1633 static void __init
taint_real_pages(void)
1635 struct sparc_phys_banks saved_sp_banks
[SPARC_PHYS_BANKS
];
1638 for (i
= 0; i
< SPARC_PHYS_BANKS
; i
++) {
1639 saved_sp_banks
[i
].base_addr
=
1640 sp_banks
[i
].base_addr
;
1641 saved_sp_banks
[i
].num_bytes
=
1642 sp_banks
[i
].num_bytes
;
1647 /* Find changes discovered in the sp_bank rescan and
1648 * reserve the lost portions in the bootmem maps.
1650 for (i
= 0; saved_sp_banks
[i
].num_bytes
; i
++) {
1651 unsigned long old_start
, old_end
;
1653 old_start
= saved_sp_banks
[i
].base_addr
;
1654 old_end
= old_start
+
1655 saved_sp_banks
[i
].num_bytes
;
1656 while (old_start
< old_end
) {
1659 for (n
= 0; sp_banks
[n
].num_bytes
; n
++) {
1660 unsigned long new_start
, new_end
;
1662 new_start
= sp_banks
[n
].base_addr
;
1663 new_end
= new_start
+ sp_banks
[n
].num_bytes
;
1665 if (new_start
<= old_start
&&
1666 new_end
>= (old_start
+ PAGE_SIZE
)) {
1667 set_bit (old_start
>> 22,
1668 sparc64_valid_addr_bitmap
);
1672 reserve_bootmem(old_start
, PAGE_SIZE
);
1675 old_start
+= PAGE_SIZE
;
1680 void __init
mem_init(void)
1682 unsigned long codepages
, datapages
, initpages
;
1683 unsigned long addr
, last
;
1686 i
= last_valid_pfn
>> ((22 - PAGE_SHIFT
) + 6);
1688 sparc64_valid_addr_bitmap
= (unsigned long *)
1689 __alloc_bootmem(i
<< 3, SMP_CACHE_BYTES
, bootmap_base
);
1690 if (sparc64_valid_addr_bitmap
== NULL
) {
1691 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1694 memset(sparc64_valid_addr_bitmap
, 0, i
<< 3);
1696 addr
= PAGE_OFFSET
+ kern_base
;
1697 last
= PAGE_ALIGN(kern_size
) + addr
;
1698 while (addr
< last
) {
1699 set_bit(__pa(addr
) >> 22, sparc64_valid_addr_bitmap
);
1705 max_mapnr
= last_valid_pfn
- pfn_base
;
1706 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
1708 #ifdef CONFIG_DEBUG_BOOTMEM
1709 prom_printf("mem_init: Calling free_all_bootmem().\n");
1711 totalram_pages
= num_physpages
= free_all_bootmem() - 1;
1714 * Set up the zero page, mark it reserved, so that page count
1715 * is not manipulated when freeing the page from user ptes.
1717 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
1718 if (mem_map_zero
== NULL
) {
1719 prom_printf("paging_init: Cannot alloc zero page.\n");
1722 SetPageReserved(mem_map_zero
);
1724 codepages
= (((unsigned long) _etext
) - ((unsigned long) _start
));
1725 codepages
= PAGE_ALIGN(codepages
) >> PAGE_SHIFT
;
1726 datapages
= (((unsigned long) _edata
) - ((unsigned long) _etext
));
1727 datapages
= PAGE_ALIGN(datapages
) >> PAGE_SHIFT
;
1728 initpages
= (((unsigned long) __init_end
) - ((unsigned long) __init_begin
));
1729 initpages
= PAGE_ALIGN(initpages
) >> PAGE_SHIFT
;
1731 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1732 nr_free_pages() << (PAGE_SHIFT
-10),
1733 codepages
<< (PAGE_SHIFT
-10),
1734 datapages
<< (PAGE_SHIFT
-10),
1735 initpages
<< (PAGE_SHIFT
-10),
1736 PAGE_OFFSET
, (last_valid_pfn
<< PAGE_SHIFT
));
1738 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1739 cheetah_ecache_flush_init();
1742 void free_initmem (void)
1744 unsigned long addr
, initend
;
1747 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1749 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
1750 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
1751 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
1756 ((unsigned long) __va(kern_base
)) -
1757 ((unsigned long) KERNBASE
));
1758 memset((void *)addr
, 0xcc, PAGE_SIZE
);
1759 p
= virt_to_page(page
);
1761 ClearPageReserved(p
);
1762 set_page_count(p
, 1);
1769 #ifdef CONFIG_BLK_DEV_INITRD
1770 void free_initrd_mem(unsigned long start
, unsigned long end
)
1773 printk ("Freeing initrd memory: %ldk freed\n", (end
- start
) >> 10);
1774 for (; start
< end
; start
+= PAGE_SIZE
) {
1775 struct page
*p
= virt_to_page(start
);
1777 ClearPageReserved(p
);
1778 set_page_count(p
, 1);