1 /******************************************************************************
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #ifndef __iwl_trans_int_pcie_h__
30 #define __iwl_trans_int_pcie_h__
32 #include <linux/spinlock.h>
33 #include <linux/interrupt.h>
34 #include <linux/skbuff.h>
35 #include <linux/wait.h>
36 #include <linux/pci.h>
37 #include <linux/timer.h>
41 #include "iwl-trans.h"
42 #include "iwl-debug.h"
44 #include "iwl-op-mode.h"
48 /*This file includes the declaration that are internal to the
51 struct iwl_rx_mem_buffer
{
54 struct list_head list
;
58 * struct isr_statistics - interrupt statistics
61 struct isr_statistics
{
76 * struct iwl_rx_queue - Rx queue
77 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
78 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
81 * @read: Shared index to newest available Rx buffer
82 * @write: Shared index to oldest written Rx packet
83 * @free_count: Number of pre-allocated buffers in rx_free
85 * @rx_free: list of free SKBs for use
86 * @rx_used: List of Rx buffers with no SKB
87 * @need_update: flag to indicate we need to update read/write index
88 * @rb_stts: driver's pointer to receive buffer status
89 * @rb_stts_dma: bus address of receive buffer status
92 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
97 struct iwl_rx_mem_buffer pool
[RX_QUEUE_SIZE
+ RX_FREE_BUFFERS
];
98 struct iwl_rx_mem_buffer
*queue
[RX_QUEUE_SIZE
];
103 struct list_head rx_free
;
104 struct list_head rx_used
;
106 struct iwl_rb_status
*rb_stts
;
107 dma_addr_t rb_stts_dma
;
118 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
119 * @index -- current index
120 * @n_bd -- total number of entries in queue (must be power of 2)
122 static inline int iwl_queue_inc_wrap(int index
, int n_bd
)
124 return ++index
& (n_bd
- 1);
128 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
129 * @index -- current index
130 * @n_bd -- total number of entries in queue (must be power of 2)
132 static inline int iwl_queue_dec_wrap(int index
, int n_bd
)
134 return --index
& (n_bd
- 1);
137 struct iwl_cmd_meta
{
138 /* only for SYNC commands, iff the reply skb is wanted */
139 struct iwl_host_cmd
*source
;
141 DEFINE_DMA_UNMAP_ADDR(mapping
);
142 DEFINE_DMA_UNMAP_LEN(len
);
148 * Generic queue structure
150 * Contains common data for Rx and Tx queues.
152 * Note the difference between n_bd and n_window: the hardware
153 * always assumes 256 descriptors, so n_bd is always 256 (unless
154 * there might be HW changes in the future). For the normal TX
155 * queues, n_window, which is the size of the software queue data
156 * is also 256; however, for the command queue, n_window is only
157 * 32 since we don't need so many commands pending. Since the HW
158 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
159 * the software buffers (in the variables @meta, @txb in struct
160 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
161 * in the same struct) have 256.
162 * This means that we end up with the following:
163 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
164 * SW entries: | 0 | ... | 31 |
165 * where N is a number between 0 and 7. This means that the SW
166 * data is a window overlayed over the HW queue.
169 int n_bd
; /* number of BDs in this queue */
170 int write_ptr
; /* 1-st empty entry (index) host_w*/
171 int read_ptr
; /* last used entry (index) host_r*/
172 /* use for monitoring and recovering the stuck queue */
173 dma_addr_t dma_addr
; /* physical addr for BD's */
174 int n_window
; /* safe queue window */
176 int low_mark
; /* low watermark, resume queue if free
177 * space more than this */
178 int high_mark
; /* high watermark, stop queue if free
179 * space less than this */
182 #define TFD_TX_CMD_SLOTS 256
183 #define TFD_CMD_SLOTS 32
185 struct iwl_pcie_tx_queue_entry
{
186 struct iwl_device_cmd
*cmd
;
188 struct iwl_cmd_meta meta
;
192 * struct iwl_tx_queue - Tx Queue for DMA
193 * @q: generic Rx/Tx queue descriptor
194 * @tfds: transmit frame descriptors (DMA memory)
195 * @entries: transmit entries (driver state)
197 * @stuck_timer: timer that fires if queue gets stuck
198 * @trans_pcie: pointer back to transport (for timer)
199 * @need_update: indicates need to update read/write index
200 * @active: stores if queue is active
202 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
203 * descriptors) and required locking structures.
205 struct iwl_tx_queue
{
207 struct iwl_tfd
*tfds
;
208 struct iwl_pcie_tx_queue_entry
*entries
;
210 struct timer_list stuck_timer
;
211 struct iwl_trans_pcie
*trans_pcie
;
217 * struct iwl_trans_pcie - PCIe transport specific data
218 * @rxq: all the RX queue data
219 * @rx_replenish: work that will be called when buffers need to be allocated
220 * @drv - pointer to iwl_drv
221 * @trans: pointer to the generic transport area
222 * @irq - the irq number for the device
223 * @irq_requested: true when the irq has been requested
224 * @scd_base_addr: scheduler sram base address in SRAM
225 * @scd_bc_tbls: pointer to the byte count table of the scheduler
226 * @kw: keep warm address
227 * @pci_dev: basic pci-network driver stuff
228 * @hw_base: pci hardware address support
229 * @ucode_write_complete: indicates that the ucode has been copied.
230 * @ucode_write_waitq: wait queue for uCode load
231 * @status - transport specific status flags
232 * @cmd_queue - command queue number
233 * @rx_buf_size_8k: 8 kB RX buffer size
234 * @rx_page_order: page order for receive buffer size
235 * @wd_timeout: queue watchdog timeout (jiffies)
237 struct iwl_trans_pcie
{
238 struct iwl_rx_queue rxq
;
239 struct work_struct rx_replenish
;
240 struct iwl_trans
*trans
;
245 dma_addr_t ict_tbl_dma
;
250 struct tasklet_struct irq_tasklet
;
251 struct isr_statistics isr_stats
;
257 struct iwl_dma_ptr scd_bc_tbls
;
258 struct iwl_dma_ptr kw
;
260 struct iwl_tx_queue
*txq
;
261 unsigned long queue_used
[BITS_TO_LONGS(IWL_MAX_HW_QUEUES
)];
262 unsigned long queue_stopped
[BITS_TO_LONGS(IWL_MAX_HW_QUEUES
)];
264 /* PCI bus related data */
265 struct pci_dev
*pci_dev
;
266 void __iomem
*hw_base
;
268 bool ucode_write_complete
;
269 wait_queue_head_t ucode_write_waitq
;
270 unsigned long status
;
273 u8 n_no_reclaim_cmds
;
274 u8 no_reclaim_cmds
[MAX_NO_RECLAIM_CMDS
];
279 const char **command_names
;
282 unsigned long wd_timeout
;
285 /*****************************************************
286 * DRIVER STATUS FUNCTIONS
287 ******************************************************/
288 #define STATUS_HCMD_ACTIVE 0
289 #define STATUS_DEVICE_ENABLED 1
290 #define STATUS_TPOWER_PMI 2
291 #define STATUS_INT_ENABLED 3
293 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
294 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
296 static inline struct iwl_trans
*
297 iwl_trans_pcie_get_trans(struct iwl_trans_pcie
*trans_pcie
)
299 return container_of((void *)trans_pcie
, struct iwl_trans
,
303 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
304 const struct pci_device_id
*ent
,
305 const struct iwl_cfg
*cfg
);
306 void iwl_trans_pcie_free(struct iwl_trans
*trans
);
308 /*****************************************************
310 ******************************************************/
311 void iwl_bg_rx_replenish(struct work_struct
*data
);
312 void iwl_irq_tasklet(struct iwl_trans
*trans
);
313 void iwlagn_rx_replenish(struct iwl_trans
*trans
);
314 void iwl_rx_queue_update_write_ptr(struct iwl_trans
*trans
,
315 struct iwl_rx_queue
*q
);
317 /*****************************************************
319 ******************************************************/
320 void iwl_reset_ict(struct iwl_trans
*trans
);
321 void iwl_disable_ict(struct iwl_trans
*trans
);
322 int iwl_alloc_isr_ict(struct iwl_trans
*trans
);
323 void iwl_free_isr_ict(struct iwl_trans
*trans
);
324 irqreturn_t
iwl_isr_ict(int irq
, void *data
);
326 /*****************************************************
328 ******************************************************/
329 void iwl_txq_update_write_ptr(struct iwl_trans
*trans
,
330 struct iwl_tx_queue
*txq
);
331 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans
*trans
,
332 struct iwl_tx_queue
*txq
,
333 dma_addr_t addr
, u16 len
, u8 reset
);
334 int iwl_queue_init(struct iwl_queue
*q
, int count
, int slots_num
, u32 id
);
335 int iwl_trans_pcie_send_cmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
);
336 void iwl_tx_cmd_complete(struct iwl_trans
*trans
,
337 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
);
338 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
339 struct iwl_tx_queue
*txq
,
341 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, int fifo
,
342 int sta_id
, int tid
, int frame_limit
, u16 ssn
);
343 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int queue
);
344 void iwl_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_tx_queue
*txq
,
345 enum dma_data_direction dma_dir
);
346 int iwl_tx_queue_reclaim(struct iwl_trans
*trans
, int txq_id
, int index
,
347 struct sk_buff_head
*skbs
);
348 int iwl_queue_space(const struct iwl_queue
*q
);
350 /*****************************************************
352 ******************************************************/
353 int iwl_dump_fh(struct iwl_trans
*trans
, char **buf
, bool display
);
354 void iwl_dump_csr(struct iwl_trans
*trans
);
356 /*****************************************************
358 ******************************************************/
359 static inline void iwl_disable_interrupts(struct iwl_trans
*trans
)
361 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
362 clear_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
);
364 /* disable interrupts from uCode/NIC to host */
365 iwl_write32(trans
, CSR_INT_MASK
, 0x00000000);
367 /* acknowledge/clear/reset any interrupts still pending
368 * from uCode or flow handler (Rx/Tx DMA) */
369 iwl_write32(trans
, CSR_INT
, 0xffffffff);
370 iwl_write32(trans
, CSR_FH_INT_STATUS
, 0xffffffff);
371 IWL_DEBUG_ISR(trans
, "Disabled interrupts\n");
374 static inline void iwl_enable_interrupts(struct iwl_trans
*trans
)
376 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
378 IWL_DEBUG_ISR(trans
, "Enabling interrupts\n");
379 set_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
);
380 iwl_write32(trans
, CSR_INT_MASK
, trans_pcie
->inta_mask
);
383 static inline void iwl_enable_rfkill_int(struct iwl_trans
*trans
)
385 IWL_DEBUG_ISR(trans
, "Enabling rfkill interrupt\n");
386 iwl_write32(trans
, CSR_INT_MASK
, CSR_INT_BIT_RF_KILL
);
389 static inline void iwl_wake_queue(struct iwl_trans
*trans
,
390 struct iwl_tx_queue
*txq
)
392 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
394 if (test_and_clear_bit(txq
->q
.id
, trans_pcie
->queue_stopped
)) {
395 IWL_DEBUG_TX_QUEUES(trans
, "Wake hwq %d\n", txq
->q
.id
);
396 iwl_op_mode_queue_not_full(trans
->op_mode
, txq
->q
.id
);
400 static inline void iwl_stop_queue(struct iwl_trans
*trans
,
401 struct iwl_tx_queue
*txq
)
403 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
405 if (!test_and_set_bit(txq
->q
.id
, trans_pcie
->queue_stopped
)) {
406 iwl_op_mode_queue_full(trans
->op_mode
, txq
->q
.id
);
407 IWL_DEBUG_TX_QUEUES(trans
, "Stop hwq %d\n", txq
->q
.id
);
409 IWL_DEBUG_TX_QUEUES(trans
, "hwq %d already stopped\n",
413 static inline int iwl_queue_used(const struct iwl_queue
*q
, int i
)
415 return q
->write_ptr
>= q
->read_ptr
?
416 (i
>= q
->read_ptr
&& i
< q
->write_ptr
) :
417 !(i
< q
->read_ptr
&& i
>= q
->write_ptr
);
420 static inline u8
get_cmd_index(struct iwl_queue
*q
, u32 index
)
422 return index
& (q
->n_window
- 1);
425 static inline const char *
426 trans_pcie_get_cmd_string(struct iwl_trans_pcie
*trans_pcie
, u8 cmd
)
428 if (!trans_pcie
->command_names
|| !trans_pcie
->command_names
[cmd
])
430 return trans_pcie
->command_names
[cmd
];
433 static inline bool iwl_is_rfkill_set(struct iwl_trans
*trans
)
435 return !(iwl_read32(trans
, CSR_GP_CNTRL
) &
436 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
);
439 #endif /* __iwl_trans_int_pcie_h__ */