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forcedeth: rx data path optimization
[linux-2.6.git] / drivers / net / forcedeth.c
blobfd91071bbc8278bdde5b355f3643f53d627c7d8c
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,5,6 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Changelog:
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41 * irq mask updated
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56 * open.
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60 * the tx length.
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * on close.
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
82 * capabilities.
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90 * per-packet flags.
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94 * of nv_remove
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
114 *
115 * Known bugs:
116 * We suspect that on some hardware no TX done interrupts are generated.
117 * This means recovery from netif_stop_queue only happens if the hw timer
118 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
119 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
120 * If your hardware reliably generates tx done interrupts, then you can remove
121 * DEV_NEED_TIMERIRQ from the driver_data flags.
122 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
123 * superfluous timer interrupts from the nic.
124 */
125 #ifdef CONFIG_FORCEDETH_NAPI
126 #define DRIVERNAPI "-NAPI"
127 #else
128 #define DRIVERNAPI
129 #endif
130 #define FORCEDETH_VERSION "0.59"
131 #define DRV_NAME "forcedeth"
132
133 #include <linux/module.h>
134 #include <linux/types.h>
135 #include <linux/pci.h>
136 #include <linux/interrupt.h>
137 #include <linux/netdevice.h>
138 #include <linux/etherdevice.h>
139 #include <linux/delay.h>
140 #include <linux/spinlock.h>
141 #include <linux/ethtool.h>
142 #include <linux/timer.h>
143 #include <linux/skbuff.h>
144 #include <linux/mii.h>
145 #include <linux/random.h>
146 #include <linux/init.h>
147 #include <linux/if_vlan.h>
148 #include <linux/dma-mapping.h>
149
150 #include <asm/irq.h>
151 #include <asm/io.h>
152 #include <asm/uaccess.h>
153 #include <asm/system.h>
154
155 #if 0
156 #define dprintk printk
157 #else
158 #define dprintk(x...) do { } while (0)
159 #endif
160
161
162 /*
163 * Hardware access:
164 */
165
166 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
167 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
168 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
169 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
170 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
171 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
172 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
173 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
174 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
175 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
176 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
177 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
178 #define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
179
180 enum {
181 NvRegIrqStatus = 0x000,
182 #define NVREG_IRQSTAT_MIIEVENT 0x040
183 #define NVREG_IRQSTAT_MASK 0x81ff
184 NvRegIrqMask = 0x004,
185 #define NVREG_IRQ_RX_ERROR 0x0001
186 #define NVREG_IRQ_RX 0x0002
187 #define NVREG_IRQ_RX_NOBUF 0x0004
188 #define NVREG_IRQ_TX_ERR 0x0008
189 #define NVREG_IRQ_TX_OK 0x0010
190 #define NVREG_IRQ_TIMER 0x0020
191 #define NVREG_IRQ_LINK 0x0040
192 #define NVREG_IRQ_RX_FORCED 0x0080
193 #define NVREG_IRQ_TX_FORCED 0x0100
194 #define NVREG_IRQ_RECOVER_ERROR 0x8000
195 #define NVREG_IRQMASK_THROUGHPUT 0x00df
196 #define NVREG_IRQMASK_CPU 0x0040
197 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
198 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
199 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
200
201 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
202 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
203 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
204
205 NvRegUnknownSetupReg6 = 0x008,
206 #define NVREG_UNKSETUP6_VAL 3
207
208 /*
209 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
210 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
211 */
212 NvRegPollingInterval = 0x00c,
213 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
214 #define NVREG_POLL_DEFAULT_CPU 13
215 NvRegMSIMap0 = 0x020,
216 NvRegMSIMap1 = 0x024,
217 NvRegMSIIrqMask = 0x030,
218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
219 NvRegMisc1 = 0x080,
220 #define NVREG_MISC1_PAUSE_TX 0x01
221 #define NVREG_MISC1_HD 0x02
222 #define NVREG_MISC1_FORCE 0x3b0f3c
223
224 NvRegMacReset = 0x3c,
225 #define NVREG_MAC_RESET_ASSERT 0x0F3
226 NvRegTransmitterControl = 0x084,
227 #define NVREG_XMITCTL_START 0x01
228 #define NVREG_XMITCTL_MGMT_ST 0x40000000
229 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
230 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
231 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
232 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
233 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
234 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
235 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
236 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
237 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
238 NvRegTransmitterStatus = 0x088,
239 #define NVREG_XMITSTAT_BUSY 0x01
240
241 NvRegPacketFilterFlags = 0x8c,
242 #define NVREG_PFF_PAUSE_RX 0x08
243 #define NVREG_PFF_ALWAYS 0x7F0000
244 #define NVREG_PFF_PROMISC 0x80
245 #define NVREG_PFF_MYADDR 0x20
246 #define NVREG_PFF_LOOPBACK 0x10
247
248 NvRegOffloadConfig = 0x90,
249 #define NVREG_OFFLOAD_HOMEPHY 0x601
250 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
251 NvRegReceiverControl = 0x094,
252 #define NVREG_RCVCTL_START 0x01
253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
254 NvRegReceiverStatus = 0x98,
255 #define NVREG_RCVSTAT_BUSY 0x01
256
257 NvRegRandomSeed = 0x9c,
258 #define NVREG_RNDSEED_MASK 0x00ff
259 #define NVREG_RNDSEED_FORCE 0x7f00
260 #define NVREG_RNDSEED_FORCE2 0x2d00
261 #define NVREG_RNDSEED_FORCE3 0x7400
262
263 NvRegTxDeferral = 0xA0,
264 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
265 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
266 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
267 NvRegRxDeferral = 0xA4,
268 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
269 NvRegMacAddrA = 0xA8,
270 NvRegMacAddrB = 0xAC,
271 NvRegMulticastAddrA = 0xB0,
272 #define NVREG_MCASTADDRA_FORCE 0x01
273 NvRegMulticastAddrB = 0xB4,
274 NvRegMulticastMaskA = 0xB8,
275 NvRegMulticastMaskB = 0xBC,
276
277 NvRegPhyInterface = 0xC0,
278 #define PHY_RGMII 0x10000000
279
280 NvRegTxRingPhysAddr = 0x100,
281 NvRegRxRingPhysAddr = 0x104,
282 NvRegRingSizes = 0x108,
283 #define NVREG_RINGSZ_TXSHIFT 0
284 #define NVREG_RINGSZ_RXSHIFT 16
285 NvRegTransmitPoll = 0x10c,
286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
287 NvRegLinkSpeed = 0x110,
288 #define NVREG_LINKSPEED_FORCE 0x10000
289 #define NVREG_LINKSPEED_10 1000
290 #define NVREG_LINKSPEED_100 100
291 #define NVREG_LINKSPEED_1000 50
292 #define NVREG_LINKSPEED_MASK (0xFFF)
293 NvRegUnknownSetupReg5 = 0x130,
294 #define NVREG_UNKSETUP5_BIT31 (1<<31)
295 NvRegTxWatermark = 0x13c,
296 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
297 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
298 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
299 NvRegTxRxControl = 0x144,
300 #define NVREG_TXRXCTL_KICK 0x0001
301 #define NVREG_TXRXCTL_BIT1 0x0002
302 #define NVREG_TXRXCTL_BIT2 0x0004
303 #define NVREG_TXRXCTL_IDLE 0x0008
304 #define NVREG_TXRXCTL_RESET 0x0010
305 #define NVREG_TXRXCTL_RXCHECK 0x0400
306 #define NVREG_TXRXCTL_DESC_1 0
307 #define NVREG_TXRXCTL_DESC_2 0x002100
308 #define NVREG_TXRXCTL_DESC_3 0xc02200
309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
310 #define NVREG_TXRXCTL_VLANINS 0x00080
311 NvRegTxRingPhysAddrHigh = 0x148,
312 NvRegRxRingPhysAddrHigh = 0x14C,
313 NvRegTxPauseFrame = 0x170,
314 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
315 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
316 NvRegMIIStatus = 0x180,
317 #define NVREG_MIISTAT_ERROR 0x0001
318 #define NVREG_MIISTAT_LINKCHANGE 0x0008
319 #define NVREG_MIISTAT_MASK 0x000f
320 #define NVREG_MIISTAT_MASK2 0x000f
321 NvRegMIIMask = 0x184,
322 #define NVREG_MII_LINKCHANGE 0x0008
323
324 NvRegAdapterControl = 0x188,
325 #define NVREG_ADAPTCTL_START 0x02
326 #define NVREG_ADAPTCTL_LINKUP 0x04
327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
328 #define NVREG_ADAPTCTL_RUNNING 0x100000
329 #define NVREG_ADAPTCTL_PHYSHIFT 24
330 NvRegMIISpeed = 0x18c,
331 #define NVREG_MIISPEED_BIT8 (1<<8)
332 #define NVREG_MIIDELAY 5
333 NvRegMIIControl = 0x190,
334 #define NVREG_MIICTL_INUSE 0x08000
335 #define NVREG_MIICTL_WRITE 0x00400
336 #define NVREG_MIICTL_ADDRSHIFT 5
337 NvRegMIIData = 0x194,
338 NvRegWakeUpFlags = 0x200,
339 #define NVREG_WAKEUPFLAGS_VAL 0x7770
340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
342 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
343 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
344 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
345 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
349 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
350
351 NvRegPatternCRC = 0x204,
352 NvRegPatternMask = 0x208,
353 NvRegPowerCap = 0x268,
354 #define NVREG_POWERCAP_D3SUPP (1<<30)
355 #define NVREG_POWERCAP_D2SUPP (1<<26)
356 #define NVREG_POWERCAP_D1SUPP (1<<25)
357 NvRegPowerState = 0x26c,
358 #define NVREG_POWERSTATE_POWEREDUP 0x8000
359 #define NVREG_POWERSTATE_VALID 0x0100
360 #define NVREG_POWERSTATE_MASK 0x0003
361 #define NVREG_POWERSTATE_D0 0x0000
362 #define NVREG_POWERSTATE_D1 0x0001
363 #define NVREG_POWERSTATE_D2 0x0002
364 #define NVREG_POWERSTATE_D3 0x0003
365 NvRegTxCnt = 0x280,
366 NvRegTxZeroReXmt = 0x284,
367 NvRegTxOneReXmt = 0x288,
368 NvRegTxManyReXmt = 0x28c,
369 NvRegTxLateCol = 0x290,
370 NvRegTxUnderflow = 0x294,
371 NvRegTxLossCarrier = 0x298,
372 NvRegTxExcessDef = 0x29c,
373 NvRegTxRetryErr = 0x2a0,
374 NvRegRxFrameErr = 0x2a4,
375 NvRegRxExtraByte = 0x2a8,
376 NvRegRxLateCol = 0x2ac,
377 NvRegRxRunt = 0x2b0,
378 NvRegRxFrameTooLong = 0x2b4,
379 NvRegRxOverflow = 0x2b8,
380 NvRegRxFCSErr = 0x2bc,
381 NvRegRxFrameAlignErr = 0x2c0,
382 NvRegRxLenErr = 0x2c4,
383 NvRegRxUnicast = 0x2c8,
384 NvRegRxMulticast = 0x2cc,
385 NvRegRxBroadcast = 0x2d0,
386 NvRegTxDef = 0x2d4,
387 NvRegTxFrame = 0x2d8,
388 NvRegRxCnt = 0x2dc,
389 NvRegTxPause = 0x2e0,
390 NvRegRxPause = 0x2e4,
391 NvRegRxDropFrame = 0x2e8,
392 NvRegVlanControl = 0x300,
393 #define NVREG_VLANCONTROL_ENABLE 0x2000
394 NvRegMSIXMap0 = 0x3e0,
395 NvRegMSIXMap1 = 0x3e4,
396 NvRegMSIXIrqStatus = 0x3f0,
397
398 NvRegPowerState2 = 0x600,
399 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
400 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
401 };
402
403 /* Big endian: should work, but is untested */
404 struct ring_desc {
405 __le32 buf;
406 __le32 flaglen;
407 };
408
409 struct ring_desc_ex {
410 __le32 bufhigh;
411 __le32 buflow;
412 __le32 txvlan;
413 __le32 flaglen;
414 };
415
416 union ring_type {
417 struct ring_desc* orig;
418 struct ring_desc_ex* ex;
419 };
420
421 #define FLAG_MASK_V1 0xffff0000
422 #define FLAG_MASK_V2 0xffffc000
423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
425
426 #define NV_TX_LASTPACKET (1<<16)
427 #define NV_TX_RETRYERROR (1<<19)
428 #define NV_TX_FORCED_INTERRUPT (1<<24)
429 #define NV_TX_DEFERRED (1<<26)
430 #define NV_TX_CARRIERLOST (1<<27)
431 #define NV_TX_LATECOLLISION (1<<28)
432 #define NV_TX_UNDERFLOW (1<<29)
433 #define NV_TX_ERROR (1<<30)
434 #define NV_TX_VALID (1<<31)
435
436 #define NV_TX2_LASTPACKET (1<<29)
437 #define NV_TX2_RETRYERROR (1<<18)
438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
439 #define NV_TX2_DEFERRED (1<<25)
440 #define NV_TX2_CARRIERLOST (1<<26)
441 #define NV_TX2_LATECOLLISION (1<<27)
442 #define NV_TX2_UNDERFLOW (1<<28)
443 /* error and valid are the same for both */
444 #define NV_TX2_ERROR (1<<30)
445 #define NV_TX2_VALID (1<<31)
446 #define NV_TX2_TSO (1<<28)
447 #define NV_TX2_TSO_SHIFT 14
448 #define NV_TX2_TSO_MAX_SHIFT 14
449 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
450 #define NV_TX2_CHECKSUM_L3 (1<<27)
451 #define NV_TX2_CHECKSUM_L4 (1<<26)
452
453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
454
455 #define NV_RX_DESCRIPTORVALID (1<<16)
456 #define NV_RX_MISSEDFRAME (1<<17)
457 #define NV_RX_SUBSTRACT1 (1<<18)
458 #define NV_RX_ERROR1 (1<<23)
459 #define NV_RX_ERROR2 (1<<24)
460 #define NV_RX_ERROR3 (1<<25)
461 #define NV_RX_ERROR4 (1<<26)
462 #define NV_RX_CRCERR (1<<27)
463 #define NV_RX_OVERFLOW (1<<28)
464 #define NV_RX_FRAMINGERR (1<<29)
465 #define NV_RX_ERROR (1<<30)
466 #define NV_RX_AVAIL (1<<31)
467
468 #define NV_RX2_CHECKSUMMASK (0x1C000000)
469 #define NV_RX2_CHECKSUMOK1 (0x10000000)
470 #define NV_RX2_CHECKSUMOK2 (0x14000000)
471 #define NV_RX2_CHECKSUMOK3 (0x18000000)
472 #define NV_RX2_DESCRIPTORVALID (1<<29)
473 #define NV_RX2_SUBSTRACT1 (1<<25)
474 #define NV_RX2_ERROR1 (1<<18)
475 #define NV_RX2_ERROR2 (1<<19)
476 #define NV_RX2_ERROR3 (1<<20)
477 #define NV_RX2_ERROR4 (1<<21)
478 #define NV_RX2_CRCERR (1<<22)
479 #define NV_RX2_OVERFLOW (1<<23)
480 #define NV_RX2_FRAMINGERR (1<<24)
481 /* error and avail are the same for both */
482 #define NV_RX2_ERROR (1<<30)
483 #define NV_RX2_AVAIL (1<<31)
484
485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
486 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
487
488 /* Miscelaneous hardware related defines: */
489 #define NV_PCI_REGSZ_VER1 0x270
490 #define NV_PCI_REGSZ_VER2 0x604
491
492 /* various timeout delays: all in usec */
493 #define NV_TXRX_RESET_DELAY 4
494 #define NV_TXSTOP_DELAY1 10
495 #define NV_TXSTOP_DELAY1MAX 500000
496 #define NV_TXSTOP_DELAY2 100
497 #define NV_RXSTOP_DELAY1 10
498 #define NV_RXSTOP_DELAY1MAX 500000
499 #define NV_RXSTOP_DELAY2 100
500 #define NV_SETUP5_DELAY 5
501 #define NV_SETUP5_DELAYMAX 50000
502 #define NV_POWERUP_DELAY 5
503 #define NV_POWERUP_DELAYMAX 5000
504 #define NV_MIIBUSY_DELAY 50
505 #define NV_MIIPHY_DELAY 10
506 #define NV_MIIPHY_DELAYMAX 10000
507 #define NV_MAC_RESET_DELAY 64
508
509 #define NV_WAKEUPPATTERNS 5
510 #define NV_WAKEUPMASKENTRIES 4
511
512 /* General driver defaults */
513 #define NV_WATCHDOG_TIMEO (5*HZ)
514
515 #define RX_RING_DEFAULT 128
516 #define TX_RING_DEFAULT 256
517 #define RX_RING_MIN 128
518 #define TX_RING_MIN 64
519 #define RING_MAX_DESC_VER_1 1024
520 #define RING_MAX_DESC_VER_2_3 16384
521
522 /* rx/tx mac addr + type + vlan + align + slack*/
523 #define NV_RX_HEADERS (64)
524 /* even more slack. */
525 #define NV_RX_ALLOC_PAD (64)
526
527 /* maximum mtu size */
528 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
529 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
530
531 #define OOM_REFILL (1+HZ/20)
532 #define POLL_WAIT (1+HZ/100)
533 #define LINK_TIMEOUT (3*HZ)
534 #define STATS_INTERVAL (10*HZ)
535
536 /*
537 * desc_ver values:
538 * The nic supports three different descriptor types:
539 * - DESC_VER_1: Original
540 * - DESC_VER_2: support for jumbo frames.
541 * - DESC_VER_3: 64-bit format.
542 */
543 #define DESC_VER_1 1
544 #define DESC_VER_2 2
545 #define DESC_VER_3 3
546
547 /* PHY defines */
548 #define PHY_OUI_MARVELL 0x5043
549 #define PHY_OUI_CICADA 0x03f1
550 #define PHYID1_OUI_MASK 0x03ff
551 #define PHYID1_OUI_SHFT 6
552 #define PHYID2_OUI_MASK 0xfc00
553 #define PHYID2_OUI_SHFT 10
554 #define PHYID2_MODEL_MASK 0x03f0
555 #define PHY_MODEL_MARVELL_E3016 0x220
556 #define PHY_MARVELL_E3016_INITMASK 0x0300
557 #define PHY_INIT1 0x0f000
558 #define PHY_INIT2 0x0e00
559 #define PHY_INIT3 0x01000
560 #define PHY_INIT4 0x0200
561 #define PHY_INIT5 0x0004
562 #define PHY_INIT6 0x02000
563 #define PHY_GIGABIT 0x0100
564
565 #define PHY_TIMEOUT 0x1
566 #define PHY_ERROR 0x2
567
568 #define PHY_100 0x1
569 #define PHY_1000 0x2
570 #define PHY_HALF 0x100
571
572 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
573 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
574 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
575 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
576 #define NV_PAUSEFRAME_RX_REQ 0x0010
577 #define NV_PAUSEFRAME_TX_REQ 0x0020
578 #define NV_PAUSEFRAME_AUTONEG 0x0040
579
580 /* MSI/MSI-X defines */
581 #define NV_MSI_X_MAX_VECTORS 8
582 #define NV_MSI_X_VECTORS_MASK 0x000f
583 #define NV_MSI_CAPABLE 0x0010
584 #define NV_MSI_X_CAPABLE 0x0020
585 #define NV_MSI_ENABLED 0x0040
586 #define NV_MSI_X_ENABLED 0x0080
587
588 #define NV_MSI_X_VECTOR_ALL 0x0
589 #define NV_MSI_X_VECTOR_RX 0x0
590 #define NV_MSI_X_VECTOR_TX 0x1
591 #define NV_MSI_X_VECTOR_OTHER 0x2
592
593 /* statistics */
594 struct nv_ethtool_str {
595 char name[ETH_GSTRING_LEN];
596 };
597
598 static const struct nv_ethtool_str nv_estats_str[] = {
599 { "tx_bytes" },
600 { "tx_zero_rexmt" },
601 { "tx_one_rexmt" },
602 { "tx_many_rexmt" },
603 { "tx_late_collision" },
604 { "tx_fifo_errors" },
605 { "tx_carrier_errors" },
606 { "tx_excess_deferral" },
607 { "tx_retry_error" },
608 { "tx_deferral" },
609 { "tx_packets" },
610 { "tx_pause" },
611 { "rx_frame_error" },
612 { "rx_extra_byte" },
613 { "rx_late_collision" },
614 { "rx_runt" },
615 { "rx_frame_too_long" },
616 { "rx_over_errors" },
617 { "rx_crc_errors" },
618 { "rx_frame_align_error" },
619 { "rx_length_error" },
620 { "rx_unicast" },
621 { "rx_multicast" },
622 { "rx_broadcast" },
623 { "rx_bytes" },
624 { "rx_pause" },
625 { "rx_drop_frame" },
626 { "rx_packets" },
627 { "rx_errors_total" }
628 };
629
630 struct nv_ethtool_stats {
631 u64 tx_bytes;
632 u64 tx_zero_rexmt;
633 u64 tx_one_rexmt;
634 u64 tx_many_rexmt;
635 u64 tx_late_collision;
636 u64 tx_fifo_errors;
637 u64 tx_carrier_errors;
638 u64 tx_excess_deferral;
639 u64 tx_retry_error;
640 u64 tx_deferral;
641 u64 tx_packets;
642 u64 tx_pause;
643 u64 rx_frame_error;
644 u64 rx_extra_byte;
645 u64 rx_late_collision;
646 u64 rx_runt;
647 u64 rx_frame_too_long;
648 u64 rx_over_errors;
649 u64 rx_crc_errors;
650 u64 rx_frame_align_error;
651 u64 rx_length_error;
652 u64 rx_unicast;
653 u64 rx_multicast;
654 u64 rx_broadcast;
655 u64 rx_bytes;
656 u64 rx_pause;
657 u64 rx_drop_frame;
658 u64 rx_packets;
659 u64 rx_errors_total;
660 };
661
662 /* diagnostics */
663 #define NV_TEST_COUNT_BASE 3
664 #define NV_TEST_COUNT_EXTENDED 4
665
666 static const struct nv_ethtool_str nv_etests_str[] = {
667 { "link (online/offline)" },
668 { "register (offline) " },
669 { "interrupt (offline) " },
670 { "loopback (offline) " }
671 };
672
673 struct register_test {
674 __le32 reg;
675 __le32 mask;
676 };
677
678 static const struct register_test nv_registers_test[] = {
679 { NvRegUnknownSetupReg6, 0x01 },
680 { NvRegMisc1, 0x03c },
681 { NvRegOffloadConfig, 0x03ff },
682 { NvRegMulticastAddrA, 0xffffffff },
683 { NvRegTxWatermark, 0x0ff },
684 { NvRegWakeUpFlags, 0x07777 },
685 { 0,0 }
686 };
687
688 struct nv_skb_map {
689 struct sk_buff *skb;
690 dma_addr_t dma;
691 unsigned int dma_len;
692 };
693
694 /*
695 * SMP locking:
696 * All hardware access under dev->priv->lock, except the performance
697 * critical parts:
698 * - rx is (pseudo-) lockless: it relies on the single-threading provided
699 * by the arch code for interrupts.
700 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
701 * needs dev->priv->lock :-(
702 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
703 */
704
705 /* in dev: base, irq */
706 struct fe_priv {
707 spinlock_t lock;
708
709 /* General data:
710 * Locking: spin_lock(&np->lock); */
711 struct net_device_stats stats;
712 struct nv_ethtool_stats estats;
713 int in_shutdown;
714 u32 linkspeed;
715 int duplex;
716 int autoneg;
717 int fixed_mode;
718 int phyaddr;
719 int wolenabled;
720 unsigned int phy_oui;
721 unsigned int phy_model;
722 u16 gigabit;
723 int intr_test;
724 int recover_error;
725
726 /* General data: RO fields */
727 dma_addr_t ring_addr;
728 struct pci_dev *pci_dev;
729 u32 orig_mac[2];
730 u32 irqmask;
731 u32 desc_ver;
732 u32 txrxctl_bits;
733 u32 vlanctl_bits;
734 u32 driver_data;
735 u32 register_size;
736 int rx_csum;
737 u32 mac_in_use;
738
739 void __iomem *base;
740
741 /* rx specific fields.
742 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
743 */
744 union ring_type get_rx, put_rx, first_rx, last_rx;
745 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
746 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
747 struct nv_skb_map *rx_skb;
748
749 union ring_type rx_ring;
750 unsigned int rx_buf_sz;
751 unsigned int pkt_limit;
752 struct timer_list oom_kick;
753 struct timer_list nic_poll;
754 struct timer_list stats_poll;
755 u32 nic_poll_irq;
756 int rx_ring_size;
757
758 /* media detection workaround.
759 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
760 */
761 int need_linktimer;
762 unsigned long link_timeout;
763 /*
764 * tx specific fields.
765 */
766 union ring_type get_tx, put_tx, first_tx, last_tx;
767 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
768 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
769 struct nv_skb_map *tx_skb;
770
771 union ring_type tx_ring;
772 u32 tx_flags;
773 int tx_ring_size;
774 int tx_stop;
775
776 /* vlan fields */
777 struct vlan_group *vlangrp;
778
779 /* msi/msi-x fields */
780 u32 msi_flags;
781 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
782
783 /* flow control */
784 u32 pause_flags;
785 };
786
787 /*
788 * Maximum number of loops until we assume that a bit in the irq mask
789 * is stuck. Overridable with module param.
790 */
791 static int max_interrupt_work = 5;
792
793 /*
794 * Optimization can be either throuput mode or cpu mode
795 *
796 * Throughput Mode: Every tx and rx packet will generate an interrupt.
797 * CPU Mode: Interrupts are controlled by a timer.
798 */
799 enum {
800 NV_OPTIMIZATION_MODE_THROUGHPUT,
801 NV_OPTIMIZATION_MODE_CPU
802 };
803 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
804
805 /*
806 * Poll interval for timer irq
807 *
808 * This interval determines how frequent an interrupt is generated.
809 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
810 * Min = 0, and Max = 65535
811 */
812 static int poll_interval = -1;
813
814 /*
815 * MSI interrupts
816 */
817 enum {
818 NV_MSI_INT_DISABLED,
819 NV_MSI_INT_ENABLED
820 };
821 static int msi = NV_MSI_INT_ENABLED;
822
823 /*
824 * MSIX interrupts
825 */
826 enum {
827 NV_MSIX_INT_DISABLED,
828 NV_MSIX_INT_ENABLED
829 };
830 static int msix = NV_MSIX_INT_ENABLED;
831
832 /*
833 * DMA 64bit
834 */
835 enum {
836 NV_DMA_64BIT_DISABLED,
837 NV_DMA_64BIT_ENABLED
838 };
839 static int dma_64bit = NV_DMA_64BIT_ENABLED;
840
841 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
842 {
843 return netdev_priv(dev);
844 }
845
846 static inline u8 __iomem *get_hwbase(struct net_device *dev)
847 {
848 return ((struct fe_priv *)netdev_priv(dev))->base;
849 }
850
851 static inline void pci_push(u8 __iomem *base)
852 {
853 /* force out pending posted writes */
854 readl(base);
855 }
856
857 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
858 {
859 return le32_to_cpu(prd->flaglen)
860 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
861 }
862
863 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
864 {
865 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
866 }
867
868 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
869 int delay, int delaymax, const char *msg)
870 {
871 u8 __iomem *base = get_hwbase(dev);
872
873 pci_push(base);
874 do {
875 udelay(delay);
876 delaymax -= delay;
877 if (delaymax < 0) {
878 if (msg)
879 printk(msg);
880 return 1;
881 }
882 } while ((readl(base + offset) & mask) != target);
883 return 0;
884 }
885
886 #define NV_SETUP_RX_RING 0x01
887 #define NV_SETUP_TX_RING 0x02
888
889 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
890 {
891 struct fe_priv *np = get_nvpriv(dev);
892 u8 __iomem *base = get_hwbase(dev);
893
894 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
895 if (rxtx_flags & NV_SETUP_RX_RING) {
896 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
897 }
898 if (rxtx_flags & NV_SETUP_TX_RING) {
899 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
900 }
901 } else {
902 if (rxtx_flags & NV_SETUP_RX_RING) {
903 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
904 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
905 }
906 if (rxtx_flags & NV_SETUP_TX_RING) {
907 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
908 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
909 }
910 }
911 }
912
913 static void free_rings(struct net_device *dev)
914 {
915 struct fe_priv *np = get_nvpriv(dev);
916
917 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
918 if (np->rx_ring.orig)
919 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
920 np->rx_ring.orig, np->ring_addr);
921 } else {
922 if (np->rx_ring.ex)
923 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
924 np->rx_ring.ex, np->ring_addr);
925 }
926 if (np->rx_skb)
927 kfree(np->rx_skb);
928 if (np->tx_skb)
929 kfree(np->tx_skb);
930 }
931
932 static int using_multi_irqs(struct net_device *dev)
933 {
934 struct fe_priv *np = get_nvpriv(dev);
935
936 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
937 ((np->msi_flags & NV_MSI_X_ENABLED) &&
938 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
939 return 0;
940 else
941 return 1;
942 }
943
944 static void nv_enable_irq(struct net_device *dev)
945 {
946 struct fe_priv *np = get_nvpriv(dev);
947
948 if (!using_multi_irqs(dev)) {
949 if (np->msi_flags & NV_MSI_X_ENABLED)
950 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
951 else
952 enable_irq(dev->irq);
953 } else {
954 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
955 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
956 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
957 }
958 }
959
960 static void nv_disable_irq(struct net_device *dev)
961 {
962 struct fe_priv *np = get_nvpriv(dev);
963
964 if (!using_multi_irqs(dev)) {
965 if (np->msi_flags & NV_MSI_X_ENABLED)
966 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
967 else
968 disable_irq(dev->irq);
969 } else {
970 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
971 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
972 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
973 }
974 }
975
976 /* In MSIX mode, a write to irqmask behaves as XOR */
977 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
978 {
979 u8 __iomem *base = get_hwbase(dev);
980
981 writel(mask, base + NvRegIrqMask);
982 }
983
984 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
985 {
986 struct fe_priv *np = get_nvpriv(dev);
987 u8 __iomem *base = get_hwbase(dev);
988
989 if (np->msi_flags & NV_MSI_X_ENABLED) {
990 writel(mask, base + NvRegIrqMask);
991 } else {
992 if (np->msi_flags & NV_MSI_ENABLED)
993 writel(0, base + NvRegMSIIrqMask);
994 writel(0, base + NvRegIrqMask);
995 }
996 }
997
998 #define MII_READ (-1)
999 /* mii_rw: read/write a register on the PHY.
1000 *
1001 * Caller must guarantee serialization
1002 */
1003 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1004 {
1005 u8 __iomem *base = get_hwbase(dev);
1006 u32 reg;
1007 int retval;
1008
1009 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1010
1011 reg = readl(base + NvRegMIIControl);
1012 if (reg & NVREG_MIICTL_INUSE) {
1013 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1014 udelay(NV_MIIBUSY_DELAY);
1015 }
1016
1017 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1018 if (value != MII_READ) {
1019 writel(value, base + NvRegMIIData);
1020 reg |= NVREG_MIICTL_WRITE;
1021 }
1022 writel(reg, base + NvRegMIIControl);
1023
1024 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1025 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1026 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1027 dev->name, miireg, addr);
1028 retval = -1;
1029 } else if (value != MII_READ) {
1030 /* it was a write operation - fewer failures are detectable */
1031 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1032 dev->name, value, miireg, addr);
1033 retval = 0;
1034 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1035 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1036 dev->name, miireg, addr);
1037 retval = -1;
1038 } else {
1039 retval = readl(base + NvRegMIIData);
1040 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1041 dev->name, miireg, addr, retval);
1042 }
1043
1044 return retval;
1045 }
1046
1047 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1048 {
1049 struct fe_priv *np = netdev_priv(dev);
1050 u32 miicontrol;
1051 unsigned int tries = 0;
1052
1053 miicontrol = BMCR_RESET | bmcr_setup;
1054 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1055 return -1;
1056 }
1057
1058 /* wait for 500ms */
1059 msleep(500);
1060
1061 /* must wait till reset is deasserted */
1062 while (miicontrol & BMCR_RESET) {
1063 msleep(10);
1064 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1065 /* FIXME: 100 tries seem excessive */
1066 if (tries++ > 100)
1067 return -1;
1068 }
1069 return 0;
1070 }
1071
1072 static int phy_init(struct net_device *dev)
1073 {
1074 struct fe_priv *np = get_nvpriv(dev);
1075 u8 __iomem *base = get_hwbase(dev);
1076 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1077
1078 /* phy errata for E3016 phy */
1079 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1080 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1081 reg &= ~PHY_MARVELL_E3016_INITMASK;
1082 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1083 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1084 return PHY_ERROR;
1085 }
1086 }
1087
1088 /* set advertise register */
1089 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1090 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1091 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1092 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1093 return PHY_ERROR;
1094 }
1095
1096 /* get phy interface type */
1097 phyinterface = readl(base + NvRegPhyInterface);
1098
1099 /* see if gigabit phy */
1100 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1101 if (mii_status & PHY_GIGABIT) {
1102 np->gigabit = PHY_GIGABIT;
1103 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1104 mii_control_1000 &= ~ADVERTISE_1000HALF;
1105 if (phyinterface & PHY_RGMII)
1106 mii_control_1000 |= ADVERTISE_1000FULL;
1107 else
1108 mii_control_1000 &= ~ADVERTISE_1000FULL;
1109
1110 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1111 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1112 return PHY_ERROR;
1113 }
1114 }
1115 else
1116 np->gigabit = 0;
1117
1118 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1119 mii_control |= BMCR_ANENABLE;
1120
1121 /* reset the phy
1122 * (certain phys need bmcr to be setup with reset)
1123 */
1124 if (phy_reset(dev, mii_control)) {
1125 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1126 return PHY_ERROR;
1127 }
1128
1129 /* phy vendor specific configuration */
1130 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1131 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1132 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1133 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1134 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1135 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1136 return PHY_ERROR;
1137 }
1138 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1139 phy_reserved |= PHY_INIT5;
1140 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1141 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1142 return PHY_ERROR;
1143 }
1144 }
1145 if (np->phy_oui == PHY_OUI_CICADA) {
1146 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1147 phy_reserved |= PHY_INIT6;
1148 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1149 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1150 return PHY_ERROR;
1151 }
1152 }
1153 /* some phys clear out pause advertisment on reset, set it back */
1154 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1155
1156 /* restart auto negotiation */
1157 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1158 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1159 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1160 return PHY_ERROR;
1161 }
1162
1163 return 0;
1164 }
1165
1166 static void nv_start_rx(struct net_device *dev)
1167 {
1168 struct fe_priv *np = netdev_priv(dev);
1169 u8 __iomem *base = get_hwbase(dev);
1170 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1171
1172 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1173 /* Already running? Stop it. */
1174 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1175 rx_ctrl &= ~NVREG_RCVCTL_START;
1176 writel(rx_ctrl, base + NvRegReceiverControl);
1177 pci_push(base);
1178 }
1179 writel(np->linkspeed, base + NvRegLinkSpeed);
1180 pci_push(base);
1181 rx_ctrl |= NVREG_RCVCTL_START;
1182 if (np->mac_in_use)
1183 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1184 writel(rx_ctrl, base + NvRegReceiverControl);
1185 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1186 dev->name, np->duplex, np->linkspeed);
1187 pci_push(base);
1188 }
1189
1190 static void nv_stop_rx(struct net_device *dev)
1191 {
1192 struct fe_priv *np = netdev_priv(dev);
1193 u8 __iomem *base = get_hwbase(dev);
1194 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1195
1196 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1197 if (!np->mac_in_use)
1198 rx_ctrl &= ~NVREG_RCVCTL_START;
1199 else
1200 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1201 writel(rx_ctrl, base + NvRegReceiverControl);
1202 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1203 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1204 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1205
1206 udelay(NV_RXSTOP_DELAY2);
1207 if (!np->mac_in_use)
1208 writel(0, base + NvRegLinkSpeed);
1209 }
1210
1211 static void nv_start_tx(struct net_device *dev)
1212 {
1213 struct fe_priv *np = netdev_priv(dev);
1214 u8 __iomem *base = get_hwbase(dev);
1215 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1216
1217 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1218 tx_ctrl |= NVREG_XMITCTL_START;
1219 if (np->mac_in_use)
1220 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1221 writel(tx_ctrl, base + NvRegTransmitterControl);
1222 pci_push(base);
1223 }
1224
1225 static void nv_stop_tx(struct net_device *dev)
1226 {
1227 struct fe_priv *np = netdev_priv(dev);
1228 u8 __iomem *base = get_hwbase(dev);
1229 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1230
1231 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1232 if (!np->mac_in_use)
1233 tx_ctrl &= ~NVREG_XMITCTL_START;
1234 else
1235 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1236 writel(tx_ctrl, base + NvRegTransmitterControl);
1237 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1238 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1239 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1240
1241 udelay(NV_TXSTOP_DELAY2);
1242 if (!np->mac_in_use)
1243 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1244 base + NvRegTransmitPoll);
1245 }
1246
1247 static void nv_txrx_reset(struct net_device *dev)
1248 {
1249 struct fe_priv *np = netdev_priv(dev);
1250 u8 __iomem *base = get_hwbase(dev);
1251
1252 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1253 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1254 pci_push(base);
1255 udelay(NV_TXRX_RESET_DELAY);
1256 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1257 pci_push(base);
1258 }
1259
1260 static void nv_mac_reset(struct net_device *dev)
1261 {
1262 struct fe_priv *np = netdev_priv(dev);
1263 u8 __iomem *base = get_hwbase(dev);
1264
1265 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1266 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1267 pci_push(base);
1268 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1269 pci_push(base);
1270 udelay(NV_MAC_RESET_DELAY);
1271 writel(0, base + NvRegMacReset);
1272 pci_push(base);
1273 udelay(NV_MAC_RESET_DELAY);
1274 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1275 pci_push(base);
1276 }
1277
1278 /*
1279 * nv_get_stats: dev->get_stats function
1280 * Get latest stats value from the nic.
1281 * Called with read_lock(&dev_base_lock) held for read -
1282 * only synchronized against unregister_netdevice.
1283 */
1284 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1285 {
1286 struct fe_priv *np = netdev_priv(dev);
1287
1288 /* It seems that the nic always generates interrupts and doesn't
1289 * accumulate errors internally. Thus the current values in np->stats
1290 * are already up to date.
1291 */
1292 return &np->stats;
1293 }
1294
1295 /*
1296 * nv_alloc_rx: fill rx ring entries.
1297 * Return 1 if the allocations for the skbs failed and the
1298 * rx engine is without Available descriptors
1299 */
1300 static int nv_alloc_rx(struct net_device *dev)
1301 {
1302 struct fe_priv *np = netdev_priv(dev);
1303 struct ring_desc* less_rx;
1304
1305 less_rx = np->get_rx.orig;
1306 if (less_rx-- == np->first_rx.orig)
1307 less_rx = np->last_rx.orig;
1308
1309 while (np->put_rx.orig != less_rx) {
1310 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1311 if (skb) {
1312 skb->dev = dev;
1313 np->put_rx_ctx->skb = skb;
1314 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1315 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1316 np->put_rx_ctx->dma_len = skb->end-skb->data;
1317 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1318 wmb();
1319 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1320 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1321 np->put_rx.orig = np->first_rx.orig;
1322 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1323 np->put_rx_ctx = np->first_rx_ctx;
1324 } else {
1325 return 1;
1326 }
1327 }
1328 return 0;
1329 }
1330
1331 static int nv_alloc_rx_optimized(struct net_device *dev)
1332 {
1333 struct fe_priv *np = netdev_priv(dev);
1334 struct ring_desc_ex* less_rx;
1335
1336 less_rx = np->get_rx.ex;
1337 if (less_rx-- == np->first_rx.ex)
1338 less_rx = np->last_rx.ex;
1339
1340 while (np->put_rx.ex != less_rx) {
1341 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1342 if (skb) {
1343 skb->dev = dev;
1344 np->put_rx_ctx->skb = skb;
1345 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1346 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1347 np->put_rx_ctx->dma_len = skb->end-skb->data;
1348 np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1349 np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1350 wmb();
1351 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1352 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1353 np->put_rx.ex = np->first_rx.ex;
1354 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1355 np->put_rx_ctx = np->first_rx_ctx;
1356 } else {
1357 return 1;
1358 }
1359 }
1360 return 0;
1361 }
1362
1363 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1364 #ifdef CONFIG_FORCEDETH_NAPI
1365 static void nv_do_rx_refill(unsigned long data)
1366 {
1367 struct net_device *dev = (struct net_device *) data;
1368
1369 /* Just reschedule NAPI rx processing */
1370 netif_rx_schedule(dev);
1371 }
1372 #else
1373 static void nv_do_rx_refill(unsigned long data)
1374 {
1375 struct net_device *dev = (struct net_device *) data;
1376 struct fe_priv *np = netdev_priv(dev);
1377 int retcode;
1378
1379 if (!using_multi_irqs(dev)) {
1380 if (np->msi_flags & NV_MSI_X_ENABLED)
1381 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1382 else
1383 disable_irq(dev->irq);
1384 } else {
1385 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1386 }
1387 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1388 retcode = nv_alloc_rx(dev);
1389 else
1390 retcode = nv_alloc_rx_optimized(dev);
1391 if (retcode) {
1392 spin_lock_irq(&np->lock);
1393 if (!np->in_shutdown)
1394 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1395 spin_unlock_irq(&np->lock);
1396 }
1397 if (!using_multi_irqs(dev)) {
1398 if (np->msi_flags & NV_MSI_X_ENABLED)
1399 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1400 else
1401 enable_irq(dev->irq);
1402 } else {
1403 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1404 }
1405 }
1406 #endif
1407
1408 static void nv_init_rx(struct net_device *dev)
1409 {
1410 struct fe_priv *np = netdev_priv(dev);
1411 int i;
1412 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1413 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1414 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1415 else
1416 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1417 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1418 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1419
1420 for (i = 0; i < np->rx_ring_size; i++) {
1421 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1422 np->rx_ring.orig[i].flaglen = 0;
1423 np->rx_ring.orig[i].buf = 0;
1424 } else {
1425 np->rx_ring.ex[i].flaglen = 0;
1426 np->rx_ring.ex[i].txvlan = 0;
1427 np->rx_ring.ex[i].bufhigh = 0;
1428 np->rx_ring.ex[i].buflow = 0;
1429 }
1430 np->rx_skb[i].skb = NULL;
1431 np->rx_skb[i].dma = 0;
1432 }
1433 }
1434
1435 static void nv_init_tx(struct net_device *dev)
1436 {
1437 struct fe_priv *np = netdev_priv(dev);
1438 int i;
1439 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1440 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1441 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1442 else
1443 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1444 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1445 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1446
1447 for (i = 0; i < np->tx_ring_size; i++) {
1448 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1449 np->tx_ring.orig[i].flaglen = 0;
1450 np->tx_ring.orig[i].buf = 0;
1451 } else {
1452 np->tx_ring.ex[i].flaglen = 0;
1453 np->tx_ring.ex[i].txvlan = 0;
1454 np->tx_ring.ex[i].bufhigh = 0;
1455 np->tx_ring.ex[i].buflow = 0;
1456 }
1457 np->tx_skb[i].skb = NULL;
1458 np->tx_skb[i].dma = 0;
1459 }
1460 }
1461
1462 static int nv_init_ring(struct net_device *dev)
1463 {
1464 struct fe_priv *np = netdev_priv(dev);
1465
1466 nv_init_tx(dev);
1467 nv_init_rx(dev);
1468 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1469 return nv_alloc_rx(dev);
1470 else
1471 return nv_alloc_rx_optimized(dev);
1472 }
1473
1474 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1475 {
1476 struct fe_priv *np = netdev_priv(dev);
1477
1478 if (tx_skb->dma) {
1479 pci_unmap_page(np->pci_dev, tx_skb->dma,
1480 tx_skb->dma_len,
1481 PCI_DMA_TODEVICE);
1482 tx_skb->dma = 0;
1483 }
1484 if (tx_skb->skb) {
1485 dev_kfree_skb_any(tx_skb->skb);
1486 tx_skb->skb = NULL;
1487 return 1;
1488 } else {
1489 return 0;
1490 }
1491 }
1492
1493 static void nv_drain_tx(struct net_device *dev)
1494 {
1495 struct fe_priv *np = netdev_priv(dev);
1496 unsigned int i;
1497
1498 for (i = 0; i < np->tx_ring_size; i++) {
1499 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1500 np->tx_ring.orig[i].flaglen = 0;
1501 np->tx_ring.orig[i].buf = 0;
1502 } else {
1503 np->tx_ring.ex[i].flaglen = 0;
1504 np->tx_ring.ex[i].txvlan = 0;
1505 np->tx_ring.ex[i].bufhigh = 0;
1506 np->tx_ring.ex[i].buflow = 0;
1507 }
1508 if (nv_release_txskb(dev, &np->tx_skb[i]))
1509 np->stats.tx_dropped++;
1510 }
1511 }
1512
1513 static void nv_drain_rx(struct net_device *dev)
1514 {
1515 struct fe_priv *np = netdev_priv(dev);
1516 int i;
1517
1518 for (i = 0; i < np->rx_ring_size; i++) {
1519 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1520 np->rx_ring.orig[i].flaglen = 0;
1521 np->rx_ring.orig[i].buf = 0;
1522 } else {
1523 np->rx_ring.ex[i].flaglen = 0;
1524 np->rx_ring.ex[i].txvlan = 0;
1525 np->rx_ring.ex[i].bufhigh = 0;
1526 np->rx_ring.ex[i].buflow = 0;
1527 }
1528 wmb();
1529 if (np->rx_skb[i].skb) {
1530 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1531 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1532 PCI_DMA_FROMDEVICE);
1533 dev_kfree_skb(np->rx_skb[i].skb);
1534 np->rx_skb[i].skb = NULL;
1535 }
1536 }
1537 }
1538
1539 static void drain_ring(struct net_device *dev)
1540 {
1541 nv_drain_tx(dev);
1542 nv_drain_rx(dev);
1543 }
1544
1545 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1546 {
1547 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1548 }
1549
1550 /*
1551 * nv_start_xmit: dev->hard_start_xmit function
1552 * Called with netif_tx_lock held.
1553 */
1554 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1555 {
1556 struct fe_priv *np = netdev_priv(dev);
1557 u32 tx_flags = 0;
1558 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1559 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1560 unsigned int i;
1561 u32 offset = 0;
1562 u32 bcnt;
1563 u32 size = skb->len-skb->data_len;
1564 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1565 u32 empty_slots;
1566 struct ring_desc* put_tx;
1567 struct ring_desc* start_tx;
1568 struct ring_desc* prev_tx;
1569 struct nv_skb_map* prev_tx_ctx;
1570
1571 /* add fragments to entries count */
1572 for (i = 0; i < fragments; i++) {
1573 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1574 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1575 }
1576
1577 empty_slots = nv_get_empty_tx_slots(np);
1578 if (unlikely(empty_slots <= entries)) {
1579 spin_lock_irq(&np->lock);
1580 netif_stop_queue(dev);
1581 np->tx_stop = 1;
1582 spin_unlock_irq(&np->lock);
1583 return NETDEV_TX_BUSY;
1584 }
1585
1586 start_tx = put_tx = np->put_tx.orig;
1587
1588 /* setup the header buffer */
1589 do {
1590 prev_tx = put_tx;
1591 prev_tx_ctx = np->put_tx_ctx;
1592 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1593 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1594 PCI_DMA_TODEVICE);
1595 np->put_tx_ctx->dma_len = bcnt;
1596 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1597 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1598
1599 tx_flags = np->tx_flags;
1600 offset += bcnt;
1601 size -= bcnt;
1602 if (unlikely(put_tx++ == np->last_tx.orig))
1603 put_tx = np->first_tx.orig;
1604 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1605 np->put_tx_ctx = np->first_tx_ctx;
1606 } while (size);
1607
1608 /* setup the fragments */
1609 for (i = 0; i < fragments; i++) {
1610 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1611 u32 size = frag->size;
1612 offset = 0;
1613
1614 do {
1615 prev_tx = put_tx;
1616 prev_tx_ctx = np->put_tx_ctx;
1617 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1618 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1619 PCI_DMA_TODEVICE);
1620 np->put_tx_ctx->dma_len = bcnt;
1621 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1622 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1623
1624 offset += bcnt;
1625 size -= bcnt;
1626 if (unlikely(put_tx++ == np->last_tx.orig))
1627 put_tx = np->first_tx.orig;
1628 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1629 np->put_tx_ctx = np->first_tx_ctx;
1630 } while (size);
1631 }
1632
1633 /* set last fragment flag */
1634 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1635
1636 /* save skb in this slot's context area */
1637 prev_tx_ctx->skb = skb;
1638
1639 if (skb_is_gso(skb))
1640 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1641 else
1642 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1643 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1644
1645 spin_lock_irq(&np->lock);
1646
1647 /* set tx flags */
1648 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1649 np->put_tx.orig = put_tx;
1650
1651 spin_unlock_irq(&np->lock);
1652
1653 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1654 dev->name, entries, tx_flags_extra);
1655 {
1656 int j;
1657 for (j=0; j<64; j++) {
1658 if ((j%16) == 0)
1659 dprintk("\n%03x:", j);
1660 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1661 }
1662 dprintk("\n");
1663 }
1664
1665 dev->trans_start = jiffies;
1666 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1667 return NETDEV_TX_OK;
1668 }
1669
1670 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1671 {
1672 struct fe_priv *np = netdev_priv(dev);
1673 u32 tx_flags = 0;
1674 u32 tx_flags_extra;
1675 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1676 unsigned int i;
1677 u32 offset = 0;
1678 u32 bcnt;
1679 u32 size = skb->len-skb->data_len;
1680 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1681 u32 empty_slots;
1682 struct ring_desc_ex* put_tx;
1683 struct ring_desc_ex* start_tx;
1684 struct ring_desc_ex* prev_tx;
1685 struct nv_skb_map* prev_tx_ctx;
1686
1687 /* add fragments to entries count */
1688 for (i = 0; i < fragments; i++) {
1689 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1690 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1691 }
1692
1693 empty_slots = nv_get_empty_tx_slots(np);
1694 if (unlikely(empty_slots <= entries)) {
1695 spin_lock_irq(&np->lock);
1696 netif_stop_queue(dev);
1697 np->tx_stop = 1;
1698 spin_unlock_irq(&np->lock);
1699 return NETDEV_TX_BUSY;
1700 }
1701
1702 start_tx = put_tx = np->put_tx.ex;
1703
1704 /* setup the header buffer */
1705 do {
1706 prev_tx = put_tx;
1707 prev_tx_ctx = np->put_tx_ctx;
1708 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1709 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1710 PCI_DMA_TODEVICE);
1711 np->put_tx_ctx->dma_len = bcnt;
1712 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1713 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1714 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1715
1716 tx_flags = NV_TX2_VALID;
1717 offset += bcnt;
1718 size -= bcnt;
1719 if (unlikely(put_tx++ == np->last_tx.ex))
1720 put_tx = np->first_tx.ex;
1721 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1722 np->put_tx_ctx = np->first_tx_ctx;
1723 } while (size);
1724
1725 /* setup the fragments */
1726 for (i = 0; i < fragments; i++) {
1727 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1728 u32 size = frag->size;
1729 offset = 0;
1730
1731 do {
1732 prev_tx = put_tx;
1733 prev_tx_ctx = np->put_tx_ctx;
1734 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1735 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1736 PCI_DMA_TODEVICE);
1737 np->put_tx_ctx->dma_len = bcnt;
1738 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1739 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1740 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1741
1742 offset += bcnt;
1743 size -= bcnt;
1744 if (unlikely(put_tx++ == np->last_tx.ex))
1745 put_tx = np->first_tx.ex;
1746 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1747 np->put_tx_ctx = np->first_tx_ctx;
1748 } while (size);
1749 }
1750
1751 /* set last fragment flag */
1752 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1753
1754 /* save skb in this slot's context area */
1755 prev_tx_ctx->skb = skb;
1756
1757 if (skb_is_gso(skb))
1758 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1759 else
1760 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1761 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1762
1763 /* vlan tag */
1764 if (likely(!np->vlangrp)) {
1765 start_tx->txvlan = 0;
1766 } else {
1767 if (vlan_tx_tag_present(skb))
1768 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1769 else
1770 start_tx->txvlan = 0;
1771 }
1772
1773 spin_lock_irq(&np->lock);
1774
1775 /* set tx flags */
1776 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1777 np->put_tx.ex = put_tx;
1778
1779 spin_unlock_irq(&np->lock);
1780
1781 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
1782 dev->name, entries, tx_flags_extra);
1783 {
1784 int j;
1785 for (j=0; j<64; j++) {
1786 if ((j%16) == 0)
1787 dprintk("\n%03x:", j);
1788 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1789 }
1790 dprintk("\n");
1791 }
1792
1793 dev->trans_start = jiffies;
1794 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1795 return NETDEV_TX_OK;
1796 }
1797
1798 /*
1799 * nv_tx_done: check for completed packets, release the skbs.
1800 *
1801 * Caller must own np->lock.
1802 */
1803 static void nv_tx_done(struct net_device *dev)
1804 {
1805 struct fe_priv *np = netdev_priv(dev);
1806 u32 flags;
1807 struct ring_desc* orig_get_tx = np->get_tx.orig;
1808
1809 while ((np->get_tx.orig != np->put_tx.orig) &&
1810 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
1811
1812 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1813 dev->name, flags);
1814
1815 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1816 np->get_tx_ctx->dma_len,
1817 PCI_DMA_TODEVICE);
1818 np->get_tx_ctx->dma = 0;
1819
1820 if (np->desc_ver == DESC_VER_1) {
1821 if (flags & NV_TX_LASTPACKET) {
1822 if (flags & NV_TX_ERROR) {
1823 if (flags & NV_TX_UNDERFLOW)
1824 np->stats.tx_fifo_errors++;
1825 if (flags & NV_TX_CARRIERLOST)
1826 np->stats.tx_carrier_errors++;
1827 np->stats.tx_errors++;
1828 } else {
1829 np->stats.tx_packets++;
1830 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1831 }
1832 dev_kfree_skb_any(np->get_tx_ctx->skb);
1833 np->get_tx_ctx->skb = NULL;
1834 }
1835 } else {
1836 if (flags & NV_TX2_LASTPACKET) {
1837 if (flags & NV_TX2_ERROR) {
1838 if (flags & NV_TX2_UNDERFLOW)
1839 np->stats.tx_fifo_errors++;
1840 if (flags & NV_TX2_CARRIERLOST)
1841 np->stats.tx_carrier_errors++;
1842 np->stats.tx_errors++;
1843 } else {
1844 np->stats.tx_packets++;
1845 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1846 }
1847 dev_kfree_skb_any(np->get_tx_ctx->skb);
1848 np->get_tx_ctx->skb = NULL;
1849 }
1850 }
1851 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
1852 np->get_tx.orig = np->first_tx.orig;
1853 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1854 np->get_tx_ctx = np->first_tx_ctx;
1855 }
1856 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
1857 np->tx_stop = 0;
1858 netif_wake_queue(dev);
1859 }
1860 }
1861
1862 static void nv_tx_done_optimized(struct net_device *dev)
1863 {
1864 struct fe_priv *np = netdev_priv(dev);
1865 u32 flags;
1866 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
1867
1868 while ((np->get_tx.ex != np->put_tx.ex) &&
1869 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID)) {
1870
1871 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
1872 dev->name, flags);
1873
1874 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1875 np->get_tx_ctx->dma_len,
1876 PCI_DMA_TODEVICE);
1877 np->get_tx_ctx->dma = 0;
1878
1879 if (flags & NV_TX2_LASTPACKET) {
1880 if (flags & NV_TX2_ERROR) {
1881 if (flags & NV_TX2_UNDERFLOW)
1882 np->stats.tx_fifo_errors++;
1883 if (flags & NV_TX2_CARRIERLOST)
1884 np->stats.tx_carrier_errors++;
1885 np->stats.tx_errors++;
1886 } else {
1887 np->stats.tx_packets++;
1888 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1889 }
1890 dev_kfree_skb_any(np->get_tx_ctx->skb);
1891 np->get_tx_ctx->skb = NULL;
1892 }
1893 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
1894 np->get_tx.ex = np->first_tx.ex;
1895 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1896 np->get_tx_ctx = np->first_tx_ctx;
1897 }
1898 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
1899 np->tx_stop = 0;
1900 netif_wake_queue(dev);
1901 }
1902 }
1903
1904 /*
1905 * nv_tx_timeout: dev->tx_timeout function
1906 * Called with netif_tx_lock held.
1907 */
1908 static void nv_tx_timeout(struct net_device *dev)
1909 {
1910 struct fe_priv *np = netdev_priv(dev);
1911 u8 __iomem *base = get_hwbase(dev);
1912 u32 status;
1913
1914 if (np->msi_flags & NV_MSI_X_ENABLED)
1915 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1916 else
1917 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1918
1919 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1920
1921 {
1922 int i;
1923
1924 printk(KERN_INFO "%s: Ring at %lx\n",
1925 dev->name, (unsigned long)np->ring_addr);
1926 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1927 for (i=0;i<=np->register_size;i+= 32) {
1928 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1929 i,
1930 readl(base + i + 0), readl(base + i + 4),
1931 readl(base + i + 8), readl(base + i + 12),
1932 readl(base + i + 16), readl(base + i + 20),
1933 readl(base + i + 24), readl(base + i + 28));
1934 }
1935 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1936 for (i=0;i<np->tx_ring_size;i+= 4) {
1937 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1938 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1939 i,
1940 le32_to_cpu(np->tx_ring.orig[i].buf),
1941 le32_to_cpu(np->tx_ring.orig[i].flaglen),
1942 le32_to_cpu(np->tx_ring.orig[i+1].buf),
1943 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1944 le32_to_cpu(np->tx_ring.orig[i+2].buf),
1945 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1946 le32_to_cpu(np->tx_ring.orig[i+3].buf),
1947 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1948 } else {
1949 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1950 i,
1951 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1952 le32_to_cpu(np->tx_ring.ex[i].buflow),
1953 le32_to_cpu(np->tx_ring.ex[i].flaglen),
1954 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1955 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1956 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1957 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1958 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1959 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1960 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1961 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1962 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1963 }
1964 }
1965 }
1966
1967 spin_lock_irq(&np->lock);
1968
1969 /* 1) stop tx engine */
1970 nv_stop_tx(dev);
1971
1972 /* 2) check that the packets were not sent already: */
1973 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1974 nv_tx_done(dev);
1975 else
1976 nv_tx_done_optimized(dev);
1977
1978 /* 3) if there are dead entries: clear everything */
1979 if (np->get_tx_ctx != np->put_tx_ctx) {
1980 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1981 nv_drain_tx(dev);
1982 nv_init_tx(dev);
1983 setup_hw_rings(dev, NV_SETUP_TX_RING);
1984 netif_wake_queue(dev);
1985 }
1986
1987 /* 4) restart tx engine */
1988 nv_start_tx(dev);
1989 spin_unlock_irq(&np->lock);
1990 }
1991
1992 /*
1993 * Called when the nic notices a mismatch between the actual data len on the
1994 * wire and the len indicated in the 802 header
1995 */
1996 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1997 {
1998 int hdrlen; /* length of the 802 header */
1999 int protolen; /* length as stored in the proto field */
2000
2001 /* 1) calculate len according to header */
2002 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2003 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2004 hdrlen = VLAN_HLEN;
2005 } else {
2006 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2007 hdrlen = ETH_HLEN;
2008 }
2009 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2010 dev->name, datalen, protolen, hdrlen);
2011 if (protolen > ETH_DATA_LEN)
2012 return datalen; /* Value in proto field not a len, no checks possible */
2013
2014 protolen += hdrlen;
2015 /* consistency checks: */
2016 if (datalen > ETH_ZLEN) {
2017 if (datalen >= protolen) {
2018 /* more data on wire than in 802 header, trim of
2019 * additional data.
2020 */
2021 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2022 dev->name, protolen);
2023 return protolen;
2024 } else {
2025 /* less data on wire than mentioned in header.
2026 * Discard the packet.
2027 */
2028 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2029 dev->name);
2030 return -1;
2031 }
2032 } else {
2033 /* short packet. Accept only if 802 values are also short */
2034 if (protolen > ETH_ZLEN) {
2035 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2036 dev->name);
2037 return -1;
2038 }
2039 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2040 dev->name, datalen);
2041 return datalen;
2042 }
2043 }
2044
2045 static int nv_rx_process(struct net_device *dev, int limit)
2046 {
2047 struct fe_priv *np = netdev_priv(dev);
2048 u32 flags;
2049 u32 rx_processed_cnt = 0;
2050 struct sk_buff *skb;
2051 int len;
2052
2053 while((np->get_rx.orig != np->put_rx.orig) &&
2054 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2055 (rx_processed_cnt++ < limit)) {
2056
2057 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2058 dev->name, flags);
2059
2060 /*
2061 * the packet is for us - immediately tear down the pci mapping.
2062 * TODO: check if a prefetch of the first cacheline improves
2063 * the performance.
2064 */
2065 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2066 np->get_rx_ctx->dma_len,
2067 PCI_DMA_FROMDEVICE);
2068 skb = np->get_rx_ctx->skb;
2069 np->get_rx_ctx->skb = NULL;
2070
2071 {
2072 int j;
2073 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2074 for (j=0; j<64; j++) {
2075 if ((j%16) == 0)
2076 dprintk("\n%03x:", j);
2077 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2078 }
2079 dprintk("\n");
2080 }
2081 /* look at what we actually got: */
2082 if (np->desc_ver == DESC_VER_1) {
2083 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2084 len = flags & LEN_MASK_V1;
2085 if (unlikely(flags & NV_RX_ERROR)) {
2086 if (flags & NV_RX_ERROR4) {
2087 len = nv_getlen(dev, skb->data, len);
2088 if (len < 0) {
2089 np->stats.rx_errors++;
2090 dev_kfree_skb(skb);
2091 goto next_pkt;
2092 }
2093 }
2094 /* framing errors are soft errors */
2095 else if (flags & NV_RX_FRAMINGERR) {
2096 if (flags & NV_RX_SUBSTRACT1) {
2097 len--;
2098 }
2099 }
2100 /* the rest are hard errors */
2101 else {
2102 if (flags & NV_RX_MISSEDFRAME)
2103 np->stats.rx_missed_errors++;
2104 if (flags & NV_RX_CRCERR)
2105 np->stats.rx_crc_errors++;
2106 if (flags & NV_RX_OVERFLOW)
2107 np->stats.rx_over_errors++;
2108 np->stats.rx_errors++;
2109 dev_kfree_skb(skb);
2110 goto next_pkt;
2111 }
2112 }
2113 } else {
2114 dev_kfree_skb(skb);
2115 goto next_pkt;
2116 }
2117 } else {
2118 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2119 len = flags & LEN_MASK_V2;
2120 if (unlikely(flags & NV_RX2_ERROR)) {
2121 if (flags & NV_RX2_ERROR4) {
2122 len = nv_getlen(dev, skb->data, len);
2123 if (len < 0) {
2124 np->stats.rx_errors++;
2125 dev_kfree_skb(skb);
2126 goto next_pkt;
2127 }
2128 }
2129 /* framing errors are soft errors */
2130 else if (flags & NV_RX2_FRAMINGERR) {
2131 if (flags & NV_RX2_SUBSTRACT1) {
2132 len--;
2133 }
2134 }
2135 /* the rest are hard errors */
2136 else {
2137 if (flags & NV_RX2_CRCERR)
2138 np->stats.rx_crc_errors++;
2139 if (flags & NV_RX2_OVERFLOW)
2140 np->stats.rx_over_errors++;
2141 np->stats.rx_errors++;
2142 dev_kfree_skb(skb);
2143 goto next_pkt;
2144 }
2145 }
2146 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2147 skb->ip_summed = CHECKSUM_UNNECESSARY;
2148 } else {
2149 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2150 (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2151 skb->ip_summed = CHECKSUM_UNNECESSARY;
2152 }
2153 }
2154 } else {
2155 dev_kfree_skb(skb);
2156 goto next_pkt;
2157 }
2158 }
2159 /* got a valid packet - forward it to the network core */
2160 skb_put(skb, len);
2161 skb->protocol = eth_type_trans(skb, dev);
2162 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2163 dev->name, len, skb->protocol);
2164 #ifdef CONFIG_FORCEDETH_NAPI
2165 netif_receive_skb(skb);
2166 #else
2167 netif_rx(skb);
2168 #endif
2169 dev->last_rx = jiffies;
2170 np->stats.rx_packets++;
2171 np->stats.rx_bytes += len;
2172 next_pkt:
2173 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2174 np->get_rx.orig = np->first_rx.orig;
2175 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2176 np->get_rx_ctx = np->first_rx_ctx;
2177 }
2178
2179 return rx_processed_cnt;
2180 }
2181
2182 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2183 {
2184 struct fe_priv *np = netdev_priv(dev);
2185 u32 flags;
2186 u32 vlanflags = 0;
2187 u32 rx_processed_cnt = 0;
2188 struct sk_buff *skb;
2189 int len;
2190
2191 while((np->get_rx.ex != np->put_rx.ex) &&
2192 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2193 (rx_processed_cnt++ < limit)) {
2194
2195 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2196 dev->name, flags);
2197
2198 /*
2199 * the packet is for us - immediately tear down the pci mapping.
2200 * TODO: check if a prefetch of the first cacheline improves
2201 * the performance.
2202 */
2203 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2204 np->get_rx_ctx->dma_len,
2205 PCI_DMA_FROMDEVICE);
2206 skb = np->get_rx_ctx->skb;
2207 np->get_rx_ctx->skb = NULL;
2208
2209 {
2210 int j;
2211 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2212 for (j=0; j<64; j++) {
2213 if ((j%16) == 0)
2214 dprintk("\n%03x:", j);
2215 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2216 }
2217 dprintk("\n");
2218 }
2219 /* look at what we actually got: */
2220 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2221 len = flags & LEN_MASK_V2;
2222 if (unlikely(flags & NV_RX2_ERROR)) {
2223 if (flags & NV_RX2_ERROR4) {
2224 len = nv_getlen(dev, skb->data, len);
2225 if (len < 0) {
2226 np->stats.rx_errors++;
2227 dev_kfree_skb(skb);
2228 goto next_pkt;
2229 }
2230 }
2231 /* framing errors are soft errors */
2232 else if (flags & NV_RX2_FRAMINGERR) {
2233 if (flags & NV_RX2_SUBSTRACT1) {
2234 len--;
2235 }
2236 }
2237 /* the rest are hard errors */
2238 else {
2239 if (flags & NV_RX2_CRCERR)
2240 np->stats.rx_crc_errors++;
2241 if (flags & NV_RX2_OVERFLOW)
2242 np->stats.rx_over_errors++;
2243 np->stats.rx_errors++;
2244 dev_kfree_skb(skb);
2245 goto next_pkt;
2246 }
2247 }
2248
2249 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2250 skb->ip_summed = CHECKSUM_UNNECESSARY;
2251 } else {
2252 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2253 (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2254 skb->ip_summed = CHECKSUM_UNNECESSARY;
2255 }
2256 }
2257
2258 /* got a valid packet - forward it to the network core */
2259 skb_put(skb, len);
2260 skb->protocol = eth_type_trans(skb, dev);
2261 prefetch(skb->data);
2262
2263 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2264 dev->name, len, skb->protocol);
2265
2266 if (likely(!np->vlangrp)) {
2267 #ifdef CONFIG_FORCEDETH_NAPI
2268 netif_receive_skb(skb);
2269 #else
2270 netif_rx(skb);
2271 #endif
2272 } else {
2273 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2274 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2275 #ifdef CONFIG_FORCEDETH_NAPI
2276 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2277 vlanflags & NV_RX3_VLAN_TAG_MASK);
2278 #else
2279 vlan_hwaccel_rx(skb, np->vlangrp,
2280 vlanflags & NV_RX3_VLAN_TAG_MASK);
2281 #endif
2282 } else {
2283 #ifdef CONFIG_FORCEDETH_NAPI
2284 netif_receive_skb(skb);
2285 #else
2286 netif_rx(skb);
2287 #endif
2288 }
2289 }
2290
2291 dev->last_rx = jiffies;
2292 np->stats.rx_packets++;
2293 np->stats.rx_bytes += len;
2294 } else {
2295 dev_kfree_skb(skb);
2296 }
2297 next_pkt:
2298 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2299 np->get_rx.ex = np->first_rx.ex;
2300 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2301 np->get_rx_ctx = np->first_rx_ctx;
2302 }
2303
2304 return rx_processed_cnt;
2305 }
2306
2307 static void set_bufsize(struct net_device *dev)
2308 {
2309 struct fe_priv *np = netdev_priv(dev);
2310
2311 if (dev->mtu <= ETH_DATA_LEN)
2312 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2313 else
2314 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2315 }
2316
2317 /*
2318 * nv_change_mtu: dev->change_mtu function
2319 * Called with dev_base_lock held for read.
2320 */
2321 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2322 {
2323 struct fe_priv *np = netdev_priv(dev);
2324 int old_mtu;
2325
2326 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2327 return -EINVAL;
2328
2329 old_mtu = dev->mtu;
2330 dev->mtu = new_mtu;
2331
2332 /* return early if the buffer sizes will not change */
2333 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2334 return 0;
2335 if (old_mtu == new_mtu)
2336 return 0;
2337
2338 /* synchronized against open : rtnl_lock() held by caller */
2339 if (netif_running(dev)) {
2340 u8 __iomem *base = get_hwbase(dev);
2341 /*
2342 * It seems that the nic preloads valid ring entries into an
2343 * internal buffer. The procedure for flushing everything is
2344 * guessed, there is probably a simpler approach.
2345 * Changing the MTU is a rare event, it shouldn't matter.
2346 */
2347 nv_disable_irq(dev);
2348 netif_tx_lock_bh(dev);
2349 spin_lock(&np->lock);
2350 /* stop engines */
2351 nv_stop_rx(dev);
2352 nv_stop_tx(dev);
2353 nv_txrx_reset(dev);
2354 /* drain rx queue */
2355 nv_drain_rx(dev);
2356 nv_drain_tx(dev);
2357 /* reinit driver view of the rx queue */
2358 set_bufsize(dev);
2359 if (nv_init_ring(dev)) {
2360 if (!np->in_shutdown)
2361 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2362 }
2363 /* reinit nic view of the rx queue */
2364 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2365 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2366 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2367 base + NvRegRingSizes);
2368 pci_push(base);
2369 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2370 pci_push(base);
2371
2372 /* restart rx engine */
2373 nv_start_rx(dev);
2374 nv_start_tx(dev);
2375 spin_unlock(&np->lock);
2376 netif_tx_unlock_bh(dev);
2377 nv_enable_irq(dev);
2378 }
2379 return 0;
2380 }
2381
2382 static void nv_copy_mac_to_hw(struct net_device *dev)
2383 {
2384 u8 __iomem *base = get_hwbase(dev);
2385 u32 mac[2];
2386
2387 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2388 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2389 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2390
2391 writel(mac[0], base + NvRegMacAddrA);
2392 writel(mac[1], base + NvRegMacAddrB);
2393 }
2394
2395 /*
2396 * nv_set_mac_address: dev->set_mac_address function
2397 * Called with rtnl_lock() held.
2398 */
2399 static int nv_set_mac_address(struct net_device *dev, void *addr)
2400 {
2401 struct fe_priv *np = netdev_priv(dev);
2402 struct sockaddr *macaddr = (struct sockaddr*)addr;
2403
2404 if (!is_valid_ether_addr(macaddr->sa_data))
2405 return -EADDRNOTAVAIL;
2406
2407 /* synchronized against open : rtnl_lock() held by caller */
2408 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2409
2410 if (netif_running(dev)) {
2411 netif_tx_lock_bh(dev);
2412 spin_lock_irq(&np->lock);
2413
2414 /* stop rx engine */
2415 nv_stop_rx(dev);
2416
2417 /* set mac address */
2418 nv_copy_mac_to_hw(dev);
2419
2420 /* restart rx engine */
2421 nv_start_rx(dev);
2422 spin_unlock_irq(&np->lock);
2423 netif_tx_unlock_bh(dev);
2424 } else {
2425 nv_copy_mac_to_hw(dev);
2426 }
2427 return 0;
2428 }
2429
2430 /*
2431 * nv_set_multicast: dev->set_multicast function
2432 * Called with netif_tx_lock held.
2433 */
2434 static void nv_set_multicast(struct net_device *dev)
2435 {
2436 struct fe_priv *np = netdev_priv(dev);
2437 u8 __iomem *base = get_hwbase(dev);
2438 u32 addr[2];
2439 u32 mask[2];
2440 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2441
2442 memset(addr, 0, sizeof(addr));
2443 memset(mask, 0, sizeof(mask));
2444
2445 if (dev->flags & IFF_PROMISC) {
2446 pff |= NVREG_PFF_PROMISC;
2447 } else {
2448 pff |= NVREG_PFF_MYADDR;
2449
2450 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2451 u32 alwaysOff[2];
2452 u32 alwaysOn[2];
2453
2454 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2455 if (dev->flags & IFF_ALLMULTI) {
2456 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2457 } else {
2458 struct dev_mc_list *walk;
2459
2460 walk = dev->mc_list;
2461 while (walk != NULL) {
2462 u32 a, b;
2463 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2464 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2465 alwaysOn[0] &= a;
2466 alwaysOff[0] &= ~a;
2467 alwaysOn[1] &= b;
2468 alwaysOff[1] &= ~b;
2469 walk = walk->next;
2470 }
2471 }
2472 addr[0] = alwaysOn[0];
2473 addr[1] = alwaysOn[1];
2474 mask[0] = alwaysOn[0] | alwaysOff[0];
2475 mask[1] = alwaysOn[1] | alwaysOff[1];
2476 }
2477 }
2478 addr[0] |= NVREG_MCASTADDRA_FORCE;
2479 pff |= NVREG_PFF_ALWAYS;
2480 spin_lock_irq(&np->lock);
2481 nv_stop_rx(dev);
2482 writel(addr[0], base + NvRegMulticastAddrA);
2483 writel(addr[1], base + NvRegMulticastAddrB);
2484 writel(mask[0], base + NvRegMulticastMaskA);
2485 writel(mask[1], base + NvRegMulticastMaskB);
2486 writel(pff, base + NvRegPacketFilterFlags);
2487 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2488 dev->name);
2489 nv_start_rx(dev);
2490 spin_unlock_irq(&np->lock);
2491 }
2492
2493 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2494 {
2495 struct fe_priv *np = netdev_priv(dev);
2496 u8 __iomem *base = get_hwbase(dev);
2497
2498 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2499
2500 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2501 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2502 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2503 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2504 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2505 } else {
2506 writel(pff, base + NvRegPacketFilterFlags);
2507 }
2508 }
2509 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2510 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2511 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2512 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2513 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2514 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2515 } else {
2516 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2517 writel(regmisc, base + NvRegMisc1);
2518 }
2519 }
2520 }
2521
2522 /**
2523 * nv_update_linkspeed: Setup the MAC according to the link partner
2524 * @dev: Network device to be configured
2525 *
2526 * The function queries the PHY and checks if there is a link partner.
2527 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2528 * set to 10 MBit HD.
2529 *
2530 * The function returns 0 if there is no link partner and 1 if there is
2531 * a good link partner.
2532 */
2533 static int nv_update_linkspeed(struct net_device *dev)
2534 {
2535 struct fe_priv *np = netdev_priv(dev);
2536 u8 __iomem *base = get_hwbase(dev);
2537 int adv = 0;
2538 int lpa = 0;
2539 int adv_lpa, adv_pause, lpa_pause;
2540 int newls = np->linkspeed;
2541 int newdup = np->duplex;
2542 int mii_status;
2543 int retval = 0;
2544 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2545
2546 /* BMSR_LSTATUS is latched, read it twice:
2547 * we want the current value.
2548 */
2549 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2550 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2551
2552 if (!(mii_status & BMSR_LSTATUS)) {
2553 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2554 dev->name);
2555 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2556 newdup = 0;
2557 retval = 0;
2558 goto set_speed;
2559 }
2560
2561 if (np->autoneg == 0) {
2562 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2563 dev->name, np->fixed_mode);
2564 if (np->fixed_mode & LPA_100FULL) {
2565 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2566 newdup = 1;
2567 } else if (np->fixed_mode & LPA_100HALF) {
2568 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2569 newdup = 0;
2570 } else if (np->fixed_mode & LPA_10FULL) {
2571 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2572 newdup = 1;
2573 } else {
2574 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2575 newdup = 0;
2576 }
2577 retval = 1;
2578 goto set_speed;
2579 }
2580 /* check auto negotiation is complete */
2581 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2582 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2583 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2584 newdup = 0;
2585 retval = 0;
2586 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2587 goto set_speed;
2588 }
2589
2590 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2591 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2592 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2593 dev->name, adv, lpa);
2594
2595 retval = 1;
2596 if (np->gigabit == PHY_GIGABIT) {
2597 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2598 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2599
2600 if ((control_1000 & ADVERTISE_1000FULL) &&
2601 (status_1000 & LPA_1000FULL)) {
2602 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2603 dev->name);
2604 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2605 newdup = 1;
2606 goto set_speed;
2607 }
2608 }
2609
2610 /* FIXME: handle parallel detection properly */
2611 adv_lpa = lpa & adv;
2612 if (adv_lpa & LPA_100FULL) {
2613 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2614 newdup = 1;
2615 } else if (adv_lpa & LPA_100HALF) {
2616 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2617 newdup = 0;
2618 } else if (adv_lpa & LPA_10FULL) {
2619 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2620 newdup = 1;
2621 } else if (adv_lpa & LPA_10HALF) {
2622 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2623 newdup = 0;
2624 } else {
2625 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2626 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2627 newdup = 0;
2628 }
2629
2630 set_speed:
2631 if (np->duplex == newdup && np->linkspeed == newls)
2632 return retval;
2633
2634 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2635 dev->name, np->linkspeed, np->duplex, newls, newdup);
2636
2637 np->duplex = newdup;
2638 np->linkspeed = newls;
2639
2640 if (np->gigabit == PHY_GIGABIT) {
2641 phyreg = readl(base + NvRegRandomSeed);
2642 phyreg &= ~(0x3FF00);
2643 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2644 phyreg |= NVREG_RNDSEED_FORCE3;
2645 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2646 phyreg |= NVREG_RNDSEED_FORCE2;
2647 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2648 phyreg |= NVREG_RNDSEED_FORCE;
2649 writel(phyreg, base + NvRegRandomSeed);
2650 }
2651
2652 phyreg = readl(base + NvRegPhyInterface);
2653 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2654 if (np->duplex == 0)
2655 phyreg |= PHY_HALF;
2656 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2657 phyreg |= PHY_100;
2658 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2659 phyreg |= PHY_1000;
2660 writel(phyreg, base + NvRegPhyInterface);
2661
2662 if (phyreg & PHY_RGMII) {
2663 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2664 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2665 else
2666 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2667 } else {
2668 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2669 }
2670 writel(txreg, base + NvRegTxDeferral);
2671
2672 if (np->desc_ver == DESC_VER_1) {
2673 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2674 } else {
2675 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2676 txreg = NVREG_TX_WM_DESC2_3_1000;
2677 else
2678 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2679 }
2680 writel(txreg, base + NvRegTxWatermark);
2681
2682 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2683 base + NvRegMisc1);
2684 pci_push(base);
2685 writel(np->linkspeed, base + NvRegLinkSpeed);
2686 pci_push(base);
2687
2688 pause_flags = 0;
2689 /* setup pause frame */
2690 if (np->duplex != 0) {
2691 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2692 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2693 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2694
2695 switch (adv_pause) {
2696 case ADVERTISE_PAUSE_CAP:
2697 if (lpa_pause & LPA_PAUSE_CAP) {
2698 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2699 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2700 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2701 }
2702 break;
2703 case ADVERTISE_PAUSE_ASYM:
2704 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2705 {
2706 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2707 }
2708 break;
2709 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2710 if (lpa_pause & LPA_PAUSE_CAP)
2711 {
2712 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2713 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2714 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2715 }
2716 if (lpa_pause == LPA_PAUSE_ASYM)
2717 {
2718 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2719 }
2720 break;
2721 }
2722 } else {
2723 pause_flags = np->pause_flags;
2724 }
2725 }
2726 nv_update_pause(dev, pause_flags);
2727
2728 return retval;
2729 }
2730
2731 static void nv_linkchange(struct net_device *dev)
2732 {
2733 if (nv_update_linkspeed(dev)) {
2734 if (!netif_carrier_ok(dev)) {
2735 netif_carrier_on(dev);
2736 printk(KERN_INFO "%s: link up.\n", dev->name);
2737 nv_start_rx(dev);
2738 }
2739 } else {
2740 if (netif_carrier_ok(dev)) {
2741 netif_carrier_off(dev);
2742 printk(KERN_INFO "%s: link down.\n", dev->name);
2743 nv_stop_rx(dev);
2744 }
2745 }
2746 }
2747
2748 static void nv_link_irq(struct net_device *dev)
2749 {
2750 u8 __iomem *base = get_hwbase(dev);
2751 u32 miistat;
2752
2753 miistat = readl(base + NvRegMIIStatus);
2754 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2755 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2756
2757 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2758 nv_linkchange(dev);
2759 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2760 }
2761
2762 static irqreturn_t nv_nic_irq(int foo, void *data)
2763 {
2764 struct net_device *dev = (struct net_device *) data;
2765 struct fe_priv *np = netdev_priv(dev);
2766 u8 __iomem *base = get_hwbase(dev);
2767 u32 events;
2768 int i;
2769
2770 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2771
2772 for (i=0; ; i++) {
2773 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2774 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2775 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2776 } else {
2777 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2778 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2779 }
2780 pci_push(base);
2781 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2782 if (!(events & np->irqmask))
2783 break;
2784
2785 spin_lock(&np->lock);
2786 nv_tx_done(dev);
2787 spin_unlock(&np->lock);
2788
2789 if (events & NVREG_IRQ_LINK) {
2790 spin_lock(&np->lock);
2791 nv_link_irq(dev);
2792 spin_unlock(&np->lock);
2793 }
2794 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2795 spin_lock(&np->lock);
2796 nv_linkchange(dev);
2797 spin_unlock(&np->lock);
2798 np->link_timeout = jiffies + LINK_TIMEOUT;
2799 }
2800 if (events & (NVREG_IRQ_TX_ERR)) {
2801 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2802 dev->name, events);
2803 }
2804 if (events & (NVREG_IRQ_UNKNOWN)) {
2805 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2806 dev->name, events);
2807 }
2808 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2809 spin_lock(&np->lock);
2810 /* disable interrupts on the nic */
2811 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2812 writel(0, base + NvRegIrqMask);
2813 else
2814 writel(np->irqmask, base + NvRegIrqMask);
2815 pci_push(base);
2816
2817 if (!np->in_shutdown) {
2818 np->nic_poll_irq = np->irqmask;
2819 np->recover_error = 1;
2820 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2821 }
2822 spin_unlock(&np->lock);
2823 break;
2824 }
2825 #ifdef CONFIG_FORCEDETH_NAPI
2826 if (events & NVREG_IRQ_RX_ALL) {
2827 netif_rx_schedule(dev);
2828
2829 /* Disable furthur receive irq's */
2830 spin_lock(&np->lock);
2831 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2832
2833 if (np->msi_flags & NV_MSI_X_ENABLED)
2834 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2835 else
2836 writel(np->irqmask, base + NvRegIrqMask);
2837 spin_unlock(&np->lock);
2838 }
2839 #else
2840 nv_rx_process(dev, dev->weight);
2841 if (nv_alloc_rx(dev)) {
2842 spin_lock(&np->lock);
2843 if (!np->in_shutdown)
2844 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2845 spin_unlock(&np->lock);
2846 }
2847 #endif
2848 if (i > max_interrupt_work) {
2849 spin_lock(&np->lock);
2850 /* disable interrupts on the nic */
2851 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2852 writel(0, base + NvRegIrqMask);
2853 else
2854 writel(np->irqmask, base + NvRegIrqMask);
2855 pci_push(base);
2856
2857 if (!np->in_shutdown) {
2858 np->nic_poll_irq = np->irqmask;
2859 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2860 }
2861 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2862 spin_unlock(&np->lock);
2863 break;
2864 }
2865
2866 }
2867 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2868
2869 return IRQ_RETVAL(i);
2870 }
2871
2872 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
2873 {
2874 struct net_device *dev = (struct net_device *) data;
2875 struct fe_priv *np = netdev_priv(dev);
2876 u8 __iomem *base = get_hwbase(dev);
2877 u32 events;
2878 int i;
2879
2880 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
2881
2882 for (i=0; ; i++) {
2883 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2884 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2885 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2886 } else {
2887 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2888 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2889 }
2890 pci_push(base);
2891 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2892 if (!(events & np->irqmask))
2893 break;
2894
2895 spin_lock(&np->lock);
2896 nv_tx_done_optimized(dev);
2897 spin_unlock(&np->lock);
2898
2899 if (events & NVREG_IRQ_LINK) {
2900 spin_lock(&np->lock);
2901 nv_link_irq(dev);
2902 spin_unlock(&np->lock);
2903 }
2904 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2905 spin_lock(&np->lock);
2906 nv_linkchange(dev);
2907 spin_unlock(&np->lock);
2908 np->link_timeout = jiffies + LINK_TIMEOUT;
2909 }
2910 if (events & (NVREG_IRQ_TX_ERR)) {
2911 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2912 dev->name, events);
2913 }
2914 if (events & (NVREG_IRQ_UNKNOWN)) {
2915 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2916 dev->name, events);
2917 }
2918 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2919 spin_lock(&np->lock);
2920 /* disable interrupts on the nic */
2921 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2922 writel(0, base + NvRegIrqMask);
2923 else
2924 writel(np->irqmask, base + NvRegIrqMask);
2925 pci_push(base);
2926
2927 if (!np->in_shutdown) {
2928 np->nic_poll_irq = np->irqmask;
2929 np->recover_error = 1;
2930 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2931 }
2932 spin_unlock(&np->lock);
2933 break;
2934 }
2935
2936 #ifdef CONFIG_FORCEDETH_NAPI
2937 if (events & NVREG_IRQ_RX_ALL) {
2938 netif_rx_schedule(dev);
2939
2940 /* Disable furthur receive irq's */
2941 spin_lock(&np->lock);
2942 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2943
2944 if (np->msi_flags & NV_MSI_X_ENABLED)
2945 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2946 else
2947 writel(np->irqmask, base + NvRegIrqMask);
2948 spin_unlock(&np->lock);
2949 }
2950 #else
2951 nv_rx_process_optimized(dev, dev->weight);
2952 if (nv_alloc_rx_optimized(dev)) {
2953 spin_lock(&np->lock);
2954 if (!np->in_shutdown)
2955 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2956 spin_unlock(&np->lock);
2957 }
2958 #endif
2959 if (i > max_interrupt_work) {
2960 spin_lock(&np->lock);
2961 /* disable interrupts on the nic */
2962 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2963 writel(0, base + NvRegIrqMask);
2964 else
2965 writel(np->irqmask, base + NvRegIrqMask);
2966 pci_push(base);
2967
2968 if (!np->in_shutdown) {
2969 np->nic_poll_irq = np->irqmask;
2970 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2971 }
2972 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2973 spin_unlock(&np->lock);
2974 break;
2975 }
2976
2977 }
2978 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
2979
2980 return IRQ_RETVAL(i);
2981 }
2982
2983 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2984 {
2985 struct net_device *dev = (struct net_device *) data;
2986 struct fe_priv *np = netdev_priv(dev);
2987 u8 __iomem *base = get_hwbase(dev);
2988 u32 events;
2989 int i;
2990 unsigned long flags;
2991
2992 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2993
2994 for (i=0; ; i++) {
2995 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2996 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2997 pci_push(base);
2998 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2999 if (!(events & np->irqmask))
3000 break;
3001
3002 spin_lock_irqsave(&np->lock, flags);
3003 nv_tx_done_optimized(dev);
3004 spin_unlock_irqrestore(&np->lock, flags);
3005
3006 if (events & (NVREG_IRQ_TX_ERR)) {
3007 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3008 dev->name, events);
3009 }
3010 if (i > max_interrupt_work) {
3011 spin_lock_irqsave(&np->lock, flags);
3012 /* disable interrupts on the nic */
3013 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3014 pci_push(base);
3015
3016 if (!np->in_shutdown) {
3017 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3018 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3019 }
3020 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3021 spin_unlock_irqrestore(&np->lock, flags);
3022 break;
3023 }
3024
3025 }
3026 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3027
3028 return IRQ_RETVAL(i);
3029 }
3030
3031 #ifdef CONFIG_FORCEDETH_NAPI
3032 static int nv_napi_poll(struct net_device *dev, int *budget)
3033 {
3034 int pkts, limit = min(*budget, dev->quota);
3035 struct fe_priv *np = netdev_priv(dev);
3036 u8 __iomem *base = get_hwbase(dev);
3037 unsigned long flags;
3038
3039 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
3040 pkts = nv_rx_process(dev, limit);
3041 else
3042 pkts = nv_rx_process_optimized(dev, limit);
3043
3044 if (nv_alloc_rx(dev)) {
3045 spin_lock_irqsave(&np->lock, flags);
3046 if (!np->in_shutdown)
3047 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3048 spin_unlock_irqrestore(&np->lock, flags);
3049 }
3050
3051 if (pkts < limit) {
3052 /* all done, no more packets present */
3053 netif_rx_complete(dev);
3054
3055 /* re-enable receive interrupts */
3056 spin_lock_irqsave(&np->lock, flags);
3057
3058 np->irqmask |= NVREG_IRQ_RX_ALL;
3059 if (np->msi_flags & NV_MSI_X_ENABLED)
3060 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3061 else
3062 writel(np->irqmask, base + NvRegIrqMask);
3063
3064 spin_unlock_irqrestore(&np->lock, flags);
3065 return 0;
3066 } else {
3067 /* used up our quantum, so reschedule */
3068 dev->quota -= pkts;
3069 *budget -= pkts;
3070 return 1;
3071 }
3072 }
3073 #endif
3074
3075 #ifdef CONFIG_FORCEDETH_NAPI
3076 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3077 {
3078 struct net_device *dev = (struct net_device *) data;
3079 u8 __iomem *base = get_hwbase(dev);
3080 u32 events;
3081
3082 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3083 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3084
3085 if (events) {
3086 netif_rx_schedule(dev);
3087 /* disable receive interrupts on the nic */
3088 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3089 pci_push(base);
3090 }
3091 return IRQ_HANDLED;
3092 }
3093 #else
3094 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3095 {
3096 struct net_device *dev = (struct net_device *) data;
3097 struct fe_priv *np = netdev_priv(dev);
3098 u8 __iomem *base = get_hwbase(dev);
3099 u32 events;
3100 int i;
3101 unsigned long flags;
3102
3103 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3104
3105 for (i=0; ; i++) {
3106 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3107 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3108 pci_push(base);
3109 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3110 if (!(events & np->irqmask))
3111 break;
3112
3113 nv_rx_process_optimized(dev, dev->weight);
3114 if (nv_alloc_rx_optimized(dev)) {
3115 spin_lock_irqsave(&np->lock, flags);
3116 if (!np->in_shutdown)
3117 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3118 spin_unlock_irqrestore(&np->lock, flags);
3119 }
3120
3121 if (i > max_interrupt_work) {
3122 spin_lock_irqsave(&np->lock, flags);
3123 /* disable interrupts on the nic */
3124 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3125 pci_push(base);
3126
3127 if (!np->in_shutdown) {
3128 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3129 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3130 }
3131 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3132 spin_unlock_irqrestore(&np->lock, flags);
3133 break;
3134 }
3135 }
3136 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3137
3138 return IRQ_RETVAL(i);
3139 }
3140 #endif
3141
3142 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3143 {
3144 struct net_device *dev = (struct net_device *) data;
3145 struct fe_priv *np = netdev_priv(dev);
3146 u8 __iomem *base = get_hwbase(dev);
3147 u32 events;
3148 int i;
3149 unsigned long flags;
3150
3151 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3152
3153 for (i=0; ; i++) {
3154 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3155 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3156 pci_push(base);
3157 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3158 if (!(events & np->irqmask))
3159 break;
3160
3161 if (events & NVREG_IRQ_LINK) {
3162 spin_lock_irqsave(&np->lock, flags);
3163 nv_link_irq(dev);
3164 spin_unlock_irqrestore(&np->lock, flags);
3165 }
3166 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3167 spin_lock_irqsave(&np->lock, flags);
3168 nv_linkchange(dev);
3169 spin_unlock_irqrestore(&np->lock, flags);
3170 np->link_timeout = jiffies + LINK_TIMEOUT;
3171 }
3172 if (events & NVREG_IRQ_RECOVER_ERROR) {
3173 spin_lock_irq(&np->lock);
3174 /* disable interrupts on the nic */
3175 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3176 pci_push(base);
3177
3178 if (!np->in_shutdown) {
3179 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3180 np->recover_error = 1;
3181 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3182 }
3183 spin_unlock_irq(&np->lock);
3184 break;
3185 }
3186 if (events & (NVREG_IRQ_UNKNOWN)) {
3187 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3188 dev->name, events);
3189 }
3190 if (i > max_interrupt_work) {
3191 spin_lock_irqsave(&np->lock, flags);
3192 /* disable interrupts on the nic */
3193 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3194 pci_push(base);
3195
3196 if (!np->in_shutdown) {
3197 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3198 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3199 }
3200 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3201 spin_unlock_irqrestore(&np->lock, flags);
3202 break;
3203 }
3204
3205 }
3206 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3207
3208 return IRQ_RETVAL(i);
3209 }
3210
3211 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3212 {
3213 struct net_device *dev = (struct net_device *) data;
3214 struct fe_priv *np = netdev_priv(dev);
3215 u8 __iomem *base = get_hwbase(dev);
3216 u32 events;
3217
3218 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3219
3220 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3221 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3222 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3223 } else {
3224 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3225 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3226 }
3227 pci_push(base);
3228 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3229 if (!(events & NVREG_IRQ_TIMER))
3230 return IRQ_RETVAL(0);
3231
3232 spin_lock(&np->lock);
3233 np->intr_test = 1;
3234 spin_unlock(&np->lock);
3235
3236 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3237
3238 return IRQ_RETVAL(1);
3239 }
3240
3241 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3242 {
3243 u8 __iomem *base = get_hwbase(dev);
3244 int i;
3245 u32 msixmap = 0;
3246
3247 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3248 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3249 * the remaining 8 interrupts.
3250 */
3251 for (i = 0; i < 8; i++) {
3252 if ((irqmask >> i) & 0x1) {
3253 msixmap |= vector << (i << 2);
3254 }
3255 }
3256 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3257
3258 msixmap = 0;
3259 for (i = 0; i < 8; i++) {
3260 if ((irqmask >> (i + 8)) & 0x1) {
3261 msixmap |= vector << (i << 2);
3262 }
3263 }
3264 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3265 }
3266
3267 static int nv_request_irq(struct net_device *dev, int intr_test)
3268 {
3269 struct fe_priv *np = get_nvpriv(dev);
3270 u8 __iomem *base = get_hwbase(dev);
3271 int ret = 1;
3272 int i;
3273 irqreturn_t (*handler)(int foo, void *data);
3274
3275 if (intr_test) {
3276 handler = nv_nic_irq_test;
3277 } else {
3278 if (np->desc_ver == DESC_VER_3)
3279 handler = nv_nic_irq_optimized;
3280 else
3281 handler = nv_nic_irq;
3282 }
3283
3284 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3285 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3286 np->msi_x_entry[i].entry = i;
3287 }
3288 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3289 np->msi_flags |= NV_MSI_X_ENABLED;
3290 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3291 /* Request irq for rx handling */
3292 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3293 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3294 pci_disable_msix(np->pci_dev);
3295 np->msi_flags &= ~NV_MSI_X_ENABLED;
3296 goto out_err;
3297 }
3298 /* Request irq for tx handling */
3299 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3300 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3301 pci_disable_msix(np->pci_dev);
3302 np->msi_flags &= ~NV_MSI_X_ENABLED;
3303 goto out_free_rx;
3304 }
3305 /* Request irq for link and timer handling */
3306 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3307 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3308 pci_disable_msix(np->pci_dev);
3309 np->msi_flags &= ~NV_MSI_X_ENABLED;
3310 goto out_free_tx;
3311 }
3312 /* map interrupts to their respective vector */
3313 writel(0, base + NvRegMSIXMap0);
3314 writel(0, base + NvRegMSIXMap1);
3315 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3316 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3317 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3318 } else {
3319 /* Request irq for all interrupts */
3320 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3321 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3322 pci_disable_msix(np->pci_dev);
3323 np->msi_flags &= ~NV_MSI_X_ENABLED;
3324 goto out_err;
3325 }
3326
3327 /* map interrupts to vector 0 */
3328 writel(0, base + NvRegMSIXMap0);
3329 writel(0, base + NvRegMSIXMap1);
3330 }
3331 }
3332 }
3333 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3334 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3335 np->msi_flags |= NV_MSI_ENABLED;
3336 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3337 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3338 pci_disable_msi(np->pci_dev);
3339 np->msi_flags &= ~NV_MSI_ENABLED;
3340 goto out_err;
3341 }
3342
3343 /* map interrupts to vector 0 */
3344 writel(0, base + NvRegMSIMap0);
3345 writel(0, base + NvRegMSIMap1);
3346 /* enable msi vector 0 */
3347 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3348 }
3349 }
3350 if (ret != 0) {
3351 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3352 goto out_err;
3353
3354 }
3355
3356 return 0;
3357 out_free_tx:
3358 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3359 out_free_rx:
3360 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3361 out_err:
3362 return 1;
3363 }
3364
3365 static void nv_free_irq(struct net_device *dev)
3366 {
3367 struct fe_priv *np = get_nvpriv(dev);
3368 int i;
3369
3370 if (np->msi_flags & NV_MSI_X_ENABLED) {
3371 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3372 free_irq(np->msi_x_entry[i].vector, dev);
3373 }
3374 pci_disable_msix(np->pci_dev);
3375 np->msi_flags &= ~NV_MSI_X_ENABLED;
3376 } else {
3377 free_irq(np->pci_dev->irq, dev);
3378 if (np->msi_flags & NV_MSI_ENABLED) {
3379 pci_disable_msi(np->pci_dev);
3380 np->msi_flags &= ~NV_MSI_ENABLED;
3381 }
3382 }
3383 }
3384
3385 static void nv_do_nic_poll(unsigned long data)
3386 {
3387 struct net_device *dev = (struct net_device *) data;
3388 struct fe_priv *np = netdev_priv(dev);
3389 u8 __iomem *base = get_hwbase(dev);
3390 u32 mask = 0;
3391
3392 /*
3393 * First disable irq(s) and then
3394 * reenable interrupts on the nic, we have to do this before calling
3395 * nv_nic_irq because that may decide to do otherwise
3396 */
3397
3398 if (!using_multi_irqs(dev)) {
3399 if (np->msi_flags & NV_MSI_X_ENABLED)
3400 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3401 else
3402 disable_irq_lockdep(dev->irq);
3403 mask = np->irqmask;
3404 } else {
3405 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3406 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3407 mask |= NVREG_IRQ_RX_ALL;
3408 }
3409 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3410 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3411 mask |= NVREG_IRQ_TX_ALL;
3412 }
3413 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3414 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3415 mask |= NVREG_IRQ_OTHER;
3416 }
3417 }
3418 np->nic_poll_irq = 0;
3419
3420 if (np->recover_error) {
3421 np->recover_error = 0;
3422 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3423 if (netif_running(dev)) {
3424 netif_tx_lock_bh(dev);
3425 spin_lock(&np->lock);
3426 /* stop engines */
3427 nv_stop_rx(dev);
3428 nv_stop_tx(dev);
3429 nv_txrx_reset(dev);
3430 /* drain rx queue */
3431 nv_drain_rx(dev);
3432 nv_drain_tx(dev);
3433 /* reinit driver view of the rx queue */
3434 set_bufsize(dev);
3435 if (nv_init_ring(dev)) {
3436 if (!np->in_shutdown)
3437 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3438 }
3439 /* reinit nic view of the rx queue */
3440 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3441 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3442 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3443 base + NvRegRingSizes);
3444 pci_push(base);
3445 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3446 pci_push(base);
3447
3448 /* restart rx engine */
3449 nv_start_rx(dev);
3450 nv_start_tx(dev);
3451 spin_unlock(&np->lock);
3452 netif_tx_unlock_bh(dev);
3453 }
3454 }
3455
3456 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3457
3458 writel(mask, base + NvRegIrqMask);
3459 pci_push(base);
3460
3461 if (!using_multi_irqs(dev)) {
3462 nv_nic_irq(0, dev);
3463 if (np->msi_flags & NV_MSI_X_ENABLED)
3464 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3465 else
3466 enable_irq_lockdep(dev->irq);
3467 } else {
3468 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3469 nv_nic_irq_rx(0, dev);
3470 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3471 }
3472 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3473 nv_nic_irq_tx(0, dev);
3474 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3475 }
3476 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3477 nv_nic_irq_other(0, dev);
3478 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3479 }
3480 }
3481 }
3482
3483 #ifdef CONFIG_NET_POLL_CONTROLLER
3484 static void nv_poll_controller(struct net_device *dev)
3485 {
3486 nv_do_nic_poll((unsigned long) dev);
3487 }
3488 #endif
3489
3490 static void nv_do_stats_poll(unsigned long data)
3491 {
3492 struct net_device *dev = (struct net_device *) data;
3493 struct fe_priv *np = netdev_priv(dev);
3494 u8 __iomem *base = get_hwbase(dev);
3495
3496 np->estats.tx_bytes += readl(base + NvRegTxCnt);
3497 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
3498 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
3499 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
3500 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
3501 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
3502 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
3503 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
3504 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
3505 np->estats.tx_deferral += readl(base + NvRegTxDef);
3506 np->estats.tx_packets += readl(base + NvRegTxFrame);
3507 np->estats.tx_pause += readl(base + NvRegTxPause);
3508 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
3509 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
3510 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
3511 np->estats.rx_runt += readl(base + NvRegRxRunt);
3512 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
3513 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
3514 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
3515 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
3516 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
3517 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
3518 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
3519 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
3520 np->estats.rx_bytes += readl(base + NvRegRxCnt);
3521 np->estats.rx_pause += readl(base + NvRegRxPause);
3522 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
3523 np->estats.rx_packets =
3524 np->estats.rx_unicast +
3525 np->estats.rx_multicast +
3526 np->estats.rx_broadcast;
3527 np->estats.rx_errors_total =
3528 np->estats.rx_crc_errors +
3529 np->estats.rx_over_errors +
3530 np->estats.rx_frame_error +
3531 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
3532 np->estats.rx_late_collision +
3533 np->estats.rx_runt +
3534 np->estats.rx_frame_too_long;
3535
3536 if (!np->in_shutdown)
3537 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3538 }
3539
3540 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3541 {
3542 struct fe_priv *np = netdev_priv(dev);
3543 strcpy(info->driver, "forcedeth");
3544 strcpy(info->version, FORCEDETH_VERSION);
3545 strcpy(info->bus_info, pci_name(np->pci_dev));
3546 }
3547
3548 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3549 {
3550 struct fe_priv *np = netdev_priv(dev);
3551 wolinfo->supported = WAKE_MAGIC;
3552
3553 spin_lock_irq(&np->lock);
3554 if (np->wolenabled)
3555 wolinfo->wolopts = WAKE_MAGIC;
3556 spin_unlock_irq(&np->lock);
3557 }
3558
3559 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3560 {
3561 struct fe_priv *np = netdev_priv(dev);
3562 u8 __iomem *base = get_hwbase(dev);
3563 u32 flags = 0;
3564
3565 if (wolinfo->wolopts == 0) {
3566 np->wolenabled = 0;
3567 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3568 np->wolenabled = 1;
3569 flags = NVREG_WAKEUPFLAGS_ENABLE;
3570 }
3571 if (netif_running(dev)) {
3572 spin_lock_irq(&np->lock);
3573 writel(flags, base + NvRegWakeUpFlags);
3574 spin_unlock_irq(&np->lock);
3575 }
3576 return 0;
3577 }
3578
3579 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3580 {
3581 struct fe_priv *np = netdev_priv(dev);
3582 int adv;
3583
3584 spin_lock_irq(&np->lock);
3585 ecmd->port = PORT_MII;
3586 if (!netif_running(dev)) {
3587 /* We do not track link speed / duplex setting if the
3588 * interface is disabled. Force a link check */
3589 if (nv_update_linkspeed(dev)) {
3590 if (!netif_carrier_ok(dev))
3591 netif_carrier_on(dev);
3592 } else {
3593 if (netif_carrier_ok(dev))
3594 netif_carrier_off(dev);
3595 }
3596 }
3597
3598 if (netif_carrier_ok(dev)) {
3599 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3600 case NVREG_LINKSPEED_10:
3601 ecmd->speed = SPEED_10;
3602 break;
3603 case NVREG_LINKSPEED_100:
3604 ecmd->speed = SPEED_100;
3605 break;
3606 case NVREG_LINKSPEED_1000:
3607 ecmd->speed = SPEED_1000;
3608 break;
3609 }
3610 ecmd->duplex = DUPLEX_HALF;
3611 if (np->duplex)
3612 ecmd->duplex = DUPLEX_FULL;
3613 } else {
3614 ecmd->speed = -1;
3615 ecmd->duplex = -1;
3616 }
3617
3618 ecmd->autoneg = np->autoneg;
3619
3620 ecmd->advertising = ADVERTISED_MII;
3621 if (np->autoneg) {
3622 ecmd->advertising |= ADVERTISED_Autoneg;
3623 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3624 if (adv & ADVERTISE_10HALF)
3625 ecmd->advertising |= ADVERTISED_10baseT_Half;
3626 if (adv & ADVERTISE_10FULL)
3627 ecmd->advertising |= ADVERTISED_10baseT_Full;
3628 if (adv & ADVERTISE_100HALF)
3629 ecmd->advertising |= ADVERTISED_100baseT_Half;
3630 if (adv & ADVERTISE_100FULL)
3631 ecmd->advertising |= ADVERTISED_100baseT_Full;
3632 if (np->gigabit == PHY_GIGABIT) {
3633 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3634 if (adv & ADVERTISE_1000FULL)
3635 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3636 }
3637 }
3638 ecmd->supported = (SUPPORTED_Autoneg |
3639 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3640 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3641 SUPPORTED_MII);
3642 if (np->gigabit == PHY_GIGABIT)
3643 ecmd->supported |= SUPPORTED_1000baseT_Full;
3644
3645 ecmd->phy_address = np->phyaddr;
3646 ecmd->transceiver = XCVR_EXTERNAL;
3647
3648 /* ignore maxtxpkt, maxrxpkt for now */
3649 spin_unlock_irq(&np->lock);
3650 return 0;
3651 }
3652
3653 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3654 {
3655 struct fe_priv *np = netdev_priv(dev);
3656
3657 if (ecmd->port != PORT_MII)
3658 return -EINVAL;
3659 if (ecmd->transceiver != XCVR_EXTERNAL)
3660 return -EINVAL;
3661 if (ecmd->phy_address != np->phyaddr) {
3662 /* TODO: support switching between multiple phys. Should be
3663 * trivial, but not enabled due to lack of test hardware. */
3664 return -EINVAL;
3665 }
3666 if (ecmd->autoneg == AUTONEG_ENABLE) {
3667 u32 mask;
3668
3669 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3670 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3671 if (np->gigabit == PHY_GIGABIT)
3672 mask |= ADVERTISED_1000baseT_Full;
3673
3674 if ((ecmd->advertising & mask) == 0)
3675 return -EINVAL;
3676
3677 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3678 /* Note: autonegotiation disable, speed 1000 intentionally
3679 * forbidden - noone should need that. */
3680
3681 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3682 return -EINVAL;
3683 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3684 return -EINVAL;
3685 } else {
3686 return -EINVAL;
3687 }
3688
3689 netif_carrier_off(dev);
3690 if (netif_running(dev)) {
3691 nv_disable_irq(dev);
3692 netif_tx_lock_bh(dev);
3693 spin_lock(&np->lock);
3694 /* stop engines */
3695 nv_stop_rx(dev);
3696 nv_stop_tx(dev);
3697 spin_unlock(&np->lock);
3698 netif_tx_unlock_bh(dev);
3699 }
3700
3701 if (ecmd->autoneg == AUTONEG_ENABLE) {
3702 int adv, bmcr;
3703
3704 np->autoneg = 1;
3705
3706 /* advertise only what has been requested */
3707 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3708 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3709 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3710 adv |= ADVERTISE_10HALF;
3711 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3712 adv |= ADVERTISE_10FULL;
3713 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3714 adv |= ADVERTISE_100HALF;
3715 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3716 adv |= ADVERTISE_100FULL;
3717 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3718 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3719 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3720 adv |= ADVERTISE_PAUSE_ASYM;
3721 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3722
3723 if (np->gigabit == PHY_GIGABIT) {
3724 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3725 adv &= ~ADVERTISE_1000FULL;
3726 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3727 adv |= ADVERTISE_1000FULL;
3728 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3729 }
3730
3731 if (netif_running(dev))
3732 printk(KERN_INFO "%s: link down.\n", dev->name);
3733 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3734 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3735 bmcr |= BMCR_ANENABLE;
3736 /* reset the phy in order for settings to stick,
3737 * and cause autoneg to start */
3738 if (phy_reset(dev, bmcr)) {
3739 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3740 return -EINVAL;
3741 }
3742 } else {
3743 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3744 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3745 }
3746 } else {
3747 int adv, bmcr;
3748
3749 np->autoneg = 0;
3750
3751 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3752 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3753 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3754 adv |= ADVERTISE_10HALF;
3755 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3756 adv |= ADVERTISE_10FULL;
3757 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3758 adv |= ADVERTISE_100HALF;
3759 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3760 adv |= ADVERTISE_100FULL;
3761 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3762 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3763 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3764 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3765 }
3766 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3767 adv |= ADVERTISE_PAUSE_ASYM;
3768 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3769 }
3770 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3771 np->fixed_mode = adv;
3772
3773 if (np->gigabit == PHY_GIGABIT) {
3774 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3775 adv &= ~ADVERTISE_1000FULL;
3776 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3777 }
3778
3779 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3780 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3781 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3782 bmcr |= BMCR_FULLDPLX;
3783 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3784 bmcr |= BMCR_SPEED100;
3785 if (np->phy_oui == PHY_OUI_MARVELL) {
3786 /* reset the phy in order for forced mode settings to stick */
3787 if (phy_reset(dev, bmcr)) {
3788 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3789 return -EINVAL;
3790 }
3791 } else {
3792 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3793 if (netif_running(dev)) {
3794 /* Wait a bit and then reconfigure the nic. */
3795 udelay(10);
3796 nv_linkchange(dev);
3797 }
3798 }
3799 }
3800
3801 if (netif_running(dev)) {
3802 nv_start_rx(dev);
3803 nv_start_tx(dev);
3804 nv_enable_irq(dev);
3805 }
3806
3807 return 0;
3808 }
3809
3810 #define FORCEDETH_REGS_VER 1
3811
3812 static int nv_get_regs_len(struct net_device *dev)
3813 {
3814 struct fe_priv *np = netdev_priv(dev);
3815 return np->register_size;
3816 }
3817
3818 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3819 {
3820 struct fe_priv *np = netdev_priv(dev);
3821 u8 __iomem *base = get_hwbase(dev);
3822 u32 *rbuf = buf;
3823 int i;
3824
3825 regs->version = FORCEDETH_REGS_VER;
3826 spin_lock_irq(&np->lock);
3827 for (i = 0;i <= np->register_size/sizeof(u32); i++)
3828 rbuf[i] = readl(base + i*sizeof(u32));
3829 spin_unlock_irq(&np->lock);
3830 }
3831
3832 static int nv_nway_reset(struct net_device *dev)
3833 {
3834 struct fe_priv *np = netdev_priv(dev);
3835 int ret;
3836
3837 if (np->autoneg) {
3838 int bmcr;
3839
3840 netif_carrier_off(dev);
3841 if (netif_running(dev)) {
3842 nv_disable_irq(dev);
3843 netif_tx_lock_bh(dev);
3844 spin_lock(&np->lock);
3845 /* stop engines */
3846 nv_stop_rx(dev);
3847 nv_stop_tx(dev);
3848 spin_unlock(&np->lock);
3849 netif_tx_unlock_bh(dev);
3850 printk(KERN_INFO "%s: link down.\n", dev->name);
3851 }
3852
3853 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3854 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3855 bmcr |= BMCR_ANENABLE;
3856 /* reset the phy in order for settings to stick*/
3857 if (phy_reset(dev, bmcr)) {
3858 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3859 return -EINVAL;
3860 }
3861 } else {
3862 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3863 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3864 }
3865
3866 if (netif_running(dev)) {
3867 nv_start_rx(dev);
3868 nv_start_tx(dev);
3869 nv_enable_irq(dev);
3870 }
3871 ret = 0;
3872 } else {
3873 ret = -EINVAL;
3874 }
3875
3876 return ret;
3877 }
3878
3879 static int nv_set_tso(struct net_device *dev, u32 value)
3880 {
3881 struct fe_priv *np = netdev_priv(dev);
3882
3883 if ((np->driver_data & DEV_HAS_CHECKSUM))
3884 return ethtool_op_set_tso(dev, value);
3885 else
3886 return -EOPNOTSUPP;
3887 }
3888
3889 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3890 {
3891 struct fe_priv *np = netdev_priv(dev);
3892
3893 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3894 ring->rx_mini_max_pending = 0;
3895 ring->rx_jumbo_max_pending = 0;
3896 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3897
3898 ring->rx_pending = np->rx_ring_size;
3899 ring->rx_mini_pending = 0;
3900 ring->rx_jumbo_pending = 0;
3901 ring->tx_pending = np->tx_ring_size;
3902 }
3903
3904 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3905 {
3906 struct fe_priv *np = netdev_priv(dev);
3907 u8 __iomem *base = get_hwbase(dev);
3908 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3909 dma_addr_t ring_addr;
3910
3911 if (ring->rx_pending < RX_RING_MIN ||
3912 ring->tx_pending < TX_RING_MIN ||
3913 ring->rx_mini_pending != 0 ||
3914 ring->rx_jumbo_pending != 0 ||
3915 (np->desc_ver == DESC_VER_1 &&
3916 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3917 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3918 (np->desc_ver != DESC_VER_1 &&
3919 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3920 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3921 return -EINVAL;
3922 }
3923
3924 /* allocate new rings */
3925 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3926 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3927 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3928 &ring_addr);
3929 } else {
3930 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3931 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3932 &ring_addr);
3933 }
3934 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3935 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3936 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3937 /* fall back to old rings */
3938 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3939 if (rxtx_ring)
3940 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3941 rxtx_ring, ring_addr);
3942 } else {
3943 if (rxtx_ring)
3944 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3945 rxtx_ring, ring_addr);
3946 }
3947 if (rx_skbuff)
3948 kfree(rx_skbuff);
3949 if (tx_skbuff)
3950 kfree(tx_skbuff);
3951 goto exit;
3952 }
3953
3954 if (netif_running(dev)) {
3955 nv_disable_irq(dev);
3956 netif_tx_lock_bh(dev);
3957 spin_lock(&np->lock);
3958 /* stop engines */
3959 nv_stop_rx(dev);
3960 nv_stop_tx(dev);
3961 nv_txrx_reset(dev);
3962 /* drain queues */
3963 nv_drain_rx(dev);
3964 nv_drain_tx(dev);
3965 /* delete queues */
3966 free_rings(dev);
3967 }
3968
3969 /* set new values */
3970 np->rx_ring_size = ring->rx_pending;
3971 np->tx_ring_size = ring->tx_pending;
3972 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3973 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3974 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3975 } else {
3976 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3977 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3978 }
3979 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
3980 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
3981 np->ring_addr = ring_addr;
3982
3983 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
3984 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
3985
3986 if (netif_running(dev)) {
3987 /* reinit driver view of the queues */
3988 set_bufsize(dev);
3989 if (nv_init_ring(dev)) {
3990 if (!np->in_shutdown)
3991 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3992 }
3993
3994 /* reinit nic view of the queues */
3995 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3996 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3997 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3998 base + NvRegRingSizes);
3999 pci_push(base);
4000 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4001 pci_push(base);
4002
4003 /* restart engines */
4004 nv_start_rx(dev);
4005 nv_start_tx(dev);
4006 spin_unlock(&np->lock);
4007 netif_tx_unlock_bh(dev);
4008 nv_enable_irq(dev);
4009 }
4010 return 0;
4011 exit:
4012 return -ENOMEM;
4013 }
4014
4015 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4016 {
4017 struct fe_priv *np = netdev_priv(dev);
4018
4019 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4020 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4021 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4022 }
4023
4024 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4025 {
4026 struct fe_priv *np = netdev_priv(dev);
4027 int adv, bmcr;
4028
4029 if ((!np->autoneg && np->duplex == 0) ||
4030 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4031 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4032 dev->name);
4033 return -EINVAL;
4034 }
4035 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4036 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4037 return -EINVAL;
4038 }
4039
4040 netif_carrier_off(dev);
4041 if (netif_running(dev)) {
4042 nv_disable_irq(dev);
4043 netif_tx_lock_bh(dev);
4044 spin_lock(&np->lock);
4045 /* stop engines */
4046 nv_stop_rx(dev);
4047 nv_stop_tx(dev);
4048 spin_unlock(&np->lock);
4049 netif_tx_unlock_bh(dev);
4050 }
4051
4052 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4053 if (pause->rx_pause)
4054 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4055 if (pause->tx_pause)
4056 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4057
4058 if (np->autoneg && pause->autoneg) {
4059 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4060
4061 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4062 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4063 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4064 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4065 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4066 adv |= ADVERTISE_PAUSE_ASYM;
4067 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4068
4069 if (netif_running(dev))
4070 printk(KERN_INFO "%s: link down.\n", dev->name);
4071 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4072 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4073 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4074 } else {
4075 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4076 if (pause->rx_pause)
4077 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4078 if (pause->tx_pause)
4079 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4080
4081 if (!netif_running(dev))
4082 nv_update_linkspeed(dev);
4083 else
4084 nv_update_pause(dev, np->pause_flags);
4085 }
4086
4087 if (netif_running(dev)) {
4088 nv_start_rx(dev);
4089 nv_start_tx(dev);
4090 nv_enable_irq(dev);
4091 }
4092 return 0;
4093 }
4094
4095 static u32 nv_get_rx_csum(struct net_device *dev)
4096 {
4097 struct fe_priv *np = netdev_priv(dev);
4098 return (np->rx_csum) != 0;
4099 }
4100
4101 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4102 {
4103 struct fe_priv *np = netdev_priv(dev);
4104 u8 __iomem *base = get_hwbase(dev);
4105 int retcode = 0;
4106
4107 if (np->driver_data & DEV_HAS_CHECKSUM) {
4108 if (data) {
4109 np->rx_csum = 1;
4110 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4111 } else {
4112 np->rx_csum = 0;
4113 /* vlan is dependent on rx checksum offload */
4114 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4115 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4116 }
4117 if (netif_running(dev)) {
4118 spin_lock_irq(&np->lock);
4119 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4120 spin_unlock_irq(&np->lock);
4121 }
4122 } else {
4123 return -EINVAL;
4124 }
4125
4126 return retcode;
4127 }
4128
4129 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4130 {
4131 struct fe_priv *np = netdev_priv(dev);
4132
4133 if (np->driver_data & DEV_HAS_CHECKSUM)
4134 return ethtool_op_set_tx_hw_csum(dev, data);
4135 else
4136 return -EOPNOTSUPP;
4137 }
4138
4139 static int nv_set_sg(struct net_device *dev, u32 data)
4140 {
4141 struct fe_priv *np = netdev_priv(dev);
4142
4143 if (np->driver_data & DEV_HAS_CHECKSUM)
4144 return ethtool_op_set_sg(dev, data);
4145 else
4146 return -EOPNOTSUPP;
4147 }
4148
4149 static int nv_get_stats_count(struct net_device *dev)
4150 {
4151 struct fe_priv *np = netdev_priv(dev);
4152
4153 if (np->driver_data & DEV_HAS_STATISTICS)
4154 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
4155 else
4156 return 0;
4157 }
4158
4159 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4160 {
4161 struct fe_priv *np = netdev_priv(dev);
4162
4163 /* update stats */
4164 nv_do_stats_poll((unsigned long)dev);
4165
4166 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
4167 }
4168
4169 static int nv_self_test_count(struct net_device *dev)
4170 {
4171 struct fe_priv *np = netdev_priv(dev);
4172
4173 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4174 return NV_TEST_COUNT_EXTENDED;
4175 else
4176 return NV_TEST_COUNT_BASE;
4177 }
4178
4179 static int nv_link_test(struct net_device *dev)
4180 {
4181 struct fe_priv *np = netdev_priv(dev);
4182 int mii_status;
4183
4184 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4185 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4186
4187 /* check phy link status */
4188 if (!(mii_status & BMSR_LSTATUS))
4189 return 0;
4190 else
4191 return 1;
4192 }
4193
4194 static int nv_register_test(struct net_device *dev)
4195 {
4196 u8 __iomem *base = get_hwbase(dev);
4197 int i = 0;
4198 u32 orig_read, new_read;
4199
4200 do {
4201 orig_read = readl(base + nv_registers_test[i].reg);
4202
4203 /* xor with mask to toggle bits */
4204 orig_read ^= nv_registers_test[i].mask;
4205
4206 writel(orig_read, base + nv_registers_test[i].reg);
4207
4208 new_read = readl(base + nv_registers_test[i].reg);
4209
4210 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4211 return 0;
4212
4213 /* restore original value */
4214 orig_read ^= nv_registers_test[i].mask;
4215 writel(orig_read, base + nv_registers_test[i].reg);
4216
4217 } while (nv_registers_test[++i].reg != 0);
4218
4219 return 1;
4220 }
4221
4222 static int nv_interrupt_test(struct net_device *dev)
4223 {
4224 struct fe_priv *np = netdev_priv(dev);
4225 u8 __iomem *base = get_hwbase(dev);
4226 int ret = 1;
4227 int testcnt;
4228 u32 save_msi_flags, save_poll_interval = 0;
4229
4230 if (netif_running(dev)) {
4231 /* free current irq */
4232 nv_free_irq(dev);
4233 save_poll_interval = readl(base+NvRegPollingInterval);
4234 }
4235
4236 /* flag to test interrupt handler */
4237 np->intr_test = 0;
4238
4239 /* setup test irq */
4240 save_msi_flags = np->msi_flags;
4241 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4242 np->msi_flags |= 0x001; /* setup 1 vector */
4243 if (nv_request_irq(dev, 1))
4244 return 0;
4245
4246 /* setup timer interrupt */
4247 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4248 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4249
4250 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4251
4252 /* wait for at least one interrupt */
4253 msleep(100);
4254
4255 spin_lock_irq(&np->lock);
4256
4257 /* flag should be set within ISR */
4258 testcnt = np->intr_test;
4259 if (!testcnt)
4260 ret = 2;
4261
4262 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4263 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4264 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4265 else
4266 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4267
4268 spin_unlock_irq(&np->lock);
4269
4270 nv_free_irq(dev);
4271
4272 np->msi_flags = save_msi_flags;
4273
4274 if (netif_running(dev)) {
4275 writel(save_poll_interval, base + NvRegPollingInterval);
4276 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4277 /* restore original irq */
4278 if (nv_request_irq(dev, 0))
4279 return 0;
4280 }
4281
4282 return ret;
4283 }
4284
4285 static int nv_loopback_test(struct net_device *dev)
4286 {
4287 struct fe_priv *np = netdev_priv(dev);
4288 u8 __iomem *base = get_hwbase(dev);
4289 struct sk_buff *tx_skb, *rx_skb;
4290 dma_addr_t test_dma_addr;
4291 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4292 u32 flags;
4293 int len, i, pkt_len;
4294 u8 *pkt_data;
4295 u32 filter_flags = 0;
4296 u32 misc1_flags = 0;
4297 int ret = 1;
4298
4299 if (netif_running(dev)) {
4300 nv_disable_irq(dev);
4301 filter_flags = readl(base + NvRegPacketFilterFlags);
4302 misc1_flags = readl(base + NvRegMisc1);
4303 } else {
4304 nv_txrx_reset(dev);
4305 }
4306
4307 /* reinit driver view of the rx queue */
4308 set_bufsize(dev);
4309 nv_init_ring(dev);
4310
4311 /* setup hardware for loopback */
4312 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4313 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4314
4315 /* reinit nic view of the rx queue */
4316 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4317 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4318 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4319 base + NvRegRingSizes);
4320 pci_push(base);
4321
4322 /* restart rx engine */
4323 nv_start_rx(dev);
4324 nv_start_tx(dev);
4325
4326 /* setup packet for tx */
4327 pkt_len = ETH_DATA_LEN;
4328 tx_skb = dev_alloc_skb(pkt_len);
4329 if (!tx_skb) {
4330 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4331 " of %s\n", dev->name);
4332 ret = 0;
4333 goto out;
4334 }
4335 pkt_data = skb_put(tx_skb, pkt_len);
4336 for (i = 0; i < pkt_len; i++)
4337 pkt_data[i] = (u8)(i & 0xff);
4338 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4339 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
4340
4341 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4342 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4343 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4344 } else {
4345 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4346 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4347 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4348 }
4349 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4350 pci_push(get_hwbase(dev));
4351
4352 msleep(500);
4353
4354 /* check for rx of the packet */
4355 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4356 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4357 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4358
4359 } else {
4360 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4361 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4362 }
4363
4364 if (flags & NV_RX_AVAIL) {
4365 ret = 0;
4366 } else if (np->desc_ver == DESC_VER_1) {
4367 if (flags & NV_RX_ERROR)
4368 ret = 0;
4369 } else {
4370 if (flags & NV_RX2_ERROR) {
4371 ret = 0;
4372 }
4373 }
4374
4375 if (ret) {
4376 if (len != pkt_len) {
4377 ret = 0;
4378 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4379 dev->name, len, pkt_len);
4380 } else {
4381 rx_skb = np->rx_skb[0].skb;
4382 for (i = 0; i < pkt_len; i++) {
4383 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4384 ret = 0;
4385 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4386 dev->name, i);
4387 break;
4388 }
4389 }
4390 }
4391 } else {
4392 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4393 }
4394
4395 pci_unmap_page(np->pci_dev, test_dma_addr,
4396 tx_skb->end-tx_skb->data,
4397 PCI_DMA_TODEVICE);
4398 dev_kfree_skb_any(tx_skb);
4399 out:
4400 /* stop engines */
4401 nv_stop_rx(dev);
4402 nv_stop_tx(dev);
4403 nv_txrx_reset(dev);
4404 /* drain rx queue */
4405 nv_drain_rx(dev);
4406 nv_drain_tx(dev);
4407
4408 if (netif_running(dev)) {
4409 writel(misc1_flags, base + NvRegMisc1);
4410 writel(filter_flags, base + NvRegPacketFilterFlags);
4411 nv_enable_irq(dev);
4412 }
4413
4414 return ret;
4415 }
4416
4417 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4418 {
4419 struct fe_priv *np = netdev_priv(dev);
4420 u8 __iomem *base = get_hwbase(dev);
4421 int result;
4422 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4423
4424 if (!nv_link_test(dev)) {
4425 test->flags |= ETH_TEST_FL_FAILED;
4426 buffer[0] = 1;
4427 }
4428
4429 if (test->flags & ETH_TEST_FL_OFFLINE) {
4430 if (netif_running(dev)) {
4431 netif_stop_queue(dev);
4432 netif_poll_disable(dev);
4433 netif_tx_lock_bh(dev);
4434 spin_lock_irq(&np->lock);
4435 nv_disable_hw_interrupts(dev, np->irqmask);
4436 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4437 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4438 } else {
4439 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4440 }
4441 /* stop engines */
4442 nv_stop_rx(dev);
4443 nv_stop_tx(dev);
4444 nv_txrx_reset(dev);
4445 /* drain rx queue */
4446 nv_drain_rx(dev);
4447 nv_drain_tx(dev);
4448 spin_unlock_irq(&np->lock);
4449 netif_tx_unlock_bh(dev);
4450 }
4451
4452 if (!nv_register_test(dev)) {
4453 test->flags |= ETH_TEST_FL_FAILED;
4454 buffer[1] = 1;
4455 }
4456
4457 result = nv_interrupt_test(dev);
4458 if (result != 1) {
4459 test->flags |= ETH_TEST_FL_FAILED;
4460 buffer[2] = 1;
4461 }
4462 if (result == 0) {
4463 /* bail out */
4464 return;
4465 }
4466
4467 if (!nv_loopback_test(dev)) {
4468 test->flags |= ETH_TEST_FL_FAILED;
4469 buffer[3] = 1;
4470 }
4471
4472 if (netif_running(dev)) {
4473 /* reinit driver view of the rx queue */
4474 set_bufsize(dev);
4475 if (nv_init_ring(dev)) {
4476 if (!np->in_shutdown)
4477 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4478 }
4479 /* reinit nic view of the rx queue */
4480 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4481 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4482 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4483 base + NvRegRingSizes);
4484 pci_push(base);
4485 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4486 pci_push(base);
4487 /* restart rx engine */
4488 nv_start_rx(dev);
4489 nv_start_tx(dev);
4490 netif_start_queue(dev);
4491 netif_poll_enable(dev);
4492 nv_enable_hw_interrupts(dev, np->irqmask);
4493 }
4494 }
4495 }
4496
4497 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4498 {
4499 switch (stringset) {
4500 case ETH_SS_STATS:
4501 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4502 break;
4503 case ETH_SS_TEST:
4504 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4505 break;
4506 }
4507 }
4508
4509 static const struct ethtool_ops ops = {
4510 .get_drvinfo = nv_get_drvinfo,
4511 .get_link = ethtool_op_get_link,
4512 .get_wol = nv_get_wol,
4513 .set_wol = nv_set_wol,
4514 .get_settings = nv_get_settings,
4515 .set_settings = nv_set_settings,
4516 .get_regs_len = nv_get_regs_len,
4517 .get_regs = nv_get_regs,
4518 .nway_reset = nv_nway_reset,
4519 .get_perm_addr = ethtool_op_get_perm_addr,
4520 .get_tso = ethtool_op_get_tso,
4521 .set_tso = nv_set_tso,
4522 .get_ringparam = nv_get_ringparam,
4523 .set_ringparam = nv_set_ringparam,
4524 .get_pauseparam = nv_get_pauseparam,
4525 .set_pauseparam = nv_set_pauseparam,
4526 .get_rx_csum = nv_get_rx_csum,
4527 .set_rx_csum = nv_set_rx_csum,
4528 .get_tx_csum = ethtool_op_get_tx_csum,
4529 .set_tx_csum = nv_set_tx_csum,
4530 .get_sg = ethtool_op_get_sg,
4531 .set_sg = nv_set_sg,
4532 .get_strings = nv_get_strings,
4533 .get_stats_count = nv_get_stats_count,
4534 .get_ethtool_stats = nv_get_ethtool_stats,
4535 .self_test_count = nv_self_test_count,
4536 .self_test = nv_self_test,
4537 };
4538
4539 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4540 {
4541 struct fe_priv *np = get_nvpriv(dev);
4542
4543 spin_lock_irq(&np->lock);
4544
4545 /* save vlan group */
4546 np->vlangrp = grp;
4547
4548 if (grp) {
4549 /* enable vlan on MAC */
4550 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4551 } else {
4552 /* disable vlan on MAC */
4553 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4554 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4555 }
4556
4557 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4558
4559 spin_unlock_irq(&np->lock);
4560 };
4561
4562 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4563 {
4564 /* nothing to do */
4565 };
4566
4567 /* The mgmt unit and driver use a semaphore to access the phy during init */
4568 static int nv_mgmt_acquire_sema(struct net_device *dev)
4569 {
4570 u8 __iomem *base = get_hwbase(dev);
4571 int i;
4572 u32 tx_ctrl, mgmt_sema;
4573
4574 for (i = 0; i < 10; i++) {
4575 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4576 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4577 break;
4578 msleep(500);
4579 }
4580
4581 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4582 return 0;
4583
4584 for (i = 0; i < 2; i++) {
4585 tx_ctrl = readl(base + NvRegTransmitterControl);
4586 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4587 writel(tx_ctrl, base + NvRegTransmitterControl);
4588
4589 /* verify that semaphore was acquired */
4590 tx_ctrl = readl(base + NvRegTransmitterControl);
4591 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4592 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4593 return 1;
4594 else
4595 udelay(50);
4596 }
4597
4598 return 0;
4599 }
4600
4601 static int nv_open(struct net_device *dev)
4602 {
4603 struct fe_priv *np = netdev_priv(dev);
4604 u8 __iomem *base = get_hwbase(dev);
4605 int ret = 1;
4606 int oom, i;
4607
4608 dprintk(KERN_DEBUG "nv_open: begin\n");
4609
4610 /* erase previous misconfiguration */
4611 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4612 nv_mac_reset(dev);
4613 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4614 writel(0, base + NvRegMulticastAddrB);
4615 writel(0, base + NvRegMulticastMaskA);
4616 writel(0, base + NvRegMulticastMaskB);
4617 writel(0, base + NvRegPacketFilterFlags);
4618
4619 writel(0, base + NvRegTransmitterControl);
4620 writel(0, base + NvRegReceiverControl);
4621
4622 writel(0, base + NvRegAdapterControl);
4623
4624 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4625 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4626
4627 /* initialize descriptor rings */
4628 set_bufsize(dev);
4629 oom = nv_init_ring(dev);
4630
4631 writel(0, base + NvRegLinkSpeed);
4632 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4633 nv_txrx_reset(dev);
4634 writel(0, base + NvRegUnknownSetupReg6);
4635
4636 np->in_shutdown = 0;
4637
4638 /* give hw rings */
4639 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4640 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4641 base + NvRegRingSizes);
4642
4643 writel(np->linkspeed, base + NvRegLinkSpeed);
4644 if (np->desc_ver == DESC_VER_1)
4645 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4646 else
4647 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4648 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4649 writel(np->vlanctl_bits, base + NvRegVlanControl);
4650 pci_push(base);
4651 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4652 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4653 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4654 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4655
4656 writel(0, base + NvRegMIIMask);
4657 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4658 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4659
4660 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4661 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4662 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4663 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4664
4665 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4666 get_random_bytes(&i, sizeof(i));
4667 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4668 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4669 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4670 if (poll_interval == -1) {
4671 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4672 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4673 else
4674 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4675 }
4676 else
4677 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4678 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4679 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4680 base + NvRegAdapterControl);
4681 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4682 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4683 if (np->wolenabled)
4684 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4685
4686 i = readl(base + NvRegPowerState);
4687 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4688 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4689
4690 pci_push(base);
4691 udelay(10);
4692 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4693
4694 nv_disable_hw_interrupts(dev, np->irqmask);
4695 pci_push(base);
4696 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4697 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4698 pci_push(base);
4699
4700 if (nv_request_irq(dev, 0)) {
4701 goto out_drain;
4702 }
4703
4704 /* ask for interrupts */
4705 nv_enable_hw_interrupts(dev, np->irqmask);
4706
4707 spin_lock_irq(&np->lock);
4708 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4709 writel(0, base + NvRegMulticastAddrB);
4710 writel(0, base + NvRegMulticastMaskA);
4711 writel(0, base + NvRegMulticastMaskB);
4712 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4713 /* One manual link speed update: Interrupts are enabled, future link
4714 * speed changes cause interrupts and are handled by nv_link_irq().
4715 */
4716 {
4717 u32 miistat;
4718 miistat = readl(base + NvRegMIIStatus);
4719 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4720 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4721 }
4722 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4723 * to init hw */
4724 np->linkspeed = 0;
4725 ret = nv_update_linkspeed(dev);
4726 nv_start_rx(dev);
4727 nv_start_tx(dev);
4728 netif_start_queue(dev);
4729 netif_poll_enable(dev);
4730
4731 if (ret) {
4732 netif_carrier_on(dev);
4733 } else {
4734 printk("%s: no link during initialization.\n", dev->name);
4735 netif_carrier_off(dev);
4736 }
4737 if (oom)
4738 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4739
4740 /* start statistics timer */
4741 if (np->driver_data & DEV_HAS_STATISTICS)
4742 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4743
4744 spin_unlock_irq(&np->lock);
4745
4746 return 0;
4747 out_drain:
4748 drain_ring(dev);
4749 return ret;
4750 }
4751
4752 static int nv_close(struct net_device *dev)
4753 {
4754 struct fe_priv *np = netdev_priv(dev);
4755 u8 __iomem *base;
4756
4757 spin_lock_irq(&np->lock);
4758 np->in_shutdown = 1;
4759 spin_unlock_irq(&np->lock);
4760 netif_poll_disable(dev);
4761 synchronize_irq(dev->irq);
4762
4763 del_timer_sync(&np->oom_kick);
4764 del_timer_sync(&np->nic_poll);
4765 del_timer_sync(&np->stats_poll);
4766
4767 netif_stop_queue(dev);
4768 spin_lock_irq(&np->lock);
4769 nv_stop_tx(dev);
4770 nv_stop_rx(dev);
4771 nv_txrx_reset(dev);
4772
4773 /* disable interrupts on the nic or we will lock up */
4774 base = get_hwbase(dev);
4775 nv_disable_hw_interrupts(dev, np->irqmask);
4776 pci_push(base);
4777 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4778
4779 spin_unlock_irq(&np->lock);
4780
4781 nv_free_irq(dev);
4782
4783 drain_ring(dev);
4784
4785 if (np->wolenabled)
4786 nv_start_rx(dev);
4787
4788 /* FIXME: power down nic */
4789
4790 return 0;
4791 }
4792
4793 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4794 {
4795 struct net_device *dev;
4796 struct fe_priv *np;
4797 unsigned long addr;
4798 u8 __iomem *base;
4799 int err, i;
4800 u32 powerstate, txreg;
4801 u32 phystate_orig = 0, phystate;
4802 int phyinitialized = 0;
4803
4804 dev = alloc_etherdev(sizeof(struct fe_priv));
4805 err = -ENOMEM;
4806 if (!dev)
4807 goto out;
4808
4809 np = netdev_priv(dev);
4810 np->pci_dev = pci_dev;
4811 spin_lock_init(&np->lock);
4812 SET_MODULE_OWNER(dev);
4813 SET_NETDEV_DEV(dev, &pci_dev->dev);
4814
4815 init_timer(&np->oom_kick);
4816 np->oom_kick.data = (unsigned long) dev;
4817 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
4818 init_timer(&np->nic_poll);
4819 np->nic_poll.data = (unsigned long) dev;
4820 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
4821 init_timer(&np->stats_poll);
4822 np->stats_poll.data = (unsigned long) dev;
4823 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
4824
4825 err = pci_enable_device(pci_dev);
4826 if (err) {
4827 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4828 err, pci_name(pci_dev));
4829 goto out_free;
4830 }
4831
4832 pci_set_master(pci_dev);
4833
4834 err = pci_request_regions(pci_dev, DRV_NAME);
4835 if (err < 0)
4836 goto out_disable;
4837
4838 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4839 np->register_size = NV_PCI_REGSZ_VER2;
4840 else
4841 np->register_size = NV_PCI_REGSZ_VER1;
4842
4843 err = -EINVAL;
4844 addr = 0;
4845 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4846 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4847 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4848 pci_resource_len(pci_dev, i),
4849 pci_resource_flags(pci_dev, i));
4850 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4851 pci_resource_len(pci_dev, i) >= np->register_size) {
4852 addr = pci_resource_start(pci_dev, i);
4853 break;
4854 }
4855 }
4856 if (i == DEVICE_COUNT_RESOURCE) {
4857 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4858 pci_name(pci_dev));
4859 goto out_relreg;
4860 }
4861
4862 /* copy of driver data */
4863 np->driver_data = id->driver_data;
4864
4865 /* handle different descriptor versions */
4866 if (id->driver_data & DEV_HAS_HIGH_DMA) {
4867 /* packet format 3: supports 40-bit addressing */
4868 np->desc_ver = DESC_VER_3;
4869 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4870 if (dma_64bit) {
4871 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4872 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4873 pci_name(pci_dev));
4874 } else {
4875 dev->features |= NETIF_F_HIGHDMA;
4876 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4877 }
4878 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4879 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4880 pci_name(pci_dev));
4881 }
4882 }
4883 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4884 /* packet format 2: supports jumbo frames */
4885 np->desc_ver = DESC_VER_2;
4886 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4887 } else {
4888 /* original packet format */
4889 np->desc_ver = DESC_VER_1;
4890 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4891 }
4892
4893 np->pkt_limit = NV_PKTLIMIT_1;
4894 if (id->driver_data & DEV_HAS_LARGEDESC)
4895 np->pkt_limit = NV_PKTLIMIT_2;
4896
4897 if (id->driver_data & DEV_HAS_CHECKSUM) {
4898 np->rx_csum = 1;
4899 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4900 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4901 dev->features |= NETIF_F_TSO;
4902 }
4903
4904 np->vlanctl_bits = 0;
4905 if (id->driver_data & DEV_HAS_VLAN) {
4906 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4907 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4908 dev->vlan_rx_register = nv_vlan_rx_register;
4909 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4910 }
4911
4912 np->msi_flags = 0;
4913 if ((id->driver_data & DEV_HAS_MSI) && msi) {
4914 np->msi_flags |= NV_MSI_CAPABLE;
4915 }
4916 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4917 np->msi_flags |= NV_MSI_X_CAPABLE;
4918 }
4919
4920 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4921 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4922 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4923 }
4924
4925
4926 err = -ENOMEM;
4927 np->base = ioremap(addr, np->register_size);
4928 if (!np->base)
4929 goto out_relreg;
4930 dev->base_addr = (unsigned long)np->base;
4931
4932 dev->irq = pci_dev->irq;
4933
4934 np->rx_ring_size = RX_RING_DEFAULT;
4935 np->tx_ring_size = TX_RING_DEFAULT;
4936
4937 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4938 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4939 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4940 &np->ring_addr);
4941 if (!np->rx_ring.orig)
4942 goto out_unmap;
4943 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4944 } else {
4945 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4946 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4947 &np->ring_addr);
4948 if (!np->rx_ring.ex)
4949 goto out_unmap;
4950 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4951 }
4952 np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
4953 np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
4954 if (!np->rx_skb || !np->tx_skb)
4955 goto out_freering;
4956 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4957 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4958
4959 dev->open = nv_open;
4960 dev->stop = nv_close;
4961 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
4962 dev->hard_start_xmit = nv_start_xmit;
4963 else
4964 dev->hard_start_xmit = nv_start_xmit_optimized;
4965 dev->get_stats = nv_get_stats;
4966 dev->change_mtu = nv_change_mtu;
4967 dev->set_mac_address = nv_set_mac_address;
4968 dev->set_multicast_list = nv_set_multicast;
4969 #ifdef CONFIG_NET_POLL_CONTROLLER
4970 dev->poll_controller = nv_poll_controller;
4971 #endif
4972 dev->weight = 64;
4973 #ifdef CONFIG_FORCEDETH_NAPI
4974 dev->poll = nv_napi_poll;
4975 #endif
4976 SET_ETHTOOL_OPS(dev, &ops);
4977 dev->tx_timeout = nv_tx_timeout;
4978 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4979
4980 pci_set_drvdata(pci_dev, dev);
4981
4982 /* read the mac address */
4983 base = get_hwbase(dev);
4984 np->orig_mac[0] = readl(base + NvRegMacAddrA);
4985 np->orig_mac[1] = readl(base + NvRegMacAddrB);
4986
4987 /* check the workaround bit for correct mac address order */
4988 txreg = readl(base + NvRegTransmitPoll);
4989 if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4990 /* mac address is already in correct order */
4991 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
4992 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
4993 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4994 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4995 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
4996 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
4997 } else {
4998 /* need to reverse mac address to correct order */
4999 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5000 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5001 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5002 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5003 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5004 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5005 /* set permanent address to be correct aswell */
5006 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
5007 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
5008 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
5009 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5010 }
5011 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5012
5013 if (!is_valid_ether_addr(dev->perm_addr)) {
5014 /*
5015 * Bad mac address. At least one bios sets the mac address
5016 * to 01:23:45:67:89:ab
5017 */
5018 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
5019 pci_name(pci_dev),
5020 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5021 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5022 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
5023 dev->dev_addr[0] = 0x00;
5024 dev->dev_addr[1] = 0x00;
5025 dev->dev_addr[2] = 0x6c;
5026 get_random_bytes(&dev->dev_addr[3], 3);
5027 }
5028
5029 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
5030 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5031 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5032
5033 /* set mac address */
5034 nv_copy_mac_to_hw(dev);
5035
5036 /* disable WOL */
5037 writel(0, base + NvRegWakeUpFlags);
5038 np->wolenabled = 0;
5039
5040 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5041 u8 revision_id;
5042 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
5043
5044 /* take phy and nic out of low power mode */
5045 powerstate = readl(base + NvRegPowerState2);
5046 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5047 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5048 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5049 revision_id >= 0xA3)
5050 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5051 writel(powerstate, base + NvRegPowerState2);
5052 }
5053
5054 if (np->desc_ver == DESC_VER_1) {
5055 np->tx_flags = NV_TX_VALID;
5056 } else {
5057 np->tx_flags = NV_TX2_VALID;
5058 }
5059 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5060 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5061 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5062 np->msi_flags |= 0x0003;
5063 } else {
5064 np->irqmask = NVREG_IRQMASK_CPU;
5065 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5066 np->msi_flags |= 0x0001;
5067 }
5068
5069 if (id->driver_data & DEV_NEED_TIMERIRQ)
5070 np->irqmask |= NVREG_IRQ_TIMER;
5071 if (id->driver_data & DEV_NEED_LINKTIMER) {
5072 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5073 np->need_linktimer = 1;
5074 np->link_timeout = jiffies + LINK_TIMEOUT;
5075 } else {
5076 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5077 np->need_linktimer = 0;
5078 }
5079
5080 /* clear phy state and temporarily halt phy interrupts */
5081 writel(0, base + NvRegMIIMask);
5082 phystate = readl(base + NvRegAdapterControl);
5083 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5084 phystate_orig = 1;
5085 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5086 writel(phystate, base + NvRegAdapterControl);
5087 }
5088 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
5089
5090 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5091 /* management unit running on the mac? */
5092 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5093 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5094 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5095 for (i = 0; i < 5000; i++) {
5096 msleep(1);
5097 if (nv_mgmt_acquire_sema(dev)) {
5098 /* management unit setup the phy already? */
5099 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5100 NVREG_XMITCTL_SYNC_PHY_INIT) {
5101 /* phy is inited by mgmt unit */
5102 phyinitialized = 1;
5103 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5104 } else {
5105 /* we need to init the phy */
5106 }
5107 break;
5108 }
5109 }
5110 }
5111 }
5112
5113 /* find a suitable phy */
5114 for (i = 1; i <= 32; i++) {
5115 int id1, id2;
5116 int phyaddr = i & 0x1F;
5117
5118 spin_lock_irq(&np->lock);
5119 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5120 spin_unlock_irq(&np->lock);
5121 if (id1 < 0 || id1 == 0xffff)
5122 continue;
5123 spin_lock_irq(&np->lock);
5124 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5125 spin_unlock_irq(&np->lock);
5126 if (id2 < 0 || id2 == 0xffff)
5127 continue;
5128
5129 np->phy_model = id2 & PHYID2_MODEL_MASK;
5130 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5131 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5132 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5133 pci_name(pci_dev), id1, id2, phyaddr);
5134 np->phyaddr = phyaddr;
5135 np->phy_oui = id1 | id2;
5136 break;
5137 }
5138 if (i == 33) {
5139 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
5140 pci_name(pci_dev));
5141 goto out_error;
5142 }
5143
5144 if (!phyinitialized) {
5145 /* reset it */
5146 phy_init(dev);
5147 } else {
5148 /* see if it is a gigabit phy */
5149 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5150 if (mii_status & PHY_GIGABIT) {
5151 np->gigabit = PHY_GIGABIT;
5152 }
5153 }
5154
5155 /* set default link speed settings */
5156 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5157 np->duplex = 0;
5158 np->autoneg = 1;
5159
5160 err = register_netdev(dev);
5161 if (err) {
5162 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
5163 goto out_error;
5164 }
5165 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
5166 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
5167 pci_name(pci_dev));
5168
5169 return 0;
5170
5171 out_error:
5172 if (phystate_orig)
5173 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5174 pci_set_drvdata(pci_dev, NULL);
5175 out_freering:
5176 free_rings(dev);
5177 out_unmap:
5178 iounmap(get_hwbase(dev));
5179 out_relreg:
5180 pci_release_regions(pci_dev);
5181 out_disable:
5182 pci_disable_device(pci_dev);
5183 out_free:
5184 free_netdev(dev);
5185 out:
5186 return err;
5187 }
5188
5189 static void __devexit nv_remove(struct pci_dev *pci_dev)
5190 {
5191 struct net_device *dev = pci_get_drvdata(pci_dev);
5192 struct fe_priv *np = netdev_priv(dev);
5193 u8 __iomem *base = get_hwbase(dev);
5194
5195 unregister_netdev(dev);
5196
5197 /* special op: write back the misordered MAC address - otherwise
5198 * the next nv_probe would see a wrong address.
5199 */
5200 writel(np->orig_mac[0], base + NvRegMacAddrA);
5201 writel(np->orig_mac[1], base + NvRegMacAddrB);
5202
5203 /* free all structures */
5204 free_rings(dev);
5205 iounmap(get_hwbase(dev));
5206 pci_release_regions(pci_dev);
5207 pci_disable_device(pci_dev);
5208 free_netdev(dev);
5209 pci_set_drvdata(pci_dev, NULL);
5210 }
5211
5212 #ifdef CONFIG_PM
5213 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5214 {
5215 struct net_device *dev = pci_get_drvdata(pdev);
5216 struct fe_priv *np = netdev_priv(dev);
5217
5218 if (!netif_running(dev))
5219 goto out;
5220
5221 netif_device_detach(dev);
5222
5223 // Gross.
5224 nv_close(dev);
5225
5226 pci_save_state(pdev);
5227 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5228 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5229 out:
5230 return 0;
5231 }
5232
5233 static int nv_resume(struct pci_dev *pdev)
5234 {
5235 struct net_device *dev = pci_get_drvdata(pdev);
5236 int rc = 0;
5237
5238 if (!netif_running(dev))
5239 goto out;
5240
5241 netif_device_attach(dev);
5242
5243 pci_set_power_state(pdev, PCI_D0);
5244 pci_restore_state(pdev);
5245 pci_enable_wake(pdev, PCI_D0, 0);
5246
5247 rc = nv_open(dev);
5248 out:
5249 return rc;
5250 }
5251 #else
5252 #define nv_suspend NULL
5253 #define nv_resume NULL
5254 #endif /* CONFIG_PM */
5255
5256 static struct pci_device_id pci_tbl[] = {
5257 { /* nForce Ethernet Controller */
5258 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5259 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5260 },
5261 { /* nForce2 Ethernet Controller */
5262 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5263 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5264 },
5265 { /* nForce3 Ethernet Controller */
5266 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5267 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5268 },
5269 { /* nForce3 Ethernet Controller */
5270 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5271 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5272 },
5273 { /* nForce3 Ethernet Controller */
5274 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5275 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5276 },
5277 { /* nForce3 Ethernet Controller */
5278 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5279 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5280 },
5281 { /* nForce3 Ethernet Controller */
5282 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5283 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5284 },
5285 { /* CK804 Ethernet Controller */
5286 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5287 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5288 },
5289 { /* CK804 Ethernet Controller */
5290 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5291 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5292 },
5293 { /* MCP04 Ethernet Controller */
5294 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5295 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5296 },
5297 { /* MCP04 Ethernet Controller */
5298 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5299 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5300 },
5301 { /* MCP51 Ethernet Controller */
5302 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5303 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
5304 },
5305 { /* MCP51 Ethernet Controller */
5306 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5307 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
5308 },
5309 { /* MCP55 Ethernet Controller */
5310 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5311 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5312 },
5313 { /* MCP55 Ethernet Controller */
5314 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5315 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5316 },
5317 { /* MCP61 Ethernet Controller */
5318 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5319 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5320 },
5321 { /* MCP61 Ethernet Controller */
5322 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5323 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5324 },
5325 { /* MCP61 Ethernet Controller */
5326 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5327 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5328 },
5329 { /* MCP61 Ethernet Controller */
5330 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5331 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5332 },
5333 { /* MCP65 Ethernet Controller */
5334 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5335 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5336 },
5337 { /* MCP65 Ethernet Controller */
5338 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5339 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5340 },
5341 { /* MCP65 Ethernet Controller */
5342 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5343 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5344 },
5345 { /* MCP65 Ethernet Controller */
5346 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5347 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5348 },
5349 { /* MCP67 Ethernet Controller */
5350 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5351 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5352 },
5353 { /* MCP67 Ethernet Controller */
5354 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5355 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5356 },
5357 { /* MCP67 Ethernet Controller */
5358 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5359 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5360 },
5361 { /* MCP67 Ethernet Controller */
5362 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5363 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5364 },
5365 {0,},
5366 };
5367
5368 static struct pci_driver driver = {
5369 .name = "forcedeth",
5370 .id_table = pci_tbl,
5371 .probe = nv_probe,
5372 .remove = __devexit_p(nv_remove),
5373 .suspend = nv_suspend,
5374 .resume = nv_resume,
5375 };
5376
5377 static int __init init_nic(void)
5378 {
5379 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5380 return pci_register_driver(&driver);
5381 }
5382
5383 static void __exit exit_nic(void)
5384 {
5385 pci_unregister_driver(&driver);
5386 }
5387
5388 module_param(max_interrupt_work, int, 0);
5389 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5390 module_param(optimization_mode, int, 0);
5391 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5392 module_param(poll_interval, int, 0);
5393 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5394 module_param(msi, int, 0);
5395 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5396 module_param(msix, int, 0);
5397 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5398 module_param(dma_64bit, int, 0);
5399 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5400
5401 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5402 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5403 MODULE_LICENSE("GPL");
5404
5405 MODULE_DEVICE_TABLE(pci, pci_tbl);
5406
5407 module_init(init_nic);
5408 module_exit(exit_nic);
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