drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /* defined here to avoid adding to pci_ids.h for single instance use */
  26 #define PCI_DEVICE_ID_INTEL_CE4100_USB  0x2e70
  27
  28 /*-------------------------------------------------------------------------*/
  29
  30 /* called after powerup, by probe or system-pm "wakeup" */
  31 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  32 {
  33         int                     retval;
  34
  35         /* we expect static quirk code to handle the "extended capabilities"
  36          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  37          */
  38
  39         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  40         retval = pci_set_mwi(pdev);
  41         if (!retval)
  42                 ehci_dbg(ehci, "MWI active\n");
  43
  44         return 0;
  45 }
  46
  47 /* called during probe() after chip reset completes */
  48 static int ehci_pci_setup(struct usb_hcd *hcd)
  49 {
  50         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  51         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  52         struct pci_dev          *p_smbus;
  53         u8                      rev;
  54         u32                     temp;
  55         int                     retval;
  56
  57         switch (pdev->vendor) {
  58         case PCI_VENDOR_ID_TOSHIBA_2:
  59                 /* celleb's companion chip */
  60                 if (pdev->device == 0x01b5) {
  61 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  62                         ehci->big_endian_mmio = 1;
  63 #else
  64                         ehci_warn(ehci,
  65                                   "unsupported big endian Toshiba quirk\n");
  66 #endif
  67                 }
  68                 break;
  69         }
  70
  71         ehci->caps = hcd->regs;
  72         ehci->regs = hcd->regs +
  73                 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
  74
  75         dbg_hcs_params(ehci, "reset");
  76         dbg_hcc_params(ehci, "reset");
  77
  78         /* ehci_init() causes memory for DMA transfers to be
  79          * allocated.  Thus, any vendor-specific workarounds based on
  80          * limiting the type of memory used for DMA transfers must
  81          * happen before ehci_init() is called. */
  82         switch (pdev->vendor) {
  83         case PCI_VENDOR_ID_NVIDIA:
  84                 /* NVidia reports that certain chips don't handle
  85                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
  86                  * data buffer, and periodic schedule are normal.)
  87                  */
  88                 switch (pdev->device) {
  89                 case 0x003c:    /* MCP04 */
  90                 case 0x005b:    /* CK804 */
  91                 case 0x00d8:    /* CK8 */
  92                 case 0x00e8:    /* CK8S */
  93                         if (pci_set_consistent_dma_mask(pdev,
  94                                                 DMA_BIT_MASK(31)) < 0)
  95                                 ehci_warn(ehci, "can't enable NVidia "
  96                                         "workaround for >2GB RAM\n");
  97                         break;
  98                 }
  99                 break;
 100         }
 101
 102         /* cache this readonly data; minimize chip reads */
 103         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 104
 105         retval = ehci_halt(ehci);
 106         if (retval)
 107                 return retval;
 108
 109         if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
 110             (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
 111                 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 112                  * read/write memory space which does not belong to it when
 113                  * there is NULL pointer with T-bit set to 1 in the frame list
 114                  * table. To avoid the issue, the frame list link pointer
 115                  * should always contain a valid pointer to a inactive qh.
 116                  */
 117                 ehci->use_dummy_qh = 1;
 118                 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
 119                                 "dummy qh workaround\n");
 120         }
 121
 122         /* data structure init */
 123         retval = ehci_init(hcd);
 124         if (retval)
 125                 return retval;
 126
 127         switch (pdev->vendor) {
 128         case PCI_VENDOR_ID_NEC:
 129                 ehci->need_io_watchdog = 0;
 130                 break;
 131         case PCI_VENDOR_ID_INTEL:
 132                 ehci->need_io_watchdog = 0;
 133                 ehci->fs_i_thresh = 1;
 134                 if (pdev->device == 0x27cc) {
 135                         ehci->broken_periodic = 1;
 136                         ehci_info(ehci, "using broken periodic workaround\n");
 137                 }
 138                 if (pdev->device == 0x0806 || pdev->device == 0x0811
 139                                 || pdev->device == 0x0829) {
 140                         ehci_info(ehci, "disable lpm for langwell/penwell\n");
 141                         ehci->has_lpm = 0;
 142                 }
 143                 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
 144                         hcd->has_tt = 1;
 145                         tdi_reset(ehci);
 146                 }
 147                 break;
 148         case PCI_VENDOR_ID_TDI:
 149                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 150                         hcd->has_tt = 1;
 151                         tdi_reset(ehci);
 152                 }
 153                 break;
 154         case PCI_VENDOR_ID_AMD:
 155                 /* AMD PLL quirk */
 156                 if (usb_amd_find_chipset_info())
 157                         ehci->amd_pll_fix = 1;
 158                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 159                 if (pdev->device == 0x7463) {
 160                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 161                         retval = -EIO;
 162                         goto done;
 163                 }
 164                 break;
 165         case PCI_VENDOR_ID_NVIDIA:
 166                 switch (pdev->device) {
 167                 /* Some NForce2 chips have problems with selective suspend;
 168                  * fixed in newer silicon.
 169                  */
 170                 case 0x0068:
 171                         if (pdev->revision < 0xa4)
 172                                 ehci->no_selective_suspend = 1;
 173                         break;
 174
 175                 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 176                  * fetching device descriptors unless LPM is disabled.
 177                  * There are also intermittent problems enumerating
 178                  * devices with PPCD enabled.
 179                  */
 180                 case 0x0d9d:
 181                         ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
 182                         ehci->has_lpm = 0;
 183                         ehci->has_ppcd = 0;
 184                         ehci->command &= ~CMD_PPCEE;
 185                         break;
 186                 }
 187                 break;
 188         case PCI_VENDOR_ID_VIA:
 189                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 190                         u8 tmp;
 191
 192                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 193                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 194                          * that sleep time use the conventional 10 usec.
 195                          */
 196                         pci_read_config_byte(pdev, 0x4b, &tmp);
 197                         if (tmp & 0x20)
 198                                 break;
 199                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 200                 }
 201                 break;
 202         case PCI_VENDOR_ID_ATI:
 203                 /* AMD PLL quirk */
 204                 if (usb_amd_find_chipset_info())
 205                         ehci->amd_pll_fix = 1;
 206                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 207                  * which causes usb devices lose response in some cases.
 208                  */
 209                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
 210                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 211                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 212                                                  NULL);
 213                         if (!p_smbus)
 214                                 break;
 215                         rev = p_smbus->revision;
 216                         if ((pdev->device == 0x4386) || (rev == 0x3a)
 217                             || (rev == 0x3b)) {
 218                                 u8 tmp;
 219                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
 220                                         "freeze workaround\n");
 221                                 pci_read_config_byte(pdev, 0x53, &tmp);
 222                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 223                         }
 224                         pci_dev_put(p_smbus);
 225                 }
 226                 break;
 227         case PCI_VENDOR_ID_NETMOS:
 228                 /* MosChip frame-index-register bug */
 229                 ehci_info(ehci, "applying MosChip frame-index workaround\n");
 230                 ehci->frame_index_bug = 1;
 231                 break;
 232         }
 233
 234         /* optional debug port, normally in the first BAR */
 235         temp = pci_find_capability(pdev, 0x0a);
 236         if (temp) {
 237                 pci_read_config_dword(pdev, temp, &temp);
 238                 temp >>= 16;
 239                 if ((temp & (3 << 13)) == (1 << 13)) {
 240                         temp &= 0x1fff;
 241                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
 242                         temp = ehci_readl(ehci, &ehci->debug->control);
 243                         ehci_info(ehci, "debug port %d%s\n",
 244                                 HCS_DEBUG_PORT(ehci->hcs_params),
 245                                 (temp & DBGP_ENABLED)
 246                                         ? " IN USE"
 247                                         : "");
 248                         if (!(temp & DBGP_ENABLED))
 249                                 ehci->debug = NULL;
 250                 }
 251         }
 252
 253         ehci_reset(ehci);
 254
 255         /* at least the Genesys GL880S needs fixup here */
 256         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 257         temp &= 0x0f;
 258         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 259                 ehci_dbg(ehci, "bogus port configuration: "
 260                         "cc=%d x pcc=%d < ports=%d\n",
 261                         HCS_N_CC(ehci->hcs_params),
 262                         HCS_N_PCC(ehci->hcs_params),
 263                         HCS_N_PORTS(ehci->hcs_params));
 264
 265                 switch (pdev->vendor) {
 266                 case 0x17a0:            /* GENESYS */
 267                         /* GL880S: should be PORTS=2 */
 268                         temp |= (ehci->hcs_params & ~0xf);
 269                         ehci->hcs_params = temp;
 270                         break;
 271                 case PCI_VENDOR_ID_NVIDIA:
 272                         /* NF4: should be PCC=10 */
 273                         break;
 274                 }
 275         }
 276
 277         /* Serial Bus Release Number is at PCI 0x60 offset */
 278         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 279         if (pdev->vendor == PCI_VENDOR_ID_STMICRO
 280             && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
 281                 ehci->sbrn = 0x20; /* ConneXT has no sbrn register */
 282
 283         /* Keep this around for a while just in case some EHCI
 284          * implementation uses legacy PCI PM support.  This test
 285          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 286          * been triggered by then.
 287          */
 288         if (!device_can_wakeup(&pdev->dev)) {
 289                 u16     port_wake;
 290
 291                 pci_read_config_word(pdev, 0x62, &port_wake);
 292                 if (port_wake & 0x0001) {
 293                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 294                         device_set_wakeup_capable(&pdev->dev, 1);
 295                 }
 296         }
 297
 298 #ifdef  CONFIG_USB_SUSPEND
 299         /* REVISIT: the controller works fine for wakeup iff the root hub
 300          * itself is "globally" suspended, but usbcore currently doesn't
 301          * understand such things.
 302          *
 303          * System suspend currently expects to be able to suspend the entire
 304          * device tree, device-at-a-time.  If we failed selective suspend
 305          * reports, system suspend would fail; so the root hub code must claim
 306          * success.  That's lying to usbcore, and it matters for runtime
 307          * PM scenarios with selective suspend and remote wakeup...
 308          */
 309         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 310                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 311 #endif
 312
 313         ehci_port_power(ehci, 1);
 314         retval = ehci_pci_reinit(ehci, pdev);
 315 done:
 316         return retval;
 317 }
 318
 319 /*-------------------------------------------------------------------------*/
 320
 321 #ifdef  CONFIG_PM
 322
 323 /* suspend/resume, section 4.3 */
 324
 325 /* These routines rely on the PCI bus glue
 326  * to handle powerdown and wakeup, and currently also on
 327  * transceivers that don't need any software attention to set up
 328  * the right sort of wakeup.
 329  * Also they depend on separate root hub suspend/resume.
 330  */
 331
 332 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 333 {
 334         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 335         unsigned long           flags;
 336         int                     rc = 0;
 337
 338         if (time_before(jiffies, ehci->next_statechange))
 339                 msleep(10);
 340
 341         /* Root hub was already suspended. Disable irq emission and
 342          * mark HW unaccessible.  The PM and USB cores make sure that
 343          * the root hub is either suspended or stopped.
 344          */
 345         ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
 346         spin_lock_irqsave (&ehci->lock, flags);
 347         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 348         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 349
 350         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 351         spin_unlock_irqrestore (&ehci->lock, flags);
 352
 353         // could save FLADJ in case of Vaux power loss
 354         // ... we'd only use it to handle clock skew
 355
 356         return rc;
 357 }
 358
 359 static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
 360 {
 361         return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
 362                 pdev->vendor == PCI_VENDOR_ID_INTEL &&
 363                 pdev->device == 0x1E26;
 364 }
 365
 366 static void ehci_enable_xhci_companion(void)
 367 {
 368         struct pci_dev          *companion = NULL;
 369
 370         /* The xHCI and EHCI controllers are not on the same PCI slot */
 371         for_each_pci_dev(companion) {
 372                 if (!usb_is_intel_switchable_xhci(companion))
 373                         continue;
 374                 usb_enable_xhci_ports(companion);
 375                 return;
 376         }
 377 }
 378
 379 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 380 {
 381         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 382         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 383
 384         /* The BIOS on systems with the Intel Panther Point chipset may or may
 385          * not support xHCI natively.  That means that during system resume, it
 386          * may switch the ports back to EHCI so that users can use their
 387          * keyboard to select a kernel from GRUB after resume from hibernate.
 388          *
 389          * The BIOS is supposed to remember whether the OS had xHCI ports
 390          * enabled before resume, and switch the ports back to xHCI when the
 391          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 392          * writers.
 393          *
 394          * Unconditionally switch the ports back to xHCI after a system resume.
 395          * We can't tell whether the EHCI or xHCI controller will be resumed
 396          * first, so we have to do the port switchover in both drivers.  Writing
 397          * a '1' to the port switchover registers should have no effect if the
 398          * port was already switched over.
 399          */
 400         if (usb_is_intel_switchable_ehci(pdev))
 401                 ehci_enable_xhci_companion();
 402
 403         // maybe restore FLADJ
 404
 405         if (time_before(jiffies, ehci->next_statechange))
 406                 msleep(100);
 407
 408         /* Mark hardware accessible again as we are out of D3 state by now */
 409         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 410
 411         /* If CF is still set and we aren't resuming from hibernation
 412          * then we maintained PCI Vaux power.
 413          * Just undo the effect of ehci_pci_suspend().
 414          */
 415         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
 416                                 !hibernated) {
 417                 int     mask = INTR_MASK;
 418
 419                 ehci_prepare_ports_for_controller_resume(ehci);
 420                 if (!hcd->self.root_hub->do_remote_wakeup)
 421                         mask &= ~STS_PCD;
 422                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 423                 ehci_readl(ehci, &ehci->regs->intr_enable);
 424                 return 0;
 425         }
 426
 427         usb_root_hub_lost_power(hcd->self.root_hub);
 428
 429         /* Else reset, to cope with power loss or flush-to-storage
 430          * style "resume" having let BIOS kick in during reboot.
 431          */
 432         (void) ehci_halt(ehci);
 433         (void) ehci_reset(ehci);
 434         (void) ehci_pci_reinit(ehci, pdev);
 435
 436         /* emptying the schedule aborts any urbs */
 437         spin_lock_irq(&ehci->lock);
 438         if (ehci->reclaim)
 439                 end_unlink_async(ehci);
 440         ehci_work(ehci);
 441         spin_unlock_irq(&ehci->lock);
 442
 443         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 444         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 445         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 446
 447         /* here we "know" root ports should always stay powered */
 448         ehci_port_power(ehci, 1);
 449
 450         ehci->rh_state = EHCI_RH_SUSPENDED;
 451         return 0;
 452 }
 453 #endif
 454
 455 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
 456 {
 457         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 458         int rc = 0;
 459
 460         if (!udev->parent) /* udev is root hub itself, impossible */
 461                 rc = -1;
 462         /* we only support lpm device connected to root hub yet */
 463         if (ehci->has_lpm && !udev->parent->parent) {
 464                 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
 465                 if (!rc)
 466                         rc = ehci_lpm_check(ehci, udev->portnum);
 467         }
 468         return rc;
 469 }
 470
 471 static const struct hc_driver ehci_pci_hc_driver = {
 472         .description =          hcd_name,
 473         .product_desc =         "EHCI Host Controller",
 474         .hcd_priv_size =        sizeof(struct ehci_hcd),
 475
 476         /*
 477          * generic hardware linkage
 478          */
 479         .irq =                  ehci_irq,
 480         .flags =                HCD_MEMORY | HCD_USB2,
 481
 482         /*
 483          * basic lifecycle operations
 484          */
 485         .reset =                ehci_pci_setup,
 486         .start =                ehci_run,
 487 #ifdef  CONFIG_PM
 488         .pci_suspend =          ehci_pci_suspend,
 489         .pci_resume =           ehci_pci_resume,
 490 #endif
 491         .stop =                 ehci_stop,
 492         .shutdown =             ehci_shutdown,
 493
 494         /*
 495          * managing i/o requests and associated device resources
 496          */
 497         .urb_enqueue =          ehci_urb_enqueue,
 498         .urb_dequeue =          ehci_urb_dequeue,
 499         .endpoint_disable =     ehci_endpoint_disable,
 500         .endpoint_reset =       ehci_endpoint_reset,
 501
 502         /*
 503          * scheduling support
 504          */
 505         .get_frame_number =     ehci_get_frame,
 506
 507         /*
 508          * root hub support
 509          */
 510         .hub_status_data =      ehci_hub_status_data,
 511         .hub_control =          ehci_hub_control,
 512         .bus_suspend =          ehci_bus_suspend,
 513         .bus_resume =           ehci_bus_resume,
 514         .relinquish_port =      ehci_relinquish_port,
 515         .port_handed_over =     ehci_port_handed_over,
 516
 517         /*
 518          * call back when device connected and addressed
 519          */
 520         .update_device =        ehci_update_device,
 521
 522         .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
 523 };
 524
 525 /*-------------------------------------------------------------------------*/
 526
 527 /* PCI driver selection metadata; PCI hotplugging uses this */
 528 static const struct pci_device_id pci_ids [] = { {
 529         /* handle any USB 2.0 EHCI controller */
 530         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 531         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 532         }, {
 533         PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
 534         .driver_data = (unsigned long) &ehci_pci_hc_driver,
 535         },
 536         { /* end: all zeroes */ }
 537 };
 538 MODULE_DEVICE_TABLE(pci, pci_ids);
 539
 540 /* pci driver glue; this is a "new style" PCI driver module */
 541 static struct pci_driver ehci_pci_driver = {
 542         .name =         (char *) hcd_name,
 543         .id_table =     pci_ids,
 544
 545         .probe =        usb_hcd_pci_probe,
 546         .remove =       usb_hcd_pci_remove,
 547         .shutdown =     usb_hcd_pci_shutdown,
 548
 549 #ifdef CONFIG_PM_SLEEP
 550         .driver =       {
 551                 .pm =   &usb_hcd_pci_pm_ops
 552         },
 553 #endif
 554 };