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memcg: always create memsw files if CONFIG_CGROUP_MEM_RES_CTLR_SWAP
[linux-2.6.git] / drivers / ata / ata_piix.c
blob68013f96729ffc624aad80342ec92af6768b89fa
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
129
130 PIIX_AHCI_DEVICE = 6,
131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 };
135
136 enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
144 ich5_sata,
145 ich6_sata,
146 ich6m_sata,
147 ich8_sata,
148 ich8_2port_sata,
149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152 ich8_sata_snb,
153 };
154
155 struct piix_map_db {
156 const u32 mask;
157 const u16 port_enable;
158 const int map[][4];
159 };
160
161 struct piix_host_priv {
162 const int *map;
163 u32 saved_iocfg;
164 void __iomem *sidpr;
165 };
166
167 static int piix_init_one(struct pci_dev *pdev,
168 const struct pci_device_id *ent);
169 static void piix_remove_one(struct pci_dev *pdev);
170 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
171 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
172 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
173 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
174 static int ich_pata_cable_detect(struct ata_port *ap);
175 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
176 static int piix_sidpr_scr_read(struct ata_link *link,
177 unsigned int reg, u32 *val);
178 static int piix_sidpr_scr_write(struct ata_link *link,
179 unsigned int reg, u32 val);
180 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
181 unsigned hints);
182 static bool piix_irq_check(struct ata_port *ap);
183 static int piix_port_start(struct ata_port *ap);
184 #ifdef CONFIG_PM
185 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
186 static int piix_pci_device_resume(struct pci_dev *pdev);
187 #endif
188
189 static unsigned int in_module_init = 1;
190
191 static const struct pci_device_id piix_pci_tbl[] = {
192 /* Intel PIIX3 for the 430HX etc */
193 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
194 /* VMware ICH4 */
195 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
196 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
197 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
198 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
199 /* Intel PIIX4 */
200 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
201 /* Intel PIIX4 */
202 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
203 /* Intel PIIX */
204 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
205 /* Intel ICH (i810, i815, i840) UDMA 66*/
206 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
207 /* Intel ICH0 : UDMA 33*/
208 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
209 /* Intel ICH2M */
210 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
212 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH3M */
214 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 /* Intel ICH3 (E7500/1) UDMA 100 */
216 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* Intel ICH4-L */
218 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
220 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
222 /* Intel ICH5 */
223 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
224 /* C-ICH (i810E2) */
225 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
226 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
227 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
228 /* ICH6 (and 6) (i915) UDMA 100 */
229 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
230 /* ICH7/7-R (i945, i975) UDMA 100*/
231 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
232 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
233 /* ICH8 Mobile PATA Controller */
234 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
235
236 /* SATA ports */
237
238 /* 82801EB (ICH5) */
239 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
240 /* 82801EB (ICH5) */
241 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
242 /* 6300ESB (ICH5 variant with broken PCS present bits) */
243 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
244 /* 6300ESB pretending RAID */
245 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
246 /* 82801FB/FW (ICH6/ICH6W) */
247 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* 82801FR/FRW (ICH6R/ICH6RW) */
249 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
250 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
251 * Attach iff the controller is in IDE mode. */
252 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
253 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
254 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
255 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
256 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
257 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
258 /* Enterprise Southbridge 2 (631xESB/632xESB) */
259 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
260 /* SATA Controller 1 IDE (ICH8) */
261 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
262 /* SATA Controller 2 IDE (ICH8) */
263 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* Mobile SATA Controller IDE (ICH8M), Apple */
265 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
266 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
267 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
268 /* Mobile SATA Controller IDE (ICH8M) */
269 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
270 /* SATA Controller IDE (ICH9) */
271 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (ICH9) */
273 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH9) */
275 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (ICH9M) */
277 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (ICH9M) */
279 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (ICH9M) */
281 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (Tolapai) */
283 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
284 /* SATA Controller IDE (ICH10) */
285 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
286 /* SATA Controller IDE (ICH10) */
287 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (ICH10) */
289 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
290 /* SATA Controller IDE (ICH10) */
291 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
296 /* SATA Controller IDE (PCH) */
297 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
298 /* SATA Controller IDE (PCH) */
299 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
300 /* SATA Controller IDE (PCH) */
301 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (PCH) */
303 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
304 /* SATA Controller IDE (CPT) */
305 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
306 /* SATA Controller IDE (CPT) */
307 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
308 /* SATA Controller IDE (CPT) */
309 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
310 /* SATA Controller IDE (CPT) */
311 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
312 /* SATA Controller IDE (PBG) */
313 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
314 /* SATA Controller IDE (PBG) */
315 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
316 /* SATA Controller IDE (Panther Point) */
317 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
318 /* SATA Controller IDE (Panther Point) */
319 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
320 /* SATA Controller IDE (Panther Point) */
321 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
322 /* SATA Controller IDE (Panther Point) */
323 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
324 /* SATA Controller IDE (Lynx Point) */
325 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
326 /* SATA Controller IDE (Lynx Point) */
327 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
328 /* SATA Controller IDE (Lynx Point) */
329 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
330 /* SATA Controller IDE (Lynx Point) */
331 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
332 { } /* terminate list */
333 };
334
335 static struct pci_driver piix_pci_driver = {
336 .name = DRV_NAME,
337 .id_table = piix_pci_tbl,
338 .probe = piix_init_one,
339 .remove = piix_remove_one,
340 #ifdef CONFIG_PM
341 .suspend = piix_pci_device_suspend,
342 .resume = piix_pci_device_resume,
343 #endif
344 };
345
346 static struct scsi_host_template piix_sht = {
347 ATA_BMDMA_SHT(DRV_NAME),
348 };
349
350 static struct ata_port_operations piix_sata_ops = {
351 .inherits = &ata_bmdma32_port_ops,
352 .sff_irq_check = piix_irq_check,
353 .port_start = piix_port_start,
354 };
355
356 static struct ata_port_operations piix_pata_ops = {
357 .inherits = &piix_sata_ops,
358 .cable_detect = ata_cable_40wire,
359 .set_piomode = piix_set_piomode,
360 .set_dmamode = piix_set_dmamode,
361 .prereset = piix_pata_prereset,
362 };
363
364 static struct ata_port_operations piix_vmw_ops = {
365 .inherits = &piix_pata_ops,
366 .bmdma_status = piix_vmw_bmdma_status,
367 };
368
369 static struct ata_port_operations ich_pata_ops = {
370 .inherits = &piix_pata_ops,
371 .cable_detect = ich_pata_cable_detect,
372 .set_dmamode = ich_set_dmamode,
373 };
374
375 static struct device_attribute *piix_sidpr_shost_attrs[] = {
376 &dev_attr_link_power_management_policy,
377 NULL
378 };
379
380 static struct scsi_host_template piix_sidpr_sht = {
381 ATA_BMDMA_SHT(DRV_NAME),
382 .shost_attrs = piix_sidpr_shost_attrs,
383 };
384
385 static struct ata_port_operations piix_sidpr_sata_ops = {
386 .inherits = &piix_sata_ops,
387 .hardreset = sata_std_hardreset,
388 .scr_read = piix_sidpr_scr_read,
389 .scr_write = piix_sidpr_scr_write,
390 .set_lpm = piix_sidpr_set_lpm,
391 };
392
393 static const struct piix_map_db ich5_map_db = {
394 .mask = 0x7,
395 .port_enable = 0x3,
396 .map = {
397 /* PM PS SM SS MAP */
398 { P0, NA, P1, NA }, /* 000b */
399 { P1, NA, P0, NA }, /* 001b */
400 { RV, RV, RV, RV },
401 { RV, RV, RV, RV },
402 { P0, P1, IDE, IDE }, /* 100b */
403 { P1, P0, IDE, IDE }, /* 101b */
404 { IDE, IDE, P0, P1 }, /* 110b */
405 { IDE, IDE, P1, P0 }, /* 111b */
406 },
407 };
408
409 static const struct piix_map_db ich6_map_db = {
410 .mask = 0x3,
411 .port_enable = 0xf,
412 .map = {
413 /* PM PS SM SS MAP */
414 { P0, P2, P1, P3 }, /* 00b */
415 { IDE, IDE, P1, P3 }, /* 01b */
416 { P0, P2, IDE, IDE }, /* 10b */
417 { RV, RV, RV, RV },
418 },
419 };
420
421 static const struct piix_map_db ich6m_map_db = {
422 .mask = 0x3,
423 .port_enable = 0x5,
424
425 /* Map 01b isn't specified in the doc but some notebooks use
426 * it anyway. MAP 01b have been spotted on both ICH6M and
427 * ICH7M.
428 */
429 .map = {
430 /* PM PS SM SS MAP */
431 { P0, P2, NA, NA }, /* 00b */
432 { IDE, IDE, P1, P3 }, /* 01b */
433 { P0, P2, IDE, IDE }, /* 10b */
434 { RV, RV, RV, RV },
435 },
436 };
437
438 static const struct piix_map_db ich8_map_db = {
439 .mask = 0x3,
440 .port_enable = 0xf,
441 .map = {
442 /* PM PS SM SS MAP */
443 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
444 { RV, RV, RV, RV },
445 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
446 { RV, RV, RV, RV },
447 },
448 };
449
450 static const struct piix_map_db ich8_2port_map_db = {
451 .mask = 0x3,
452 .port_enable = 0x3,
453 .map = {
454 /* PM PS SM SS MAP */
455 { P0, NA, P1, NA }, /* 00b */
456 { RV, RV, RV, RV }, /* 01b */
457 { RV, RV, RV, RV }, /* 10b */
458 { RV, RV, RV, RV },
459 },
460 };
461
462 static const struct piix_map_db ich8m_apple_map_db = {
463 .mask = 0x3,
464 .port_enable = 0x1,
465 .map = {
466 /* PM PS SM SS MAP */
467 { P0, NA, NA, NA }, /* 00b */
468 { RV, RV, RV, RV },
469 { P0, P2, IDE, IDE }, /* 10b */
470 { RV, RV, RV, RV },
471 },
472 };
473
474 static const struct piix_map_db tolapai_map_db = {
475 .mask = 0x3,
476 .port_enable = 0x3,
477 .map = {
478 /* PM PS SM SS MAP */
479 { P0, NA, P1, NA }, /* 00b */
480 { RV, RV, RV, RV }, /* 01b */
481 { RV, RV, RV, RV }, /* 10b */
482 { RV, RV, RV, RV },
483 },
484 };
485
486 static const struct piix_map_db *piix_map_db_table[] = {
487 [ich5_sata] = &ich5_map_db,
488 [ich6_sata] = &ich6_map_db,
489 [ich6m_sata] = &ich6m_map_db,
490 [ich8_sata] = &ich8_map_db,
491 [ich8_2port_sata] = &ich8_2port_map_db,
492 [ich8m_apple_sata] = &ich8m_apple_map_db,
493 [tolapai_sata] = &tolapai_map_db,
494 [ich8_sata_snb] = &ich8_map_db,
495 };
496
497 static struct ata_port_info piix_port_info[] = {
498 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
499 {
500 .flags = PIIX_PATA_FLAGS,
501 .pio_mask = ATA_PIO4,
502 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
503 .port_ops = &piix_pata_ops,
504 },
505
506 [piix_pata_33] = /* PIIX4 at 33MHz */
507 {
508 .flags = PIIX_PATA_FLAGS,
509 .pio_mask = ATA_PIO4,
510 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
511 .udma_mask = ATA_UDMA2,
512 .port_ops = &piix_pata_ops,
513 },
514
515 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
516 {
517 .flags = PIIX_PATA_FLAGS,
518 .pio_mask = ATA_PIO4,
519 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
520 .udma_mask = ATA_UDMA2,
521 .port_ops = &ich_pata_ops,
522 },
523
524 [ich_pata_66] = /* ICH controllers up to 66MHz */
525 {
526 .flags = PIIX_PATA_FLAGS,
527 .pio_mask = ATA_PIO4,
528 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
529 .udma_mask = ATA_UDMA4,
530 .port_ops = &ich_pata_ops,
531 },
532
533 [ich_pata_100] =
534 {
535 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
536 .pio_mask = ATA_PIO4,
537 .mwdma_mask = ATA_MWDMA12_ONLY,
538 .udma_mask = ATA_UDMA5,
539 .port_ops = &ich_pata_ops,
540 },
541
542 [ich_pata_100_nomwdma1] =
543 {
544 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
545 .pio_mask = ATA_PIO4,
546 .mwdma_mask = ATA_MWDMA2_ONLY,
547 .udma_mask = ATA_UDMA5,
548 .port_ops = &ich_pata_ops,
549 },
550
551 [ich5_sata] =
552 {
553 .flags = PIIX_SATA_FLAGS,
554 .pio_mask = ATA_PIO4,
555 .mwdma_mask = ATA_MWDMA2,
556 .udma_mask = ATA_UDMA6,
557 .port_ops = &piix_sata_ops,
558 },
559
560 [ich6_sata] =
561 {
562 .flags = PIIX_SATA_FLAGS,
563 .pio_mask = ATA_PIO4,
564 .mwdma_mask = ATA_MWDMA2,
565 .udma_mask = ATA_UDMA6,
566 .port_ops = &piix_sata_ops,
567 },
568
569 [ich6m_sata] =
570 {
571 .flags = PIIX_SATA_FLAGS,
572 .pio_mask = ATA_PIO4,
573 .mwdma_mask = ATA_MWDMA2,
574 .udma_mask = ATA_UDMA6,
575 .port_ops = &piix_sata_ops,
576 },
577
578 [ich8_sata] =
579 {
580 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
581 .pio_mask = ATA_PIO4,
582 .mwdma_mask = ATA_MWDMA2,
583 .udma_mask = ATA_UDMA6,
584 .port_ops = &piix_sata_ops,
585 },
586
587 [ich8_2port_sata] =
588 {
589 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
590 .pio_mask = ATA_PIO4,
591 .mwdma_mask = ATA_MWDMA2,
592 .udma_mask = ATA_UDMA6,
593 .port_ops = &piix_sata_ops,
594 },
595
596 [tolapai_sata] =
597 {
598 .flags = PIIX_SATA_FLAGS,
599 .pio_mask = ATA_PIO4,
600 .mwdma_mask = ATA_MWDMA2,
601 .udma_mask = ATA_UDMA6,
602 .port_ops = &piix_sata_ops,
603 },
604
605 [ich8m_apple_sata] =
606 {
607 .flags = PIIX_SATA_FLAGS,
608 .pio_mask = ATA_PIO4,
609 .mwdma_mask = ATA_MWDMA2,
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &piix_sata_ops,
612 },
613
614 [piix_pata_vmw] =
615 {
616 .flags = PIIX_PATA_FLAGS,
617 .pio_mask = ATA_PIO4,
618 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
619 .udma_mask = ATA_UDMA2,
620 .port_ops = &piix_vmw_ops,
621 },
622
623 /*
624 * some Sandybridge chipsets have broken 32 mode up to now,
625 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
626 */
627 [ich8_sata_snb] =
628 {
629 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
630 .pio_mask = ATA_PIO4,
631 .mwdma_mask = ATA_MWDMA2,
632 .udma_mask = ATA_UDMA6,
633 .port_ops = &piix_sata_ops,
634 },
635
636 };
637
638 static struct pci_bits piix_enable_bits[] = {
639 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
640 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
641 };
642
643 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
644 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
645 MODULE_LICENSE("GPL");
646 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
647 MODULE_VERSION(DRV_VERSION);
648
649 struct ich_laptop {
650 u16 device;
651 u16 subvendor;
652 u16 subdevice;
653 };
654
655 /*
656 * List of laptops that use short cables rather than 80 wire
657 */
658
659 static const struct ich_laptop ich_laptop[] = {
660 /* devid, subvendor, subdev */
661 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
662 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
663 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
664 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
665 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
666 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
667 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
668 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
669 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
670 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
671 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
672 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
673 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
674 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
675 /* end marker */
676 { 0, }
677 };
678
679 static int piix_port_start(struct ata_port *ap)
680 {
681 if (!(ap->flags & PIIX_FLAG_PIO16))
682 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
683
684 return ata_bmdma_port_start(ap);
685 }
686
687 /**
688 * ich_pata_cable_detect - Probe host controller cable detect info
689 * @ap: Port for which cable detect info is desired
690 *
691 * Read 80c cable indicator from ATA PCI device's PCI config
692 * register. This register is normally set by firmware (BIOS).
693 *
694 * LOCKING:
695 * None (inherited from caller).
696 */
697
698 static int ich_pata_cable_detect(struct ata_port *ap)
699 {
700 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
701 struct piix_host_priv *hpriv = ap->host->private_data;
702 const struct ich_laptop *lap = &ich_laptop[0];
703 u8 mask;
704
705 /* Check for specials - Acer Aspire 5602WLMi */
706 while (lap->device) {
707 if (lap->device == pdev->device &&
708 lap->subvendor == pdev->subsystem_vendor &&
709 lap->subdevice == pdev->subsystem_device)
710 return ATA_CBL_PATA40_SHORT;
711
712 lap++;
713 }
714
715 /* check BIOS cable detect results */
716 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
717 if ((hpriv->saved_iocfg & mask) == 0)
718 return ATA_CBL_PATA40;
719 return ATA_CBL_PATA80;
720 }
721
722 /**
723 * piix_pata_prereset - prereset for PATA host controller
724 * @link: Target link
725 * @deadline: deadline jiffies for the operation
726 *
727 * LOCKING:
728 * None (inherited from caller).
729 */
730 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
731 {
732 struct ata_port *ap = link->ap;
733 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
734
735 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
736 return -ENOENT;
737 return ata_sff_prereset(link, deadline);
738 }
739
740 static DEFINE_SPINLOCK(piix_lock);
741
742 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
743 u8 pio)
744 {
745 struct pci_dev *dev = to_pci_dev(ap->host->dev);
746 unsigned long flags;
747 unsigned int is_slave = (adev->devno != 0);
748 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
749 unsigned int slave_port = 0x44;
750 u16 master_data;
751 u8 slave_data;
752 u8 udma_enable;
753 int control = 0;
754
755 /*
756 * See Intel Document 298600-004 for the timing programing rules
757 * for ICH controllers.
758 */
759
760 static const /* ISP RTC */
761 u8 timings[][2] = { { 0, 0 },
762 { 0, 0 },
763 { 1, 0 },
764 { 2, 1 },
765 { 2, 3 }, };
766
767 if (pio >= 2)
768 control |= 1; /* TIME1 enable */
769 if (ata_pio_need_iordy(adev))
770 control |= 2; /* IE enable */
771 /* Intel specifies that the PPE functionality is for disk only */
772 if (adev->class == ATA_DEV_ATA)
773 control |= 4; /* PPE enable */
774 /*
775 * If the drive MWDMA is faster than it can do PIO then
776 * we must force PIO into PIO0
777 */
778 if (adev->pio_mode < XFER_PIO_0 + pio)
779 /* Enable DMA timing only */
780 control |= 8; /* PIO cycles in PIO0 */
781
782 spin_lock_irqsave(&piix_lock, flags);
783
784 /* PIO configuration clears DTE unconditionally. It will be
785 * programmed in set_dmamode which is guaranteed to be called
786 * after set_piomode if any DMA mode is available.
787 */
788 pci_read_config_word(dev, master_port, &master_data);
789 if (is_slave) {
790 /* clear TIME1|IE1|PPE1|DTE1 */
791 master_data &= 0xff0f;
792 /* enable PPE1, IE1 and TIME1 as needed */
793 master_data |= (control << 4);
794 pci_read_config_byte(dev, slave_port, &slave_data);
795 slave_data &= (ap->port_no ? 0x0f : 0xf0);
796 /* Load the timing nibble for this slave */
797 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
798 << (ap->port_no ? 4 : 0);
799 } else {
800 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
801 master_data &= 0xccf0;
802 /* Enable PPE, IE and TIME as appropriate */
803 master_data |= control;
804 /* load ISP and RCT */
805 master_data |=
806 (timings[pio][0] << 12) |
807 (timings[pio][1] << 8);
808 }
809
810 /* Enable SITRE (separate slave timing register) */
811 master_data |= 0x4000;
812 pci_write_config_word(dev, master_port, master_data);
813 if (is_slave)
814 pci_write_config_byte(dev, slave_port, slave_data);
815
816 /* Ensure the UDMA bit is off - it will be turned back on if
817 UDMA is selected */
818
819 if (ap->udma_mask) {
820 pci_read_config_byte(dev, 0x48, &udma_enable);
821 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
822 pci_write_config_byte(dev, 0x48, udma_enable);
823 }
824
825 spin_unlock_irqrestore(&piix_lock, flags);
826 }
827
828 /**
829 * piix_set_piomode - Initialize host controller PATA PIO timings
830 * @ap: Port whose timings we are configuring
831 * @adev: Drive in question
832 *
833 * Set PIO mode for device, in host controller PCI config space.
834 *
835 * LOCKING:
836 * None (inherited from caller).
837 */
838
839 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
840 {
841 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
842 }
843
844 /**
845 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
846 * @ap: Port whose timings we are configuring
847 * @adev: Drive in question
848 * @isich: set if the chip is an ICH device
849 *
850 * Set UDMA mode for device, in host controller PCI config space.
851 *
852 * LOCKING:
853 * None (inherited from caller).
854 */
855
856 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
857 {
858 struct pci_dev *dev = to_pci_dev(ap->host->dev);
859 unsigned long flags;
860 u8 speed = adev->dma_mode;
861 int devid = adev->devno + 2 * ap->port_no;
862 u8 udma_enable = 0;
863
864 if (speed >= XFER_UDMA_0) {
865 unsigned int udma = speed - XFER_UDMA_0;
866 u16 udma_timing;
867 u16 ideconf;
868 int u_clock, u_speed;
869
870 spin_lock_irqsave(&piix_lock, flags);
871
872 pci_read_config_byte(dev, 0x48, &udma_enable);
873
874 /*
875 * UDMA is handled by a combination of clock switching and
876 * selection of dividers
877 *
878 * Handy rule: Odd modes are UDMATIMx 01, even are 02
879 * except UDMA0 which is 00
880 */
881 u_speed = min(2 - (udma & 1), udma);
882 if (udma == 5)
883 u_clock = 0x1000; /* 100Mhz */
884 else if (udma > 2)
885 u_clock = 1; /* 66Mhz */
886 else
887 u_clock = 0; /* 33Mhz */
888
889 udma_enable |= (1 << devid);
890
891 /* Load the CT/RP selection */
892 pci_read_config_word(dev, 0x4A, &udma_timing);
893 udma_timing &= ~(3 << (4 * devid));
894 udma_timing |= u_speed << (4 * devid);
895 pci_write_config_word(dev, 0x4A, udma_timing);
896
897 if (isich) {
898 /* Select a 33/66/100Mhz clock */
899 pci_read_config_word(dev, 0x54, &ideconf);
900 ideconf &= ~(0x1001 << devid);
901 ideconf |= u_clock << devid;
902 /* For ICH or later we should set bit 10 for better
903 performance (WR_PingPong_En) */
904 pci_write_config_word(dev, 0x54, ideconf);
905 }
906
907 pci_write_config_byte(dev, 0x48, udma_enable);
908
909 spin_unlock_irqrestore(&piix_lock, flags);
910 } else {
911 /* MWDMA is driven by the PIO timings. */
912 unsigned int mwdma = speed - XFER_MW_DMA_0;
913 const unsigned int needed_pio[3] = {
914 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
915 };
916 int pio = needed_pio[mwdma] - XFER_PIO_0;
917
918 /* XFER_PIO_0 is never used currently */
919 piix_set_timings(ap, adev, pio);
920 }
921 }
922
923 /**
924 * piix_set_dmamode - Initialize host controller PATA DMA timings
925 * @ap: Port whose timings we are configuring
926 * @adev: um
927 *
928 * Set MW/UDMA mode for device, in host controller PCI config space.
929 *
930 * LOCKING:
931 * None (inherited from caller).
932 */
933
934 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
935 {
936 do_pata_set_dmamode(ap, adev, 0);
937 }
938
939 /**
940 * ich_set_dmamode - Initialize host controller PATA DMA timings
941 * @ap: Port whose timings we are configuring
942 * @adev: um
943 *
944 * Set MW/UDMA mode for device, in host controller PCI config space.
945 *
946 * LOCKING:
947 * None (inherited from caller).
948 */
949
950 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
951 {
952 do_pata_set_dmamode(ap, adev, 1);
953 }
954
955 /*
956 * Serial ATA Index/Data Pair Superset Registers access
957 *
958 * Beginning from ICH8, there's a sane way to access SCRs using index
959 * and data register pair located at BAR5 which means that we have
960 * separate SCRs for master and slave. This is handled using libata
961 * slave_link facility.
962 */
963 static const int piix_sidx_map[] = {
964 [SCR_STATUS] = 0,
965 [SCR_ERROR] = 2,
966 [SCR_CONTROL] = 1,
967 };
968
969 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
970 {
971 struct ata_port *ap = link->ap;
972 struct piix_host_priv *hpriv = ap->host->private_data;
973
974 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
975 hpriv->sidpr + PIIX_SIDPR_IDX);
976 }
977
978 static int piix_sidpr_scr_read(struct ata_link *link,
979 unsigned int reg, u32 *val)
980 {
981 struct piix_host_priv *hpriv = link->ap->host->private_data;
982
983 if (reg >= ARRAY_SIZE(piix_sidx_map))
984 return -EINVAL;
985
986 piix_sidpr_sel(link, reg);
987 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
988 return 0;
989 }
990
991 static int piix_sidpr_scr_write(struct ata_link *link,
992 unsigned int reg, u32 val)
993 {
994 struct piix_host_priv *hpriv = link->ap->host->private_data;
995
996 if (reg >= ARRAY_SIZE(piix_sidx_map))
997 return -EINVAL;
998
999 piix_sidpr_sel(link, reg);
1000 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1001 return 0;
1002 }
1003
1004 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
1005 unsigned hints)
1006 {
1007 return sata_link_scr_lpm(link, policy, false);
1008 }
1009
1010 static bool piix_irq_check(struct ata_port *ap)
1011 {
1012 if (unlikely(!ap->ioaddr.bmdma_addr))
1013 return false;
1014
1015 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1016 }
1017
1018 #ifdef CONFIG_PM
1019 static int piix_broken_suspend(void)
1020 {
1021 static const struct dmi_system_id sysids[] = {
1022 {
1023 .ident = "TECRA M3",
1024 .matches = {
1025 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1026 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1027 },
1028 },
1029 {
1030 .ident = "TECRA M3",
1031 .matches = {
1032 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1033 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1034 },
1035 },
1036 {
1037 .ident = "TECRA M4",
1038 .matches = {
1039 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1040 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1041 },
1042 },
1043 {
1044 .ident = "TECRA M4",
1045 .matches = {
1046 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1047 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1048 },
1049 },
1050 {
1051 .ident = "TECRA M5",
1052 .matches = {
1053 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1054 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1055 },
1056 },
1057 {
1058 .ident = "TECRA M6",
1059 .matches = {
1060 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1061 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1062 },
1063 },
1064 {
1065 .ident = "TECRA M7",
1066 .matches = {
1067 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1068 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1069 },
1070 },
1071 {
1072 .ident = "TECRA A8",
1073 .matches = {
1074 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1075 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1076 },
1077 },
1078 {
1079 .ident = "Satellite R20",
1080 .matches = {
1081 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1082 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1083 },
1084 },
1085 {
1086 .ident = "Satellite R25",
1087 .matches = {
1088 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1089 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1090 },
1091 },
1092 {
1093 .ident = "Satellite U200",
1094 .matches = {
1095 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1096 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1097 },
1098 },
1099 {
1100 .ident = "Satellite U200",
1101 .matches = {
1102 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1103 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1104 },
1105 },
1106 {
1107 .ident = "Satellite Pro U200",
1108 .matches = {
1109 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1110 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1111 },
1112 },
1113 {
1114 .ident = "Satellite U205",
1115 .matches = {
1116 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1117 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1118 },
1119 },
1120 {
1121 .ident = "SATELLITE U205",
1122 .matches = {
1123 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1124 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1125 },
1126 },
1127 {
1128 .ident = "Satellite Pro A120",
1129 .matches = {
1130 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1131 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
1132 },
1133 },
1134 {
1135 .ident = "Portege M500",
1136 .matches = {
1137 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1138 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1139 },
1140 },
1141 {
1142 .ident = "VGN-BX297XP",
1143 .matches = {
1144 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1145 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1146 },
1147 },
1148
1149 { } /* terminate list */
1150 };
1151 static const char *oemstrs[] = {
1152 "Tecra M3,",
1153 };
1154 int i;
1155
1156 if (dmi_check_system(sysids))
1157 return 1;
1158
1159 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1160 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1161 return 1;
1162
1163 /* TECRA M4 sometimes forgets its identify and reports bogus
1164 * DMI information. As the bogus information is a bit
1165 * generic, match as many entries as possible. This manual
1166 * matching is necessary because dmi_system_id.matches is
1167 * limited to four entries.
1168 */
1169 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1170 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1171 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1172 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1173 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1174 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1175 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1176 return 1;
1177
1178 return 0;
1179 }
1180
1181 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1182 {
1183 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1184 unsigned long flags;
1185 int rc = 0;
1186
1187 rc = ata_host_suspend(host, mesg);
1188 if (rc)
1189 return rc;
1190
1191 /* Some braindamaged ACPI suspend implementations expect the
1192 * controller to be awake on entry; otherwise, it burns cpu
1193 * cycles and power trying to do something to the sleeping
1194 * beauty.
1195 */
1196 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1197 pci_save_state(pdev);
1198
1199 /* mark its power state as "unknown", since we don't
1200 * know if e.g. the BIOS will change its device state
1201 * when we suspend.
1202 */
1203 if (pdev->current_state == PCI_D0)
1204 pdev->current_state = PCI_UNKNOWN;
1205
1206 /* tell resume that it's waking up from broken suspend */
1207 spin_lock_irqsave(&host->lock, flags);
1208 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1209 spin_unlock_irqrestore(&host->lock, flags);
1210 } else
1211 ata_pci_device_do_suspend(pdev, mesg);
1212
1213 return 0;
1214 }
1215
1216 static int piix_pci_device_resume(struct pci_dev *pdev)
1217 {
1218 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1219 unsigned long flags;
1220 int rc;
1221
1222 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1223 spin_lock_irqsave(&host->lock, flags);
1224 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1225 spin_unlock_irqrestore(&host->lock, flags);
1226
1227 pci_set_power_state(pdev, PCI_D0);
1228 pci_restore_state(pdev);
1229
1230 /* PCI device wasn't disabled during suspend. Use
1231 * pci_reenable_device() to avoid affecting the enable
1232 * count.
1233 */
1234 rc = pci_reenable_device(pdev);
1235 if (rc)
1236 dev_err(&pdev->dev,
1237 "failed to enable device after resume (%d)\n",
1238 rc);
1239 } else
1240 rc = ata_pci_device_do_resume(pdev);
1241
1242 if (rc == 0)
1243 ata_host_resume(host);
1244
1245 return rc;
1246 }
1247 #endif
1248
1249 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1250 {
1251 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1252 }
1253
1254 #define AHCI_PCI_BAR 5
1255 #define AHCI_GLOBAL_CTL 0x04
1256 #define AHCI_ENABLE (1 << 31)
1257 static int piix_disable_ahci(struct pci_dev *pdev)
1258 {
1259 void __iomem *mmio;
1260 u32 tmp;
1261 int rc = 0;
1262
1263 /* BUG: pci_enable_device has not yet been called. This
1264 * works because this device is usually set up by BIOS.
1265 */
1266
1267 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1268 !pci_resource_len(pdev, AHCI_PCI_BAR))
1269 return 0;
1270
1271 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1272 if (!mmio)
1273 return -ENOMEM;
1274
1275 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1276 if (tmp & AHCI_ENABLE) {
1277 tmp &= ~AHCI_ENABLE;
1278 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1279
1280 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1281 if (tmp & AHCI_ENABLE)
1282 rc = -EIO;
1283 }
1284
1285 pci_iounmap(pdev, mmio);
1286 return rc;
1287 }
1288
1289 /**
1290 * piix_check_450nx_errata - Check for problem 450NX setup
1291 * @ata_dev: the PCI device to check
1292 *
1293 * Check for the present of 450NX errata #19 and errata #25. If
1294 * they are found return an error code so we can turn off DMA
1295 */
1296
1297 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1298 {
1299 struct pci_dev *pdev = NULL;
1300 u16 cfg;
1301 int no_piix_dma = 0;
1302
1303 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1304 /* Look for 450NX PXB. Check for problem configurations
1305 A PCI quirk checks bit 6 already */
1306 pci_read_config_word(pdev, 0x41, &cfg);
1307 /* Only on the original revision: IDE DMA can hang */
1308 if (pdev->revision == 0x00)
1309 no_piix_dma = 1;
1310 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1311 else if (cfg & (1<<14) && pdev->revision < 5)
1312 no_piix_dma = 2;
1313 }
1314 if (no_piix_dma)
1315 dev_warn(&ata_dev->dev,
1316 "450NX errata present, disabling IDE DMA%s\n",
1317 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1318 : "");
1319
1320 return no_piix_dma;
1321 }
1322
1323 static void __devinit piix_init_pcs(struct ata_host *host,
1324 const struct piix_map_db *map_db)
1325 {
1326 struct pci_dev *pdev = to_pci_dev(host->dev);
1327 u16 pcs, new_pcs;
1328
1329 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1330
1331 new_pcs = pcs | map_db->port_enable;
1332
1333 if (new_pcs != pcs) {
1334 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1335 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1336 msleep(150);
1337 }
1338 }
1339
1340 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1341 struct ata_port_info *pinfo,
1342 const struct piix_map_db *map_db)
1343 {
1344 const int *map;
1345 int i, invalid_map = 0;
1346 u8 map_value;
1347
1348 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1349
1350 map = map_db->map[map_value & map_db->mask];
1351
1352 dev_info(&pdev->dev, "MAP [");
1353 for (i = 0; i < 4; i++) {
1354 switch (map[i]) {
1355 case RV:
1356 invalid_map = 1;
1357 pr_cont(" XX");
1358 break;
1359
1360 case NA:
1361 pr_cont(" --");
1362 break;
1363
1364 case IDE:
1365 WARN_ON((i & 1) || map[i + 1] != IDE);
1366 pinfo[i / 2] = piix_port_info[ich_pata_100];
1367 i++;
1368 pr_cont(" IDE IDE");
1369 break;
1370
1371 default:
1372 pr_cont(" P%d", map[i]);
1373 if (i & 1)
1374 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1375 break;
1376 }
1377 }
1378 pr_cont(" ]\n");
1379
1380 if (invalid_map)
1381 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1382
1383 return map;
1384 }
1385
1386 static bool piix_no_sidpr(struct ata_host *host)
1387 {
1388 struct pci_dev *pdev = to_pci_dev(host->dev);
1389
1390 /*
1391 * Samsung DB-P70 only has three ATA ports exposed and
1392 * curiously the unconnected first port reports link online
1393 * while not responding to SRST protocol causing excessive
1394 * detection delay.
1395 *
1396 * Unfortunately, the system doesn't carry enough DMI
1397 * information to identify the machine but does have subsystem
1398 * vendor and device set. As it's unclear whether the
1399 * subsystem vendor/device is used only for this specific
1400 * board, the port can't be disabled solely with the
1401 * information; however, turning off SIDPR access works around
1402 * the problem. Turn it off.
1403 *
1404 * This problem is reported in bnc#441240.
1405 *
1406 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1407 */
1408 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1409 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1410 pdev->subsystem_device == 0xb049) {
1411 dev_warn(host->dev,
1412 "Samsung DB-P70 detected, disabling SIDPR\n");
1413 return true;
1414 }
1415
1416 return false;
1417 }
1418
1419 static int __devinit piix_init_sidpr(struct ata_host *host)
1420 {
1421 struct pci_dev *pdev = to_pci_dev(host->dev);
1422 struct piix_host_priv *hpriv = host->private_data;
1423 struct ata_link *link0 = &host->ports[0]->link;
1424 u32 scontrol;
1425 int i, rc;
1426
1427 /* check for availability */
1428 for (i = 0; i < 4; i++)
1429 if (hpriv->map[i] == IDE)
1430 return 0;
1431
1432 /* is it blacklisted? */
1433 if (piix_no_sidpr(host))
1434 return 0;
1435
1436 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1437 return 0;
1438
1439 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1440 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1441 return 0;
1442
1443 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1444 return 0;
1445
1446 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1447
1448 /* SCR access via SIDPR doesn't work on some configurations.
1449 * Give it a test drive by inhibiting power save modes which
1450 * we'll do anyway.
1451 */
1452 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1453
1454 /* if IPM is already 3, SCR access is probably working. Don't
1455 * un-inhibit power save modes as BIOS might have inhibited
1456 * them for a reason.
1457 */
1458 if ((scontrol & 0xf00) != 0x300) {
1459 scontrol |= 0x300;
1460 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1461 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1462
1463 if ((scontrol & 0xf00) != 0x300) {
1464 dev_info(host->dev,
1465 "SCR access via SIDPR is available but doesn't work\n");
1466 return 0;
1467 }
1468 }
1469
1470 /* okay, SCRs available, set ops and ask libata for slave_link */
1471 for (i = 0; i < 2; i++) {
1472 struct ata_port *ap = host->ports[i];
1473
1474 ap->ops = &piix_sidpr_sata_ops;
1475
1476 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1477 rc = ata_slave_link_init(ap);
1478 if (rc)
1479 return rc;
1480 }
1481 }
1482
1483 return 0;
1484 }
1485
1486 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1487 {
1488 static const struct dmi_system_id sysids[] = {
1489 {
1490 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1491 * isn't used to boot the system which
1492 * disables the channel.
1493 */
1494 .ident = "M570U",
1495 .matches = {
1496 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1497 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1498 },
1499 },
1500
1501 { } /* terminate list */
1502 };
1503 struct pci_dev *pdev = to_pci_dev(host->dev);
1504 struct piix_host_priv *hpriv = host->private_data;
1505
1506 if (!dmi_check_system(sysids))
1507 return;
1508
1509 /* The datasheet says that bit 18 is NOOP but certain systems
1510 * seem to use it to disable a channel. Clear the bit on the
1511 * affected systems.
1512 */
1513 if (hpriv->saved_iocfg & (1 << 18)) {
1514 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1515 pci_write_config_dword(pdev, PIIX_IOCFG,
1516 hpriv->saved_iocfg & ~(1 << 18));
1517 }
1518 }
1519
1520 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1521 {
1522 static const struct dmi_system_id broken_systems[] = {
1523 {
1524 .ident = "HP Compaq 2510p",
1525 .matches = {
1526 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1527 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1528 },
1529 /* PCI slot number of the controller */
1530 .driver_data = (void *)0x1FUL,
1531 },
1532 {
1533 .ident = "HP Compaq nc6000",
1534 .matches = {
1535 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1536 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1537 },
1538 /* PCI slot number of the controller */
1539 .driver_data = (void *)0x1FUL,
1540 },
1541
1542 { } /* terminate list */
1543 };
1544 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1545
1546 if (dmi) {
1547 unsigned long slot = (unsigned long)dmi->driver_data;
1548 /* apply the quirk only to on-board controllers */
1549 return slot == PCI_SLOT(pdev->devfn);
1550 }
1551
1552 return false;
1553 }
1554
1555 /**
1556 * piix_init_one - Register PIIX ATA PCI device with kernel services
1557 * @pdev: PCI device to register
1558 * @ent: Entry in piix_pci_tbl matching with @pdev
1559 *
1560 * Called from kernel PCI layer. We probe for combined mode (sigh),
1561 * and then hand over control to libata, for it to do the rest.
1562 *
1563 * LOCKING:
1564 * Inherited from PCI layer (may sleep).
1565 *
1566 * RETURNS:
1567 * Zero on success, or -ERRNO value.
1568 */
1569
1570 static int __devinit piix_init_one(struct pci_dev *pdev,
1571 const struct pci_device_id *ent)
1572 {
1573 struct device *dev = &pdev->dev;
1574 struct ata_port_info port_info[2];
1575 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1576 struct scsi_host_template *sht = &piix_sht;
1577 unsigned long port_flags;
1578 struct ata_host *host;
1579 struct piix_host_priv *hpriv;
1580 int rc;
1581
1582 ata_print_version_once(&pdev->dev, DRV_VERSION);
1583
1584 /* no hotplugging support for later devices (FIXME) */
1585 if (!in_module_init && ent->driver_data >= ich5_sata)
1586 return -ENODEV;
1587
1588 if (piix_broken_system_poweroff(pdev)) {
1589 piix_port_info[ent->driver_data].flags |=
1590 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1591 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1592 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1593 "on poweroff and hibernation\n");
1594 }
1595
1596 port_info[0] = piix_port_info[ent->driver_data];
1597 port_info[1] = piix_port_info[ent->driver_data];
1598
1599 port_flags = port_info[0].flags;
1600
1601 /* enable device and prepare host */
1602 rc = pcim_enable_device(pdev);
1603 if (rc)
1604 return rc;
1605
1606 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1607 if (!hpriv)
1608 return -ENOMEM;
1609
1610 /* Save IOCFG, this will be used for cable detection, quirk
1611 * detection and restoration on detach. This is necessary
1612 * because some ACPI implementations mess up cable related
1613 * bits on _STM. Reported on kernel bz#11879.
1614 */
1615 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1616
1617 /* ICH6R may be driven by either ata_piix or ahci driver
1618 * regardless of BIOS configuration. Make sure AHCI mode is
1619 * off.
1620 */
1621 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1622 rc = piix_disable_ahci(pdev);
1623 if (rc)
1624 return rc;
1625 }
1626
1627 /* SATA map init can change port_info, do it before prepping host */
1628 if (port_flags & ATA_FLAG_SATA)
1629 hpriv->map = piix_init_sata_map(pdev, port_info,
1630 piix_map_db_table[ent->driver_data]);
1631
1632 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1633 if (rc)
1634 return rc;
1635 host->private_data = hpriv;
1636
1637 /* initialize controller */
1638 if (port_flags & ATA_FLAG_SATA) {
1639 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1640 rc = piix_init_sidpr(host);
1641 if (rc)
1642 return rc;
1643 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1644 sht = &piix_sidpr_sht;
1645 }
1646
1647 /* apply IOCFG bit18 quirk */
1648 piix_iocfg_bit18_quirk(host);
1649
1650 /* On ICH5, some BIOSen disable the interrupt using the
1651 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1652 * On ICH6, this bit has the same effect, but only when
1653 * MSI is disabled (and it is disabled, as we don't use
1654 * message-signalled interrupts currently).
1655 */
1656 if (port_flags & PIIX_FLAG_CHECKINTR)
1657 pci_intx(pdev, 1);
1658
1659 if (piix_check_450nx_errata(pdev)) {
1660 /* This writes into the master table but it does not
1661 really matter for this errata as we will apply it to
1662 all the PIIX devices on the board */
1663 host->ports[0]->mwdma_mask = 0;
1664 host->ports[0]->udma_mask = 0;
1665 host->ports[1]->mwdma_mask = 0;
1666 host->ports[1]->udma_mask = 0;
1667 }
1668 host->flags |= ATA_HOST_PARALLEL_SCAN;
1669
1670 pci_set_master(pdev);
1671 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1672 }
1673
1674 static void piix_remove_one(struct pci_dev *pdev)
1675 {
1676 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1677 struct piix_host_priv *hpriv = host->private_data;
1678
1679 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1680
1681 ata_pci_remove_one(pdev);
1682 }
1683
1684 static int __init piix_init(void)
1685 {
1686 int rc;
1687
1688 DPRINTK("pci_register_driver\n");
1689 rc = pci_register_driver(&piix_pci_driver);
1690 if (rc)
1691 return rc;
1692
1693 in_module_init = 0;
1694
1695 DPRINTK("done\n");
1696 return 0;
1697 }
1698
1699 static void __exit piix_exit(void)
1700 {
1701 pci_unregister_driver(&piix_pci_driver);
1702 }
1703
1704 module_init(piix_init);
1705 module_exit(piix_exit);
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