| blob | 8f39263c0768e0b14de31793f126691d731f947a |
1 config ARM
2 bool
3 default y
4 select HAVE_AOUT
5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
7 select HAVE_MEMBLOCK
8 select RTC_LIB
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_KGDB
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
23 select HAVE_IRQ_WORK
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
33 help
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
42 bool
44 config HAVE_PWM
45 bool
47 config MIGHT_HAVE_PCI
48 bool
50 config SYS_SUPPORTS_APM_EMULATION
51 bool
53 config HAVE_SCHED_CLOCK
54 bool
56 config GENERIC_GPIO
57 bool
59 config ARCH_USES_GETTIMEOFFSET
60 bool
61 default n
63 config GENERIC_CLOCKEVENTS
64 bool
66 config GENERIC_CLOCKEVENTS_BROADCAST
67 bool
68 depends on GENERIC_CLOCKEVENTS
69 default y if SMP
71 config KTIME_SCALAR
72 bool
73 default y
75 config HAVE_TCM
76 bool
77 select GENERIC_ALLOCATOR
79 config HAVE_PROC_CPU
80 bool
82 config NO_IOPORT
83 bool
85 config EISA
86 bool
87 ---help---
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
98 Otherwise, say N.
100 config SBUS
101 bool
103 config MCA
104 bool
105 help
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
112 bool
113 default y
115 config HAVE_LATENCYTOP_SUPPORT
116 bool
117 depends on !SMP
118 default y
120 config LOCKDEP_SUPPORT
121 bool
122 default y
124 config TRACE_IRQFLAGS_SUPPORT
125 bool
126 default y
128 config HARDIRQS_SW_RESEND
129 bool
130 default y
132 config GENERIC_IRQ_PROBE
133 bool
134 default y
136 config GENERIC_LOCKBREAK
137 bool
138 default y
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
142 bool
143 default y
145 config RWSEM_XCHGADD_ALGORITHM
146 bool
148 config ARCH_HAS_ILOG2_U32
149 bool
151 config ARCH_HAS_ILOG2_U64
152 bool
154 config ARCH_HAS_CPUFREQ
155 bool
156 help
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
159 it.
161 config ARCH_HAS_CPU_IDLE_WAIT
162 def_bool y
164 config GENERIC_HWEIGHT
165 bool
166 default y
168 config GENERIC_CALIBRATE_DELAY
169 bool
170 default y
172 config ARCH_MAY_HAVE_PC_FDC
173 bool
175 config ZONE_DMA
176 bool
178 config NEED_DMA_MAP_STATE
179 def_bool y
181 config GENERIC_ISA_DMA
182 bool
184 config FIQ
185 bool
187 config ARCH_MTD_XIP
188 bool
190 config VECTORS_BASE
191 hex
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
194 default 0x00000000
195 help
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 default y
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
203 help
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
216 bool
217 help
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
222 config PHYS_OFFSET
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 help
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
229 config GENERIC_BUG
230 def_bool y
231 depends on BUG
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
237 menu "System Type"
239 config MMU
240 bool "MMU-based Paged Memory Management Support"
241 default y
242 help
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
246 #
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
249 #
250 choice
251 prompt "ARM system type"
252 default ARCH_VERSATILE
254 config ARCH_INTEGRATOR
255 bool "ARM Ltd. Integrator family"
256 select ARM_AMBA
257 select ARCH_HAS_CPUFREQ
258 select CLKDEV_LOOKUP
259 select HAVE_MACH_CLKDEV
260 select ICST
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
265 help
266 Support for ARM's Integrator platform.
268 config ARCH_REALVIEW
269 bool "ARM Ltd. RealView family"
270 select ARM_AMBA
271 select CLKDEV_LOOKUP
272 select HAVE_MACH_CLKDEV
273 select ICST
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select ARM_TIMER_SP804
279 select GPIO_PL061 if GPIOLIB
280 select NEED_MACH_MEMORY_H
281 select MULTI_IRQ_HANDLER
282 help
283 This enables support for ARM Ltd RealView boards.
285 config ARCH_VERSATILE
286 bool "ARM Ltd. Versatile family"
287 select ARM_AMBA
288 select ARM_VIC
289 select CLKDEV_LOOKUP
290 select HAVE_MACH_CLKDEV
291 select ICST
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select PLAT_VERSATILE_FPGA_IRQ
297 select ARM_TIMER_SP804
298 help
299 This enables support for ARM Ltd Versatile board.
301 config ARCH_VEXPRESS
302 bool "ARM Ltd. Versatile Express family"
303 select ARCH_WANT_OPTIONAL_GPIOLIB
304 select ARM_AMBA
305 select ARM_TIMER_SP804
306 select CLKDEV_LOOKUP
307 select HAVE_MACH_CLKDEV
308 select GENERIC_CLOCKEVENTS
309 select HAVE_CLK
310 select HAVE_PATA_PLATFORM
311 select ICST
312 select PLAT_VERSATILE
313 select PLAT_VERSATILE_CLCD
314 select MULTI_IRQ_HANDLER
315 help
316 This enables support for the ARM Ltd Versatile Express boards.
318 config ARCH_AT91
319 bool "Atmel AT91"
320 select ARCH_REQUIRE_GPIOLIB
321 select HAVE_CLK
322 select CLKDEV_LOOKUP
323 help
324 This enables support for systems based on the Atmel AT91RM9200,
325 AT91SAM9 and AT91CAP9 processors.
327 config ARCH_BCMRING
328 bool "Broadcom BCMRING"
329 depends on MMU
330 select CPU_V6
331 select ARM_AMBA
332 select ARM_TIMER_SP804
333 select CLKDEV_LOOKUP
334 select GENERIC_CLOCKEVENTS
335 select ARCH_WANT_OPTIONAL_GPIOLIB
336 help
337 Support for Broadcom's BCMRing platform.
339 config ARCH_HIGHBANK
340 bool "Calxeda Highbank-based"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_AMBA
343 select ARM_GIC
344 select ARM_TIMER_SP804
345 select CLKDEV_LOOKUP
346 select CPU_V7
347 select GENERIC_CLOCKEVENTS
348 select HAVE_ARM_SCU
349 select USE_OF
350 select MULTI_IRQ_HANDLER
351 help
352 Support for the Calxeda Highbank SoC based boards.
354 config ARCH_CLPS711X
355 bool "Cirrus Logic CLPS711x/EP721x-based"
356 select CPU_ARM720T
357 select ARCH_USES_GETTIMEOFFSET
358 select NEED_MACH_MEMORY_H
359 help
360 Support for Cirrus Logic 711x/721x based boards.
362 config ARCH_CNS3XXX
363 bool "Cavium Networks CNS3XXX family"
364 select CPU_V6K
365 select GENERIC_CLOCKEVENTS
366 select ARM_GIC
367 select MIGHT_HAVE_PCI
368 select PCI_DOMAINS if PCI
369 help
370 Support for Cavium Networks CNS3XXX platform.
372 config ARCH_GEMINI
373 bool "Cortina Systems Gemini"
374 select CPU_FA526
375 select ARCH_REQUIRE_GPIOLIB
376 select ARCH_USES_GETTIMEOFFSET
377 help
378 Support for the Cortina Systems Gemini family SoCs
380 config ARCH_PRIMA2
381 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
382 select CPU_V7
383 select NO_IOPORT
384 select GENERIC_CLOCKEVENTS
385 select CLKDEV_LOOKUP
386 select GENERIC_IRQ_CHIP
387 select USE_OF
388 select ZONE_DMA
389 help
390 Support for CSR SiRFSoC ARM Cortex A9 Platform
392 config ARCH_EBSA110
393 bool "EBSA-110"
394 select CPU_SA110
395 select ISA
396 select NO_IOPORT
397 select ARCH_USES_GETTIMEOFFSET
398 select NEED_MACH_MEMORY_H
399 help
400 This is an evaluation board for the StrongARM processor available
401 from Digital. It has limited hardware on-board, including an
402 Ethernet interface, two PCMCIA sockets, two serial ports and a
403 parallel port.
405 config ARCH_EP93XX
406 bool "EP93xx-based"
407 select CPU_ARM920T
408 select ARM_AMBA
409 select ARM_VIC
410 select CLKDEV_LOOKUP
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_HAS_HOLES_MEMORYMODEL
413 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_MEMORY_H
415 help
416 This enables support for the Cirrus EP93xx series of CPUs.
418 config ARCH_FOOTBRIDGE
419 bool "FootBridge"
420 select CPU_SA110
421 select FOOTBRIDGE
422 select GENERIC_CLOCKEVENTS
423 select HAVE_IDE
424 select NEED_MACH_MEMORY_H
425 help
426 Support for systems based on the DC21285 companion chip
427 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
429 config ARCH_MXC
430 bool "Freescale MXC/iMX-based"
431 select GENERIC_CLOCKEVENTS
432 select ARCH_REQUIRE_GPIOLIB
433 select CLKDEV_LOOKUP
434 select CLKSRC_MMIO
435 select GENERIC_IRQ_CHIP
436 select HAVE_SCHED_CLOCK
437 select MULTI_IRQ_HANDLER
438 help
439 Support for Freescale MXC/iMX-based family of processors
441 config ARCH_MXS
442 bool "Freescale MXS-based"
443 select GENERIC_CLOCKEVENTS
444 select ARCH_REQUIRE_GPIOLIB
445 select CLKDEV_LOOKUP
446 select CLKSRC_MMIO
447 help
448 Support for Freescale MXS-based family of processors
450 config ARCH_NETX
451 bool "Hilscher NetX based"
452 select CLKSRC_MMIO
453 select CPU_ARM926T
454 select ARM_VIC
455 select GENERIC_CLOCKEVENTS
456 help
457 This enables support for systems based on the Hilscher NetX Soc
459 config ARCH_H720X
460 bool "Hynix HMS720x-based"
461 select CPU_ARM720T
462 select ISA_DMA_API
463 select ARCH_USES_GETTIMEOFFSET
464 help
465 This enables support for systems based on the Hynix HMS720x
467 config ARCH_IOP13XX
468 bool "IOP13xx-based"
469 depends on MMU
470 select CPU_XSC3
471 select PLAT_IOP
472 select PCI
473 select ARCH_SUPPORTS_MSI
474 select VMSPLIT_1G
475 select NEED_MACH_MEMORY_H
476 help
477 Support for Intel's IOP13XX (XScale) family of processors.
479 config ARCH_IOP32X
480 bool "IOP32x-based"
481 depends on MMU
482 select CPU_XSCALE
483 select PLAT_IOP
484 select PCI
485 select ARCH_REQUIRE_GPIOLIB
486 help
487 Support for Intel's 80219 and IOP32X (XScale) family of
488 processors.
490 config ARCH_IOP33X
491 bool "IOP33x-based"
492 depends on MMU
493 select CPU_XSCALE
494 select PLAT_IOP
495 select PCI
496 select ARCH_REQUIRE_GPIOLIB
497 help
498 Support for Intel's IOP33X (XScale) family of processors.
500 config ARCH_IXP23XX
501 bool "IXP23XX-based"
502 depends on MMU
503 select CPU_XSC3
504 select PCI
505 select ARCH_USES_GETTIMEOFFSET
506 select NEED_MACH_MEMORY_H
507 help
508 Support for Intel's IXP23xx (XScale) family of processors.
510 config ARCH_IXP2000
511 bool "IXP2400/2800-based"
512 depends on MMU
513 select CPU_XSCALE
514 select PCI
515 select ARCH_USES_GETTIMEOFFSET
516 select NEED_MACH_MEMORY_H
517 help
518 Support for Intel's IXP2400/2800 (XScale) family of processors.
520 config ARCH_IXP4XX
521 bool "IXP4xx-based"
522 depends on MMU
523 select CLKSRC_MMIO
524 select CPU_XSCALE
525 select GENERIC_GPIO
526 select GENERIC_CLOCKEVENTS
527 select HAVE_SCHED_CLOCK
528 select MIGHT_HAVE_PCI
529 select DMABOUNCE if PCI
530 help
531 Support for Intel's IXP4XX (XScale) family of processors.
533 config ARCH_DOVE
534 bool "Marvell Dove"
535 select CPU_V7
536 select PCI
537 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION
540 help
541 Support for the Marvell Dove SoC 88AP510
543 config ARCH_KIRKWOOD
544 bool "Marvell Kirkwood"
545 select CPU_FEROCEON
546 select PCI
547 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
549 select PLAT_ORION
550 help
551 Support for the following Marvell Kirkwood series SoCs:
552 88F6180, 88F6192 and 88F6281.
554 config ARCH_LPC32XX
555 bool "NXP LPC32XX"
556 select CLKSRC_MMIO
557 select CPU_ARM926T
558 select ARCH_REQUIRE_GPIOLIB
559 select HAVE_IDE
560 select ARM_AMBA
561 select USB_ARCH_HAS_OHCI
562 select CLKDEV_LOOKUP
563 select GENERIC_CLOCKEVENTS
564 help
565 Support for the NXP LPC32XX family of processors
567 config ARCH_MV78XX0
568 bool "Marvell MV78xx0"
569 select CPU_FEROCEON
570 select PCI
571 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select PLAT_ORION
574 help
575 Support for the following Marvell MV78xx0 series SoCs:
576 MV781x0, MV782x0.
578 config ARCH_ORION5X
579 bool "Marvell Orion"
580 depends on MMU
581 select CPU_FEROCEON
582 select PCI
583 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
585 select PLAT_ORION
586 help
587 Support for the following Marvell Orion 5x series SoCs:
588 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
589 Orion-2 (5281), Orion-1-90 (6183).
591 config ARCH_MMP
592 bool "Marvell PXA168/910/MMP2"
593 depends on MMU
594 select ARCH_REQUIRE_GPIOLIB
595 select CLKDEV_LOOKUP
596 select GENERIC_CLOCKEVENTS
597 select HAVE_SCHED_CLOCK
598 select TICK_ONESHOT
599 select PLAT_PXA
600 select SPARSE_IRQ
601 select GENERIC_ALLOCATOR
602 help
603 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
605 config ARCH_KS8695
606 bool "Micrel/Kendin KS8695"
607 select CPU_ARM922T
608 select ARCH_REQUIRE_GPIOLIB
609 select ARCH_USES_GETTIMEOFFSET
610 select NEED_MACH_MEMORY_H
611 help
612 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
613 System-on-Chip devices.
615 config ARCH_W90X900
616 bool "Nuvoton W90X900 CPU"
617 select CPU_ARM926T
618 select ARCH_REQUIRE_GPIOLIB
619 select CLKDEV_LOOKUP
620 select CLKSRC_MMIO
621 select GENERIC_CLOCKEVENTS
622 help
623 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
624 At present, the w90x900 has been renamed nuc900, regarding
625 the ARM series product line, you can login the following
626 link address to know more.
628 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
629 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
631 config ARCH_TEGRA
632 bool "NVIDIA Tegra"
633 select CLKDEV_LOOKUP
634 select CLKSRC_MMIO
635 select GENERIC_CLOCKEVENTS
636 select GENERIC_GPIO
637 select HAVE_CLK
638 select HAVE_SCHED_CLOCK
639 select ARCH_HAS_CPUFREQ
640 help
641 This enables support for NVIDIA Tegra based systems (Tegra APX,
642 Tegra 6xx and Tegra 2 series).
644 config ARCH_PICOXCELL
645 bool "Picochip picoXcell"
646 select ARCH_REQUIRE_GPIOLIB
647 select ARM_PATCH_PHYS_VIRT
648 select ARM_VIC
649 select CPU_V6K
650 select DW_APB_TIMER
651 select GENERIC_CLOCKEVENTS
652 select GENERIC_GPIO
653 select HAVE_SCHED_CLOCK
654 select HAVE_TCM
655 select NO_IOPORT
656 select USE_OF
657 help
658 This enables support for systems based on the Picochip picoXcell
659 family of Femtocell devices. The picoxcell support requires device tree
660 for all boards.
662 config ARCH_PNX4008
663 bool "Philips Nexperia PNX4008 Mobile"
664 select CPU_ARM926T
665 select CLKDEV_LOOKUP
666 select ARCH_USES_GETTIMEOFFSET
667 help
668 This enables support for Philips PNX4008 mobile platform.
670 config ARCH_PXA
671 bool "PXA2xx/PXA3xx-based"
672 depends on MMU
673 select ARCH_MTD_XIP
674 select ARCH_HAS_CPUFREQ
675 select CLKDEV_LOOKUP
676 select CLKSRC_MMIO
677 select ARCH_REQUIRE_GPIOLIB
678 select GENERIC_CLOCKEVENTS
679 select HAVE_SCHED_CLOCK
680 select TICK_ONESHOT
681 select PLAT_PXA
682 select SPARSE_IRQ
683 select AUTO_ZRELADDR
684 select MULTI_IRQ_HANDLER
685 select ARM_CPU_SUSPEND if PM
686 select HAVE_IDE
687 help
688 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
690 config ARCH_MSM
691 bool "Qualcomm MSM"
692 select HAVE_CLK
693 select GENERIC_CLOCKEVENTS
694 select ARCH_REQUIRE_GPIOLIB
695 select CLKDEV_LOOKUP
696 help
697 Support for Qualcomm MSM/QSD based systems. This runs on the
698 apps processor of the MSM/QSD and depends on a shared memory
699 interface to the modem processor which runs the baseband
700 stack and controls some vital subsystems
701 (clock and power control, etc).
703 config ARCH_SHMOBILE
704 bool "Renesas SH-Mobile / R-Mobile"
705 select HAVE_CLK
706 select CLKDEV_LOOKUP
707 select HAVE_MACH_CLKDEV
708 select GENERIC_CLOCKEVENTS
709 select NO_IOPORT
710 select SPARSE_IRQ
711 select MULTI_IRQ_HANDLER
712 select PM_GENERIC_DOMAINS if PM
713 select NEED_MACH_MEMORY_H
714 help
715 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
717 config ARCH_RPC
718 bool "RiscPC"
719 select ARCH_ACORN
720 select FIQ
721 select TIMER_ACORN
722 select ARCH_MAY_HAVE_PC_FDC
723 select HAVE_PATA_PLATFORM
724 select ISA_DMA_API
725 select NO_IOPORT
726 select ARCH_SPARSEMEM_ENABLE
727 select ARCH_USES_GETTIMEOFFSET
728 select HAVE_IDE
729 select NEED_MACH_MEMORY_H
730 help
731 On the Acorn Risc-PC, Linux can support the internal IDE disk and
732 CD-ROM interface, serial and parallel port, and the floppy drive.
734 config ARCH_SA1100
735 bool "SA1100-based"
736 select CLKSRC_MMIO
737 select CPU_SA1100
738 select ISA
739 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_MTD_XIP
741 select ARCH_HAS_CPUFREQ
742 select CPU_FREQ
743 select GENERIC_CLOCKEVENTS
744 select HAVE_CLK
745 select HAVE_SCHED_CLOCK
746 select TICK_ONESHOT
747 select ARCH_REQUIRE_GPIOLIB
748 select HAVE_IDE
749 select NEED_MACH_MEMORY_H
750 help
751 Support for StrongARM 11x0 based boards.
753 config ARCH_S3C2410
754 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
755 select GENERIC_GPIO
756 select ARCH_HAS_CPUFREQ
757 select HAVE_CLK
758 select CLKDEV_LOOKUP
759 select ARCH_USES_GETTIMEOFFSET
760 select HAVE_S3C2410_I2C if I2C
761 help
762 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
763 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
764 the Samsung SMDK2410 development board (and derivatives).
766 Note, the S3C2416 and the S3C2450 are so close that they even share
767 the same SoC ID code. This means that there is no separate machine
768 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
770 config ARCH_S3C64XX
771 bool "Samsung S3C64XX"
772 select PLAT_SAMSUNG
773 select CPU_V6
774 select ARM_VIC
775 select HAVE_CLK
776 select HAVE_TCM
777 select CLKDEV_LOOKUP
778 select NO_IOPORT
779 select ARCH_USES_GETTIMEOFFSET
780 select ARCH_HAS_CPUFREQ
781 select ARCH_REQUIRE_GPIOLIB
782 select SAMSUNG_CLKSRC
783 select SAMSUNG_IRQ_VIC_TIMER
784 select S3C_GPIO_TRACK
785 select S3C_DEV_NAND
786 select USB_ARCH_HAS_OHCI
787 select SAMSUNG_GPIOLIB_4BIT
788 select HAVE_S3C2410_I2C if I2C
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 help
791 Samsung S3C64XX series based systems
793 config ARCH_S5P64X0
794 bool "Samsung S5P6440 S5P6450"
795 select CPU_V6
796 select GENERIC_GPIO
797 select HAVE_CLK
798 select CLKDEV_LOOKUP
799 select CLKSRC_MMIO
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 select GENERIC_CLOCKEVENTS
802 select HAVE_SCHED_CLOCK
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C_RTC if RTC_CLASS
805 help
806 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
807 SMDK6450.
809 config ARCH_S5PC100
810 bool "Samsung S5PC100"
811 select GENERIC_GPIO
812 select HAVE_CLK
813 select CLKDEV_LOOKUP
814 select CPU_V7
815 select ARM_L1_CACHE_SHIFT_6
816 select ARCH_USES_GETTIMEOFFSET
817 select HAVE_S3C2410_I2C if I2C
818 select HAVE_S3C_RTC if RTC_CLASS
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 help
821 Samsung S5PC100 series based systems
823 config ARCH_S5PV210
824 bool "Samsung S5PV210/S5PC110"
825 select CPU_V7
826 select ARCH_SPARSEMEM_ENABLE
827 select ARCH_HAS_HOLES_MEMORYMODEL
828 select GENERIC_GPIO
829 select HAVE_CLK
830 select CLKDEV_LOOKUP
831 select CLKSRC_MMIO
832 select ARM_L1_CACHE_SHIFT_6
833 select ARCH_HAS_CPUFREQ
834 select GENERIC_CLOCKEVENTS
835 select HAVE_SCHED_CLOCK
836 select HAVE_S3C2410_I2C if I2C
837 select HAVE_S3C_RTC if RTC_CLASS
838 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 select NEED_MACH_MEMORY_H
840 help
841 Samsung S5PV210/S5PC110 series based systems
843 config ARCH_EXYNOS
844 bool "SAMSUNG EXYNOS"
845 select CPU_V7
846 select ARCH_SPARSEMEM_ENABLE
847 select ARCH_HAS_HOLES_MEMORYMODEL
848 select GENERIC_GPIO
849 select HAVE_CLK
850 select CLKDEV_LOOKUP
851 select ARCH_HAS_CPUFREQ
852 select GENERIC_CLOCKEVENTS
853 select HAVE_S3C_RTC if RTC_CLASS
854 select HAVE_S3C2410_I2C if I2C
855 select HAVE_S3C2410_WATCHDOG if WATCHDOG
856 select NEED_MACH_MEMORY_H
857 help
858 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
860 config ARCH_SHARK
861 bool "Shark"
862 select CPU_SA110
863 select ISA
864 select ISA_DMA
865 select ZONE_DMA
866 select PCI
867 select ARCH_USES_GETTIMEOFFSET
868 select NEED_MACH_MEMORY_H
869 help
870 Support for the StrongARM based Digital DNARD machine, also known
871 as "Shark" (<http://www.shark-linux.de/shark.html>).
873 config ARCH_TCC_926
874 bool "Telechips TCC ARM926-based systems"
875 select CLKSRC_MMIO
876 select CPU_ARM926T
877 select HAVE_CLK
878 select CLKDEV_LOOKUP
879 select GENERIC_CLOCKEVENTS
880 help
881 Support for Telechips TCC ARM926-based systems.
883 config ARCH_U300
884 bool "ST-Ericsson U300 Series"
885 depends on MMU
886 select CLKSRC_MMIO
887 select CPU_ARM926T
888 select HAVE_SCHED_CLOCK
889 select HAVE_TCM
890 select ARM_AMBA
891 select ARM_PATCH_PHYS_VIRT
892 select ARM_VIC
893 select GENERIC_CLOCKEVENTS
894 select CLKDEV_LOOKUP
895 select HAVE_MACH_CLKDEV
896 select GENERIC_GPIO
897 select ARCH_REQUIRE_GPIOLIB
898 select NEED_MACH_MEMORY_H
899 help
900 Support for ST-Ericsson U300 series mobile platforms.
902 config ARCH_U8500
903 bool "ST-Ericsson U8500 Series"
904 select CPU_V7
905 select ARM_AMBA
906 select GENERIC_CLOCKEVENTS
907 select CLKDEV_LOOKUP
908 select ARCH_REQUIRE_GPIOLIB
909 select ARCH_HAS_CPUFREQ
910 help
911 Support for ST-Ericsson's Ux500 architecture
913 config ARCH_NOMADIK
914 bool "STMicroelectronics Nomadik"
915 select ARM_AMBA
916 select ARM_VIC
917 select CPU_ARM926T
918 select CLKDEV_LOOKUP
919 select GENERIC_CLOCKEVENTS
920 select ARCH_REQUIRE_GPIOLIB
921 help
922 Support for the Nomadik platform by ST-Ericsson
924 config ARCH_DAVINCI
925 bool "TI DaVinci"
926 select GENERIC_CLOCKEVENTS
927 select ARCH_REQUIRE_GPIOLIB
928 select ZONE_DMA
929 select HAVE_IDE
930 select CLKDEV_LOOKUP
931 select GENERIC_ALLOCATOR
932 select GENERIC_IRQ_CHIP
933 select ARCH_HAS_HOLES_MEMORYMODEL
934 help
935 Support for TI's DaVinci platform.
937 config ARCH_OMAP
938 bool "TI OMAP"
939 select HAVE_CLK
940 select ARCH_REQUIRE_GPIOLIB
941 select ARCH_HAS_CPUFREQ
942 select CLKSRC_MMIO
943 select GENERIC_CLOCKEVENTS
944 select HAVE_SCHED_CLOCK
945 select ARCH_HAS_HOLES_MEMORYMODEL
946 help
947 Support for TI's OMAP platform (OMAP1/2/3/4).
949 config PLAT_SPEAR
950 bool "ST SPEAr"
951 select ARM_AMBA
952 select ARCH_REQUIRE_GPIOLIB
953 select CLKDEV_LOOKUP
954 select CLKSRC_MMIO
955 select GENERIC_CLOCKEVENTS
956 select HAVE_CLK
957 help
958 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
960 config ARCH_VT8500
961 bool "VIA/WonderMedia 85xx"
962 select CPU_ARM926T
963 select GENERIC_GPIO
964 select ARCH_HAS_CPUFREQ
965 select GENERIC_CLOCKEVENTS
966 select ARCH_REQUIRE_GPIOLIB
967 select HAVE_PWM
968 help
969 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
971 config ARCH_ZYNQ
972 bool "Xilinx Zynq ARM Cortex A9 Platform"
973 select CPU_V7
974 select GENERIC_CLOCKEVENTS
975 select CLKDEV_LOOKUP
976 select ARM_GIC
977 select ARM_AMBA
978 select ICST
979 select USE_OF
980 help
981 Support for Xilinx Zynq ARM Cortex A9 Platform
982 endchoice
984 #
985 # This is sorted alphabetically by mach-* pathname. However, plat-*
986 # Kconfigs may be included either alphabetically (according to the
987 # plat- suffix) or along side the corresponding mach-* source.
988 #
989 source "arch/arm/mach-at91/Kconfig"
991 source "arch/arm/mach-bcmring/Kconfig"
993 source "arch/arm/mach-clps711x/Kconfig"
995 source "arch/arm/mach-cns3xxx/Kconfig"
997 source "arch/arm/mach-davinci/Kconfig"
999 source "arch/arm/mach-dove/Kconfig"
1001 source "arch/arm/mach-ep93xx/Kconfig"
1003 source "arch/arm/mach-footbridge/Kconfig"
1005 source "arch/arm/mach-gemini/Kconfig"
1007 source "arch/arm/mach-h720x/Kconfig"
1009 source "arch/arm/mach-integrator/Kconfig"
1011 source "arch/arm/mach-iop32x/Kconfig"
1013 source "arch/arm/mach-iop33x/Kconfig"
1015 source "arch/arm/mach-iop13xx/Kconfig"
1017 source "arch/arm/mach-ixp4xx/Kconfig"
1019 source "arch/arm/mach-ixp2000/Kconfig"
1021 source "arch/arm/mach-ixp23xx/Kconfig"
1023 source "arch/arm/mach-kirkwood/Kconfig"
1025 source "arch/arm/mach-ks8695/Kconfig"
1027 source "arch/arm/mach-lpc32xx/Kconfig"
1029 source "arch/arm/mach-msm/Kconfig"
1031 source "arch/arm/mach-mv78xx0/Kconfig"
1033 source "arch/arm/plat-mxc/Kconfig"
1035 source "arch/arm/mach-mxs/Kconfig"
1037 source "arch/arm/mach-netx/Kconfig"
1039 source "arch/arm/mach-nomadik/Kconfig"
1040 source "arch/arm/plat-nomadik/Kconfig"
1042 source "arch/arm/plat-omap/Kconfig"
1044 source "arch/arm/mach-omap1/Kconfig"
1046 source "arch/arm/mach-omap2/Kconfig"
1048 source "arch/arm/mach-orion5x/Kconfig"
1050 source "arch/arm/mach-pxa/Kconfig"
1051 source "arch/arm/plat-pxa/Kconfig"
1053 source "arch/arm/mach-mmp/Kconfig"
1055 source "arch/arm/mach-realview/Kconfig"
1057 source "arch/arm/mach-sa1100/Kconfig"
1059 source "arch/arm/plat-samsung/Kconfig"
1060 source "arch/arm/plat-s3c24xx/Kconfig"
1061 source "arch/arm/plat-s5p/Kconfig"
1063 source "arch/arm/plat-spear/Kconfig"
1065 source "arch/arm/plat-tcc/Kconfig"
1067 if ARCH_S3C2410
1068 source "arch/arm/mach-s3c2410/Kconfig"
1069 source "arch/arm/mach-s3c2412/Kconfig"
1070 source "arch/arm/mach-s3c2416/Kconfig"
1071 source "arch/arm/mach-s3c2440/Kconfig"
1072 source "arch/arm/mach-s3c2443/Kconfig"
1073 endif
1075 if ARCH_S3C64XX
1076 source "arch/arm/mach-s3c64xx/Kconfig"
1077 endif
1079 source "arch/arm/mach-s5p64x0/Kconfig"
1081 source "arch/arm/mach-s5pc100/Kconfig"
1083 source "arch/arm/mach-s5pv210/Kconfig"
1085 source "arch/arm/mach-exynos/Kconfig"
1087 source "arch/arm/mach-shmobile/Kconfig"
1089 source "arch/arm/mach-tegra/Kconfig"
1091 source "arch/arm/mach-u300/Kconfig"
1093 source "arch/arm/mach-ux500/Kconfig"
1095 source "arch/arm/mach-versatile/Kconfig"
1097 source "arch/arm/mach-vexpress/Kconfig"
1098 source "arch/arm/plat-versatile/Kconfig"
1100 source "arch/arm/mach-vt8500/Kconfig"
1102 source "arch/arm/mach-w90x900/Kconfig"
1104 # Definitions to make life easier
1105 config ARCH_ACORN
1106 bool
1108 config PLAT_IOP
1109 bool
1110 select GENERIC_CLOCKEVENTS
1111 select HAVE_SCHED_CLOCK
1113 config PLAT_ORION
1114 bool
1115 select CLKSRC_MMIO
1116 select GENERIC_IRQ_CHIP
1117 select HAVE_SCHED_CLOCK
1119 config PLAT_PXA
1120 bool
1122 config PLAT_VERSATILE
1123 bool
1125 config ARM_TIMER_SP804
1126 bool
1127 select CLKSRC_MMIO
1129 source arch/arm/mm/Kconfig
1131 config IWMMXT
1132 bool "Enable iWMMXt support"
1133 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1134 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1135 help
1136 Enable support for iWMMXt context switching at run time if
1137 running on a CPU that supports it.
1139 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1140 config XSCALE_PMU
1141 bool
1142 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1143 default y
1145 config CPU_HAS_PMU
1146 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1147 (!ARCH_OMAP3 || OMAP3_EMU)
1148 default y
1149 bool
1151 config MULTI_IRQ_HANDLER
1152 bool
1153 help
1154 Allow each machine to specify it's own IRQ handler at run time.
1156 if !MMU
1157 source "arch/arm/Kconfig-nommu"
1158 endif
1160 config ARM_ERRATA_411920
1161 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1162 depends on CPU_V6 || CPU_V6K
1163 help
1164 Invalidation of the Instruction Cache operation can
1165 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1166 It does not affect the MPCore. This option enables the ARM Ltd.
1167 recommended workaround.
1169 config ARM_ERRATA_430973
1170 bool "ARM errata: Stale prediction on replaced interworking branch"
1171 depends on CPU_V7
1172 help
1173 This option enables the workaround for the 430973 Cortex-A8
1174 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1175 interworking branch is replaced with another code sequence at the
1176 same virtual address, whether due to self-modifying code or virtual
1177 to physical address re-mapping, Cortex-A8 does not recover from the
1178 stale interworking branch prediction. This results in Cortex-A8
1179 executing the new code sequence in the incorrect ARM or Thumb state.
1180 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1181 and also flushes the branch target cache at every context switch.
1182 Note that setting specific bits in the ACTLR register may not be
1183 available in non-secure mode.
1185 config ARM_ERRATA_458693
1186 bool "ARM errata: Processor deadlock when a false hazard is created"
1187 depends on CPU_V7
1188 help
1189 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1190 erratum. For very specific sequences of memory operations, it is
1191 possible for a hazard condition intended for a cache line to instead
1192 be incorrectly associated with a different cache line. This false
1193 hazard might then cause a processor deadlock. The workaround enables
1194 the L1 caching of the NEON accesses and disables the PLD instruction
1195 in the ACTLR register. Note that setting specific bits in the ACTLR
1196 register may not be available in non-secure mode.
1198 config ARM_ERRATA_460075
1199 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1200 depends on CPU_V7
1201 help
1202 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1203 erratum. Any asynchronous access to the L2 cache may encounter a
1204 situation in which recent store transactions to the L2 cache are lost
1205 and overwritten with stale memory contents from external memory. The
1206 workaround disables the write-allocate mode for the L2 cache via the
1207 ACTLR register. Note that setting specific bits in the ACTLR register
1208 may not be available in non-secure mode.
1210 config ARM_ERRATA_742230
1211 bool "ARM errata: DMB operation may be faulty"
1212 depends on CPU_V7 && SMP
1213 help
1214 This option enables the workaround for the 742230 Cortex-A9
1215 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1216 between two write operations may not ensure the correct visibility
1217 ordering of the two writes. This workaround sets a specific bit in
1218 the diagnostic register of the Cortex-A9 which causes the DMB
1219 instruction to behave as a DSB, ensuring the correct behaviour of
1220 the two writes.
1222 config ARM_ERRATA_742231
1223 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1224 depends on CPU_V7 && SMP
1225 help
1226 This option enables the workaround for the 742231 Cortex-A9
1227 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1228 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1229 accessing some data located in the same cache line, may get corrupted
1230 data due to bad handling of the address hazard when the line gets
1231 replaced from one of the CPUs at the same time as another CPU is
1232 accessing it. This workaround sets specific bits in the diagnostic
1233 register of the Cortex-A9 which reduces the linefill issuing
1234 capabilities of the processor.
1236 config PL310_ERRATA_588369
1237 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1238 depends on CACHE_L2X0
1239 help
1240 The PL310 L2 cache controller implements three types of Clean &
1241 Invalidate maintenance operations: by Physical Address
1242 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1243 They are architecturally defined to behave as the execution of a
1244 clean operation followed immediately by an invalidate operation,
1245 both performing to the same memory location. This functionality
1246 is not correctly implemented in PL310 as clean lines are not
1247 invalidated as a result of these operations.
1249 config ARM_ERRATA_720789
1250 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1251 depends on CPU_V7 && SMP
1252 help
1253 This option enables the workaround for the 720789 Cortex-A9 (prior to
1254 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1255 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1256 As a consequence of this erratum, some TLB entries which should be
1257 invalidated are not, resulting in an incoherency in the system page
1258 tables. The workaround changes the TLB flushing routines to invalidate
1259 entries regardless of the ASID.
1261 config PL310_ERRATA_727915
1262 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1263 depends on CACHE_L2X0
1264 help
1265 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1266 operation (offset 0x7FC). This operation runs in background so that
1267 PL310 can handle normal accesses while it is in progress. Under very
1268 rare circumstances, due to this erratum, write data can be lost when
1269 PL310 treats a cacheable write transaction during a Clean &
1270 Invalidate by Way operation.
1272 config ARM_ERRATA_743622
1273 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1274 depends on CPU_V7
1275 help
1276 This option enables the workaround for the 743622 Cortex-A9
1277 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1278 optimisation in the Cortex-A9 Store Buffer may lead to data
1279 corruption. This workaround sets a specific bit in the diagnostic
1280 register of the Cortex-A9 which disables the Store Buffer
1281 optimisation, preventing the defect from occurring. This has no
1282 visible impact on the overall performance or power consumption of the
1283 processor.
1285 config ARM_ERRATA_751472
1286 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1287 depends on CPU_V7 && SMP
1288 help
1289 This option enables the workaround for the 751472 Cortex-A9 (prior
1290 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1291 completion of a following broadcasted operation if the second
1292 operation is received by a CPU before the ICIALLUIS has completed,
1293 potentially leading to corrupted entries in the cache or TLB.
1295 config ARM_ERRATA_753970
1296 bool "ARM errata: cache sync operation may be faulty"
1297 depends on CACHE_PL310
1298 help
1299 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1301 Under some condition the effect of cache sync operation on
1302 the store buffer still remains when the operation completes.
1303 This means that the store buffer is always asked to drain and
1304 this prevents it from merging any further writes. The workaround
1305 is to replace the normal offset of cache sync operation (0x730)
1306 by another offset targeting an unmapped PL310 register 0x740.
1307 This has the same effect as the cache sync operation: store buffer
1308 drain and waiting for all buffers empty.
1310 config ARM_ERRATA_754322
1311 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1312 depends on CPU_V7
1313 help
1314 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1315 r3p*) erratum. A speculative memory access may cause a page table walk
1316 which starts prior to an ASID switch but completes afterwards. This
1317 can populate the micro-TLB with a stale entry which may be hit with
1318 the new ASID. This workaround places two dsb instructions in the mm
1319 switching code so that no page table walks can cross the ASID switch.
1321 config ARM_ERRATA_754327
1322 bool "ARM errata: no automatic Store Buffer drain"
1323 depends on CPU_V7 && SMP
1324 help
1325 This option enables the workaround for the 754327 Cortex-A9 (prior to
1326 r2p0) erratum. The Store Buffer does not have any automatic draining
1327 mechanism and therefore a livelock may occur if an external agent
1328 continuously polls a memory location waiting to observe an update.
1329 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1330 written polling loops from denying visibility of updates to memory.
1332 config ARM_ERRATA_364296
1333 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1334 depends on CPU_V6 && !SMP
1335 help
1336 This options enables the workaround for the 364296 ARM1136
1337 r0p2 erratum (possible cache data corruption with
1338 hit-under-miss enabled). It sets the undocumented bit 31 in
1339 the auxiliary control register and the FI bit in the control
1340 register, thus disabling hit-under-miss without putting the
1341 processor into full low interrupt latency mode. ARM11MPCore
1342 is not affected.
1344 config ARM_ERRATA_764369
1345 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1346 depends on CPU_V7 && SMP
1347 help
1348 This option enables the workaround for erratum 764369
1349 affecting Cortex-A9 MPCore with two or more processors (all
1350 current revisions). Under certain timing circumstances, a data
1351 cache line maintenance operation by MVA targeting an Inner
1352 Shareable memory region may fail to proceed up to either the
1353 Point of Coherency or to the Point of Unification of the
1354 system. This workaround adds a DSB instruction before the
1355 relevant cache maintenance functions and sets a specific bit
1356 in the diagnostic control register of the SCU.
1358 endmenu
1360 source "arch/arm/common/Kconfig"
1362 menu "Bus support"
1364 config ARM_AMBA
1365 bool
1367 config ISA
1368 bool
1369 help
1370 Find out whether you have ISA slots on your motherboard. ISA is the
1371 name of a bus system, i.e. the way the CPU talks to the other stuff
1372 inside your box. Other bus systems are PCI, EISA, MicroChannel
1373 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1374 newer boards don't support it. If you have ISA, say Y, otherwise N.
1376 # Select ISA DMA controller support
1377 config ISA_DMA
1378 bool
1379 select ISA_DMA_API
1381 # Select ISA DMA interface
1382 config ISA_DMA_API
1383 bool
1385 config PCI
1386 bool "PCI support" if MIGHT_HAVE_PCI
1387 help
1388 Find out whether you have a PCI motherboard. PCI is the name of a
1389 bus system, i.e. the way the CPU talks to the other stuff inside
1390 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1391 VESA. If you have PCI, say Y, otherwise N.
1393 config PCI_DOMAINS
1394 bool
1395 depends on PCI
1397 config PCI_NANOENGINE
1398 bool "BSE nanoEngine PCI support"
1399 depends on SA1100_NANOENGINE
1400 help
1401 Enable PCI on the BSE nanoEngine board.
1403 config PCI_SYSCALL
1404 def_bool PCI
1406 # Select the host bridge type
1407 config PCI_HOST_VIA82C505
1408 bool
1409 depends on PCI && ARCH_SHARK
1410 default y
1412 config PCI_HOST_ITE8152
1413 bool
1414 depends on PCI && MACH_ARMCORE
1415 default y
1416 select DMABOUNCE
1418 source "drivers/pci/Kconfig"
1420 source "drivers/pcmcia/Kconfig"
1422 endmenu
1424 menu "Kernel Features"
1426 source "kernel/time/Kconfig"
1428 config SMP
1429 bool "Symmetric Multi-Processing"
1430 depends on CPU_V6K || CPU_V7
1431 depends on GENERIC_CLOCKEVENTS
1432 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1433 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1434 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1435 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1436 depends on MMU
1437 select USE_GENERIC_SMP_HELPERS
1438 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1439 help
1440 This enables support for systems with more than one CPU. If you have
1441 a system with only one CPU, like most personal computers, say N. If
1442 you have a system with more than one CPU, say Y.
1444 If you say N here, the kernel will run on single and multiprocessor
1445 machines, but will use only one CPU of a multiprocessor machine. If
1446 you say Y here, the kernel will run on many, but not all, single
1447 processor machines. On a single processor machine, the kernel will
1448 run faster if you say N here.
1450 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1451 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1452 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1454 If you don't know what to do here, say N.
1456 config SMP_ON_UP
1457 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1458 depends on EXPERIMENTAL
1459 depends on SMP && !XIP_KERNEL
1460 default y
1461 help
1462 SMP kernels contain instructions which fail on non-SMP processors.
1463 Enabling this option allows the kernel to modify itself to make
1464 these instructions safe. Disabling it allows about 1K of space
1465 savings.
1467 If you don't know what to do here, say Y.
1469 config ARM_CPU_TOPOLOGY
1470 bool "Support cpu topology definition"
1471 depends on SMP && CPU_V7
1472 default y
1473 help
1474 Support ARM cpu topology definition. The MPIDR register defines
1475 affinity between processors which is then used to describe the cpu
1476 topology of an ARM System.
1478 config SCHED_MC
1479 bool "Multi-core scheduler support"
1480 depends on ARM_CPU_TOPOLOGY
1481 help
1482 Multi-core scheduler support improves the CPU scheduler's decision
1483 making when dealing with multi-core CPU chips at a cost of slightly
1484 increased overhead in some places. If unsure say N here.
1486 config SCHED_SMT
1487 bool "SMT scheduler support"
1488 depends on ARM_CPU_TOPOLOGY
1489 help
1490 Improves the CPU scheduler's decision making when dealing with
1491 MultiThreading at a cost of slightly increased overhead in some
1492 places. If unsure say N here.
1494 config HAVE_ARM_SCU
1495 bool
1496 help
1497 This option enables support for the ARM system coherency unit
1499 config HAVE_ARM_TWD
1500 bool
1501 depends on SMP
1502 select TICK_ONESHOT
1503 help
1504 This options enables support for the ARM timer and watchdog unit
1506 choice
1507 prompt "Memory split"
1508 default VMSPLIT_3G
1509 help
1510 Select the desired split between kernel and user memory.
1512 If you are not absolutely sure what you are doing, leave this
1513 option alone!
1515 config VMSPLIT_3G
1516 bool "3G/1G user/kernel split"
1517 config VMSPLIT_2G
1518 bool "2G/2G user/kernel split"
1519 config VMSPLIT_1G
1520 bool "1G/3G user/kernel split"
1521 endchoice
1523 config PAGE_OFFSET
1524 hex
1525 default 0x40000000 if VMSPLIT_1G
1526 default 0x80000000 if VMSPLIT_2G
1527 default 0xC0000000
1529 config NR_CPUS
1530 int "Maximum number of CPUs (2-32)"
1531 range 2 32
1532 depends on SMP
1533 default "4"
1535 config HOTPLUG_CPU
1536 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1537 depends on SMP && HOTPLUG && EXPERIMENTAL
1538 help
1539 Say Y here to experiment with turning CPUs off and on. CPUs
1540 can be controlled through /sys/devices/system/cpu.
1542 config LOCAL_TIMERS
1543 bool "Use local timer interrupts"
1544 depends on SMP
1545 default y
1546 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1547 help
1548 Enable support for local timers on SMP platforms, rather then the
1549 legacy IPI broadcast method. Local timers allows the system
1550 accounting to be spread across the timer interval, preventing a
1551 "thundering herd" at every timer tick.
1553 source kernel/Kconfig.preempt
1555 config HZ
1556 int
1557 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1558 ARCH_S5PV210 || ARCH_EXYNOS4
1559 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1560 default AT91_TIMER_HZ if ARCH_AT91
1561 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1562 default 100
1564 config THUMB2_KERNEL
1565 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1566 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1567 select AEABI
1568 select ARM_ASM_UNIFIED
1569 select ARM_UNWIND
1570 help
1571 By enabling this option, the kernel will be compiled in
1572 Thumb-2 mode. A compiler/assembler that understand the unified
1573 ARM-Thumb syntax is needed.
1575 If unsure, say N.
1577 config THUMB2_AVOID_R_ARM_THM_JUMP11
1578 bool "Work around buggy Thumb-2 short branch relocations in gas"
1579 depends on THUMB2_KERNEL && MODULES
1580 default y
1581 help
1582 Various binutils versions can resolve Thumb-2 branches to
1583 locally-defined, preemptible global symbols as short-range "b.n"
1584 branch instructions.
1586 This is a problem, because there's no guarantee the final
1587 destination of the symbol, or any candidate locations for a
1588 trampoline, are within range of the branch. For this reason, the
1589 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1590 relocation in modules at all, and it makes little sense to add
1591 support.
1593 The symptom is that the kernel fails with an "unsupported
1594 relocation" error when loading some modules.
1596 Until fixed tools are available, passing
1597 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1598 code which hits this problem, at the cost of a bit of extra runtime
1599 stack usage in some cases.
1601 The problem is described in more detail at:
1602 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1604 Only Thumb-2 kernels are affected.
1606 Unless you are sure your tools don't have this problem, say Y.
1608 config ARM_ASM_UNIFIED
1609 bool
1611 config AEABI
1612 bool "Use the ARM EABI to compile the kernel"
1613 help
1614 This option allows for the kernel to be compiled using the latest
1615 ARM ABI (aka EABI). This is only useful if you are using a user
1616 space environment that is also compiled with EABI.
1618 Since there are major incompatibilities between the legacy ABI and
1619 EABI, especially with regard to structure member alignment, this
1620 option also changes the kernel syscall calling convention to
1621 disambiguate both ABIs and allow for backward compatibility support
1622 (selected with CONFIG_OABI_COMPAT).
1624 To use this you need GCC version 4.0.0 or later.
1626 config OABI_COMPAT
1627 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1628 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1629 default y
1630 help
1631 This option preserves the old syscall interface along with the
1632 new (ARM EABI) one. It also provides a compatibility layer to
1633 intercept syscalls that have structure arguments which layout
1634 in memory differs between the legacy ABI and the new ARM EABI
1635 (only for non "thumb" binaries). This option adds a tiny
1636 overhead to all syscalls and produces a slightly larger kernel.
1637 If you know you'll be using only pure EABI user space then you
1638 can say N here. If this option is not selected and you attempt
1639 to execute a legacy ABI binary then the result will be
1640 UNPREDICTABLE (in fact it can be predicted that it won't work
1641 at all). If in doubt say Y.
1643 config ARCH_HAS_HOLES_MEMORYMODEL
1644 bool
1646 config ARCH_SPARSEMEM_ENABLE
1647 bool
1649 config ARCH_SPARSEMEM_DEFAULT
1650 def_bool ARCH_SPARSEMEM_ENABLE
1652 config ARCH_SELECT_MEMORY_MODEL
1653 def_bool ARCH_SPARSEMEM_ENABLE
1655 config HAVE_ARCH_PFN_VALID
1656 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1658 config HIGHMEM
1659 bool "High Memory Support"
1660 depends on MMU
1661 help
1662 The address space of ARM processors is only 4 Gigabytes large
1663 and it has to accommodate user address space, kernel address
1664 space as well as some memory mapped IO. That means that, if you
1665 have a large amount of physical memory and/or IO, not all of the
1666 memory can be "permanently mapped" by the kernel. The physical
1667 memory that is not permanently mapped is called "high memory".
1669 Depending on the selected kernel/user memory split, minimum
1670 vmalloc space and actual amount of RAM, you may not need this
1671 option which should result in a slightly faster kernel.
1673 If unsure, say n.
1675 config HIGHPTE
1676 bool "Allocate 2nd-level pagetables from highmem"
1677 depends on HIGHMEM
1679 config HW_PERF_EVENTS
1680 bool "Enable hardware performance counter support for perf events"
1681 depends on PERF_EVENTS && CPU_HAS_PMU
1682 default y
1683 help
1684 Enable hardware performance counter support for perf events. If
1685 disabled, perf events will use software events only.
1687 source "mm/Kconfig"
1689 config FORCE_MAX_ZONEORDER
1690 int "Maximum zone order" if ARCH_SHMOBILE
1691 range 11 64 if ARCH_SHMOBILE
1692 default "9" if SA1111
1693 default "11"
1694 help
1695 The kernel memory allocator divides physically contiguous memory
1696 blocks into "zones", where each zone is a power of two number of
1697 pages. This option selects the largest power of two that the kernel
1698 keeps in the memory allocator. If you need to allocate very large
1699 blocks of physically contiguous memory, then you may need to
1700 increase this value.
1702 This config option is actually maximum order plus one. For example,
1703 a value of 11 means that the largest free memory block is 2^10 pages.
1705 config LEDS
1706 bool "Timer and CPU usage LEDs"
1707 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1708 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1709 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1710 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1711 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1712 ARCH_AT91 || ARCH_DAVINCI || \
1713 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1714 help
1715 If you say Y here, the LEDs on your machine will be used
1716 to provide useful information about your current system status.
1718 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1719 be able to select which LEDs are active using the options below. If
1720 you are compiling a kernel for the EBSA-110 or the LART however, the
1721 red LED will simply flash regularly to indicate that the system is
1722 still functional. It is safe to say Y here if you have a CATS
1723 system, but the driver will do nothing.
1725 config LEDS_TIMER
1726 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1727 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1728 || MACH_OMAP_PERSEUS2
1729 depends on LEDS
1730 depends on !GENERIC_CLOCKEVENTS
1731 default y if ARCH_EBSA110
1732 help
1733 If you say Y here, one of the system LEDs (the green one on the
1734 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1735 will flash regularly to indicate that the system is still
1736 operational. This is mainly useful to kernel hackers who are
1737 debugging unstable kernels.
1739 The LART uses the same LED for both Timer LED and CPU usage LED
1740 functions. You may choose to use both, but the Timer LED function
1741 will overrule the CPU usage LED.
1743 config LEDS_CPU
1744 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1745 !ARCH_OMAP) \
1746 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1747 || MACH_OMAP_PERSEUS2
1748 depends on LEDS
1749 help
1750 If you say Y here, the red LED will be used to give a good real
1751 time indication of CPU usage, by lighting whenever the idle task
1752 is not currently executing.
1754 The LART uses the same LED for both Timer LED and CPU usage LED
1755 functions. You may choose to use both, but the Timer LED function
1756 will overrule the CPU usage LED.
1758 config ALIGNMENT_TRAP
1759 bool
1760 depends on CPU_CP15_MMU
1761 default y if !ARCH_EBSA110
1762 select HAVE_PROC_CPU if PROC_FS
1763 help
1764 ARM processors cannot fetch/store information which is not
1765 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1766 address divisible by 4. On 32-bit ARM processors, these non-aligned
1767 fetch/store instructions will be emulated in software if you say
1768 here, which has a severe performance impact. This is necessary for
1769 correct operation of some network protocols. With an IP-only
1770 configuration it is safe to say N, otherwise say Y.
1772 config UACCESS_WITH_MEMCPY
1773 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1774 depends on MMU && EXPERIMENTAL
1775 default y if CPU_FEROCEON
1776 help
1777 Implement faster copy_to_user and clear_user methods for CPU
1778 cores where a 8-word STM instruction give significantly higher
1779 memory write throughput than a sequence of individual 32bit stores.
1781 A possible side effect is a slight increase in scheduling latency
1782 between threads sharing the same address space if they invoke
1783 such copy operations with large buffers.
1785 However, if the CPU data cache is using a write-allocate mode,
1786 this option is unlikely to provide any performance gain.
1788 config SECCOMP
1789 bool
1790 prompt "Enable seccomp to safely compute untrusted bytecode"
1791 ---help---
1792 This kernel feature is useful for number crunching applications
1793 that may need to compute untrusted bytecode during their
1794 execution. By using pipes or other transports made available to
1795 the process as file descriptors supporting the read/write
1796 syscalls, it's possible to isolate those applications in
1797 their own address space using seccomp. Once seccomp is
1798 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1799 and the task is only allowed to execute a few safe syscalls
1800 defined by each seccomp mode.
1802 config CC_STACKPROTECTOR
1803 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1804 depends on EXPERIMENTAL
1805 help
1806 This option turns on the -fstack-protector GCC feature. This
1807 feature puts, at the beginning of functions, a canary value on
1808 the stack just before the return address, and validates
1809 the value just before actually returning. Stack based buffer
1810 overflows (that need to overwrite this return address) now also
1811 overwrite the canary, which gets detected and the attack is then
1812 neutralized via a kernel panic.
1813 This feature requires gcc version 4.2 or above.
1815 config DEPRECATED_PARAM_STRUCT
1816 bool "Provide old way to pass kernel parameters"
1817 help
1818 This was deprecated in 2001 and announced to live on for 5 years.
1819 Some old boot loaders still use this way.
1821 endmenu
1823 menu "Boot options"
1825 config USE_OF
1826 bool "Flattened Device Tree support"
1827 select OF
1828 select OF_EARLY_FLATTREE
1829 select IRQ_DOMAIN
1830 help
1831 Include support for flattened device tree machine descriptions.
1833 # Compressed boot loader in ROM. Yes, we really want to ask about
1834 # TEXT and BSS so we preserve their values in the config files.
1835 config ZBOOT_ROM_TEXT
1836 hex "Compressed ROM boot loader base address"
1837 default "0"
1838 help
1839 The physical address at which the ROM-able zImage is to be
1840 placed in the target. Platforms which normally make use of
1841 ROM-able zImage formats normally set this to a suitable
1842 value in their defconfig file.
1844 If ZBOOT_ROM is not enabled, this has no effect.
1846 config ZBOOT_ROM_BSS
1847 hex "Compressed ROM boot loader BSS address"
1848 default "0"
1849 help
1850 The base address of an area of read/write memory in the target
1851 for the ROM-able zImage which must be available while the
1852 decompressor is running. It must be large enough to hold the
1853 entire decompressed kernel plus an additional 128 KiB.
1854 Platforms which normally make use of ROM-able zImage formats
1855 normally set this to a suitable value in their defconfig file.
1857 If ZBOOT_ROM is not enabled, this has no effect.
1859 config ZBOOT_ROM
1860 bool "Compressed boot loader in ROM/flash"
1861 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1862 help
1863 Say Y here if you intend to execute your compressed kernel image
1864 (zImage) directly from ROM or flash. If unsure, say N.
1866 choice
1867 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1868 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1869 default ZBOOT_ROM_NONE
1870 help
1871 Include experimental SD/MMC loading code in the ROM-able zImage.
1872 With this enabled it is possible to write the the ROM-able zImage
1873 kernel image to an MMC or SD card and boot the kernel straight
1874 from the reset vector. At reset the processor Mask ROM will load
1875 the first part of the the ROM-able zImage which in turn loads the
1876 rest the kernel image to RAM.
1878 config ZBOOT_ROM_NONE
1879 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1880 help
1881 Do not load image from SD or MMC
1883 config ZBOOT_ROM_MMCIF
1884 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1885 help
1886 Load image from MMCIF hardware block.
1888 config ZBOOT_ROM_SH_MOBILE_SDHI
1889 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1890 help
1891 Load image from SDHI hardware block
1893 endchoice
1895 config ARM_APPENDED_DTB
1896 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1897 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1898 help
1899 With this option, the boot code will look for a device tree binary
1900 (DTB) appended to zImage
1901 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1903 This is meant as a backward compatibility convenience for those
1904 systems with a bootloader that can't be upgraded to accommodate
1905 the documented boot protocol using a device tree.
1907 Beware that there is very little in terms of protection against
1908 this option being confused by leftover garbage in memory that might
1909 look like a DTB header after a reboot if no actual DTB is appended
1910 to zImage. Do not leave this option active in a production kernel
1911 if you don't intend to always append a DTB. Proper passing of the
1912 location into r2 of a bootloader provided DTB is always preferable
1913 to this option.
1915 config ARM_ATAG_DTB_COMPAT
1916 bool "Supplement the appended DTB with traditional ATAG information"
1917 depends on ARM_APPENDED_DTB
1918 help
1919 Some old bootloaders can't be updated to a DTB capable one, yet
1920 they provide ATAGs with memory configuration, the ramdisk address,
1921 the kernel cmdline string, etc. Such information is dynamically
1922 provided by the bootloader and can't always be stored in a static
1923 DTB. To allow a device tree enabled kernel to be used with such
1924 bootloaders, this option allows zImage to extract the information
1925 from the ATAG list and store it at run time into the appended DTB.
1927 config CMDLINE
1928 string "Default kernel command string"
1929 default ""
1930 help
1931 On some architectures (EBSA110 and CATS), there is currently no way
1932 for the boot loader to pass arguments to the kernel. For these
1933 architectures, you should supply some command-line options at build
1934 time by entering them here. As a minimum, you should specify the
1935 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1937 choice
1938 prompt "Kernel command line type" if CMDLINE != ""
1939 default CMDLINE_FROM_BOOTLOADER
1941 config CMDLINE_FROM_BOOTLOADER
1942 bool "Use bootloader kernel arguments if available"
1943 help
1944 Uses the command-line options passed by the boot loader. If
1945 the boot loader doesn't provide any, the default kernel command
1946 string provided in CMDLINE will be used.
1948 config CMDLINE_EXTEND
1949 bool "Extend bootloader kernel arguments"
1950 help
1951 The command-line arguments provided by the boot loader will be
1952 appended to the default kernel command string.
1954 config CMDLINE_FORCE
1955 bool "Always use the default kernel command string"
1956 help
1957 Always use the default kernel command string, even if the boot
1958 loader passes other arguments to the kernel.
1959 This is useful if you cannot or don't want to change the
1960 command-line options your boot loader passes to the kernel.
1961 endchoice
1963 config XIP_KERNEL
1964 bool "Kernel Execute-In-Place from ROM"
1965 depends on !ZBOOT_ROM
1966 help
1967 Execute-In-Place allows the kernel to run from non-volatile storage
1968 directly addressable by the CPU, such as NOR flash. This saves RAM
1969 space since the text section of the kernel is not loaded from flash
1970 to RAM. Read-write sections, such as the data section and stack,
1971 are still copied to RAM. The XIP kernel is not compressed since
1972 it has to run directly from flash, so it will take more space to
1973 store it. The flash address used to link the kernel object files,
1974 and for storing it, is configuration dependent. Therefore, if you
1975 say Y here, you must know the proper physical address where to
1976 store the kernel image depending on your own flash memory usage.
1978 Also note that the make target becomes "make xipImage" rather than
1979 "make zImage" or "make Image". The final kernel binary to put in
1980 ROM memory will be arch/arm/boot/xipImage.
1982 If unsure, say N.
1984 config XIP_PHYS_ADDR
1985 hex "XIP Kernel Physical Location"
1986 depends on XIP_KERNEL
1987 default "0x00080000"
1988 help
1989 This is the physical address in your flash memory the kernel will
1990 be linked for and stored to. This address is dependent on your
1991 own flash usage.
1993 config KEXEC
1994 bool "Kexec system call (EXPERIMENTAL)"
1995 depends on EXPERIMENTAL
1996 help
1997 kexec is a system call that implements the ability to shutdown your
1998 current kernel, and to start another kernel. It is like a reboot
1999 but it is independent of the system firmware. And like a reboot
2000 you can start any kernel with it, not just Linux.
2002 It is an ongoing process to be certain the hardware in a machine
2003 is properly shutdown, so do not be surprised if this code does not
2004 initially work for you. It may help to enable device hotplugging
2005 support.
2007 config ATAGS_PROC
2008 bool "Export atags in procfs"
2009 depends on KEXEC
2010 default y
2011 help
2012 Should the atags used to boot the kernel be exported in an "atags"
2013 file in procfs. Useful with kexec.
2015 config CRASH_DUMP
2016 bool "Build kdump crash kernel (EXPERIMENTAL)"
2017 depends on EXPERIMENTAL
2018 help
2019 Generate crash dump after being started by kexec. This should
2020 be normally only set in special crash dump kernels which are
2021 loaded in the main kernel with kexec-tools into a specially
2022 reserved region and then later executed after a crash by
2023 kdump/kexec. The crash dump kernel must be compiled to a
2024 memory address not used by the main kernel
2026 For more details see Documentation/kdump/kdump.txt
2028 config AUTO_ZRELADDR
2029 bool "Auto calculation of the decompressed kernel image address"
2030 depends on !ZBOOT_ROM && !ARCH_U300
2031 help
2032 ZRELADDR is the physical address where the decompressed kernel
2033 image will be placed. If AUTO_ZRELADDR is selected, the address
2034 will be determined at run-time by masking the current IP with
2035 0xf8000000. This assumes the zImage being placed in the first 128MB
2036 from start of memory.
2038 endmenu
2040 menu "CPU Power Management"
2042 if ARCH_HAS_CPUFREQ
2044 source "drivers/cpufreq/Kconfig"
2046 config CPU_FREQ_IMX
2047 tristate "CPUfreq driver for i.MX CPUs"
2048 depends on ARCH_MXC && CPU_FREQ
2049 help
2050 This enables the CPUfreq driver for i.MX CPUs.
2052 config CPU_FREQ_SA1100
2053 bool
2055 config CPU_FREQ_SA1110
2056 bool
2058 config CPU_FREQ_INTEGRATOR
2059 tristate "CPUfreq driver for ARM Integrator CPUs"
2060 depends on ARCH_INTEGRATOR && CPU_FREQ
2061 default y
2062 help
2063 This enables the CPUfreq driver for ARM Integrator CPUs.
2065 For details, take a look at <file:Documentation/cpu-freq>.
2067 If in doubt, say Y.
2069 config CPU_FREQ_PXA
2070 bool
2071 depends on CPU_FREQ && ARCH_PXA && PXA25x
2072 default y
2073 select CPU_FREQ_TABLE
2074 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2076 config CPU_FREQ_S3C
2077 bool
2078 help
2079 Internal configuration node for common cpufreq on Samsung SoC
2081 config CPU_FREQ_S3C24XX
2082 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2083 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2084 select CPU_FREQ_S3C
2085 help
2086 This enables the CPUfreq driver for the Samsung S3C24XX family
2087 of CPUs.
2089 For details, take a look at <file:Documentation/cpu-freq>.
2091 If in doubt, say N.
2093 config CPU_FREQ_S3C24XX_PLL
2094 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2095 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2096 help
2097 Compile in support for changing the PLL frequency from the
2098 S3C24XX series CPUfreq driver. The PLL takes time to settle
2099 after a frequency change, so by default it is not enabled.
2101 This also means that the PLL tables for the selected CPU(s) will
2102 be built which may increase the size of the kernel image.
2104 config CPU_FREQ_S3C24XX_DEBUG
2105 bool "Debug CPUfreq Samsung driver core"
2106 depends on CPU_FREQ_S3C24XX
2107 help
2108 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2110 config CPU_FREQ_S3C24XX_IODEBUG
2111 bool "Debug CPUfreq Samsung driver IO timing"
2112 depends on CPU_FREQ_S3C24XX
2113 help
2114 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2116 config CPU_FREQ_S3C24XX_DEBUGFS
2117 bool "Export debugfs for CPUFreq"
2118 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2119 help
2120 Export status information via debugfs.
2122 endif
2124 source "drivers/cpuidle/Kconfig"
2126 endmenu
2128 menu "Floating point emulation"
2130 comment "At least one emulation must be selected"
2132 config FPE_NWFPE
2133 bool "NWFPE math emulation"
2134 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2135 ---help---
2136 Say Y to include the NWFPE floating point emulator in the kernel.
2137 This is necessary to run most binaries. Linux does not currently
2138 support floating point hardware so you need to say Y here even if
2139 your machine has an FPA or floating point co-processor podule.
2141 You may say N here if you are going to load the Acorn FPEmulator
2142 early in the bootup.
2144 config FPE_NWFPE_XP
2145 bool "Support extended precision"
2146 depends on FPE_NWFPE
2147 help
2148 Say Y to include 80-bit support in the kernel floating-point
2149 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2150 Note that gcc does not generate 80-bit operations by default,
2151 so in most cases this option only enlarges the size of the
2152 floating point emulator without any good reason.
2154 You almost surely want to say N here.
2156 config FPE_FASTFPE
2157 bool "FastFPE math emulation (EXPERIMENTAL)"
2158 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2159 ---help---
2160 Say Y here to include the FAST floating point emulator in the kernel.
2161 This is an experimental much faster emulator which now also has full
2162 precision for the mantissa. It does not support any exceptions.
2163 It is very simple, and approximately 3-6 times faster than NWFPE.
2165 It should be sufficient for most programs. It may be not suitable
2166 for scientific calculations, but you have to check this for yourself.
2167 If you do not feel you need a faster FP emulation you should better
2168 choose NWFPE.
2170 config VFP
2171 bool "VFP-format floating point maths"
2172 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2173 help
2174 Say Y to include VFP support code in the kernel. This is needed
2175 if your hardware includes a VFP unit.
2177 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2178 release notes and additional status information.
2180 Say N if your target does not have VFP hardware.
2182 config VFPv3
2183 bool
2184 depends on VFP
2185 default y if CPU_V7
2187 config NEON
2188 bool "Advanced SIMD (NEON) Extension support"
2189 depends on VFPv3 && CPU_V7
2190 help
2191 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2192 Extension.
2194 endmenu
2196 menu "Userspace binary formats"
2198 source "fs/Kconfig.binfmt"
2200 config ARTHUR
2201 tristate "RISC OS personality"
2202 depends on !AEABI
2203 help
2204 Say Y here to include the kernel code necessary if you want to run
2205 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2206 experimental; if this sounds frightening, say N and sleep in peace.
2207 You can also say M here to compile this support as a module (which
2208 will be called arthur).
2210 endmenu
2212 menu "Power management options"
2214 source "kernel/power/Kconfig"
2216 config ARCH_SUSPEND_POSSIBLE
2217 depends on !ARCH_S5PC100
2218 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2219 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2220 def_bool y
2222 config ARM_CPU_SUSPEND
2223 def_bool PM_SLEEP
2225 endmenu
2227 source "net/Kconfig"
2229 source "drivers/Kconfig"
2231 source "fs/Kconfig"
2233 source "arch/arm/Kconfig.debug"
2235 source "security/Kconfig"
2237 source "crypto/Kconfig"
2239 source "lib/Kconfig"