2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/device.h>
26 #include <subdev/bios.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/therm.h>
31 #include <subdev/devinit.h>
32 #include <subdev/mc.h>
33 #include <subdev/timer.h>
34 #include <subdev/fb.h>
35 #include <subdev/instmem.h>
36 #include <subdev/vm.h>
38 #include <engine/dmaobj.h>
39 #include <engine/fifo.h>
40 #include <engine/software.h>
41 #include <engine/graph.h>
42 #include <engine/mpeg.h>
43 #include <engine/disp.h>
46 nv40_identify(struct nouveau_device
*device
)
48 switch (device
->chipset
) {
50 device
->cname
= "NV40";
51 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
52 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
53 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
54 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
55 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
56 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
57 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
58 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
59 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
60 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
61 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
62 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
63 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
64 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
65 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
66 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
67 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
70 device
->cname
= "NV41";
71 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
72 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
73 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
74 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
75 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
76 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
77 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
78 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
79 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
80 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
81 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
82 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
83 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
84 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
85 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
86 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
87 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
90 device
->cname
= "NV42";
91 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
92 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
93 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
94 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
95 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
96 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
97 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
98 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
99 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
100 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
101 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
102 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
103 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
104 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
105 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
106 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
107 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
110 device
->cname
= "NV43";
111 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
112 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
113 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
114 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
115 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
116 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
117 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
118 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
119 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
120 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
121 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
122 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
123 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
124 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
125 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
126 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
127 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
130 device
->cname
= "NV45";
131 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
132 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
133 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
134 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
135 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
136 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
137 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
138 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
139 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
140 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
141 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
142 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
143 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
144 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
145 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
146 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
147 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
150 device
->cname
= "G70";
151 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
152 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
153 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
154 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
155 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
156 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
157 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
158 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
159 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
160 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
161 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
162 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
163 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
164 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
165 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
166 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
167 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
170 device
->cname
= "G71";
171 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
172 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
173 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
174 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
175 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
176 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
177 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
178 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
179 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
180 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
181 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
182 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
183 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
184 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
185 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
186 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
187 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
190 device
->cname
= "G73";
191 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
192 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
193 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
194 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
195 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
196 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
197 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv04_mc_oclass
;
198 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
199 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
200 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
201 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
202 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
203 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
204 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
205 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
206 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
207 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
210 device
->cname
= "NV44";
211 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
212 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
213 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
214 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
215 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
216 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
217 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
218 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
219 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
220 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
221 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
222 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
223 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
224 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
225 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
226 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
227 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
230 device
->cname
= "G72";
231 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
232 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
233 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
234 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
235 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
236 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
237 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
238 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
239 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
240 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
241 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
242 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
243 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
244 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
245 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
246 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
247 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
250 device
->cname
= "NV44A";
251 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
252 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
253 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
254 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
255 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
256 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
257 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
258 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
259 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
260 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
261 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
262 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
263 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
264 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
265 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
266 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
267 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
270 device
->cname
= "C61";
271 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
272 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
273 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
274 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
275 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
276 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
277 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
278 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
279 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
280 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
281 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
282 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
283 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
284 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
285 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
286 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
287 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
290 device
->cname
= "C51";
291 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
292 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
293 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
294 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
295 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
296 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
297 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
298 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
299 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
300 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
301 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
302 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
303 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
304 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
305 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
306 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
307 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
310 device
->cname
= "C73";
311 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
312 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
313 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
314 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
315 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
316 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
317 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
318 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
319 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
320 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
321 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
322 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
323 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
324 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
325 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
326 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
327 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
330 device
->cname
= "C67";
331 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
332 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
333 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
334 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
335 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
336 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
337 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
338 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
339 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
340 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
341 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
342 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
343 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
344 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
345 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
346 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
347 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
350 device
->cname
= "C68";
351 device
->oclass
[NVDEV_SUBDEV_VBIOS
] = &nouveau_bios_oclass
;
352 device
->oclass
[NVDEV_SUBDEV_GPIO
] = &nv10_gpio_oclass
;
353 device
->oclass
[NVDEV_SUBDEV_I2C
] = &nouveau_i2c_oclass
;
354 device
->oclass
[NVDEV_SUBDEV_CLOCK
] = &nv40_clock_oclass
;
355 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
356 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = &nv1a_devinit_oclass
;
357 device
->oclass
[NVDEV_SUBDEV_MC
] = &nv44_mc_oclass
;
358 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
359 device
->oclass
[NVDEV_SUBDEV_FB
] = &nv40_fb_oclass
;
360 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = &nv40_instmem_oclass
;
361 device
->oclass
[NVDEV_SUBDEV_VM
] = &nv04_vmmgr_oclass
;
362 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = &nv04_dmaeng_oclass
;
363 device
->oclass
[NVDEV_ENGINE_FIFO
] = &nv40_fifo_oclass
;
364 device
->oclass
[NVDEV_ENGINE_SW
] = &nv10_software_oclass
;
365 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_graph_oclass
;
366 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
367 device
->oclass
[NVDEV_ENGINE_DISP
] = &nv04_disp_oclass
;
370 nv_fatal(device
, "unknown Curie chipset\n");