drivers/net/ixgbe/ixgbe_common.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _IXGBE_COMMON_H_
  30 #define _IXGBE_COMMON_H_
  31
  32 #include "ixgbe_type.h"
  33
  34 s32 ixgbe_init_hw(struct ixgbe_hw *hw);
  35 s32 ixgbe_start_hw(struct ixgbe_hw *hw);
  36 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
  37 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
  38 s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num);
  39
  40 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
  41 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
  42
  43 s32 ixgbe_init_eeprom(struct ixgbe_hw *hw);
  44 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
  45 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
  46
  47 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind,
  48                   u32 enable_addr);
  49 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
  50                               u32 mc_addr_count, u32 pad);
  51 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);
  52 s32 ixgbe_validate_mac_addr(u8 *mac_addr);
  53
  54 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packtetbuf_num);
  55
  56 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
  57 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
  58 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
  59
  60 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
  61 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
  62
  63 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
  64
  65 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
  66
  67 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
  68     writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
  69
  70 #define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
  71     readl((a)->hw_addr + (reg) + ((offset) << 2)))
  72
  73 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
  74
  75 #ifdef DEBUG
  76 #define hw_dbg(hw, format, arg...) \
  77 printk(KERN_DEBUG, "%s: " format, ixgbe_get_hw_dev_name(hw), ##arg);
  78 #else
  79 static inline int __attribute__ ((format (printf, 2, 3)))
  80 hw_dbg(struct ixgbe_hw *hw, const char *format, ...)
  81 {
  82         return 0;
  83 }
  84 #endif
  85
  86 #endif /* IXGBE_COMMON */