arch/arm/mach-shmobile/setup-r8a7778.c

   1 /*
   2  * r8a7778 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/irqchip/arm-gic.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_data/gpio-rcar.h>
  28 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/irqchip.h>
  31 #include <linux/serial_sci.h>
  32 #include <linux/sh_timer.h>
  33 #include <mach/irqs.h>
  34 #include <mach/r8a7778.h>
  35 #include <mach/common.h>
  36 #include <asm/mach/arch.h>
  37 #include <asm/hardware/cache-l2x0.h>
  38
  39 /* SCIF */
  40 #define SCIF_INFO(baseaddr, irq)                                \
  41 {                                                               \
  42         .mapbase        = baseaddr,                             \
  43         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
  44         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
  45         .scbrr_algo_id  = SCBRR_ALGO_2,                         \
  46         .type           = PORT_SCIF,                            \
  47         .irqs           = SCIx_IRQ_MUXED(irq),                  \
  48 }
  49
  50 static struct plat_sci_port scif_platform_data[] = {
  51         SCIF_INFO(0xffe40000, gic_iid(0x66)),
  52         SCIF_INFO(0xffe41000, gic_iid(0x67)),
  53         SCIF_INFO(0xffe42000, gic_iid(0x68)),
  54         SCIF_INFO(0xffe43000, gic_iid(0x69)),
  55         SCIF_INFO(0xffe44000, gic_iid(0x6a)),
  56         SCIF_INFO(0xffe45000, gic_iid(0x6b)),
  57 };
  58
  59 /* TMU */
  60 static struct resource sh_tmu0_resources[] = {
  61         DEFINE_RES_MEM(0xffd80008, 12),
  62         DEFINE_RES_IRQ(gic_iid(0x40)),
  63 };
  64
  65 static struct sh_timer_config sh_tmu0_platform_data = {
  66         .name                   = "TMU00",
  67         .channel_offset         = 0x4,
  68         .timer_bit              = 0,
  69         .clockevent_rating      = 200,
  70 };
  71
  72 static struct resource sh_tmu1_resources[] = {
  73         DEFINE_RES_MEM(0xffd80014, 12),
  74         DEFINE_RES_IRQ(gic_iid(0x41)),
  75 };
  76
  77 static struct sh_timer_config sh_tmu1_platform_data = {
  78         .name                   = "TMU01",
  79         .channel_offset         = 0x10,
  80         .timer_bit              = 1,
  81         .clocksource_rating     = 200,
  82 };
  83
  84 #define r8a7778_register_tmu(idx)                       \
  85         platform_device_register_resndata(              \
  86                 &platform_bus, "sh_tmu", idx,           \
  87                 sh_tmu##idx##_resources,                \
  88                 ARRAY_SIZE(sh_tmu##idx##_resources),    \
  89                 &sh_tmu##idx##_platform_data,           \
  90                 sizeof(sh_tmu##idx##_platform_data))
  91
  92 /* Ether */
  93 static struct resource ether_resources[] = {
  94         DEFINE_RES_MEM(0xfde00000, 0x400),
  95         DEFINE_RES_IRQ(gic_iid(0x89)),
  96 };
  97
  98 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
  99 {
 100         platform_device_register_resndata(&platform_bus, "sh_eth", -1,
 101                                           ether_resources,
 102                                           ARRAY_SIZE(ether_resources),
 103                                           pdata, sizeof(*pdata));
 104 }
 105
 106 /* PFC/GPIO */
 107 static struct resource pfc_resources[] = {
 108         DEFINE_RES_MEM(0xfffc0000, 0x118),
 109 };
 110
 111 #define R8A7778_GPIO(idx)                                               \
 112 static struct resource r8a7778_gpio##idx##_resources[] = {              \
 113         DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
 114         DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
 115 };                                                                      \
 116                                                                         \
 117 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
 118         .gpio_base      = 32 * (idx),                                   \
 119         .irq_base       = GPIO_IRQ_BASE(idx),                           \
 120         .number_of_pins = 32,                                           \
 121         .pctl_name      = "pfc-r8a7778",                                \
 122 }
 123
 124 R8A7778_GPIO(0);
 125 R8A7778_GPIO(1);
 126 R8A7778_GPIO(2);
 127 R8A7778_GPIO(3);
 128 R8A7778_GPIO(4);
 129
 130 #define r8a7778_register_gpio(idx)                              \
 131         platform_device_register_resndata(                      \
 132                 &platform_bus, "gpio_rcar", idx,                \
 133                 r8a7778_gpio##idx##_resources,                  \
 134                 ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
 135                 &r8a7778_gpio##idx##_platform_data,             \
 136                 sizeof(r8a7778_gpio##idx##_platform_data))
 137
 138 void __init r8a7778_pinmux_init(void)
 139 {
 140         platform_device_register_simple(
 141                 "pfc-r8a7778", -1,
 142                 pfc_resources,
 143                 ARRAY_SIZE(pfc_resources));
 144
 145         r8a7778_register_gpio(0);
 146         r8a7778_register_gpio(1);
 147         r8a7778_register_gpio(2);
 148         r8a7778_register_gpio(3);
 149         r8a7778_register_gpio(4);
 150 };
 151
 152 /* SDHI */
 153 static struct resource sdhi_resources[] = {
 154         /* SDHI0 */
 155         DEFINE_RES_MEM(0xFFE4C000, 0x100),
 156         DEFINE_RES_IRQ(gic_iid(0x77)),
 157         /* SDHI1 */
 158         DEFINE_RES_MEM(0xFFE4D000, 0x100),
 159         DEFINE_RES_IRQ(gic_iid(0x78)),
 160         /* SDHI2 */
 161         DEFINE_RES_MEM(0xFFE4F000, 0x100),
 162         DEFINE_RES_IRQ(gic_iid(0x76)),
 163 };
 164
 165 void __init r8a7778_sdhi_init(int id,
 166                               struct sh_mobile_sdhi_info *info)
 167 {
 168         BUG_ON(id < 0 || id > 2);
 169
 170         platform_device_register_resndata(
 171                 &platform_bus, "sh_mobile_sdhi", id,
 172                 sdhi_resources + (2 * id), 2,
 173                 info, sizeof(*info));
 174 }
 175
 176 void __init r8a7778_add_standard_devices(void)
 177 {
 178         int i;
 179
 180 #ifdef CONFIG_CACHE_L2X0
 181         void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
 182         if (base) {
 183                 /*
 184                  * Early BRESP enable, Shared attribute override enable, 64K*16way
 185                  * don't call iounmap(base)
 186                  */
 187                 l2x0_init(base, 0x40470000, 0x82000fff);
 188         }
 189 #endif
 190
 191         for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
 192                 platform_device_register_data(&platform_bus, "sh-sci", i,
 193                                               &scif_platform_data[i],
 194                                               sizeof(struct plat_sci_port));
 195
 196         r8a7778_register_tmu(0);
 197         r8a7778_register_tmu(1);
 198 }
 199
 200 static struct renesas_intc_irqpin_config irqpin_platform_data = {
 201         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 202         .sense_bitfield_width = 2,
 203 };
 204
 205 static struct resource irqpin_resources[] = {
 206         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
 207         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
 208         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
 209         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
 210         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
 211         DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
 212         DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
 213         DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
 214         DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
 215 };
 216
 217 void __init r8a7778_init_irq_extpin(int irlm)
 218 {
 219         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 220         unsigned long tmp;
 221
 222         if (!icr0) {
 223                 pr_warn("r8a7778: unable to setup external irq pin mode\n");
 224                 return;
 225         }
 226
 227         tmp = ioread32(icr0);
 228         if (irlm)
 229                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 230         else
 231                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 232         tmp |= (1 << 21); /* LVLMODE = 1 */
 233         iowrite32(tmp, icr0);
 234         iounmap(icr0);
 235
 236         if (irlm)
 237                 platform_device_register_resndata(
 238                         &platform_bus, "renesas_intc_irqpin", -1,
 239                         irqpin_resources, ARRAY_SIZE(irqpin_resources),
 240                         &irqpin_platform_data, sizeof(irqpin_platform_data));
 241 }
 242
 243 #define INT2SMSKCR0     0x82288 /* 0xfe782288 */
 244 #define INT2SMSKCR1     0x8228c /* 0xfe78228c */
 245
 246 #define INT2NTSR0       0x00018 /* 0xfe700018 */
 247 #define INT2NTSR1       0x0002c /* 0xfe70002c */
 248 static void __init r8a7778_init_irq_common(void)
 249 {
 250         void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
 251
 252         BUG_ON(!base);
 253
 254         /* route all interrupts to ARM */
 255         __raw_writel(0x73ffffff, base + INT2NTSR0);
 256         __raw_writel(0xffffffff, base + INT2NTSR1);
 257
 258         /* unmask all known interrupts in INTCS2 */
 259         __raw_writel(0x08330773, base + INT2SMSKCR0);
 260         __raw_writel(0x00311110, base + INT2SMSKCR1);
 261
 262         iounmap(base);
 263 }
 264
 265 void __init r8a7778_init_irq(void)
 266 {
 267         void __iomem *gic_dist_base;
 268         void __iomem *gic_cpu_base;
 269
 270         gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
 271         gic_cpu_base  = ioremap_nocache(0xfe430000, PAGE_SIZE);
 272         BUG_ON(!gic_dist_base || !gic_cpu_base);
 273
 274         /* use GIC to handle interrupts */
 275         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 276
 277         r8a7778_init_irq_common();
 278 }
 279
 280 void __init r8a7778_init_delay(void)
 281 {
 282         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 283 }
 284
 285 #ifdef CONFIG_USE_OF
 286 void __init r8a7778_init_irq_dt(void)
 287 {
 288         irqchip_init();
 289         r8a7778_init_irq_common();
 290 }
 291
 292 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
 293         {},
 294 };
 295
 296 void __init r8a7778_add_standard_devices_dt(void)
 297 {
 298         of_platform_populate(NULL, of_default_bus_match_table,
 299                              r8a7778_auxdata_lookup, NULL);
 300 }
 301
 302 static const char *r8a7778_compat_dt[] __initdata = {
 303         "renesas,r8a7778",
 304         NULL,
 305 };
 306
 307 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
 308         .init_early     = r8a7778_init_delay,
 309         .init_irq       = r8a7778_init_irq_dt,
 310         .init_machine   = r8a7778_add_standard_devices_dt,
 311         .init_time      = shmobile_timer_init,
 312         .dt_compat      = r8a7778_compat_dt,
 313 MACHINE_END
 314
 315 #endif /* CONFIG_USE_OF */