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scsi: delete the MCA specific drivers and driver code
[linux-2.6.git] / drivers / scsi / qla2xxx / qla_sup.c
bloba683e766d1aea088115eb3bde698ebf8390c5a1d
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/vmalloc.h>
12 #include <asm/uaccess.h>
13
14 /*
15 * NVRAM support routines
16 */
17
18 /**
19 * qla2x00_lock_nvram_access() -
20 * @ha: HA context
21 */
22 static void
23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
24 {
25 uint16_t data;
26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(&reg->nvram);
30 while (data & NVR_BUSY) {
31 udelay(100);
32 data = RD_REG_WORD(&reg->nvram);
33 }
34
35 /* Lock resource */
36 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
38 udelay(5);
39 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
41 /* Lock failed */
42 udelay(100);
43 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
45 udelay(5);
46 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 }
48 }
49 }
50
51 /**
52 * qla2x00_unlock_nvram_access() -
53 * @ha: HA context
54 */
55 static void
56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57 {
58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
63 }
64 }
65
66 /**
67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @ha: HA context
69 * @data: Serial interface selector
70 */
71 static void
72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73 {
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75
76 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
78 NVRAM_DELAY();
79 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
80 NVR_WRT_ENABLE);
81 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
82 NVRAM_DELAY();
83 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
85 NVRAM_DELAY();
86 }
87
88 /**
89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
90 * NVRAM.
91 * @ha: HA context
92 * @nv_cmd: NVRAM command
93 *
94 * Bit definitions for NVRAM command:
95 *
96 * Bit 26 = start bit
97 * Bit 25, 24 = opcode
98 * Bit 23-16 = address
99 * Bit 15-0 = write data
100 *
101 * Returns the word read from nvram @addr.
102 */
103 static uint16_t
104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
105 {
106 uint8_t cnt;
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
108 uint16_t data = 0;
109 uint16_t reg_data;
110
111 /* Send command to NVRAM. */
112 nv_cmd <<= 5;
113 for (cnt = 0; cnt < 11; cnt++) {
114 if (nv_cmd & BIT_31)
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 else
117 qla2x00_nv_write(ha, 0);
118 nv_cmd <<= 1;
119 }
120
121 /* Read data from NVRAM. */
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
125 NVRAM_DELAY();
126 data <<= 1;
127 reg_data = RD_REG_WORD(&reg->nvram);
128 if (reg_data & NVR_DATA_IN)
129 data |= BIT_0;
130 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
131 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
132 NVRAM_DELAY();
133 }
134
135 /* Deselect chip. */
136 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
137 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
138 NVRAM_DELAY();
139
140 return data;
141 }
142
143
144 /**
145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
146 * request routine to get the word from NVRAM.
147 * @ha: HA context
148 * @addr: Address in NVRAM to read
149 *
150 * Returns the word read from nvram @addr.
151 */
152 static uint16_t
153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
154 {
155 uint16_t data;
156 uint32_t nv_cmd;
157
158 nv_cmd = addr << 16;
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
161
162 return (data);
163 }
164
165 /**
166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
167 * @ha: HA context
168 */
169 static void
170 qla2x00_nv_deselect(struct qla_hw_data *ha)
171 {
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173
174 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
175 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
176 NVRAM_DELAY();
177 }
178
179 /**
180 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @ha: HA context
182 * @addr: Address in NVRAM to write
183 * @data: word to program
184 */
185 static void
186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
187 {
188 int count;
189 uint16_t word;
190 uint32_t nv_cmd, wait_cnt;
191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
193
194 qla2x00_nv_write(ha, NVR_DATA_OUT);
195 qla2x00_nv_write(ha, 0);
196 qla2x00_nv_write(ha, 0);
197
198 for (word = 0; word < 8; word++)
199 qla2x00_nv_write(ha, NVR_DATA_OUT);
200
201 qla2x00_nv_deselect(ha);
202
203 /* Write data */
204 nv_cmd = (addr << 16) | NV_WRITE_OP;
205 nv_cmd |= data;
206 nv_cmd <<= 5;
207 for (count = 0; count < 27; count++) {
208 if (nv_cmd & BIT_31)
209 qla2x00_nv_write(ha, NVR_DATA_OUT);
210 else
211 qla2x00_nv_write(ha, 0);
212
213 nv_cmd <<= 1;
214 }
215
216 qla2x00_nv_deselect(ha);
217
218 /* Wait for NVRAM to become ready */
219 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
220 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
221 wait_cnt = NVR_WAIT_CNT;
222 do {
223 if (!--wait_cnt) {
224 ql_dbg(ql_dbg_user, vha, 0x708d,
225 "NVRAM didn't go ready...\n");
226 break;
227 }
228 NVRAM_DELAY();
229 word = RD_REG_WORD(&reg->nvram);
230 } while ((word & NVR_DATA_IN) == 0);
231
232 qla2x00_nv_deselect(ha);
233
234 /* Disable writes */
235 qla2x00_nv_write(ha, NVR_DATA_OUT);
236 for (count = 0; count < 10; count++)
237 qla2x00_nv_write(ha, 0);
238
239 qla2x00_nv_deselect(ha);
240 }
241
242 static int
243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
244 uint16_t data, uint32_t tmo)
245 {
246 int ret, count;
247 uint16_t word;
248 uint32_t nv_cmd;
249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
250
251 ret = QLA_SUCCESS;
252
253 qla2x00_nv_write(ha, NVR_DATA_OUT);
254 qla2x00_nv_write(ha, 0);
255 qla2x00_nv_write(ha, 0);
256
257 for (word = 0; word < 8; word++)
258 qla2x00_nv_write(ha, NVR_DATA_OUT);
259
260 qla2x00_nv_deselect(ha);
261
262 /* Write data */
263 nv_cmd = (addr << 16) | NV_WRITE_OP;
264 nv_cmd |= data;
265 nv_cmd <<= 5;
266 for (count = 0; count < 27; count++) {
267 if (nv_cmd & BIT_31)
268 qla2x00_nv_write(ha, NVR_DATA_OUT);
269 else
270 qla2x00_nv_write(ha, 0);
271
272 nv_cmd <<= 1;
273 }
274
275 qla2x00_nv_deselect(ha);
276
277 /* Wait for NVRAM to become ready */
278 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
279 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
280 do {
281 NVRAM_DELAY();
282 word = RD_REG_WORD(&reg->nvram);
283 if (!--tmo) {
284 ret = QLA_FUNCTION_FAILED;
285 break;
286 }
287 } while ((word & NVR_DATA_IN) == 0);
288
289 qla2x00_nv_deselect(ha);
290
291 /* Disable writes */
292 qla2x00_nv_write(ha, NVR_DATA_OUT);
293 for (count = 0; count < 10; count++)
294 qla2x00_nv_write(ha, 0);
295
296 qla2x00_nv_deselect(ha);
297
298 return ret;
299 }
300
301 /**
302 * qla2x00_clear_nvram_protection() -
303 * @ha: HA context
304 */
305 static int
306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
307 {
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
310 uint32_t word, wait_cnt;
311 uint16_t wprot, wprot_old;
312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
313
314 /* Clear NVRAM write protection. */
315 ret = QLA_FUNCTION_FAILED;
316
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319 __constant_cpu_to_le16(0x1234), 100000);
320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
322 /* Write enable. */
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
328
329 qla2x00_nv_deselect(ha);
330
331 /* Enable protection register. */
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337
338 qla2x00_nv_deselect(ha);
339
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346
347 qla2x00_nv_deselect(ha);
348
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
351 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
352 wait_cnt = NVR_WAIT_CNT;
353 do {
354 if (!--wait_cnt) {
355 ql_dbg(ql_dbg_user, vha, 0x708e,
356 "NVRAM didn't go ready...\n");
357 break;
358 }
359 NVRAM_DELAY();
360 word = RD_REG_WORD(&reg->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
363 if (wait_cnt)
364 ret = QLA_SUCCESS;
365 } else
366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
367
368 return ret;
369 }
370
371 static void
372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
373 {
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
375 uint32_t word, wait_cnt;
376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
377
378 if (stat != QLA_SUCCESS)
379 return;
380
381 /* Set NVRAM write protection. */
382 /* Write enable. */
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
388
389 qla2x00_nv_deselect(ha);
390
391 /* Enable protection register. */
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397
398 qla2x00_nv_deselect(ha);
399
400 /* Enable protection register. */
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406
407 qla2x00_nv_deselect(ha);
408
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
411 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
412 wait_cnt = NVR_WAIT_CNT;
413 do {
414 if (!--wait_cnt) {
415 ql_dbg(ql_dbg_user, vha, 0x708f,
416 "NVRAM didn't go ready...\n");
417 break;
418 }
419 NVRAM_DELAY();
420 word = RD_REG_WORD(&reg->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
422 }
423
424
425 /*****************************************************************************/
426 /* Flash Manipulation Routines */
427 /*****************************************************************************/
428
429 static inline uint32_t
430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
431 {
432 return ha->flash_conf_off | faddr;
433 }
434
435 static inline uint32_t
436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
437 {
438 return ha->flash_data_off | faddr;
439 }
440
441 static inline uint32_t
442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
443 {
444 return ha->nvram_conf_off | naddr;
445 }
446
447 static inline uint32_t
448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
449 {
450 return ha->nvram_data_off | naddr;
451 }
452
453 static uint32_t
454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
455 {
456 int rval;
457 uint32_t cnt, data;
458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
459
460 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
461 /* Wait for READ cycle to complete. */
462 rval = QLA_SUCCESS;
463 for (cnt = 3000;
464 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
465 rval == QLA_SUCCESS; cnt--) {
466 if (cnt)
467 udelay(10);
468 else
469 rval = QLA_FUNCTION_TIMEOUT;
470 cond_resched();
471 }
472
473 /* TODO: What happens if we time out? */
474 data = 0xDEADDEAD;
475 if (rval == QLA_SUCCESS)
476 data = RD_REG_DWORD(&reg->flash_data);
477
478 return data;
479 }
480
481 uint32_t *
482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
483 uint32_t dwords)
484 {
485 uint32_t i;
486 struct qla_hw_data *ha = vha->hw;
487
488 /* Dword reads to flash. */
489 for (i = 0; i < dwords; i++, faddr++)
490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491 flash_data_addr(ha, faddr)));
492
493 return dwptr;
494 }
495
496 static int
497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
498 {
499 int rval;
500 uint32_t cnt;
501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
502
503 WRT_REG_DWORD(&reg->flash_data, data);
504 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
505 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
506 /* Wait for Write cycle to complete. */
507 rval = QLA_SUCCESS;
508 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
509 rval == QLA_SUCCESS; cnt--) {
510 if (cnt)
511 udelay(10);
512 else
513 rval = QLA_FUNCTION_TIMEOUT;
514 cond_resched();
515 }
516 return rval;
517 }
518
519 static void
520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
521 uint8_t *flash_id)
522 {
523 uint32_t ids;
524
525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
526 *man_id = LSB(ids);
527 *flash_id = MSB(ids);
528
529 /* Check if man_id and flash_id are valid. */
530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
531 /* Read information using 0x9f opcode
532 * Device ID, Mfg ID would be read in the format:
533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
534 * Example: ATMEL 0x00 01 45 1F
535 * Extract MFG and Dev ID from last two bytes.
536 */
537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
538 *man_id = LSB(ids);
539 *flash_id = MSB(ids);
540 }
541 }
542
543 static int
544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
545 {
546 const char *loc, *locations[] = { "DEF", "PCI" };
547 uint32_t pcihdr, pcids;
548 uint32_t *dcode;
549 uint8_t *buf, *bcode, last_image;
550 uint16_t cnt, chksum, *wptr;
551 struct qla_flt_location *fltl;
552 struct qla_hw_data *ha = vha->hw;
553 struct req_que *req = ha->req_q_map[0];
554
555 /*
556 * FLT-location structure resides after the last PCI region.
557 */
558
559 /* Begin with sane defaults. */
560 loc = locations[0];
561 *start = 0;
562 if (IS_QLA24XX_TYPE(ha))
563 *start = FA_FLASH_LAYOUT_ADDR_24;
564 else if (IS_QLA25XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR;
566 else if (IS_QLA81XX(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_81;
568 else if (IS_QLA82XX(ha)) {
569 *start = FA_FLASH_LAYOUT_ADDR_82;
570 goto end;
571 } else if (IS_QLA83XX(ha)) {
572 *start = FA_FLASH_LAYOUT_ADDR_83;
573 goto end;
574 }
575 /* Begin with first PCI expansion ROM header. */
576 buf = (uint8_t *)req->ring;
577 dcode = (uint32_t *)req->ring;
578 pcihdr = 0;
579 last_image = 1;
580 do {
581 /* Verify PCI expansion ROM header. */
582 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
583 bcode = buf + (pcihdr % 4);
584 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
585 goto end;
586
587 /* Locate PCI data structure. */
588 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
589 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
590 bcode = buf + (pcihdr % 4);
591
592 /* Validate signature of PCI data structure. */
593 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
594 bcode[0x2] != 'I' || bcode[0x3] != 'R')
595 goto end;
596
597 last_image = bcode[0x15] & BIT_7;
598
599 /* Locate next PCI expansion ROM. */
600 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
601 } while (!last_image);
602
603 /* Now verify FLT-location structure. */
604 fltl = (struct qla_flt_location *)req->ring;
605 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
606 sizeof(struct qla_flt_location) >> 2);
607 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
608 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
609 goto end;
610
611 wptr = (uint16_t *)req->ring;
612 cnt = sizeof(struct qla_flt_location) >> 1;
613 for (chksum = 0; cnt; cnt--)
614 chksum += le16_to_cpu(*wptr++);
615 if (chksum) {
616 ql_log(ql_log_fatal, vha, 0x0045,
617 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
618 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
619 buf, sizeof(struct qla_flt_location));
620 return QLA_FUNCTION_FAILED;
621 }
622
623 /* Good data. Use specified location. */
624 loc = locations[1];
625 *start = (le16_to_cpu(fltl->start_hi) << 16 |
626 le16_to_cpu(fltl->start_lo)) >> 2;
627 end:
628 ql_dbg(ql_dbg_init, vha, 0x0046,
629 "FLTL[%s] = 0x%x.\n",
630 loc, *start);
631 return QLA_SUCCESS;
632 }
633
634 static void
635 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
636 {
637 const char *loc, *locations[] = { "DEF", "FLT" };
638 const uint32_t def_fw[] =
639 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
640 const uint32_t def_boot[] =
641 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
642 const uint32_t def_vpd_nvram[] =
643 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
644 const uint32_t def_vpd0[] =
645 { 0, 0, FA_VPD0_ADDR_81 };
646 const uint32_t def_vpd1[] =
647 { 0, 0, FA_VPD1_ADDR_81 };
648 const uint32_t def_nvram0[] =
649 { 0, 0, FA_NVRAM0_ADDR_81 };
650 const uint32_t def_nvram1[] =
651 { 0, 0, FA_NVRAM1_ADDR_81 };
652 const uint32_t def_fdt[] =
653 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
654 FA_FLASH_DESCR_ADDR_81 };
655 const uint32_t def_npiv_conf0[] =
656 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
657 FA_NPIV_CONF0_ADDR_81 };
658 const uint32_t def_npiv_conf1[] =
659 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
660 FA_NPIV_CONF1_ADDR_81 };
661 const uint32_t fcp_prio_cfg0[] =
662 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
663 0 };
664 const uint32_t fcp_prio_cfg1[] =
665 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
666 0 };
667 uint32_t def;
668 uint16_t *wptr;
669 uint16_t cnt, chksum;
670 uint32_t start;
671 struct qla_flt_header *flt;
672 struct qla_flt_region *region;
673 struct qla_hw_data *ha = vha->hw;
674 struct req_que *req = ha->req_q_map[0];
675
676 def = 0;
677 if (IS_QLA25XX(ha))
678 def = 1;
679 else if (IS_QLA81XX(ha))
680 def = 2;
681
682 /* Assign FCP prio region since older adapters may not have FLT, or
683 FCP prio region in it's FLT.
684 */
685 ha->flt_region_fcp_prio = ha->flags.port0 ?
686 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
687
688 ha->flt_region_flt = flt_addr;
689 wptr = (uint16_t *)req->ring;
690 flt = (struct qla_flt_header *)req->ring;
691 region = (struct qla_flt_region *)&flt[1];
692 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
693 flt_addr << 2, OPTROM_BURST_SIZE);
694 if (*wptr == __constant_cpu_to_le16(0xffff))
695 goto no_flash_data;
696 if (flt->version != __constant_cpu_to_le16(1)) {
697 ql_log(ql_log_warn, vha, 0x0047,
698 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
699 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
700 le16_to_cpu(flt->checksum));
701 goto no_flash_data;
702 }
703
704 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
705 for (chksum = 0; cnt; cnt--)
706 chksum += le16_to_cpu(*wptr++);
707 if (chksum) {
708 ql_log(ql_log_fatal, vha, 0x0048,
709 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
710 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
711 le16_to_cpu(flt->checksum));
712 goto no_flash_data;
713 }
714
715 loc = locations[1];
716 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
717 for ( ; cnt; cnt--, region++) {
718 /* Store addresses as DWORD offsets. */
719 start = le32_to_cpu(region->start) >> 2;
720 ql_dbg(ql_dbg_init, vha, 0x0049,
721 "FLT[%02x]: start=0x%x "
722 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code),
723 start, le32_to_cpu(region->end) >> 2,
724 le32_to_cpu(region->size));
725
726 switch (le32_to_cpu(region->code) & 0xff) {
727 case FLT_REG_FCOE_FW:
728 if (!IS_QLA8031(ha))
729 break;
730 ha->flt_region_fw = start;
731 break;
732 case FLT_REG_FW:
733 if (IS_QLA8031(ha))
734 break;
735 ha->flt_region_fw = start;
736 break;
737 case FLT_REG_BOOT_CODE:
738 ha->flt_region_boot = start;
739 break;
740 case FLT_REG_VPD_0:
741 if (IS_QLA8031(ha))
742 break;
743 ha->flt_region_vpd_nvram = start;
744 if (IS_QLA82XX(ha))
745 break;
746 if (ha->flags.port0)
747 ha->flt_region_vpd = start;
748 break;
749 case FLT_REG_VPD_1:
750 if (IS_QLA82XX(ha) || IS_QLA8031(ha))
751 break;
752 if (!ha->flags.port0)
753 ha->flt_region_vpd = start;
754 break;
755 case FLT_REG_NVRAM_0:
756 if (IS_QLA8031(ha))
757 break;
758 if (ha->flags.port0)
759 ha->flt_region_nvram = start;
760 break;
761 case FLT_REG_NVRAM_1:
762 if (IS_QLA8031(ha))
763 break;
764 if (!ha->flags.port0)
765 ha->flt_region_nvram = start;
766 break;
767 case FLT_REG_FDT:
768 ha->flt_region_fdt = start;
769 break;
770 case FLT_REG_NPIV_CONF_0:
771 if (ha->flags.port0)
772 ha->flt_region_npiv_conf = start;
773 break;
774 case FLT_REG_NPIV_CONF_1:
775 if (!ha->flags.port0)
776 ha->flt_region_npiv_conf = start;
777 break;
778 case FLT_REG_GOLD_FW:
779 ha->flt_region_gold_fw = start;
780 break;
781 case FLT_REG_FCP_PRIO_0:
782 if (ha->flags.port0)
783 ha->flt_region_fcp_prio = start;
784 break;
785 case FLT_REG_FCP_PRIO_1:
786 if (!ha->flags.port0)
787 ha->flt_region_fcp_prio = start;
788 break;
789 case FLT_REG_BOOT_CODE_82XX:
790 ha->flt_region_boot = start;
791 break;
792 case FLT_REG_FW_82XX:
793 ha->flt_region_fw = start;
794 break;
795 case FLT_REG_GOLD_FW_82XX:
796 ha->flt_region_gold_fw = start;
797 break;
798 case FLT_REG_BOOTLOAD_82XX:
799 ha->flt_region_bootload = start;
800 break;
801 case FLT_REG_VPD_82XX:
802 ha->flt_region_vpd = start;
803 break;
804 case FLT_REG_FCOE_VPD_0:
805 if (!IS_QLA8031(ha))
806 break;
807 ha->flt_region_vpd_nvram = start;
808 if (ha->flags.port0)
809 ha->flt_region_vpd = start;
810 break;
811 case FLT_REG_FCOE_VPD_1:
812 if (!IS_QLA8031(ha))
813 break;
814 if (!ha->flags.port0)
815 ha->flt_region_vpd = start;
816 break;
817 case FLT_REG_FCOE_NVRAM_0:
818 if (!IS_QLA8031(ha))
819 break;
820 if (ha->flags.port0)
821 ha->flt_region_nvram = start;
822 break;
823 case FLT_REG_FCOE_NVRAM_1:
824 if (!IS_QLA8031(ha))
825 break;
826 if (!ha->flags.port0)
827 ha->flt_region_nvram = start;
828 break;
829 }
830 }
831 goto done;
832
833 no_flash_data:
834 /* Use hardcoded defaults. */
835 loc = locations[0];
836 ha->flt_region_fw = def_fw[def];
837 ha->flt_region_boot = def_boot[def];
838 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
839 ha->flt_region_vpd = ha->flags.port0 ?
840 def_vpd0[def] : def_vpd1[def];
841 ha->flt_region_nvram = ha->flags.port0 ?
842 def_nvram0[def] : def_nvram1[def];
843 ha->flt_region_fdt = def_fdt[def];
844 ha->flt_region_npiv_conf = ha->flags.port0 ?
845 def_npiv_conf0[def] : def_npiv_conf1[def];
846 done:
847 ql_dbg(ql_dbg_init, vha, 0x004a,
848 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
849 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
850 loc, ha->flt_region_boot, ha->flt_region_fw,
851 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
852 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
853 ha->flt_region_fcp_prio);
854 }
855
856 static void
857 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
858 {
859 #define FLASH_BLK_SIZE_4K 0x1000
860 #define FLASH_BLK_SIZE_32K 0x8000
861 #define FLASH_BLK_SIZE_64K 0x10000
862 const char *loc, *locations[] = { "MID", "FDT" };
863 uint16_t cnt, chksum;
864 uint16_t *wptr;
865 struct qla_fdt_layout *fdt;
866 uint8_t man_id, flash_id;
867 uint16_t mid = 0, fid = 0;
868 struct qla_hw_data *ha = vha->hw;
869 struct req_que *req = ha->req_q_map[0];
870
871 wptr = (uint16_t *)req->ring;
872 fdt = (struct qla_fdt_layout *)req->ring;
873 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
874 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
875 if (*wptr == __constant_cpu_to_le16(0xffff))
876 goto no_flash_data;
877 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
878 fdt->sig[3] != 'D')
879 goto no_flash_data;
880
881 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
882 cnt++)
883 chksum += le16_to_cpu(*wptr++);
884 if (chksum) {
885 ql_dbg(ql_dbg_init, vha, 0x004c,
886 "Inconsistent FDT detected:"
887 " checksum=0x%x id=%c version0x%x.\n", chksum,
888 fdt->sig[0], le16_to_cpu(fdt->version));
889 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
890 (uint8_t *)fdt, sizeof(*fdt));
891 goto no_flash_data;
892 }
893
894 loc = locations[1];
895 mid = le16_to_cpu(fdt->man_id);
896 fid = le16_to_cpu(fdt->id);
897 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
898 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
899 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
900 if (fdt->unprotect_sec_cmd) {
901 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
902 fdt->unprotect_sec_cmd);
903 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
904 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
905 flash_conf_addr(ha, 0x0336);
906 }
907 goto done;
908 no_flash_data:
909 loc = locations[0];
910 if (IS_QLA82XX(ha)) {
911 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
912 goto done;
913 }
914 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
915 mid = man_id;
916 fid = flash_id;
917 ha->fdt_wrt_disable = 0x9c;
918 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
919 switch (man_id) {
920 case 0xbf: /* STT flash. */
921 if (flash_id == 0x8e)
922 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
923 else
924 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
925
926 if (flash_id == 0x80)
927 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
928 break;
929 case 0x13: /* ST M25P80. */
930 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
931 break;
932 case 0x1f: /* Atmel 26DF081A. */
933 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
934 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
935 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
936 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
937 break;
938 default:
939 /* Default to 64 kb sector size. */
940 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
941 break;
942 }
943 done:
944 ql_dbg(ql_dbg_init, vha, 0x004d,
945 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
946 "pr=%x wrtd=0x%x blk=0x%x.\n",
947 loc, mid, fid,
948 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
949 ha->fdt_wrt_disable, ha->fdt_block_size);
950
951 }
952
953 static void
954 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
955 {
956 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
957 uint32_t *wptr;
958 struct qla_hw_data *ha = vha->hw;
959 struct req_que *req = ha->req_q_map[0];
960
961 if (!IS_QLA82XX(ha))
962 return;
963
964 wptr = (uint32_t *)req->ring;
965 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
966 QLA82XX_IDC_PARAM_ADDR , 8);
967
968 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
969 ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
970 ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
971 } else {
972 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
973 ha->nx_reset_timeout = le32_to_cpu(*wptr);
974 }
975 ql_dbg(ql_dbg_init, vha, 0x004e,
976 "nx_dev_init_timeout=%d "
977 "nx_reset_timeout=%d.\n", ha->nx_dev_init_timeout,
978 ha->nx_reset_timeout);
979 return;
980 }
981
982 int
983 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
984 {
985 int ret;
986 uint32_t flt_addr;
987 struct qla_hw_data *ha = vha->hw;
988
989 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
990 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
991 return QLA_SUCCESS;
992
993 ret = qla2xxx_find_flt_start(vha, &flt_addr);
994 if (ret != QLA_SUCCESS)
995 return ret;
996
997 qla2xxx_get_flt_info(vha, flt_addr);
998 qla2xxx_get_fdt_info(vha);
999 qla2xxx_get_idc_param(vha);
1000
1001 return QLA_SUCCESS;
1002 }
1003
1004 void
1005 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
1006 {
1007 #define NPIV_CONFIG_SIZE (16*1024)
1008 void *data;
1009 uint16_t *wptr;
1010 uint16_t cnt, chksum;
1011 int i;
1012 struct qla_npiv_header hdr;
1013 struct qla_npiv_entry *entry;
1014 struct qla_hw_data *ha = vha->hw;
1015
1016 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1017 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1018 return;
1019
1020 if (ha->flags.isp82xx_reset_hdlr_active)
1021 return;
1022
1023 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
1024 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1025 if (hdr.version == __constant_cpu_to_le16(0xffff))
1026 return;
1027 if (hdr.version != __constant_cpu_to_le16(1)) {
1028 ql_dbg(ql_dbg_user, vha, 0x7090,
1029 "Unsupported NPIV-Config "
1030 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1031 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1032 le16_to_cpu(hdr.checksum));
1033 return;
1034 }
1035
1036 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1037 if (!data) {
1038 ql_log(ql_log_warn, vha, 0x7091,
1039 "Unable to allocate memory for data.\n");
1040 return;
1041 }
1042
1043 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1044 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1045
1046 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1047 sizeof(struct qla_npiv_entry)) >> 1;
1048 for (wptr = data, chksum = 0; cnt; cnt--)
1049 chksum += le16_to_cpu(*wptr++);
1050 if (chksum) {
1051 ql_dbg(ql_dbg_user, vha, 0x7092,
1052 "Inconsistent NPIV-Config "
1053 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1054 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1055 le16_to_cpu(hdr.checksum));
1056 goto done;
1057 }
1058
1059 entry = data + sizeof(struct qla_npiv_header);
1060 cnt = le16_to_cpu(hdr.entries);
1061 for (i = 0; cnt; cnt--, entry++, i++) {
1062 uint16_t flags;
1063 struct fc_vport_identifiers vid;
1064 struct fc_vport *vport;
1065
1066 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1067
1068 flags = le16_to_cpu(entry->flags);
1069 if (flags == 0xffff)
1070 continue;
1071 if ((flags & BIT_0) == 0)
1072 continue;
1073
1074 memset(&vid, 0, sizeof(vid));
1075 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1076 vid.vport_type = FC_PORTTYPE_NPIV;
1077 vid.disable = false;
1078 vid.port_name = wwn_to_u64(entry->port_name);
1079 vid.node_name = wwn_to_u64(entry->node_name);
1080
1081 ql_dbg(ql_dbg_user, vha, 0x7093,
1082 "NPIV[%02x]: wwpn=%llx "
1083 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1084 (unsigned long long)vid.port_name,
1085 (unsigned long long)vid.node_name,
1086 le16_to_cpu(entry->vf_id),
1087 entry->q_qos, entry->f_qos);
1088
1089 if (i < QLA_PRECONFIG_VPORTS) {
1090 vport = fc_vport_create(vha->host, 0, &vid);
1091 if (!vport)
1092 ql_log(ql_log_warn, vha, 0x7094,
1093 "NPIV-Config Failed to create vport [%02x]: "
1094 "wwpn=%llx wwnn=%llx.\n", cnt,
1095 (unsigned long long)vid.port_name,
1096 (unsigned long long)vid.node_name);
1097 }
1098 }
1099 done:
1100 kfree(data);
1101 }
1102
1103 static int
1104 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1105 {
1106 struct qla_hw_data *ha = vha->hw;
1107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1108
1109 if (ha->flags.fac_supported)
1110 return qla81xx_fac_do_write_enable(vha, 1);
1111
1112 /* Enable flash write. */
1113 WRT_REG_DWORD(&reg->ctrl_status,
1114 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1115 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1116
1117 if (!ha->fdt_wrt_disable)
1118 goto done;
1119
1120 /* Disable flash write-protection, first clear SR protection bit */
1121 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1122 /* Then write zero again to clear remaining SR bits.*/
1123 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1124 done:
1125 return QLA_SUCCESS;
1126 }
1127
1128 static int
1129 qla24xx_protect_flash(scsi_qla_host_t *vha)
1130 {
1131 uint32_t cnt;
1132 struct qla_hw_data *ha = vha->hw;
1133 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1134
1135 if (ha->flags.fac_supported)
1136 return qla81xx_fac_do_write_enable(vha, 0);
1137
1138 if (!ha->fdt_wrt_disable)
1139 goto skip_wrt_protect;
1140
1141 /* Enable flash write-protection and wait for completion. */
1142 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1143 ha->fdt_wrt_disable);
1144 for (cnt = 300; cnt &&
1145 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1146 cnt--) {
1147 udelay(10);
1148 }
1149
1150 skip_wrt_protect:
1151 /* Disable flash write. */
1152 WRT_REG_DWORD(&reg->ctrl_status,
1153 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1154 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1155
1156 return QLA_SUCCESS;
1157 }
1158
1159 static int
1160 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1161 {
1162 struct qla_hw_data *ha = vha->hw;
1163 uint32_t start, finish;
1164
1165 if (ha->flags.fac_supported) {
1166 start = fdata >> 2;
1167 finish = start + (ha->fdt_block_size >> 2) - 1;
1168 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1169 start), flash_data_addr(ha, finish));
1170 }
1171
1172 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1173 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1174 ((fdata >> 16) & 0xff));
1175 }
1176
1177 static int
1178 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1179 uint32_t dwords)
1180 {
1181 int ret;
1182 uint32_t liter;
1183 uint32_t sec_mask, rest_addr;
1184 uint32_t fdata;
1185 dma_addr_t optrom_dma;
1186 void *optrom = NULL;
1187 struct qla_hw_data *ha = vha->hw;
1188
1189 /* Prepare burst-capable write on supported ISPs. */
1190 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha)) &&
1191 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1192 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1193 &optrom_dma, GFP_KERNEL);
1194 if (!optrom) {
1195 ql_log(ql_log_warn, vha, 0x7095,
1196 "Unable to allocate "
1197 "memory for optrom burst write (%x KB).\n",
1198 OPTROM_BURST_SIZE / 1024);
1199 }
1200 }
1201
1202 rest_addr = (ha->fdt_block_size >> 2) - 1;
1203 sec_mask = ~rest_addr;
1204
1205 ret = qla24xx_unprotect_flash(vha);
1206 if (ret != QLA_SUCCESS) {
1207 ql_log(ql_log_warn, vha, 0x7096,
1208 "Unable to unprotect flash for update.\n");
1209 goto done;
1210 }
1211
1212 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1213 fdata = (faddr & sec_mask) << 2;
1214
1215 /* Are we at the beginning of a sector? */
1216 if ((faddr & rest_addr) == 0) {
1217 /* Do sector unprotect. */
1218 if (ha->fdt_unprotect_sec_cmd)
1219 qla24xx_write_flash_dword(ha,
1220 ha->fdt_unprotect_sec_cmd,
1221 (fdata & 0xff00) | ((fdata << 16) &
1222 0xff0000) | ((fdata >> 16) & 0xff));
1223 ret = qla24xx_erase_sector(vha, fdata);
1224 if (ret != QLA_SUCCESS) {
1225 ql_dbg(ql_dbg_user, vha, 0x7007,
1226 "Unable to erase erase sector: address=%x.\n",
1227 faddr);
1228 break;
1229 }
1230 }
1231
1232 /* Go with burst-write. */
1233 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1234 /* Copy data to DMA'ble buffer. */
1235 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1236
1237 ret = qla2x00_load_ram(vha, optrom_dma,
1238 flash_data_addr(ha, faddr),
1239 OPTROM_BURST_DWORDS);
1240 if (ret != QLA_SUCCESS) {
1241 ql_log(ql_log_warn, vha, 0x7097,
1242 "Unable to burst-write optrom segment "
1243 "(%x/%x/%llx).\n", ret,
1244 flash_data_addr(ha, faddr),
1245 (unsigned long long)optrom_dma);
1246 ql_log(ql_log_warn, vha, 0x7098,
1247 "Reverting to slow-write.\n");
1248
1249 dma_free_coherent(&ha->pdev->dev,
1250 OPTROM_BURST_SIZE, optrom, optrom_dma);
1251 optrom = NULL;
1252 } else {
1253 liter += OPTROM_BURST_DWORDS - 1;
1254 faddr += OPTROM_BURST_DWORDS - 1;
1255 dwptr += OPTROM_BURST_DWORDS - 1;
1256 continue;
1257 }
1258 }
1259
1260 ret = qla24xx_write_flash_dword(ha,
1261 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1262 if (ret != QLA_SUCCESS) {
1263 ql_dbg(ql_dbg_user, vha, 0x7006,
1264 "Unable to program flash address=%x data=%x.\n",
1265 faddr, *dwptr);
1266 break;
1267 }
1268
1269 /* Do sector protect. */
1270 if (ha->fdt_unprotect_sec_cmd &&
1271 ((faddr & rest_addr) == rest_addr))
1272 qla24xx_write_flash_dword(ha,
1273 ha->fdt_protect_sec_cmd,
1274 (fdata & 0xff00) | ((fdata << 16) &
1275 0xff0000) | ((fdata >> 16) & 0xff));
1276 }
1277
1278 ret = qla24xx_protect_flash(vha);
1279 if (ret != QLA_SUCCESS)
1280 ql_log(ql_log_warn, vha, 0x7099,
1281 "Unable to protect flash after update.\n");
1282 done:
1283 if (optrom)
1284 dma_free_coherent(&ha->pdev->dev,
1285 OPTROM_BURST_SIZE, optrom, optrom_dma);
1286
1287 return ret;
1288 }
1289
1290 uint8_t *
1291 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1292 uint32_t bytes)
1293 {
1294 uint32_t i;
1295 uint16_t *wptr;
1296 struct qla_hw_data *ha = vha->hw;
1297
1298 /* Word reads to NVRAM via registers. */
1299 wptr = (uint16_t *)buf;
1300 qla2x00_lock_nvram_access(ha);
1301 for (i = 0; i < bytes >> 1; i++, naddr++)
1302 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1303 naddr));
1304 qla2x00_unlock_nvram_access(ha);
1305
1306 return buf;
1307 }
1308
1309 uint8_t *
1310 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1311 uint32_t bytes)
1312 {
1313 uint32_t i;
1314 uint32_t *dwptr;
1315 struct qla_hw_data *ha = vha->hw;
1316
1317 if (IS_QLA82XX(ha))
1318 return buf;
1319
1320 /* Dword reads to flash. */
1321 dwptr = (uint32_t *)buf;
1322 for (i = 0; i < bytes >> 2; i++, naddr++)
1323 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1324 nvram_data_addr(ha, naddr)));
1325
1326 return buf;
1327 }
1328
1329 int
1330 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1331 uint32_t bytes)
1332 {
1333 int ret, stat;
1334 uint32_t i;
1335 uint16_t *wptr;
1336 unsigned long flags;
1337 struct qla_hw_data *ha = vha->hw;
1338
1339 ret = QLA_SUCCESS;
1340
1341 spin_lock_irqsave(&ha->hardware_lock, flags);
1342 qla2x00_lock_nvram_access(ha);
1343
1344 /* Disable NVRAM write-protection. */
1345 stat = qla2x00_clear_nvram_protection(ha);
1346
1347 wptr = (uint16_t *)buf;
1348 for (i = 0; i < bytes >> 1; i++, naddr++) {
1349 qla2x00_write_nvram_word(ha, naddr,
1350 cpu_to_le16(*wptr));
1351 wptr++;
1352 }
1353
1354 /* Enable NVRAM write-protection. */
1355 qla2x00_set_nvram_protection(ha, stat);
1356
1357 qla2x00_unlock_nvram_access(ha);
1358 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1359
1360 return ret;
1361 }
1362
1363 int
1364 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1365 uint32_t bytes)
1366 {
1367 int ret;
1368 uint32_t i;
1369 uint32_t *dwptr;
1370 struct qla_hw_data *ha = vha->hw;
1371 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1372
1373 ret = QLA_SUCCESS;
1374
1375 if (IS_QLA82XX(ha))
1376 return ret;
1377
1378 /* Enable flash write. */
1379 WRT_REG_DWORD(&reg->ctrl_status,
1380 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1381 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1382
1383 /* Disable NVRAM write-protection. */
1384 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1385 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1386
1387 /* Dword writes to flash. */
1388 dwptr = (uint32_t *)buf;
1389 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1390 ret = qla24xx_write_flash_dword(ha,
1391 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1392 if (ret != QLA_SUCCESS) {
1393 ql_dbg(ql_dbg_user, vha, 0x709a,
1394 "Unable to program nvram address=%x data=%x.\n",
1395 naddr, *dwptr);
1396 break;
1397 }
1398 }
1399
1400 /* Enable NVRAM write-protection. */
1401 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1402
1403 /* Disable flash write. */
1404 WRT_REG_DWORD(&reg->ctrl_status,
1405 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1406 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1407
1408 return ret;
1409 }
1410
1411 uint8_t *
1412 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1413 uint32_t bytes)
1414 {
1415 uint32_t i;
1416 uint32_t *dwptr;
1417 struct qla_hw_data *ha = vha->hw;
1418
1419 /* Dword reads to flash. */
1420 dwptr = (uint32_t *)buf;
1421 for (i = 0; i < bytes >> 2; i++, naddr++)
1422 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1423 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1424
1425 return buf;
1426 }
1427
1428 int
1429 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1430 uint32_t bytes)
1431 {
1432 struct qla_hw_data *ha = vha->hw;
1433 #define RMW_BUFFER_SIZE (64 * 1024)
1434 uint8_t *dbuf;
1435
1436 dbuf = vmalloc(RMW_BUFFER_SIZE);
1437 if (!dbuf)
1438 return QLA_MEMORY_ALLOC_FAILED;
1439 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1440 RMW_BUFFER_SIZE);
1441 memcpy(dbuf + (naddr << 2), buf, bytes);
1442 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1443 RMW_BUFFER_SIZE);
1444 vfree(dbuf);
1445
1446 return QLA_SUCCESS;
1447 }
1448
1449 static inline void
1450 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1451 {
1452 if (IS_QLA2322(ha)) {
1453 /* Flip all colors. */
1454 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1455 /* Turn off. */
1456 ha->beacon_color_state = 0;
1457 *pflags = GPIO_LED_ALL_OFF;
1458 } else {
1459 /* Turn on. */
1460 ha->beacon_color_state = QLA_LED_ALL_ON;
1461 *pflags = GPIO_LED_RGA_ON;
1462 }
1463 } else {
1464 /* Flip green led only. */
1465 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1466 /* Turn off. */
1467 ha->beacon_color_state = 0;
1468 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1469 } else {
1470 /* Turn on. */
1471 ha->beacon_color_state = QLA_LED_GRN_ON;
1472 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1473 }
1474 }
1475 }
1476
1477 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1478
1479 void
1480 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1481 {
1482 uint16_t gpio_enable;
1483 uint16_t gpio_data;
1484 uint16_t led_color = 0;
1485 unsigned long flags;
1486 struct qla_hw_data *ha = vha->hw;
1487 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1488
1489 if (IS_QLA82XX(ha))
1490 return;
1491
1492 spin_lock_irqsave(&ha->hardware_lock, flags);
1493
1494 /* Save the Original GPIOE. */
1495 if (ha->pio_address) {
1496 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1497 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1498 } else {
1499 gpio_enable = RD_REG_WORD(&reg->gpioe);
1500 gpio_data = RD_REG_WORD(&reg->gpiod);
1501 }
1502
1503 /* Set the modified gpio_enable values */
1504 gpio_enable |= GPIO_LED_MASK;
1505
1506 if (ha->pio_address) {
1507 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1508 } else {
1509 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1510 RD_REG_WORD(&reg->gpioe);
1511 }
1512
1513 qla2x00_flip_colors(ha, &led_color);
1514
1515 /* Clear out any previously set LED color. */
1516 gpio_data &= ~GPIO_LED_MASK;
1517
1518 /* Set the new input LED color to GPIOD. */
1519 gpio_data |= led_color;
1520
1521 /* Set the modified gpio_data values */
1522 if (ha->pio_address) {
1523 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1524 } else {
1525 WRT_REG_WORD(&reg->gpiod, gpio_data);
1526 RD_REG_WORD(&reg->gpiod);
1527 }
1528
1529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1530 }
1531
1532 int
1533 qla2x00_beacon_on(struct scsi_qla_host *vha)
1534 {
1535 uint16_t gpio_enable;
1536 uint16_t gpio_data;
1537 unsigned long flags;
1538 struct qla_hw_data *ha = vha->hw;
1539 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1540
1541 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1542 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1543
1544 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1545 ql_log(ql_log_warn, vha, 0x709b,
1546 "Unable to update fw options (beacon on).\n");
1547 return QLA_FUNCTION_FAILED;
1548 }
1549
1550 /* Turn off LEDs. */
1551 spin_lock_irqsave(&ha->hardware_lock, flags);
1552 if (ha->pio_address) {
1553 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1554 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1555 } else {
1556 gpio_enable = RD_REG_WORD(&reg->gpioe);
1557 gpio_data = RD_REG_WORD(&reg->gpiod);
1558 }
1559 gpio_enable |= GPIO_LED_MASK;
1560
1561 /* Set the modified gpio_enable values. */
1562 if (ha->pio_address) {
1563 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1564 } else {
1565 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1566 RD_REG_WORD(&reg->gpioe);
1567 }
1568
1569 /* Clear out previously set LED colour. */
1570 gpio_data &= ~GPIO_LED_MASK;
1571 if (ha->pio_address) {
1572 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1573 } else {
1574 WRT_REG_WORD(&reg->gpiod, gpio_data);
1575 RD_REG_WORD(&reg->gpiod);
1576 }
1577 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1578
1579 /*
1580 * Let the per HBA timer kick off the blinking process based on
1581 * the following flags. No need to do anything else now.
1582 */
1583 ha->beacon_blink_led = 1;
1584 ha->beacon_color_state = 0;
1585
1586 return QLA_SUCCESS;
1587 }
1588
1589 int
1590 qla2x00_beacon_off(struct scsi_qla_host *vha)
1591 {
1592 int rval = QLA_SUCCESS;
1593 struct qla_hw_data *ha = vha->hw;
1594
1595 ha->beacon_blink_led = 0;
1596
1597 /* Set the on flag so when it gets flipped it will be off. */
1598 if (IS_QLA2322(ha))
1599 ha->beacon_color_state = QLA_LED_ALL_ON;
1600 else
1601 ha->beacon_color_state = QLA_LED_GRN_ON;
1602
1603 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1604
1605 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1606 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1607
1608 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1609 if (rval != QLA_SUCCESS)
1610 ql_log(ql_log_warn, vha, 0x709c,
1611 "Unable to update fw options (beacon off).\n");
1612 return rval;
1613 }
1614
1615
1616 static inline void
1617 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1618 {
1619 /* Flip all colors. */
1620 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1621 /* Turn off. */
1622 ha->beacon_color_state = 0;
1623 *pflags = 0;
1624 } else {
1625 /* Turn on. */
1626 ha->beacon_color_state = QLA_LED_ALL_ON;
1627 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1628 }
1629 }
1630
1631 void
1632 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1633 {
1634 uint16_t led_color = 0;
1635 uint32_t gpio_data;
1636 unsigned long flags;
1637 struct qla_hw_data *ha = vha->hw;
1638 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1639
1640 /* Save the Original GPIOD. */
1641 spin_lock_irqsave(&ha->hardware_lock, flags);
1642 gpio_data = RD_REG_DWORD(&reg->gpiod);
1643
1644 /* Enable the gpio_data reg for update. */
1645 gpio_data |= GPDX_LED_UPDATE_MASK;
1646
1647 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1648 gpio_data = RD_REG_DWORD(&reg->gpiod);
1649
1650 /* Set the color bits. */
1651 qla24xx_flip_colors(ha, &led_color);
1652
1653 /* Clear out any previously set LED color. */
1654 gpio_data &= ~GPDX_LED_COLOR_MASK;
1655
1656 /* Set the new input LED color to GPIOD. */
1657 gpio_data |= led_color;
1658
1659 /* Set the modified gpio_data values. */
1660 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1661 gpio_data = RD_REG_DWORD(&reg->gpiod);
1662 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1663 }
1664
1665 void
1666 qla83xx_beacon_blink(struct scsi_qla_host *vha)
1667 {
1668 uint32_t led_select_value;
1669 struct qla_hw_data *ha = vha->hw;
1670 uint16_t led_cfg[6];
1671 uint16_t orig_led_cfg[6];
1672
1673 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha))
1674 return;
1675
1676 if (IS_QLA2031(ha) && ha->beacon_blink_led) {
1677 if (ha->flags.port0)
1678 led_select_value = 0x00201320;
1679 else
1680 led_select_value = 0x00201328;
1681
1682 qla83xx_write_remote_reg(vha, led_select_value, 0x40002000);
1683 qla83xx_write_remote_reg(vha, led_select_value + 4, 0x40002000);
1684 msleep(1000);
1685 qla83xx_write_remote_reg(vha, led_select_value, 0x40004000);
1686 qla83xx_write_remote_reg(vha, led_select_value + 4, 0x40004000);
1687 } else if ((IS_QLA8031(ha) || IS_QLA81XX(ha)) && ha->beacon_blink_led) {
1688 int rval;
1689
1690 /* Save Current */
1691 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1692 /* Do the blink */
1693 if (rval == QLA_SUCCESS) {
1694 if (IS_QLA81XX(ha)) {
1695 led_cfg[0] = 0x4000;
1696 led_cfg[1] = 0x2000;
1697 led_cfg[2] = 0;
1698 led_cfg[3] = 0;
1699 led_cfg[4] = 0;
1700 led_cfg[5] = 0;
1701 } else {
1702 led_cfg[0] = 0x4000;
1703 led_cfg[1] = 0x4000;
1704 led_cfg[2] = 0x4000;
1705 led_cfg[3] = 0x2000;
1706 led_cfg[4] = 0;
1707 led_cfg[5] = 0x2000;
1708 }
1709 rval = qla81xx_set_led_config(vha, led_cfg);
1710 msleep(1000);
1711 if (IS_QLA81XX(ha)) {
1712 led_cfg[0] = 0x4000;
1713 led_cfg[1] = 0x2000;
1714 led_cfg[2] = 0;
1715 } else {
1716 led_cfg[0] = 0x4000;
1717 led_cfg[1] = 0x2000;
1718 led_cfg[2] = 0x4000;
1719 led_cfg[3] = 0x4000;
1720 led_cfg[4] = 0;
1721 led_cfg[5] = 0x2000;
1722 }
1723 rval = qla81xx_set_led_config(vha, led_cfg);
1724 }
1725 /* On exit, restore original (presumes no status change) */
1726 qla81xx_set_led_config(vha, orig_led_cfg);
1727 }
1728 }
1729
1730 int
1731 qla24xx_beacon_on(struct scsi_qla_host *vha)
1732 {
1733 uint32_t gpio_data;
1734 unsigned long flags;
1735 struct qla_hw_data *ha = vha->hw;
1736 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1737
1738 if (IS_QLA82XX(ha))
1739 return QLA_SUCCESS;
1740
1741 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1742 goto skip_gpio; /* let blink handle it */
1743
1744 if (ha->beacon_blink_led == 0) {
1745 /* Enable firmware for update */
1746 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1747
1748 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1749 return QLA_FUNCTION_FAILED;
1750
1751 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1752 QLA_SUCCESS) {
1753 ql_log(ql_log_warn, vha, 0x7009,
1754 "Unable to update fw options (beacon on).\n");
1755 return QLA_FUNCTION_FAILED;
1756 }
1757
1758 if (IS_QLA2031(ha))
1759 goto skip_gpio;
1760
1761 spin_lock_irqsave(&ha->hardware_lock, flags);
1762 gpio_data = RD_REG_DWORD(&reg->gpiod);
1763
1764 /* Enable the gpio_data reg for update. */
1765 gpio_data |= GPDX_LED_UPDATE_MASK;
1766 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1767 RD_REG_DWORD(&reg->gpiod);
1768
1769 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1770 }
1771
1772 /* So all colors blink together. */
1773 ha->beacon_color_state = 0;
1774
1775 skip_gpio:
1776 /* Let the per HBA timer kick off the blinking process. */
1777 ha->beacon_blink_led = 1;
1778
1779 return QLA_SUCCESS;
1780 }
1781
1782 int
1783 qla24xx_beacon_off(struct scsi_qla_host *vha)
1784 {
1785 uint32_t gpio_data;
1786 unsigned long flags;
1787 struct qla_hw_data *ha = vha->hw;
1788 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1789
1790 if (IS_QLA82XX(ha))
1791 return QLA_SUCCESS;
1792
1793 ha->beacon_blink_led = 0;
1794
1795 if (IS_QLA2031(ha))
1796 goto set_fw_options;
1797
1798 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1799 return QLA_SUCCESS;
1800
1801 ha->beacon_color_state = QLA_LED_ALL_ON;
1802
1803 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1804
1805 /* Give control back to firmware. */
1806 spin_lock_irqsave(&ha->hardware_lock, flags);
1807 gpio_data = RD_REG_DWORD(&reg->gpiod);
1808
1809 /* Disable the gpio_data reg for update. */
1810 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1811 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1812 RD_REG_DWORD(&reg->gpiod);
1813 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1814
1815 set_fw_options:
1816 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1817
1818 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1819 ql_log(ql_log_warn, vha, 0x704d,
1820 "Unable to update fw options (beacon on).\n");
1821 return QLA_FUNCTION_FAILED;
1822 }
1823
1824 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1825 ql_log(ql_log_warn, vha, 0x704e,
1826 "Unable to update fw options (beacon on).\n");
1827 return QLA_FUNCTION_FAILED;
1828 }
1829
1830 return QLA_SUCCESS;
1831 }
1832
1833
1834 /*
1835 * Flash support routines
1836 */
1837
1838 /**
1839 * qla2x00_flash_enable() - Setup flash for reading and writing.
1840 * @ha: HA context
1841 */
1842 static void
1843 qla2x00_flash_enable(struct qla_hw_data *ha)
1844 {
1845 uint16_t data;
1846 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1847
1848 data = RD_REG_WORD(&reg->ctrl_status);
1849 data |= CSR_FLASH_ENABLE;
1850 WRT_REG_WORD(&reg->ctrl_status, data);
1851 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1852 }
1853
1854 /**
1855 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1856 * @ha: HA context
1857 */
1858 static void
1859 qla2x00_flash_disable(struct qla_hw_data *ha)
1860 {
1861 uint16_t data;
1862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1863
1864 data = RD_REG_WORD(&reg->ctrl_status);
1865 data &= ~(CSR_FLASH_ENABLE);
1866 WRT_REG_WORD(&reg->ctrl_status, data);
1867 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1868 }
1869
1870 /**
1871 * qla2x00_read_flash_byte() - Reads a byte from flash
1872 * @ha: HA context
1873 * @addr: Address in flash to read
1874 *
1875 * A word is read from the chip, but, only the lower byte is valid.
1876 *
1877 * Returns the byte read from flash @addr.
1878 */
1879 static uint8_t
1880 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1881 {
1882 uint16_t data;
1883 uint16_t bank_select;
1884 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1885
1886 bank_select = RD_REG_WORD(&reg->ctrl_status);
1887
1888 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1889 /* Specify 64K address range: */
1890 /* clear out Module Select and Flash Address bits [19:16]. */
1891 bank_select &= ~0xf8;
1892 bank_select |= addr >> 12 & 0xf0;
1893 bank_select |= CSR_FLASH_64K_BANK;
1894 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1895 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1896
1897 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1898 data = RD_REG_WORD(&reg->flash_data);
1899
1900 return (uint8_t)data;
1901 }
1902
1903 /* Setup bit 16 of flash address. */
1904 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1905 bank_select |= CSR_FLASH_64K_BANK;
1906 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1907 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1908 } else if (((addr & BIT_16) == 0) &&
1909 (bank_select & CSR_FLASH_64K_BANK)) {
1910 bank_select &= ~(CSR_FLASH_64K_BANK);
1911 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1912 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1913 }
1914
1915 /* Always perform IO mapped accesses to the FLASH registers. */
1916 if (ha->pio_address) {
1917 uint16_t data2;
1918
1919 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1920 do {
1921 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1922 barrier();
1923 cpu_relax();
1924 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1925 } while (data != data2);
1926 } else {
1927 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1928 data = qla2x00_debounce_register(&reg->flash_data);
1929 }
1930
1931 return (uint8_t)data;
1932 }
1933
1934 /**
1935 * qla2x00_write_flash_byte() - Write a byte to flash
1936 * @ha: HA context
1937 * @addr: Address in flash to write
1938 * @data: Data to write
1939 */
1940 static void
1941 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1942 {
1943 uint16_t bank_select;
1944 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1945
1946 bank_select = RD_REG_WORD(&reg->ctrl_status);
1947 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1948 /* Specify 64K address range: */
1949 /* clear out Module Select and Flash Address bits [19:16]. */
1950 bank_select &= ~0xf8;
1951 bank_select |= addr >> 12 & 0xf0;
1952 bank_select |= CSR_FLASH_64K_BANK;
1953 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1954 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1955
1956 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1957 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1958 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1959 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1960
1961 return;
1962 }
1963
1964 /* Setup bit 16 of flash address. */
1965 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1966 bank_select |= CSR_FLASH_64K_BANK;
1967 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1968 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1969 } else if (((addr & BIT_16) == 0) &&
1970 (bank_select & CSR_FLASH_64K_BANK)) {
1971 bank_select &= ~(CSR_FLASH_64K_BANK);
1972 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1973 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1974 }
1975
1976 /* Always perform IO mapped accesses to the FLASH registers. */
1977 if (ha->pio_address) {
1978 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1979 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1980 } else {
1981 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1982 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1983 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1984 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1985 }
1986 }
1987
1988 /**
1989 * qla2x00_poll_flash() - Polls flash for completion.
1990 * @ha: HA context
1991 * @addr: Address in flash to poll
1992 * @poll_data: Data to be polled
1993 * @man_id: Flash manufacturer ID
1994 * @flash_id: Flash ID
1995 *
1996 * This function polls the device until bit 7 of what is read matches data
1997 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1998 * out (a fatal error). The flash book recommeds reading bit 7 again after
1999 * reading bit 5 as a 1.
2000 *
2001 * Returns 0 on success, else non-zero.
2002 */
2003 static int
2004 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2005 uint8_t man_id, uint8_t flash_id)
2006 {
2007 int status;
2008 uint8_t flash_data;
2009 uint32_t cnt;
2010
2011 status = 1;
2012
2013 /* Wait for 30 seconds for command to finish. */
2014 poll_data &= BIT_7;
2015 for (cnt = 3000000; cnt; cnt--) {
2016 flash_data = qla2x00_read_flash_byte(ha, addr);
2017 if ((flash_data & BIT_7) == poll_data) {
2018 status = 0;
2019 break;
2020 }
2021
2022 if (man_id != 0x40 && man_id != 0xda) {
2023 if ((flash_data & BIT_5) && cnt > 2)
2024 cnt = 2;
2025 }
2026 udelay(10);
2027 barrier();
2028 cond_resched();
2029 }
2030 return status;
2031 }
2032
2033 /**
2034 * qla2x00_program_flash_address() - Programs a flash address
2035 * @ha: HA context
2036 * @addr: Address in flash to program
2037 * @data: Data to be written in flash
2038 * @man_id: Flash manufacturer ID
2039 * @flash_id: Flash ID
2040 *
2041 * Returns 0 on success, else non-zero.
2042 */
2043 static int
2044 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2045 uint8_t data, uint8_t man_id, uint8_t flash_id)
2046 {
2047 /* Write Program Command Sequence. */
2048 if (IS_OEM_001(ha)) {
2049 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2050 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2051 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2052 qla2x00_write_flash_byte(ha, addr, data);
2053 } else {
2054 if (man_id == 0xda && flash_id == 0xc1) {
2055 qla2x00_write_flash_byte(ha, addr, data);
2056 if (addr & 0x7e)
2057 return 0;
2058 } else {
2059 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2060 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2061 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2062 qla2x00_write_flash_byte(ha, addr, data);
2063 }
2064 }
2065
2066 udelay(150);
2067
2068 /* Wait for write to complete. */
2069 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2070 }
2071
2072 /**
2073 * qla2x00_erase_flash() - Erase the flash.
2074 * @ha: HA context
2075 * @man_id: Flash manufacturer ID
2076 * @flash_id: Flash ID
2077 *
2078 * Returns 0 on success, else non-zero.
2079 */
2080 static int
2081 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2082 {
2083 /* Individual Sector Erase Command Sequence */
2084 if (IS_OEM_001(ha)) {
2085 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2086 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2087 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2088 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2089 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2090 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2091 } else {
2092 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2093 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2094 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2095 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2096 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2097 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2098 }
2099
2100 udelay(150);
2101
2102 /* Wait for erase to complete. */
2103 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2104 }
2105
2106 /**
2107 * qla2x00_erase_flash_sector() - Erase a flash sector.
2108 * @ha: HA context
2109 * @addr: Flash sector to erase
2110 * @sec_mask: Sector address mask
2111 * @man_id: Flash manufacturer ID
2112 * @flash_id: Flash ID
2113 *
2114 * Returns 0 on success, else non-zero.
2115 */
2116 static int
2117 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2118 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2119 {
2120 /* Individual Sector Erase Command Sequence */
2121 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2122 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2123 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2124 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2125 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2126 if (man_id == 0x1f && flash_id == 0x13)
2127 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2128 else
2129 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2130
2131 udelay(150);
2132
2133 /* Wait for erase to complete. */
2134 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2135 }
2136
2137 /**
2138 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2139 * @man_id: Flash manufacturer ID
2140 * @flash_id: Flash ID
2141 */
2142 static void
2143 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2144 uint8_t *flash_id)
2145 {
2146 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2147 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2148 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2149 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2150 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2151 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2152 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2153 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2154 }
2155
2156 static void
2157 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2158 uint32_t saddr, uint32_t length)
2159 {
2160 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2161 uint32_t midpoint, ilength;
2162 uint8_t data;
2163
2164 midpoint = length / 2;
2165
2166 WRT_REG_WORD(&reg->nvram, 0);
2167 RD_REG_WORD(&reg->nvram);
2168 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2169 if (ilength == midpoint) {
2170 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2171 RD_REG_WORD(&reg->nvram);
2172 }
2173 data = qla2x00_read_flash_byte(ha, saddr);
2174 if (saddr % 100)
2175 udelay(10);
2176 *tmp_buf = data;
2177 cond_resched();
2178 }
2179 }
2180
2181 static inline void
2182 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2183 {
2184 int cnt;
2185 unsigned long flags;
2186 struct qla_hw_data *ha = vha->hw;
2187 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2188
2189 /* Suspend HBA. */
2190 scsi_block_requests(vha->host);
2191 ha->isp_ops->disable_intrs(ha);
2192 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2193
2194 /* Pause RISC. */
2195 spin_lock_irqsave(&ha->hardware_lock, flags);
2196 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2197 RD_REG_WORD(&reg->hccr);
2198 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2199 for (cnt = 0; cnt < 30000; cnt++) {
2200 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2201 break;
2202 udelay(100);
2203 }
2204 } else {
2205 udelay(10);
2206 }
2207 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2208 }
2209
2210 static inline void
2211 qla2x00_resume_hba(struct scsi_qla_host *vha)
2212 {
2213 struct qla_hw_data *ha = vha->hw;
2214
2215 /* Resume HBA. */
2216 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2217 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2218 qla2xxx_wake_dpc(vha);
2219 qla2x00_wait_for_chip_reset(vha);
2220 scsi_unblock_requests(vha->host);
2221 }
2222
2223 uint8_t *
2224 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2225 uint32_t offset, uint32_t length)
2226 {
2227 uint32_t addr, midpoint;
2228 uint8_t *data;
2229 struct qla_hw_data *ha = vha->hw;
2230 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2231
2232 /* Suspend HBA. */
2233 qla2x00_suspend_hba(vha);
2234
2235 /* Go with read. */
2236 midpoint = ha->optrom_size / 2;
2237
2238 qla2x00_flash_enable(ha);
2239 WRT_REG_WORD(&reg->nvram, 0);
2240 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2241 for (addr = offset, data = buf; addr < length; addr++, data++) {
2242 if (addr == midpoint) {
2243 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2244 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2245 }
2246
2247 *data = qla2x00_read_flash_byte(ha, addr);
2248 }
2249 qla2x00_flash_disable(ha);
2250
2251 /* Resume HBA. */
2252 qla2x00_resume_hba(vha);
2253
2254 return buf;
2255 }
2256
2257 int
2258 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2259 uint32_t offset, uint32_t length)
2260 {
2261
2262 int rval;
2263 uint8_t man_id, flash_id, sec_number, data;
2264 uint16_t wd;
2265 uint32_t addr, liter, sec_mask, rest_addr;
2266 struct qla_hw_data *ha = vha->hw;
2267 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2268
2269 /* Suspend HBA. */
2270 qla2x00_suspend_hba(vha);
2271
2272 rval = QLA_SUCCESS;
2273 sec_number = 0;
2274
2275 /* Reset ISP chip. */
2276 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2277 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2278
2279 /* Go with write. */
2280 qla2x00_flash_enable(ha);
2281 do { /* Loop once to provide quick error exit */
2282 /* Structure of flash memory based on manufacturer */
2283 if (IS_OEM_001(ha)) {
2284 /* OEM variant with special flash part. */
2285 man_id = flash_id = 0;
2286 rest_addr = 0xffff;
2287 sec_mask = 0x10000;
2288 goto update_flash;
2289 }
2290 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2291 switch (man_id) {
2292 case 0x20: /* ST flash. */
2293 if (flash_id == 0xd2 || flash_id == 0xe3) {
2294 /*
2295 * ST m29w008at part - 64kb sector size with
2296 * 32kb,8kb,8kb,16kb sectors at memory address
2297 * 0xf0000.
2298 */
2299 rest_addr = 0xffff;
2300 sec_mask = 0x10000;
2301 break;
2302 }
2303 /*
2304 * ST m29w010b part - 16kb sector size
2305 * Default to 16kb sectors
2306 */
2307 rest_addr = 0x3fff;
2308 sec_mask = 0x1c000;
2309 break;
2310 case 0x40: /* Mostel flash. */
2311 /* Mostel v29c51001 part - 512 byte sector size. */
2312 rest_addr = 0x1ff;
2313 sec_mask = 0x1fe00;
2314 break;
2315 case 0xbf: /* SST flash. */
2316 /* SST39sf10 part - 4kb sector size. */
2317 rest_addr = 0xfff;
2318 sec_mask = 0x1f000;
2319 break;
2320 case 0xda: /* Winbond flash. */
2321 /* Winbond W29EE011 part - 256 byte sector size. */
2322 rest_addr = 0x7f;
2323 sec_mask = 0x1ff80;
2324 break;
2325 case 0xc2: /* Macronix flash. */
2326 /* 64k sector size. */
2327 if (flash_id == 0x38 || flash_id == 0x4f) {
2328 rest_addr = 0xffff;
2329 sec_mask = 0x10000;
2330 break;
2331 }
2332 /* Fall through... */
2333
2334 case 0x1f: /* Atmel flash. */
2335 /* 512k sector size. */
2336 if (flash_id == 0x13) {
2337 rest_addr = 0x7fffffff;
2338 sec_mask = 0x80000000;
2339 break;
2340 }
2341 /* Fall through... */
2342
2343 case 0x01: /* AMD flash. */
2344 if (flash_id == 0x38 || flash_id == 0x40 ||
2345 flash_id == 0x4f) {
2346 /* Am29LV081 part - 64kb sector size. */
2347 /* Am29LV002BT part - 64kb sector size. */
2348 rest_addr = 0xffff;
2349 sec_mask = 0x10000;
2350 break;
2351 } else if (flash_id == 0x3e) {
2352 /*
2353 * Am29LV008b part - 64kb sector size with
2354 * 32kb,8kb,8kb,16kb sector at memory address
2355 * h0xf0000.
2356 */
2357 rest_addr = 0xffff;
2358 sec_mask = 0x10000;
2359 break;
2360 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2361 /*
2362 * Am29LV010 part or AM29f010 - 16kb sector
2363 * size.
2364 */
2365 rest_addr = 0x3fff;
2366 sec_mask = 0x1c000;
2367 break;
2368 } else if (flash_id == 0x6d) {
2369 /* Am29LV001 part - 8kb sector size. */
2370 rest_addr = 0x1fff;
2371 sec_mask = 0x1e000;
2372 break;
2373 }
2374 default:
2375 /* Default to 16 kb sector size. */
2376 rest_addr = 0x3fff;
2377 sec_mask = 0x1c000;
2378 break;
2379 }
2380
2381 update_flash:
2382 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2383 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2384 rval = QLA_FUNCTION_FAILED;
2385 break;
2386 }
2387 }
2388
2389 for (addr = offset, liter = 0; liter < length; liter++,
2390 addr++) {
2391 data = buf[liter];
2392 /* Are we at the beginning of a sector? */
2393 if ((addr & rest_addr) == 0) {
2394 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2395 if (addr >= 0x10000UL) {
2396 if (((addr >> 12) & 0xf0) &&
2397 ((man_id == 0x01 &&
2398 flash_id == 0x3e) ||
2399 (man_id == 0x20 &&
2400 flash_id == 0xd2))) {
2401 sec_number++;
2402 if (sec_number == 1) {
2403 rest_addr =
2404 0x7fff;
2405 sec_mask =
2406 0x18000;
2407 } else if (
2408 sec_number == 2 ||
2409 sec_number == 3) {
2410 rest_addr =
2411 0x1fff;
2412 sec_mask =
2413 0x1e000;
2414 } else if (
2415 sec_number == 4) {
2416 rest_addr =
2417 0x3fff;
2418 sec_mask =
2419 0x1c000;
2420 }
2421 }
2422 }
2423 } else if (addr == ha->optrom_size / 2) {
2424 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2425 RD_REG_WORD(&reg->nvram);
2426 }
2427
2428 if (flash_id == 0xda && man_id == 0xc1) {
2429 qla2x00_write_flash_byte(ha, 0x5555,
2430 0xaa);
2431 qla2x00_write_flash_byte(ha, 0x2aaa,
2432 0x55);
2433 qla2x00_write_flash_byte(ha, 0x5555,
2434 0xa0);
2435 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2436 /* Then erase it */
2437 if (qla2x00_erase_flash_sector(ha,
2438 addr, sec_mask, man_id,
2439 flash_id)) {
2440 rval = QLA_FUNCTION_FAILED;
2441 break;
2442 }
2443 if (man_id == 0x01 && flash_id == 0x6d)
2444 sec_number++;
2445 }
2446 }
2447
2448 if (man_id == 0x01 && flash_id == 0x6d) {
2449 if (sec_number == 1 &&
2450 addr == (rest_addr - 1)) {
2451 rest_addr = 0x0fff;
2452 sec_mask = 0x1f000;
2453 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2454 rest_addr = 0x3fff;
2455 sec_mask = 0x1c000;
2456 }
2457 }
2458
2459 if (qla2x00_program_flash_address(ha, addr, data,
2460 man_id, flash_id)) {
2461 rval = QLA_FUNCTION_FAILED;
2462 break;
2463 }
2464 cond_resched();
2465 }
2466 } while (0);
2467 qla2x00_flash_disable(ha);
2468
2469 /* Resume HBA. */
2470 qla2x00_resume_hba(vha);
2471
2472 return rval;
2473 }
2474
2475 uint8_t *
2476 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2477 uint32_t offset, uint32_t length)
2478 {
2479 struct qla_hw_data *ha = vha->hw;
2480
2481 /* Suspend HBA. */
2482 scsi_block_requests(vha->host);
2483 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2484
2485 /* Go with read. */
2486 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2487
2488 /* Resume HBA. */
2489 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2490 scsi_unblock_requests(vha->host);
2491
2492 return buf;
2493 }
2494
2495 int
2496 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2497 uint32_t offset, uint32_t length)
2498 {
2499 int rval;
2500 struct qla_hw_data *ha = vha->hw;
2501
2502 /* Suspend HBA. */
2503 scsi_block_requests(vha->host);
2504 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2505
2506 /* Go with write. */
2507 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2508 length >> 2);
2509
2510 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2511 scsi_unblock_requests(vha->host);
2512
2513 return rval;
2514 }
2515
2516 uint8_t *
2517 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2518 uint32_t offset, uint32_t length)
2519 {
2520 int rval;
2521 dma_addr_t optrom_dma;
2522 void *optrom;
2523 uint8_t *pbuf;
2524 uint32_t faddr, left, burst;
2525 struct qla_hw_data *ha = vha->hw;
2526
2527 if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2528 goto try_fast;
2529 if (offset & 0xfff)
2530 goto slow_read;
2531 if (length < OPTROM_BURST_SIZE)
2532 goto slow_read;
2533
2534 try_fast:
2535 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2536 &optrom_dma, GFP_KERNEL);
2537 if (!optrom) {
2538 ql_log(ql_log_warn, vha, 0x00cc,
2539 "Unable to allocate memory for optrom burst read (%x KB).\n",
2540 OPTROM_BURST_SIZE / 1024);
2541 goto slow_read;
2542 }
2543
2544 pbuf = buf;
2545 faddr = offset >> 2;
2546 left = length >> 2;
2547 burst = OPTROM_BURST_DWORDS;
2548 while (left != 0) {
2549 if (burst > left)
2550 burst = left;
2551
2552 rval = qla2x00_dump_ram(vha, optrom_dma,
2553 flash_data_addr(ha, faddr), burst);
2554 if (rval) {
2555 ql_log(ql_log_warn, vha, 0x00f5,
2556 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2557 rval, flash_data_addr(ha, faddr),
2558 (unsigned long long)optrom_dma);
2559 ql_log(ql_log_warn, vha, 0x00f6,
2560 "Reverting to slow-read.\n");
2561
2562 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2563 optrom, optrom_dma);
2564 goto slow_read;
2565 }
2566
2567 memcpy(pbuf, optrom, burst * 4);
2568
2569 left -= burst;
2570 faddr += burst;
2571 pbuf += burst * 4;
2572 }
2573
2574 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2575 optrom_dma);
2576
2577 return buf;
2578
2579 slow_read:
2580 return qla24xx_read_optrom_data(vha, buf, offset, length);
2581 }
2582
2583 /**
2584 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2585 * @ha: HA context
2586 * @pcids: Pointer to the FCODE PCI data structure
2587 *
2588 * The process of retrieving the FCODE version information is at best
2589 * described as interesting.
2590 *
2591 * Within the first 100h bytes of the image an ASCII string is present
2592 * which contains several pieces of information including the FCODE
2593 * version. Unfortunately it seems the only reliable way to retrieve
2594 * the version is by scanning for another sentinel within the string,
2595 * the FCODE build date:
2596 *
2597 * ... 2.00.02 10/17/02 ...
2598 *
2599 * Returns QLA_SUCCESS on successful retrieval of version.
2600 */
2601 static void
2602 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2603 {
2604 int ret = QLA_FUNCTION_FAILED;
2605 uint32_t istart, iend, iter, vend;
2606 uint8_t do_next, rbyte, *vbyte;
2607
2608 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2609
2610 /* Skip the PCI data structure. */
2611 istart = pcids +
2612 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2613 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2614 iend = istart + 0x100;
2615 do {
2616 /* Scan for the sentinel date string...eeewww. */
2617 do_next = 0;
2618 iter = istart;
2619 while ((iter < iend) && !do_next) {
2620 iter++;
2621 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2622 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2623 '/')
2624 do_next++;
2625 else if (qla2x00_read_flash_byte(ha,
2626 iter + 3) == '/')
2627 do_next++;
2628 }
2629 }
2630 if (!do_next)
2631 break;
2632
2633 /* Backtrack to previous ' ' (space). */
2634 do_next = 0;
2635 while ((iter > istart) && !do_next) {
2636 iter--;
2637 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2638 do_next++;
2639 }
2640 if (!do_next)
2641 break;
2642
2643 /*
2644 * Mark end of version tag, and find previous ' ' (space) or
2645 * string length (recent FCODE images -- major hack ahead!!!).
2646 */
2647 vend = iter - 1;
2648 do_next = 0;
2649 while ((iter > istart) && !do_next) {
2650 iter--;
2651 rbyte = qla2x00_read_flash_byte(ha, iter);
2652 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2653 do_next++;
2654 }
2655 if (!do_next)
2656 break;
2657
2658 /* Mark beginning of version tag, and copy data. */
2659 iter++;
2660 if ((vend - iter) &&
2661 ((vend - iter) < sizeof(ha->fcode_revision))) {
2662 vbyte = ha->fcode_revision;
2663 while (iter <= vend) {
2664 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2665 iter++;
2666 }
2667 ret = QLA_SUCCESS;
2668 }
2669 } while (0);
2670
2671 if (ret != QLA_SUCCESS)
2672 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2673 }
2674
2675 int
2676 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2677 {
2678 int ret = QLA_SUCCESS;
2679 uint8_t code_type, last_image;
2680 uint32_t pcihdr, pcids;
2681 uint8_t *dbyte;
2682 uint16_t *dcode;
2683 struct qla_hw_data *ha = vha->hw;
2684
2685 if (!ha->pio_address || !mbuf)
2686 return QLA_FUNCTION_FAILED;
2687
2688 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2689 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2690 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2691 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2692
2693 qla2x00_flash_enable(ha);
2694
2695 /* Begin with first PCI expansion ROM header. */
2696 pcihdr = 0;
2697 last_image = 1;
2698 do {
2699 /* Verify PCI expansion ROM header. */
2700 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2701 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2702 /* No signature */
2703 ql_log(ql_log_fatal, vha, 0x0050,
2704 "No matching ROM signature.\n");
2705 ret = QLA_FUNCTION_FAILED;
2706 break;
2707 }
2708
2709 /* Locate PCI data structure. */
2710 pcids = pcihdr +
2711 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2712 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2713
2714 /* Validate signature of PCI data structure. */
2715 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2716 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2717 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2718 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2719 /* Incorrect header. */
2720 ql_log(ql_log_fatal, vha, 0x0051,
2721 "PCI data struct not found pcir_adr=%x.\n", pcids);
2722 ret = QLA_FUNCTION_FAILED;
2723 break;
2724 }
2725
2726 /* Read version */
2727 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2728 switch (code_type) {
2729 case ROM_CODE_TYPE_BIOS:
2730 /* Intel x86, PC-AT compatible. */
2731 ha->bios_revision[0] =
2732 qla2x00_read_flash_byte(ha, pcids + 0x12);
2733 ha->bios_revision[1] =
2734 qla2x00_read_flash_byte(ha, pcids + 0x13);
2735 ql_dbg(ql_dbg_init, vha, 0x0052,
2736 "Read BIOS %d.%d.\n",
2737 ha->bios_revision[1], ha->bios_revision[0]);
2738 break;
2739 case ROM_CODE_TYPE_FCODE:
2740 /* Open Firmware standard for PCI (FCode). */
2741 /* Eeeewww... */
2742 qla2x00_get_fcode_version(ha, pcids);
2743 break;
2744 case ROM_CODE_TYPE_EFI:
2745 /* Extensible Firmware Interface (EFI). */
2746 ha->efi_revision[0] =
2747 qla2x00_read_flash_byte(ha, pcids + 0x12);
2748 ha->efi_revision[1] =
2749 qla2x00_read_flash_byte(ha, pcids + 0x13);
2750 ql_dbg(ql_dbg_init, vha, 0x0053,
2751 "Read EFI %d.%d.\n",
2752 ha->efi_revision[1], ha->efi_revision[0]);
2753 break;
2754 default:
2755 ql_log(ql_log_warn, vha, 0x0054,
2756 "Unrecognized code type %x at pcids %x.\n",
2757 code_type, pcids);
2758 break;
2759 }
2760
2761 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2762
2763 /* Locate next PCI expansion ROM. */
2764 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2765 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2766 } while (!last_image);
2767
2768 if (IS_QLA2322(ha)) {
2769 /* Read firmware image information. */
2770 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2771 dbyte = mbuf;
2772 memset(dbyte, 0, 8);
2773 dcode = (uint16_t *)dbyte;
2774
2775 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2776 8);
2777 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2778 "Dumping fw "
2779 "ver from flash:.\n");
2780 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2781 (uint8_t *)dbyte, 8);
2782
2783 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2784 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2785 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2786 dcode[3] == 0)) {
2787 ql_log(ql_log_warn, vha, 0x0057,
2788 "Unrecognized fw revision at %x.\n",
2789 ha->flt_region_fw * 4);
2790 } else {
2791 /* values are in big endian */
2792 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2793 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2794 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2795 ql_dbg(ql_dbg_init, vha, 0x0058,
2796 "FW Version: "
2797 "%d.%d.%d.\n", ha->fw_revision[0],
2798 ha->fw_revision[1], ha->fw_revision[2]);
2799 }
2800 }
2801
2802 qla2x00_flash_disable(ha);
2803
2804 return ret;
2805 }
2806
2807 int
2808 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2809 {
2810 int ret = QLA_SUCCESS;
2811 uint32_t pcihdr, pcids;
2812 uint32_t *dcode;
2813 uint8_t *bcode;
2814 uint8_t code_type, last_image;
2815 int i;
2816 struct qla_hw_data *ha = vha->hw;
2817
2818 if (IS_QLA82XX(ha))
2819 return ret;
2820
2821 if (!mbuf)
2822 return QLA_FUNCTION_FAILED;
2823
2824 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2825 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2826 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2827 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2828
2829 dcode = mbuf;
2830
2831 /* Begin with first PCI expansion ROM header. */
2832 pcihdr = ha->flt_region_boot << 2;
2833 last_image = 1;
2834 do {
2835 /* Verify PCI expansion ROM header. */
2836 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2837 bcode = mbuf + (pcihdr % 4);
2838 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2839 /* No signature */
2840 ql_log(ql_log_fatal, vha, 0x0059,
2841 "No matching ROM signature.\n");
2842 ret = QLA_FUNCTION_FAILED;
2843 break;
2844 }
2845
2846 /* Locate PCI data structure. */
2847 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2848
2849 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2850 bcode = mbuf + (pcihdr % 4);
2851
2852 /* Validate signature of PCI data structure. */
2853 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2854 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2855 /* Incorrect header. */
2856 ql_log(ql_log_fatal, vha, 0x005a,
2857 "PCI data struct not found pcir_adr=%x.\n", pcids);
2858 ret = QLA_FUNCTION_FAILED;
2859 break;
2860 }
2861
2862 /* Read version */
2863 code_type = bcode[0x14];
2864 switch (code_type) {
2865 case ROM_CODE_TYPE_BIOS:
2866 /* Intel x86, PC-AT compatible. */
2867 ha->bios_revision[0] = bcode[0x12];
2868 ha->bios_revision[1] = bcode[0x13];
2869 ql_dbg(ql_dbg_init, vha, 0x005b,
2870 "Read BIOS %d.%d.\n",
2871 ha->bios_revision[1], ha->bios_revision[0]);
2872 break;
2873 case ROM_CODE_TYPE_FCODE:
2874 /* Open Firmware standard for PCI (FCode). */
2875 ha->fcode_revision[0] = bcode[0x12];
2876 ha->fcode_revision[1] = bcode[0x13];
2877 ql_dbg(ql_dbg_init, vha, 0x005c,
2878 "Read FCODE %d.%d.\n",
2879 ha->fcode_revision[1], ha->fcode_revision[0]);
2880 break;
2881 case ROM_CODE_TYPE_EFI:
2882 /* Extensible Firmware Interface (EFI). */
2883 ha->efi_revision[0] = bcode[0x12];
2884 ha->efi_revision[1] = bcode[0x13];
2885 ql_dbg(ql_dbg_init, vha, 0x005d,
2886 "Read EFI %d.%d.\n",
2887 ha->efi_revision[1], ha->efi_revision[0]);
2888 break;
2889 default:
2890 ql_log(ql_log_warn, vha, 0x005e,
2891 "Unrecognized code type %x at pcids %x.\n",
2892 code_type, pcids);
2893 break;
2894 }
2895
2896 last_image = bcode[0x15] & BIT_7;
2897
2898 /* Locate next PCI expansion ROM. */
2899 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2900 } while (!last_image);
2901
2902 /* Read firmware image information. */
2903 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2904 dcode = mbuf;
2905
2906 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2907 for (i = 0; i < 4; i++)
2908 dcode[i] = be32_to_cpu(dcode[i]);
2909
2910 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2911 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2912 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2913 dcode[3] == 0)) {
2914 ql_log(ql_log_warn, vha, 0x005f,
2915 "Unrecognized fw revision at %x.\n",
2916 ha->flt_region_fw * 4);
2917 } else {
2918 ha->fw_revision[0] = dcode[0];
2919 ha->fw_revision[1] = dcode[1];
2920 ha->fw_revision[2] = dcode[2];
2921 ha->fw_revision[3] = dcode[3];
2922 ql_dbg(ql_dbg_init, vha, 0x0060,
2923 "Firmware revision %d.%d.%d.%d.\n",
2924 ha->fw_revision[0], ha->fw_revision[1],
2925 ha->fw_revision[2], ha->fw_revision[3]);
2926 }
2927
2928 /* Check for golden firmware and get version if available */
2929 if (!IS_QLA81XX(ha)) {
2930 /* Golden firmware is not present in non 81XX adapters */
2931 return ret;
2932 }
2933
2934 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
2935 dcode = mbuf;
2936 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
2937 ha->flt_region_gold_fw << 2, 32);
2938
2939 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
2940 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
2941 ql_log(ql_log_warn, vha, 0x0056,
2942 "Unrecognized golden fw at 0x%x.\n",
2943 ha->flt_region_gold_fw * 4);
2944 return ret;
2945 }
2946
2947 for (i = 4; i < 8; i++)
2948 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
2949
2950 return ret;
2951 }
2952
2953 static int
2954 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2955 {
2956 if (pos >= end || *pos != 0x82)
2957 return 0;
2958
2959 pos += 3 + pos[1];
2960 if (pos >= end || *pos != 0x90)
2961 return 0;
2962
2963 pos += 3 + pos[1];
2964 if (pos >= end || *pos != 0x78)
2965 return 0;
2966
2967 return 1;
2968 }
2969
2970 int
2971 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2972 {
2973 struct qla_hw_data *ha = vha->hw;
2974 uint8_t *pos = ha->vpd;
2975 uint8_t *end = pos + ha->vpd_size;
2976 int len = 0;
2977
2978 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2979 return 0;
2980
2981 while (pos < end && *pos != 0x78) {
2982 len = (*pos == 0x82) ? pos[1] : pos[2];
2983
2984 if (!strncmp(pos, key, strlen(key)))
2985 break;
2986
2987 if (*pos != 0x90 && *pos != 0x91)
2988 pos += len;
2989
2990 pos += 3;
2991 }
2992
2993 if (pos < end - len && *pos != 0x78)
2994 return snprintf(str, size, "%.*s", len, pos + 3);
2995
2996 return 0;
2997 }
2998
2999 int
3000 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3001 {
3002 int len, max_len;
3003 uint32_t fcp_prio_addr;
3004 struct qla_hw_data *ha = vha->hw;
3005
3006 if (!ha->fcp_prio_cfg) {
3007 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3008 if (!ha->fcp_prio_cfg) {
3009 ql_log(ql_log_warn, vha, 0x00d5,
3010 "Unable to allocate memory for fcp priorty data (%x).\n",
3011 FCP_PRIO_CFG_SIZE);
3012 return QLA_FUNCTION_FAILED;
3013 }
3014 }
3015 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3016
3017 fcp_prio_addr = ha->flt_region_fcp_prio;
3018
3019 /* first read the fcp priority data header from flash */
3020 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3021 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3022
3023 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3024 goto fail;
3025
3026 /* read remaining FCP CMD config data from flash */
3027 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3028 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3029 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3030
3031 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3032 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3033
3034 /* revalidate the entire FCP priority config data, including entries */
3035 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3036 goto fail;
3037
3038 ha->flags.fcp_prio_enabled = 1;
3039 return QLA_SUCCESS;
3040 fail:
3041 vfree(ha->fcp_prio_cfg);
3042 ha->fcp_prio_cfg = NULL;
3043 return QLA_FUNCTION_FAILED;
3044 }
Linus' kernel tree