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rt2x00: Move firmware checksumming to driver
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt61pci.c
blob23b3e163b9ba8e605009a9dc95ce0bd0dac22efd
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt61pci.h"
39
40 /*
41 * Register access.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 */
51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
52 {
53 u32 reg;
54 unsigned int i;
55
56 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
57 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
58 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59 break;
60 udelay(REGISTER_BUSY_DELAY);
61 }
62
63 return reg;
64 }
65
66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
67 const unsigned int word, const u8 value)
68 {
69 u32 reg;
70
71 /*
72 * Wait until the BBP becomes ready.
73 */
74 reg = rt61pci_bbp_check(rt2x00dev);
75 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
76 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
77 return;
78 }
79
80 /*
81 * Write the data into the BBP.
82 */
83 reg = 0;
84 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
85 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
86 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
87 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
88
89 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
90 }
91
92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
93 const unsigned int word, u8 *value)
94 {
95 u32 reg;
96
97 /*
98 * Wait until the BBP becomes ready.
99 */
100 reg = rt61pci_bbp_check(rt2x00dev);
101 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
102 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
103 return;
104 }
105
106 /*
107 * Write the request into the BBP.
108 */
109 reg = 0;
110 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
111 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
112 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
113
114 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
115
116 /*
117 * Wait until the BBP becomes ready.
118 */
119 reg = rt61pci_bbp_check(rt2x00dev);
120 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
121 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
122 *value = 0xff;
123 return;
124 }
125
126 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
127 }
128
129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
130 const unsigned int word, const u32 value)
131 {
132 u32 reg;
133 unsigned int i;
134
135 if (!word)
136 return;
137
138 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
139 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
140 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141 goto rf_write;
142 udelay(REGISTER_BUSY_DELAY);
143 }
144
145 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
146 return;
147
148 rf_write:
149 reg = 0;
150 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
151 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
152 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
153 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
154
155 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
156 rt2x00_rf_write(rt2x00dev, word, value);
157 }
158
159 #ifdef CONFIG_RT61PCI_LEDS
160 /*
161 * This function is only called from rt61pci_led_brightness()
162 * make gcc happy by placing this function inside the
163 * same ifdef statement as the caller.
164 */
165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
166 const u8 command, const u8 token,
167 const u8 arg0, const u8 arg1)
168 {
169 u32 reg;
170
171 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
172
173 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
174 ERROR(rt2x00dev, "mcu request error. "
175 "Request 0x%02x failed for token 0x%02x.\n",
176 command, token);
177 return;
178 }
179
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
182 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
183 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
184 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
185
186 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
187 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
188 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
189 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190 }
191 #endif /* CONFIG_RT61PCI_LEDS */
192
193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
194 {
195 struct rt2x00_dev *rt2x00dev = eeprom->data;
196 u32 reg;
197
198 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
199
200 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
201 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
202 eeprom->reg_data_clock =
203 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
204 eeprom->reg_chip_select =
205 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
206 }
207
208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
209 {
210 struct rt2x00_dev *rt2x00dev = eeprom->data;
211 u32 reg = 0;
212
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
215 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
216 !!eeprom->reg_data_clock);
217 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
218 !!eeprom->reg_chip_select);
219
220 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
221 }
222
223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
224 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
225
226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
227 const unsigned int word, u32 *data)
228 {
229 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
230 }
231
232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
233 const unsigned int word, u32 data)
234 {
235 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
236 }
237
238 static const struct rt2x00debug rt61pci_rt2x00debug = {
239 .owner = THIS_MODULE,
240 .csr = {
241 .read = rt61pci_read_csr,
242 .write = rt61pci_write_csr,
243 .word_size = sizeof(u32),
244 .word_count = CSR_REG_SIZE / sizeof(u32),
245 },
246 .eeprom = {
247 .read = rt2x00_eeprom_read,
248 .write = rt2x00_eeprom_write,
249 .word_size = sizeof(u16),
250 .word_count = EEPROM_SIZE / sizeof(u16),
251 },
252 .bbp = {
253 .read = rt61pci_bbp_read,
254 .write = rt61pci_bbp_write,
255 .word_size = sizeof(u8),
256 .word_count = BBP_SIZE / sizeof(u8),
257 },
258 .rf = {
259 .read = rt2x00_rf_read,
260 .write = rt61pci_rf_write,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264 };
265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267 #ifdef CONFIG_RT61PCI_RFKILL
268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269 {
270 u32 reg;
271
272 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
273 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
274 }
275 #else
276 #define rt61pci_rfkill_poll NULL
277 #endif /* CONFIG_RT61PCI_RFKILL */
278
279 #ifdef CONFIG_RT61PCI_LEDS
280 static void rt61pci_led_brightness(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282 {
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int a_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288 unsigned int bg_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293 MCU_LEDCS_RADIO_STATUS, enabled);
294
295 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296 (led->rt2x00dev->led_mcu_reg & 0xff),
297 ((led->rt2x00dev->led_mcu_reg >> 8)));
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_LINK_A_STATUS, a_mode);
303
304 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305 (led->rt2x00dev->led_mcu_reg & 0xff),
306 ((led->rt2x00dev->led_mcu_reg >> 8)));
307 } else if (led->type == LED_TYPE_QUALITY) {
308 /*
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
312 */
313 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314 brightness / (LED_FULL / 6), 0);
315 }
316 }
317 #else
318 #define rt61pci_led_brightness NULL
319 #endif /* CONFIG_RT61PCI_LEDS */
320
321 /*
322 * Configuration handlers.
323 */
324 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_intf *intf,
326 struct rt2x00intf_conf *conf,
327 const unsigned int flags)
328 {
329 unsigned int beacon_base;
330 u32 reg;
331
332 if (flags & CONFIG_UPDATE_TYPE) {
333 /*
334 * Clear current synchronisation setup.
335 * For the Beacon base registers we only need to clear
336 * the first byte since that byte contains the VALID and OWNER
337 * bits which (when set to 0) will invalidate the entire beacon.
338 */
339 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
340 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
341
342 /*
343 * Enable synchronisation.
344 */
345 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
346 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
347 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
348 }
349
350 if (flags & CONFIG_UPDATE_MAC) {
351 reg = le32_to_cpu(conf->mac[1]);
352 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
353 conf->mac[1] = cpu_to_le32(reg);
354
355 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
356 conf->mac, sizeof(conf->mac));
357 }
358
359 if (flags & CONFIG_UPDATE_BSSID) {
360 reg = le32_to_cpu(conf->bssid[1]);
361 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
362 conf->bssid[1] = cpu_to_le32(reg);
363
364 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
365 conf->bssid, sizeof(conf->bssid));
366 }
367 }
368
369 static int rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
370 const int short_preamble,
371 const int ack_timeout,
372 const int ack_consume_time)
373 {
374 u32 reg;
375
376 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
377 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
378 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
379
380 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
381 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
382 !!short_preamble);
383 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
384
385 return 0;
386 }
387
388 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
389 const int basic_rate_mask)
390 {
391 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
392 }
393
394 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
395 struct rf_channel *rf, const int txpower)
396 {
397 u8 r3;
398 u8 r94;
399 u8 smart;
400
401 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
402 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
403
404 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
405 rt2x00_rf(&rt2x00dev->chip, RF2527));
406
407 rt61pci_bbp_read(rt2x00dev, 3, &r3);
408 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
409 rt61pci_bbp_write(rt2x00dev, 3, r3);
410
411 r94 = 6;
412 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
413 r94 += txpower - MAX_TXPOWER;
414 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
415 r94 += txpower;
416 rt61pci_bbp_write(rt2x00dev, 94, r94);
417
418 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
419 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
420 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
421 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
422
423 udelay(200);
424
425 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
426 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
427 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
428 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
429
430 udelay(200);
431
432 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
433 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
434 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
435 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
436
437 msleep(1);
438 }
439
440 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
441 const int txpower)
442 {
443 struct rf_channel rf;
444
445 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
446 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
447 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
448 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
449
450 rt61pci_config_channel(rt2x00dev, &rf, txpower);
451 }
452
453 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
454 struct antenna_setup *ant)
455 {
456 u8 r3;
457 u8 r4;
458 u8 r77;
459
460 rt61pci_bbp_read(rt2x00dev, 3, &r3);
461 rt61pci_bbp_read(rt2x00dev, 4, &r4);
462 rt61pci_bbp_read(rt2x00dev, 77, &r77);
463
464 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
465 rt2x00_rf(&rt2x00dev->chip, RF5325));
466
467 /*
468 * Configure the RX antenna.
469 */
470 switch (ant->rx) {
471 case ANTENNA_HW_DIVERSITY:
472 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
473 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
474 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
475 break;
476 case ANTENNA_A:
477 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
478 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
479 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
480 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
481 else
482 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
483 break;
484 case ANTENNA_SW_DIVERSITY:
485 /*
486 * NOTE: We should never come here because rt2x00lib is
487 * supposed to catch this and send us the correct antenna
488 * explicitely. However we are nog going to bug about this.
489 * Instead, just default to antenna B.
490 */
491 case ANTENNA_B:
492 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
493 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
494 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
495 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
496 else
497 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
498 break;
499 }
500
501 rt61pci_bbp_write(rt2x00dev, 77, r77);
502 rt61pci_bbp_write(rt2x00dev, 3, r3);
503 rt61pci_bbp_write(rt2x00dev, 4, r4);
504 }
505
506 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
507 struct antenna_setup *ant)
508 {
509 u8 r3;
510 u8 r4;
511 u8 r77;
512
513 rt61pci_bbp_read(rt2x00dev, 3, &r3);
514 rt61pci_bbp_read(rt2x00dev, 4, &r4);
515 rt61pci_bbp_read(rt2x00dev, 77, &r77);
516
517 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
518 rt2x00_rf(&rt2x00dev->chip, RF2529));
519 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
520 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
521
522 /*
523 * Configure the RX antenna.
524 */
525 switch (ant->rx) {
526 case ANTENNA_HW_DIVERSITY:
527 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
528 break;
529 case ANTENNA_A:
530 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
531 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
532 break;
533 case ANTENNA_SW_DIVERSITY:
534 /*
535 * NOTE: We should never come here because rt2x00lib is
536 * supposed to catch this and send us the correct antenna
537 * explicitely. However we are nog going to bug about this.
538 * Instead, just default to antenna B.
539 */
540 case ANTENNA_B:
541 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
542 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
543 break;
544 }
545
546 rt61pci_bbp_write(rt2x00dev, 77, r77);
547 rt61pci_bbp_write(rt2x00dev, 3, r3);
548 rt61pci_bbp_write(rt2x00dev, 4, r4);
549 }
550
551 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
552 const int p1, const int p2)
553 {
554 u32 reg;
555
556 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
557
558 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
559 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
560
561 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
562 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
563
564 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
565 }
566
567 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
568 struct antenna_setup *ant)
569 {
570 u8 r3;
571 u8 r4;
572 u8 r77;
573
574 rt61pci_bbp_read(rt2x00dev, 3, &r3);
575 rt61pci_bbp_read(rt2x00dev, 4, &r4);
576 rt61pci_bbp_read(rt2x00dev, 77, &r77);
577
578 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
579 * legacy driver. The code below should be ok for non-diversity setups.
580 */
581
582 /*
583 * Configure the RX antenna.
584 */
585 switch (ant->rx) {
586 case ANTENNA_A:
587 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
588 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
589 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
590 break;
591 case ANTENNA_SW_DIVERSITY:
592 case ANTENNA_HW_DIVERSITY:
593 /*
594 * NOTE: We should never come here because rt2x00lib is
595 * supposed to catch this and send us the correct antenna
596 * explicitely. However we are nog going to bug about this.
597 * Instead, just default to antenna B.
598 */
599 case ANTENNA_B:
600 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
601 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
602 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
603 break;
604 }
605
606 rt61pci_bbp_write(rt2x00dev, 77, r77);
607 rt61pci_bbp_write(rt2x00dev, 3, r3);
608 rt61pci_bbp_write(rt2x00dev, 4, r4);
609 }
610
611 struct antenna_sel {
612 u8 word;
613 /*
614 * value[0] -> non-LNA
615 * value[1] -> LNA
616 */
617 u8 value[2];
618 };
619
620 static const struct antenna_sel antenna_sel_a[] = {
621 { 96, { 0x58, 0x78 } },
622 { 104, { 0x38, 0x48 } },
623 { 75, { 0xfe, 0x80 } },
624 { 86, { 0xfe, 0x80 } },
625 { 88, { 0xfe, 0x80 } },
626 { 35, { 0x60, 0x60 } },
627 { 97, { 0x58, 0x58 } },
628 { 98, { 0x58, 0x58 } },
629 };
630
631 static const struct antenna_sel antenna_sel_bg[] = {
632 { 96, { 0x48, 0x68 } },
633 { 104, { 0x2c, 0x3c } },
634 { 75, { 0xfe, 0x80 } },
635 { 86, { 0xfe, 0x80 } },
636 { 88, { 0xfe, 0x80 } },
637 { 35, { 0x50, 0x50 } },
638 { 97, { 0x48, 0x48 } },
639 { 98, { 0x48, 0x48 } },
640 };
641
642 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
643 struct antenna_setup *ant)
644 {
645 const struct antenna_sel *sel;
646 unsigned int lna;
647 unsigned int i;
648 u32 reg;
649
650 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
651 sel = antenna_sel_a;
652 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
653 } else {
654 sel = antenna_sel_bg;
655 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
656 }
657
658 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
659 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
660
661 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
662
663 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
664 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
665 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
666 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
667
668 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
669
670 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
671 rt2x00_rf(&rt2x00dev->chip, RF5325))
672 rt61pci_config_antenna_5x(rt2x00dev, ant);
673 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
674 rt61pci_config_antenna_2x(rt2x00dev, ant);
675 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
676 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
677 rt61pci_config_antenna_2x(rt2x00dev, ant);
678 else
679 rt61pci_config_antenna_2529(rt2x00dev, ant);
680 }
681 }
682
683 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
684 struct rt2x00lib_conf *libconf)
685 {
686 u32 reg;
687
688 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
689 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
690 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
691
692 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
693 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
694 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
695 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
696 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
697
698 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
699 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
700 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
701
702 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
703 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
704 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
705
706 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
707 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
708 libconf->conf->beacon_int * 16);
709 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
710 }
711
712 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
713 struct rt2x00lib_conf *libconf,
714 const unsigned int flags)
715 {
716 if (flags & CONFIG_UPDATE_PHYMODE)
717 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
718 if (flags & CONFIG_UPDATE_CHANNEL)
719 rt61pci_config_channel(rt2x00dev, &libconf->rf,
720 libconf->conf->power_level);
721 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
722 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
723 if (flags & CONFIG_UPDATE_ANTENNA)
724 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
725 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
726 rt61pci_config_duration(rt2x00dev, libconf);
727 }
728
729 /*
730 * Link tuning
731 */
732 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
733 struct link_qual *qual)
734 {
735 u32 reg;
736
737 /*
738 * Update FCS error count from register.
739 */
740 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
741 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
742
743 /*
744 * Update False CCA count from register.
745 */
746 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
747 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
748 }
749
750 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
751 {
752 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
753 rt2x00dev->link.vgc_level = 0x20;
754 }
755
756 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
757 {
758 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
759 u8 r17;
760 u8 up_bound;
761 u8 low_bound;
762
763 rt61pci_bbp_read(rt2x00dev, 17, &r17);
764
765 /*
766 * Determine r17 bounds.
767 */
768 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
769 low_bound = 0x28;
770 up_bound = 0x48;
771 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
772 low_bound += 0x10;
773 up_bound += 0x10;
774 }
775 } else {
776 low_bound = 0x20;
777 up_bound = 0x40;
778 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
779 low_bound += 0x10;
780 up_bound += 0x10;
781 }
782 }
783
784 /*
785 * If we are not associated, we should go straight to the
786 * dynamic CCA tuning.
787 */
788 if (!rt2x00dev->intf_associated)
789 goto dynamic_cca_tune;
790
791 /*
792 * Special big-R17 for very short distance
793 */
794 if (rssi >= -35) {
795 if (r17 != 0x60)
796 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
797 return;
798 }
799
800 /*
801 * Special big-R17 for short distance
802 */
803 if (rssi >= -58) {
804 if (r17 != up_bound)
805 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
806 return;
807 }
808
809 /*
810 * Special big-R17 for middle-short distance
811 */
812 if (rssi >= -66) {
813 low_bound += 0x10;
814 if (r17 != low_bound)
815 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
816 return;
817 }
818
819 /*
820 * Special mid-R17 for middle distance
821 */
822 if (rssi >= -74) {
823 low_bound += 0x08;
824 if (r17 != low_bound)
825 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
826 return;
827 }
828
829 /*
830 * Special case: Change up_bound based on the rssi.
831 * Lower up_bound when rssi is weaker then -74 dBm.
832 */
833 up_bound -= 2 * (-74 - rssi);
834 if (low_bound > up_bound)
835 up_bound = low_bound;
836
837 if (r17 > up_bound) {
838 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
839 return;
840 }
841
842 dynamic_cca_tune:
843
844 /*
845 * r17 does not yet exceed upper limit, continue and base
846 * the r17 tuning on the false CCA count.
847 */
848 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
849 if (++r17 > up_bound)
850 r17 = up_bound;
851 rt61pci_bbp_write(rt2x00dev, 17, r17);
852 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
853 if (--r17 < low_bound)
854 r17 = low_bound;
855 rt61pci_bbp_write(rt2x00dev, 17, r17);
856 }
857 }
858
859 /*
860 * Firmware functions
861 */
862 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
863 {
864 char *fw_name;
865
866 switch (rt2x00dev->chip.rt) {
867 case RT2561:
868 fw_name = FIRMWARE_RT2561;
869 break;
870 case RT2561s:
871 fw_name = FIRMWARE_RT2561s;
872 break;
873 case RT2661:
874 fw_name = FIRMWARE_RT2661;
875 break;
876 default:
877 fw_name = NULL;
878 break;
879 }
880
881 return fw_name;
882 }
883
884 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
885 {
886 u16 crc;
887
888 /*
889 * Use the crc itu-t algorithm.
890 * The last 2 bytes in the firmware array are the crc checksum itself,
891 * this means that we should never pass those 2 bytes to the crc
892 * algorithm.
893 */
894 crc = crc_itu_t(0, data, len - 2);
895 crc = crc_itu_t_byte(crc, 0);
896 crc = crc_itu_t_byte(crc, 0);
897
898 return crc;
899 }
900
901 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
902 const size_t len)
903 {
904 int i;
905 u32 reg;
906
907 /*
908 * Wait for stable hardware.
909 */
910 for (i = 0; i < 100; i++) {
911 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
912 if (reg)
913 break;
914 msleep(1);
915 }
916
917 if (!reg) {
918 ERROR(rt2x00dev, "Unstable hardware.\n");
919 return -EBUSY;
920 }
921
922 /*
923 * Prepare MCU and mailbox for firmware loading.
924 */
925 reg = 0;
926 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
927 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
928 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
929 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
930 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
931
932 /*
933 * Write firmware to device.
934 */
935 reg = 0;
936 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
937 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
938 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
939
940 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
941 data, len);
942
943 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
944 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
945
946 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
947 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
948
949 for (i = 0; i < 100; i++) {
950 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
951 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
952 break;
953 msleep(1);
954 }
955
956 if (i == 100) {
957 ERROR(rt2x00dev, "MCU Control register not ready.\n");
958 return -EBUSY;
959 }
960
961 /*
962 * Reset MAC and BBP registers.
963 */
964 reg = 0;
965 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
966 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
967 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
968
969 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
970 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
971 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
972 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
973
974 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
975 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
976 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
977
978 return 0;
979 }
980
981 /*
982 * Initialization functions.
983 */
984 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
985 struct queue_entry *entry)
986 {
987 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
988 u32 word;
989
990 rt2x00_desc_read(priv_rx->desc, 5, &word);
991 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
992 priv_rx->data_dma);
993 rt2x00_desc_write(priv_rx->desc, 5, word);
994
995 rt2x00_desc_read(priv_rx->desc, 0, &word);
996 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
997 rt2x00_desc_write(priv_rx->desc, 0, word);
998 }
999
1000 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1001 struct queue_entry *entry)
1002 {
1003 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
1004 u32 word;
1005
1006 rt2x00_desc_read(priv_tx->desc, 1, &word);
1007 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1008 rt2x00_desc_write(priv_tx->desc, 1, word);
1009
1010 rt2x00_desc_read(priv_tx->desc, 5, &word);
1011 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1012 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1013 rt2x00_desc_write(priv_tx->desc, 5, word);
1014
1015 rt2x00_desc_read(priv_tx->desc, 6, &word);
1016 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1017 priv_tx->data_dma);
1018 rt2x00_desc_write(priv_tx->desc, 6, word);
1019
1020 rt2x00_desc_read(priv_tx->desc, 0, &word);
1021 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1022 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1023 rt2x00_desc_write(priv_tx->desc, 0, word);
1024 }
1025
1026 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1027 {
1028 struct queue_entry_priv_pci_rx *priv_rx;
1029 struct queue_entry_priv_pci_tx *priv_tx;
1030 u32 reg;
1031
1032 /*
1033 * Initialize registers.
1034 */
1035 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1036 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1037 rt2x00dev->tx[0].limit);
1038 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1039 rt2x00dev->tx[1].limit);
1040 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1041 rt2x00dev->tx[2].limit);
1042 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1043 rt2x00dev->tx[3].limit);
1044 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1045
1046 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1047 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1048 rt2x00dev->tx[0].desc_size / 4);
1049 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1050
1051 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1052 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1053 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1054 priv_tx->desc_dma);
1055 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1056
1057 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1058 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1059 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1060 priv_tx->desc_dma);
1061 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1062
1063 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1064 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1065 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1066 priv_tx->desc_dma);
1067 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1068
1069 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1070 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1071 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1072 priv_tx->desc_dma);
1073 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1074
1075 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1076 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1077 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1078 rt2x00dev->rx->desc_size / 4);
1079 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1080 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1081
1082 priv_rx = rt2x00dev->rx->entries[0].priv_data;
1083 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1084 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1085 priv_rx->desc_dma);
1086 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1087
1088 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1089 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1090 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1091 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1092 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1093 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1094
1095 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1096 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1097 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1098 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1099 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1100 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1101
1102 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1103 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1104 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1105
1106 return 0;
1107 }
1108
1109 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1110 {
1111 u32 reg;
1112
1113 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1114 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1115 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1116 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1117 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1118
1119 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1120 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1121 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1122 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1123 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1124 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1125 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1126 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1127 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1128 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1129
1130 /*
1131 * CCK TXD BBP registers
1132 */
1133 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1134 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1135 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1136 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1137 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1138 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1139 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1140 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1141 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1142 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1143
1144 /*
1145 * OFDM TXD BBP registers
1146 */
1147 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1148 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1149 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1150 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1151 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1153 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1154 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1155
1156 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1157 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1158 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1159 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1160 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1161 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1162
1163 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1164 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1165 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1166 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1167 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1168 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1169
1170 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1171
1172 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1173
1174 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1175 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1176 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1177
1178 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1179
1180 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1181 return -EBUSY;
1182
1183 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1184
1185 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1186 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1187 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1188 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1189
1190 /*
1191 * Invalidate all Shared Keys (SEC_CSR0),
1192 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1193 */
1194 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1195 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1196 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1197
1198 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1199 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1200 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1201 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1202
1203 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1204
1205 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1206
1207 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1208
1209 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1210 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1211 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1212 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1213
1214 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1215 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1216 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1217 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1218
1219 /*
1220 * Clear all beacons
1221 * For the Beacon base registers we only need to clear
1222 * the first byte since that byte contains the VALID and OWNER
1223 * bits which (when set to 0) will invalidate the entire beacon.
1224 */
1225 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1226 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1227 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1228 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1229
1230 /*
1231 * We must clear the error counters.
1232 * These registers are cleared on read,
1233 * so we may pass a useless variable to store the value.
1234 */
1235 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1236 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1237 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1238
1239 /*
1240 * Reset MAC and BBP registers.
1241 */
1242 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1243 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1244 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1245 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1246
1247 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1248 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1249 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1250 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1251
1252 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1253 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1254 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1255
1256 return 0;
1257 }
1258
1259 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1260 {
1261 unsigned int i;
1262 u16 eeprom;
1263 u8 reg_id;
1264 u8 value;
1265
1266 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1267 rt61pci_bbp_read(rt2x00dev, 0, &value);
1268 if ((value != 0xff) && (value != 0x00))
1269 goto continue_csr_init;
1270 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1271 udelay(REGISTER_BUSY_DELAY);
1272 }
1273
1274 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1275 return -EACCES;
1276
1277 continue_csr_init:
1278 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1279 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1280 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1281 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1282 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1283 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1284 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1285 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1286 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1287 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1288 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1289 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1290 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1291 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1292 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1293 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1294 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1295 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1296 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1297 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1298 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1299 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1300 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1301 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1302
1303 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1304 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1305
1306 if (eeprom != 0xffff && eeprom != 0x0000) {
1307 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1308 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1309 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1310 }
1311 }
1312
1313 return 0;
1314 }
1315
1316 /*
1317 * Device state switch handlers.
1318 */
1319 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1320 enum dev_state state)
1321 {
1322 u32 reg;
1323
1324 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1325 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1326 state == STATE_RADIO_RX_OFF);
1327 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1328 }
1329
1330 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1331 enum dev_state state)
1332 {
1333 int mask = (state == STATE_RADIO_IRQ_OFF);
1334 u32 reg;
1335
1336 /*
1337 * When interrupts are being enabled, the interrupt registers
1338 * should clear the register to assure a clean state.
1339 */
1340 if (state == STATE_RADIO_IRQ_ON) {
1341 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1342 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1343
1344 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1345 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1346 }
1347
1348 /*
1349 * Only toggle the interrupts bits we are going to use.
1350 * Non-checked interrupt bits are disabled by default.
1351 */
1352 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1353 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1354 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1355 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1356 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1357 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1358
1359 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1360 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1361 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1362 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1363 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1364 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1365 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1366 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1367 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1368 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1369 }
1370
1371 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1372 {
1373 u32 reg;
1374
1375 /*
1376 * Initialize all registers.
1377 */
1378 if (rt61pci_init_queues(rt2x00dev) ||
1379 rt61pci_init_registers(rt2x00dev) ||
1380 rt61pci_init_bbp(rt2x00dev)) {
1381 ERROR(rt2x00dev, "Register initialization failed.\n");
1382 return -EIO;
1383 }
1384
1385 /*
1386 * Enable interrupts.
1387 */
1388 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1389
1390 /*
1391 * Enable RX.
1392 */
1393 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1394 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1395 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1396
1397 return 0;
1398 }
1399
1400 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1401 {
1402 u32 reg;
1403
1404 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1405
1406 /*
1407 * Disable synchronisation.
1408 */
1409 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1410
1411 /*
1412 * Cancel RX and TX.
1413 */
1414 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1415 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1416 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1417 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1418 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1419 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1420
1421 /*
1422 * Disable interrupts.
1423 */
1424 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1425 }
1426
1427 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1428 {
1429 u32 reg;
1430 unsigned int i;
1431 char put_to_sleep;
1432 char current_state;
1433
1434 put_to_sleep = (state != STATE_AWAKE);
1435
1436 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1437 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1438 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1439 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1440
1441 /*
1442 * Device is not guaranteed to be in the requested state yet.
1443 * We must wait until the register indicates that the
1444 * device has entered the correct state.
1445 */
1446 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1447 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1448 current_state =
1449 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1450 if (current_state == !put_to_sleep)
1451 return 0;
1452 msleep(10);
1453 }
1454
1455 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1456 "current device state %d.\n", !put_to_sleep, current_state);
1457
1458 return -EBUSY;
1459 }
1460
1461 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1462 enum dev_state state)
1463 {
1464 int retval = 0;
1465
1466 switch (state) {
1467 case STATE_RADIO_ON:
1468 retval = rt61pci_enable_radio(rt2x00dev);
1469 break;
1470 case STATE_RADIO_OFF:
1471 rt61pci_disable_radio(rt2x00dev);
1472 break;
1473 case STATE_RADIO_RX_ON:
1474 case STATE_RADIO_RX_ON_LINK:
1475 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1476 break;
1477 case STATE_RADIO_RX_OFF:
1478 case STATE_RADIO_RX_OFF_LINK:
1479 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1480 break;
1481 case STATE_DEEP_SLEEP:
1482 case STATE_SLEEP:
1483 case STATE_STANDBY:
1484 case STATE_AWAKE:
1485 retval = rt61pci_set_state(rt2x00dev, state);
1486 break;
1487 default:
1488 retval = -ENOTSUPP;
1489 break;
1490 }
1491
1492 return retval;
1493 }
1494
1495 /*
1496 * TX descriptor initialization
1497 */
1498 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1499 struct sk_buff *skb,
1500 struct txentry_desc *txdesc,
1501 struct ieee80211_tx_control *control)
1502 {
1503 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1504 __le32 *txd = skbdesc->desc;
1505 u32 word;
1506
1507 /*
1508 * Start writing the descriptor words.
1509 */
1510 rt2x00_desc_read(txd, 1, &word);
1511 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1512 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1513 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1514 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1515 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1516 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1517 rt2x00_desc_write(txd, 1, word);
1518
1519 rt2x00_desc_read(txd, 2, &word);
1520 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1521 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1522 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1523 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1524 rt2x00_desc_write(txd, 2, word);
1525
1526 rt2x00_desc_read(txd, 5, &word);
1527 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1528 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1529 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1530 rt2x00_desc_write(txd, 5, word);
1531
1532 if (skbdesc->desc_len > TXINFO_SIZE) {
1533 rt2x00_desc_read(txd, 11, &word);
1534 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1535 rt2x00_desc_write(txd, 11, word);
1536 }
1537
1538 rt2x00_desc_read(txd, 0, &word);
1539 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1540 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1541 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1542 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1543 rt2x00_set_field32(&word, TXD_W0_ACK,
1544 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1545 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1546 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1547 rt2x00_set_field32(&word, TXD_W0_OFDM,
1548 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1549 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1550 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1551 !!(control->flags &
1552 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1553 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1554 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1555 rt2x00_set_field32(&word, TXD_W0_BURST,
1556 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1557 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1558 rt2x00_desc_write(txd, 0, word);
1559 }
1560
1561 /*
1562 * TX data initialization
1563 */
1564 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1565 const unsigned int queue)
1566 {
1567 u32 reg;
1568
1569 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1570 /*
1571 * For Wi-Fi faily generated beacons between participating
1572 * stations. Set TBTT phase adaptive adjustment step to 8us.
1573 */
1574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1575
1576 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1577 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1578 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1579 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1580 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1581 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1582 }
1583 return;
1584 }
1585
1586 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1587 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1588 (queue == IEEE80211_TX_QUEUE_DATA0));
1589 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1590 (queue == IEEE80211_TX_QUEUE_DATA1));
1591 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1592 (queue == IEEE80211_TX_QUEUE_DATA2));
1593 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1594 (queue == IEEE80211_TX_QUEUE_DATA3));
1595 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1596 }
1597
1598 /*
1599 * RX control handlers
1600 */
1601 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1602 {
1603 u16 eeprom;
1604 u8 offset;
1605 u8 lna;
1606
1607 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1608 switch (lna) {
1609 case 3:
1610 offset = 90;
1611 break;
1612 case 2:
1613 offset = 74;
1614 break;
1615 case 1:
1616 offset = 64;
1617 break;
1618 default:
1619 return 0;
1620 }
1621
1622 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1623 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1624 offset += 14;
1625
1626 if (lna == 3 || lna == 2)
1627 offset += 10;
1628
1629 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1630 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1631 } else {
1632 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1633 offset += 14;
1634
1635 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1636 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1637 }
1638
1639 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1640 }
1641
1642 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1643 struct rxdone_entry_desc *rxdesc)
1644 {
1645 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1646 u32 word0;
1647 u32 word1;
1648
1649 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1650 rt2x00_desc_read(priv_rx->desc, 1, &word1);
1651
1652 rxdesc->flags = 0;
1653 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1654 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1655
1656 /*
1657 * Obtain the status about this packet.
1658 */
1659 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1660 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1661 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1662 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1663 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1664 }
1665
1666 /*
1667 * Interrupt functions.
1668 */
1669 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1670 {
1671 struct data_queue *queue;
1672 struct queue_entry *entry;
1673 struct queue_entry *entry_done;
1674 struct queue_entry_priv_pci_tx *priv_tx;
1675 struct txdone_entry_desc txdesc;
1676 u32 word;
1677 u32 reg;
1678 u32 old_reg;
1679 int type;
1680 int index;
1681
1682 /*
1683 * During each loop we will compare the freshly read
1684 * STA_CSR4 register value with the value read from
1685 * the previous loop. If the 2 values are equal then
1686 * we should stop processing because the chance it
1687 * quite big that the device has been unplugged and
1688 * we risk going into an endless loop.
1689 */
1690 old_reg = 0;
1691
1692 while (1) {
1693 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1694 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1695 break;
1696
1697 if (old_reg == reg)
1698 break;
1699 old_reg = reg;
1700
1701 /*
1702 * Skip this entry when it contains an invalid
1703 * queue identication number.
1704 */
1705 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1706 queue = rt2x00queue_get_queue(rt2x00dev, type);
1707 if (unlikely(!queue))
1708 continue;
1709
1710 /*
1711 * Skip this entry when it contains an invalid
1712 * index number.
1713 */
1714 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1715 if (unlikely(index >= queue->limit))
1716 continue;
1717
1718 entry = &queue->entries[index];
1719 priv_tx = entry->priv_data;
1720 rt2x00_desc_read(priv_tx->desc, 0, &word);
1721
1722 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1723 !rt2x00_get_field32(word, TXD_W0_VALID))
1724 return;
1725
1726 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1727 while (entry != entry_done) {
1728 /* Catch up.
1729 * Just report any entries we missed as failed.
1730 */
1731 WARNING(rt2x00dev,
1732 "TX status report missed for entry %d\n",
1733 entry_done->entry_idx);
1734
1735 txdesc.status = TX_FAIL_OTHER;
1736 txdesc.retry = 0;
1737
1738 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1739 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1740 }
1741
1742 /*
1743 * Obtain the status about this packet.
1744 */
1745 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1746 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1747
1748 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1749 }
1750 }
1751
1752 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1753 {
1754 struct rt2x00_dev *rt2x00dev = dev_instance;
1755 u32 reg_mcu;
1756 u32 reg;
1757
1758 /*
1759 * Get the interrupt sources & saved to local variable.
1760 * Write register value back to clear pending interrupts.
1761 */
1762 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1763 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1764
1765 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1766 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1767
1768 if (!reg && !reg_mcu)
1769 return IRQ_NONE;
1770
1771 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1772 return IRQ_HANDLED;
1773
1774 /*
1775 * Handle interrupts, walk through all bits
1776 * and run the tasks, the bits are checked in order of
1777 * priority.
1778 */
1779
1780 /*
1781 * 1 - Rx ring done interrupt.
1782 */
1783 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1784 rt2x00pci_rxdone(rt2x00dev);
1785
1786 /*
1787 * 2 - Tx ring done interrupt.
1788 */
1789 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1790 rt61pci_txdone(rt2x00dev);
1791
1792 /*
1793 * 3 - Handle MCU command done.
1794 */
1795 if (reg_mcu)
1796 rt2x00pci_register_write(rt2x00dev,
1797 M2H_CMD_DONE_CSR, 0xffffffff);
1798
1799 return IRQ_HANDLED;
1800 }
1801
1802 /*
1803 * Device probe functions.
1804 */
1805 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1806 {
1807 struct eeprom_93cx6 eeprom;
1808 u32 reg;
1809 u16 word;
1810 u8 *mac;
1811 s8 value;
1812
1813 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1814
1815 eeprom.data = rt2x00dev;
1816 eeprom.register_read = rt61pci_eepromregister_read;
1817 eeprom.register_write = rt61pci_eepromregister_write;
1818 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1819 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1820 eeprom.reg_data_in = 0;
1821 eeprom.reg_data_out = 0;
1822 eeprom.reg_data_clock = 0;
1823 eeprom.reg_chip_select = 0;
1824
1825 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1826 EEPROM_SIZE / sizeof(u16));
1827
1828 /*
1829 * Start validation of the data that has been read.
1830 */
1831 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1832 if (!is_valid_ether_addr(mac)) {
1833 DECLARE_MAC_BUF(macbuf);
1834
1835 random_ether_addr(mac);
1836 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1837 }
1838
1839 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1840 if (word == 0xffff) {
1841 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1842 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1843 ANTENNA_B);
1844 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1845 ANTENNA_B);
1846 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1847 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1848 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1849 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1850 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1851 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1852 }
1853
1854 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1855 if (word == 0xffff) {
1856 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1857 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1858 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1859 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1860 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1861 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1862 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1863 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1864 }
1865
1866 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1867 if (word == 0xffff) {
1868 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1869 LED_MODE_DEFAULT);
1870 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1871 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1872 }
1873
1874 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1875 if (word == 0xffff) {
1876 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1877 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1878 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1879 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1880 }
1881
1882 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1883 if (word == 0xffff) {
1884 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1885 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1886 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1887 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1888 } else {
1889 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1890 if (value < -10 || value > 10)
1891 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1892 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1893 if (value < -10 || value > 10)
1894 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1895 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1896 }
1897
1898 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1899 if (word == 0xffff) {
1900 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1901 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1902 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1903 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1904 } else {
1905 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1906 if (value < -10 || value > 10)
1907 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1908 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1909 if (value < -10 || value > 10)
1910 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1911 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1912 }
1913
1914 return 0;
1915 }
1916
1917 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1918 {
1919 u32 reg;
1920 u16 value;
1921 u16 eeprom;
1922 u16 device;
1923
1924 /*
1925 * Read EEPROM word for configuration.
1926 */
1927 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1928
1929 /*
1930 * Identify RF chipset.
1931 * To determine the RT chip we have to read the
1932 * PCI header of the device.
1933 */
1934 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1935 PCI_CONFIG_HEADER_DEVICE, &device);
1936 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1937 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1938 rt2x00_set_chip(rt2x00dev, device, value, reg);
1939
1940 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1941 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1942 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1943 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1944 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1945 return -ENODEV;
1946 }
1947
1948 /*
1949 * Determine number of antenna's.
1950 */
1951 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1952 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1953
1954 /*
1955 * Identify default antenna configuration.
1956 */
1957 rt2x00dev->default_ant.tx =
1958 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1959 rt2x00dev->default_ant.rx =
1960 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1961
1962 /*
1963 * Read the Frame type.
1964 */
1965 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1966 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1967
1968 /*
1969 * Detect if this device has an hardware controlled radio.
1970 */
1971 #ifdef CONFIG_RT61PCI_RFKILL
1972 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1973 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1974 #endif /* CONFIG_RT61PCI_RFKILL */
1975
1976 /*
1977 * Read frequency offset and RF programming sequence.
1978 */
1979 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1980 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1981 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1982
1983 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1984
1985 /*
1986 * Read external LNA informations.
1987 */
1988 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1989
1990 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1991 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1992 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1993 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1994
1995 /*
1996 * When working with a RF2529 chip without double antenna
1997 * the antenna settings should be gathered from the NIC
1998 * eeprom word.
1999 */
2000 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2001 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2002 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2003 case 0:
2004 rt2x00dev->default_ant.tx = ANTENNA_B;
2005 rt2x00dev->default_ant.rx = ANTENNA_A;
2006 break;
2007 case 1:
2008 rt2x00dev->default_ant.tx = ANTENNA_B;
2009 rt2x00dev->default_ant.rx = ANTENNA_B;
2010 break;
2011 case 2:
2012 rt2x00dev->default_ant.tx = ANTENNA_A;
2013 rt2x00dev->default_ant.rx = ANTENNA_A;
2014 break;
2015 case 3:
2016 rt2x00dev->default_ant.tx = ANTENNA_A;
2017 rt2x00dev->default_ant.rx = ANTENNA_B;
2018 break;
2019 }
2020
2021 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2022 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2023 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2024 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2025 }
2026
2027 /*
2028 * Store led settings, for correct led behaviour.
2029 * If the eeprom value is invalid,
2030 * switch to default led mode.
2031 */
2032 #ifdef CONFIG_RT61PCI_LEDS
2033 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2034
2035 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2036
2037 switch (value) {
2038 case LED_MODE_TXRX_ACTIVITY:
2039 case LED_MODE_ASUS:
2040 case LED_MODE_ALPHA:
2041 case LED_MODE_DEFAULT:
2042 rt2x00dev->led_flags =
2043 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2044 break;
2045 case LED_MODE_SIGNAL_STRENGTH:
2046 rt2x00dev->led_flags =
2047 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2048 LED_SUPPORT_QUALITY;
2049 break;
2050 }
2051
2052 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2053 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2054 rt2x00_get_field16(eeprom,
2055 EEPROM_LED_POLARITY_GPIO_0));
2056 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2057 rt2x00_get_field16(eeprom,
2058 EEPROM_LED_POLARITY_GPIO_1));
2059 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2060 rt2x00_get_field16(eeprom,
2061 EEPROM_LED_POLARITY_GPIO_2));
2062 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2063 rt2x00_get_field16(eeprom,
2064 EEPROM_LED_POLARITY_GPIO_3));
2065 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2066 rt2x00_get_field16(eeprom,
2067 EEPROM_LED_POLARITY_GPIO_4));
2068 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2069 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2070 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2071 rt2x00_get_field16(eeprom,
2072 EEPROM_LED_POLARITY_RDY_G));
2073 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2074 rt2x00_get_field16(eeprom,
2075 EEPROM_LED_POLARITY_RDY_A));
2076 #endif /* CONFIG_RT61PCI_LEDS */
2077
2078 return 0;
2079 }
2080
2081 /*
2082 * RF value list for RF5225 & RF5325
2083 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2084 */
2085 static const struct rf_channel rf_vals_noseq[] = {
2086 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2087 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2088 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2089 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2090 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2091 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2092 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2093 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2094 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2095 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2096 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2097 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2098 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2099 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2100
2101 /* 802.11 UNI / HyperLan 2 */
2102 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2103 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2104 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2105 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2106 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2107 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2108 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2109 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2110
2111 /* 802.11 HyperLan 2 */
2112 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2113 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2114 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2115 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2116 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2117 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2118 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2119 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2120 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2121 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2122
2123 /* 802.11 UNII */
2124 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2125 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2126 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2127 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2128 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2129 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2130
2131 /* MMAC(Japan)J52 ch 34,38,42,46 */
2132 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2133 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2134 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2135 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2136 };
2137
2138 /*
2139 * RF value list for RF5225 & RF5325
2140 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2141 */
2142 static const struct rf_channel rf_vals_seq[] = {
2143 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2144 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2145 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2146 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2147 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2148 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2149 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2150 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2151 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2152 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2153 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2154 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2155 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2156 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2157
2158 /* 802.11 UNI / HyperLan 2 */
2159 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2160 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2161 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2162 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2163 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2164 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2165 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2166 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2167
2168 /* 802.11 HyperLan 2 */
2169 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2170 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2171 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2172 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2173 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2174 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2175 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2176 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2177 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2178 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2179
2180 /* 802.11 UNII */
2181 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2182 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2183 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2184 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2185 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2186 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2187
2188 /* MMAC(Japan)J52 ch 34,38,42,46 */
2189 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2190 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2191 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2192 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2193 };
2194
2195 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2196 {
2197 struct hw_mode_spec *spec = &rt2x00dev->spec;
2198 u8 *txpower;
2199 unsigned int i;
2200
2201 /*
2202 * Initialize all hw fields.
2203 */
2204 rt2x00dev->hw->flags =
2205 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2206 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2207 rt2x00dev->hw->extra_tx_headroom = 0;
2208 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2209 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2210 rt2x00dev->hw->queues = 4;
2211
2212 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2213 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2214 rt2x00_eeprom_addr(rt2x00dev,
2215 EEPROM_MAC_ADDR_0));
2216
2217 /*
2218 * Convert tx_power array in eeprom.
2219 */
2220 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2221 for (i = 0; i < 14; i++)
2222 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2223
2224 /*
2225 * Initialize hw_mode information.
2226 */
2227 spec->supported_bands = SUPPORT_BAND_2GHZ;
2228 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2229 spec->tx_power_a = NULL;
2230 spec->tx_power_bg = txpower;
2231 spec->tx_power_default = DEFAULT_TXPOWER;
2232
2233 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2234 spec->num_channels = 14;
2235 spec->channels = rf_vals_noseq;
2236 } else {
2237 spec->num_channels = 14;
2238 spec->channels = rf_vals_seq;
2239 }
2240
2241 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2242 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2243 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2244 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2245
2246 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2247 for (i = 0; i < 14; i++)
2248 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2249
2250 spec->tx_power_a = txpower;
2251 }
2252 }
2253
2254 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2255 {
2256 int retval;
2257
2258 /*
2259 * Allocate eeprom data.
2260 */
2261 retval = rt61pci_validate_eeprom(rt2x00dev);
2262 if (retval)
2263 return retval;
2264
2265 retval = rt61pci_init_eeprom(rt2x00dev);
2266 if (retval)
2267 return retval;
2268
2269 /*
2270 * Initialize hw specifications.
2271 */
2272 rt61pci_probe_hw_mode(rt2x00dev);
2273
2274 /*
2275 * This device requires firmware.
2276 */
2277 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2278
2279 /*
2280 * Set the rssi offset.
2281 */
2282 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2283
2284 return 0;
2285 }
2286
2287 /*
2288 * IEEE80211 stack callback functions.
2289 */
2290 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2291 unsigned int changed_flags,
2292 unsigned int *total_flags,
2293 int mc_count,
2294 struct dev_addr_list *mc_list)
2295 {
2296 struct rt2x00_dev *rt2x00dev = hw->priv;
2297 u32 reg;
2298
2299 /*
2300 * Mask off any flags we are going to ignore from
2301 * the total_flags field.
2302 */
2303 *total_flags &=
2304 FIF_ALLMULTI |
2305 FIF_FCSFAIL |
2306 FIF_PLCPFAIL |
2307 FIF_CONTROL |
2308 FIF_OTHER_BSS |
2309 FIF_PROMISC_IN_BSS;
2310
2311 /*
2312 * Apply some rules to the filters:
2313 * - Some filters imply different filters to be set.
2314 * - Some things we can't filter out at all.
2315 */
2316 if (mc_count)
2317 *total_flags |= FIF_ALLMULTI;
2318 if (*total_flags & FIF_OTHER_BSS ||
2319 *total_flags & FIF_PROMISC_IN_BSS)
2320 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2321
2322 /*
2323 * Check if there is any work left for us.
2324 */
2325 if (rt2x00dev->packet_filter == *total_flags)
2326 return;
2327 rt2x00dev->packet_filter = *total_flags;
2328
2329 /*
2330 * Start configuration steps.
2331 * Note that the version error will always be dropped
2332 * and broadcast frames will always be accepted since
2333 * there is no filter for it at this time.
2334 */
2335 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2336 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2337 !(*total_flags & FIF_FCSFAIL));
2338 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2339 !(*total_flags & FIF_PLCPFAIL));
2340 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2341 !(*total_flags & FIF_CONTROL));
2342 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2343 !(*total_flags & FIF_PROMISC_IN_BSS));
2344 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2345 !(*total_flags & FIF_PROMISC_IN_BSS));
2346 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2347 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2348 !(*total_flags & FIF_ALLMULTI));
2349 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
2350 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
2351 !(*total_flags & FIF_CONTROL));
2352 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2353 }
2354
2355 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2356 u32 short_retry, u32 long_retry)
2357 {
2358 struct rt2x00_dev *rt2x00dev = hw->priv;
2359 u32 reg;
2360
2361 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2362 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2363 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2364 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2365
2366 return 0;
2367 }
2368
2369 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2370 {
2371 struct rt2x00_dev *rt2x00dev = hw->priv;
2372 u64 tsf;
2373 u32 reg;
2374
2375 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2376 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2377 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2378 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2379
2380 return tsf;
2381 }
2382
2383 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2384 struct ieee80211_tx_control *control)
2385 {
2386 struct rt2x00_dev *rt2x00dev = hw->priv;
2387 struct rt2x00_intf *intf = vif_to_intf(control->vif);
2388 struct skb_frame_desc *skbdesc;
2389 unsigned int beacon_base;
2390 u32 reg;
2391
2392 if (unlikely(!intf->beacon))
2393 return -ENOBUFS;
2394
2395 /*
2396 * We need to append the descriptor in front of the
2397 * beacon frame.
2398 */
2399 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2400 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2401 0, GFP_ATOMIC)) {
2402 dev_kfree_skb(skb);
2403 return -ENOMEM;
2404 }
2405 }
2406
2407 /*
2408 * Add the descriptor in front of the skb.
2409 */
2410 skb_push(skb, intf->beacon->queue->desc_size);
2411 memset(skb->data, 0, intf->beacon->queue->desc_size);
2412
2413 /*
2414 * Fill in skb descriptor
2415 */
2416 skbdesc = get_skb_frame_desc(skb);
2417 memset(skbdesc, 0, sizeof(*skbdesc));
2418 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2419 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2420 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2421 skbdesc->desc = skb->data;
2422 skbdesc->desc_len = intf->beacon->queue->desc_size;
2423 skbdesc->entry = intf->beacon;
2424
2425 /*
2426 * Disable beaconing while we are reloading the beacon data,
2427 * otherwise we might be sending out invalid data.
2428 */
2429 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2430 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2431 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2432 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2433 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2434
2435 /*
2436 * mac80211 doesn't provide the control->queue variable
2437 * for beacons. Set our own queue identification so
2438 * it can be used during descriptor initialization.
2439 */
2440 control->queue = RT2X00_BCN_QUEUE_BEACON;
2441 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2442
2443 /*
2444 * Write entire beacon with descriptor to register,
2445 * and kick the beacon generator.
2446 */
2447 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2448 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2449 skb->data, skb->len);
2450 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2451
2452 return 0;
2453 }
2454
2455 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2456 .tx = rt2x00mac_tx,
2457 .start = rt2x00mac_start,
2458 .stop = rt2x00mac_stop,
2459 .add_interface = rt2x00mac_add_interface,
2460 .remove_interface = rt2x00mac_remove_interface,
2461 .config = rt2x00mac_config,
2462 .config_interface = rt2x00mac_config_interface,
2463 .configure_filter = rt61pci_configure_filter,
2464 .get_stats = rt2x00mac_get_stats,
2465 .set_retry_limit = rt61pci_set_retry_limit,
2466 .bss_info_changed = rt2x00mac_bss_info_changed,
2467 .conf_tx = rt2x00mac_conf_tx,
2468 .get_tx_stats = rt2x00mac_get_tx_stats,
2469 .get_tsf = rt61pci_get_tsf,
2470 .beacon_update = rt61pci_beacon_update,
2471 };
2472
2473 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2474 .irq_handler = rt61pci_interrupt,
2475 .probe_hw = rt61pci_probe_hw,
2476 .get_firmware_name = rt61pci_get_firmware_name,
2477 .get_firmware_crc = rt61pci_get_firmware_crc,
2478 .load_firmware = rt61pci_load_firmware,
2479 .initialize = rt2x00pci_initialize,
2480 .uninitialize = rt2x00pci_uninitialize,
2481 .init_rxentry = rt61pci_init_rxentry,
2482 .init_txentry = rt61pci_init_txentry,
2483 .set_device_state = rt61pci_set_device_state,
2484 .rfkill_poll = rt61pci_rfkill_poll,
2485 .link_stats = rt61pci_link_stats,
2486 .reset_tuner = rt61pci_reset_tuner,
2487 .link_tuner = rt61pci_link_tuner,
2488 .led_brightness = rt61pci_led_brightness,
2489 .write_tx_desc = rt61pci_write_tx_desc,
2490 .write_tx_data = rt2x00pci_write_tx_data,
2491 .kick_tx_queue = rt61pci_kick_tx_queue,
2492 .fill_rxdone = rt61pci_fill_rxdone,
2493 .config_intf = rt61pci_config_intf,
2494 .config_preamble = rt61pci_config_preamble,
2495 .config = rt61pci_config,
2496 };
2497
2498 static const struct data_queue_desc rt61pci_queue_rx = {
2499 .entry_num = RX_ENTRIES,
2500 .data_size = DATA_FRAME_SIZE,
2501 .desc_size = RXD_DESC_SIZE,
2502 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2503 };
2504
2505 static const struct data_queue_desc rt61pci_queue_tx = {
2506 .entry_num = TX_ENTRIES,
2507 .data_size = DATA_FRAME_SIZE,
2508 .desc_size = TXD_DESC_SIZE,
2509 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2510 };
2511
2512 static const struct data_queue_desc rt61pci_queue_bcn = {
2513 .entry_num = 4 * BEACON_ENTRIES,
2514 .data_size = MGMT_FRAME_SIZE,
2515 .desc_size = TXINFO_SIZE,
2516 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2517 };
2518
2519 static const struct rt2x00_ops rt61pci_ops = {
2520 .name = KBUILD_MODNAME,
2521 .max_sta_intf = 1,
2522 .max_ap_intf = 4,
2523 .eeprom_size = EEPROM_SIZE,
2524 .rf_size = RF_SIZE,
2525 .rx = &rt61pci_queue_rx,
2526 .tx = &rt61pci_queue_tx,
2527 .bcn = &rt61pci_queue_bcn,
2528 .lib = &rt61pci_rt2x00_ops,
2529 .hw = &rt61pci_mac80211_ops,
2530 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2531 .debugfs = &rt61pci_rt2x00debug,
2532 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2533 };
2534
2535 /*
2536 * RT61pci module information.
2537 */
2538 static struct pci_device_id rt61pci_device_table[] = {
2539 /* RT2561s */
2540 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2541 /* RT2561 v2 */
2542 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2543 /* RT2661 */
2544 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2545 { 0, }
2546 };
2547
2548 MODULE_AUTHOR(DRV_PROJECT);
2549 MODULE_VERSION(DRV_VERSION);
2550 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2551 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2552 "PCI & PCMCIA chipset based cards");
2553 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2554 MODULE_FIRMWARE(FIRMWARE_RT2561);
2555 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2556 MODULE_FIRMWARE(FIRMWARE_RT2661);
2557 MODULE_LICENSE("GPL");
2558
2559 static struct pci_driver rt61pci_driver = {
2560 .name = KBUILD_MODNAME,
2561 .id_table = rt61pci_device_table,
2562 .probe = rt2x00pci_probe,
2563 .remove = __devexit_p(rt2x00pci_remove),
2564 .suspend = rt2x00pci_suspend,
2565 .resume = rt2x00pci_resume,
2566 };
2567
2568 static int __init rt61pci_init(void)
2569 {
2570 return pci_register_driver(&rt61pci_driver);
2571 }
2572
2573 static void __exit rt61pci_exit(void)
2574 {
2575 pci_unregister_driver(&rt61pci_driver);
2576 }
2577
2578 module_init(rt61pci_init);
2579 module_exit(rt61pci_exit);
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