1 /******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
10 * vxge-config.h: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
11 * Virtualized Server Adapter.
12 * Copyright(c) 2002-2010 Exar Corp.
13 ******************************************************************************/
16 #include <linux/hardirq.h>
17 #include <linux/list.h>
18 #include <linux/slab.h>
20 #ifndef VXGE_CACHE_LINE_SIZE
21 #define VXGE_CACHE_LINE_SIZE 128
25 #define VXGE_ALIGN(adrs, size) \
26 (((size) - (((u64)adrs) & ((size)-1))) & ((size)-1))
29 #define VXGE_HW_MIN_MTU 68
30 #define VXGE_HW_MAX_MTU 9600
31 #define VXGE_HW_DEFAULT_MTU 1500
33 #define VXGE_HW_MAX_ROM_IMAGES 8
42 #ifdef VXGE_DEBUG_ASSERT
45 * @test: C-condition to check
46 * @fmt: printf like format string
48 * This function implements traditional assert. By default assertions
49 * are enabled. It can be disabled by undefining VXGE_DEBUG_ASSERT macro in
53 #define vxge_assert(test) BUG_ON(!(test))
55 #define vxge_assert(test)
56 #endif /* end of VXGE_DEBUG_ASSERT */
59 * enum vxge_debug_level
60 * @VXGE_NONE: debug disabled
61 * @VXGE_ERR: all errors going to be logged out
62 * @VXGE_TRACE: all errors plus all kind of verbose tracing print outs
63 * going to be logged out. Very noisy.
65 * This enumeration going to be used to switch between different
66 * debug levels during runtime if DEBUG macro defined during
67 * compilation. If DEBUG macro not defined than code will be
70 enum vxge_debug_level
{
76 #define NULL_VPID 0xFFFFFFFF
77 #ifdef CONFIG_VXGE_DEBUG_TRACE_ALL
78 #define VXGE_DEBUG_MODULE_MASK 0xffffffff
79 #define VXGE_DEBUG_TRACE_MASK 0xffffffff
80 #define VXGE_DEBUG_ERR_MASK 0xffffffff
81 #define VXGE_DEBUG_MASK 0x000001ff
83 #define VXGE_DEBUG_MODULE_MASK 0x20000000
84 #define VXGE_DEBUG_TRACE_MASK 0x20000000
85 #define VXGE_DEBUG_ERR_MASK 0x20000000
86 #define VXGE_DEBUG_MASK 0x00000001
90 * @VXGE_COMPONENT_LL: do debug for vxge link layer module
91 * @VXGE_COMPONENT_ALL: activate debug for all modules with no exceptions
93 * This enumeration going to be used to distinguish modules
94 * or libraries during compilation and runtime. Makefile must declare
95 * VXGE_DEBUG_MODULE_MASK macro and set it to proper value.
97 #define VXGE_COMPONENT_LL 0x20000000
98 #define VXGE_COMPONENT_ALL 0xffffffff
100 #define VXGE_HW_BASE_INF 100
101 #define VXGE_HW_BASE_ERR 200
102 #define VXGE_HW_BASE_BADCFG 300
104 enum vxge_hw_status
{
108 VXGE_HW_COMPLETIONS_REMAIN
= 3,
110 VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS
= VXGE_HW_BASE_INF
+ 1,
111 VXGE_HW_INF_OUT_OF_DESCRIPTORS
= VXGE_HW_BASE_INF
+ 2,
113 VXGE_HW_ERR_INVALID_HANDLE
= VXGE_HW_BASE_ERR
+ 1,
114 VXGE_HW_ERR_OUT_OF_MEMORY
= VXGE_HW_BASE_ERR
+ 2,
115 VXGE_HW_ERR_VPATH_NOT_AVAILABLE
= VXGE_HW_BASE_ERR
+ 3,
116 VXGE_HW_ERR_VPATH_NOT_OPEN
= VXGE_HW_BASE_ERR
+ 4,
117 VXGE_HW_ERR_WRONG_IRQ
= VXGE_HW_BASE_ERR
+ 5,
118 VXGE_HW_ERR_SWAPPER_CTRL
= VXGE_HW_BASE_ERR
+ 6,
119 VXGE_HW_ERR_INVALID_MTU_SIZE
= VXGE_HW_BASE_ERR
+ 7,
120 VXGE_HW_ERR_INVALID_INDEX
= VXGE_HW_BASE_ERR
+ 8,
121 VXGE_HW_ERR_INVALID_TYPE
= VXGE_HW_BASE_ERR
+ 9,
122 VXGE_HW_ERR_INVALID_OFFSET
= VXGE_HW_BASE_ERR
+ 10,
123 VXGE_HW_ERR_INVALID_DEVICE
= VXGE_HW_BASE_ERR
+ 11,
124 VXGE_HW_ERR_VERSION_CONFLICT
= VXGE_HW_BASE_ERR
+ 12,
125 VXGE_HW_ERR_INVALID_PCI_INFO
= VXGE_HW_BASE_ERR
+ 13,
126 VXGE_HW_ERR_INVALID_TCODE
= VXGE_HW_BASE_ERR
+ 14,
127 VXGE_HW_ERR_INVALID_BLOCK_SIZE
= VXGE_HW_BASE_ERR
+ 15,
128 VXGE_HW_ERR_INVALID_STATE
= VXGE_HW_BASE_ERR
+ 16,
129 VXGE_HW_ERR_PRIVILAGED_OPEARATION
= VXGE_HW_BASE_ERR
+ 17,
130 VXGE_HW_ERR_INVALID_PORT
= VXGE_HW_BASE_ERR
+ 18,
131 VXGE_HW_ERR_FIFO
= VXGE_HW_BASE_ERR
+ 19,
132 VXGE_HW_ERR_VPATH
= VXGE_HW_BASE_ERR
+ 20,
133 VXGE_HW_ERR_CRITICAL
= VXGE_HW_BASE_ERR
+ 21,
134 VXGE_HW_ERR_SLOT_FREEZE
= VXGE_HW_BASE_ERR
+ 22,
136 VXGE_HW_BADCFG_RING_INDICATE_MAX_PKTS
= VXGE_HW_BASE_BADCFG
+ 1,
137 VXGE_HW_BADCFG_FIFO_BLOCKS
= VXGE_HW_BASE_BADCFG
+ 2,
138 VXGE_HW_BADCFG_VPATH_MTU
= VXGE_HW_BASE_BADCFG
+ 3,
139 VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG
= VXGE_HW_BASE_BADCFG
+ 4,
140 VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH
= VXGE_HW_BASE_BADCFG
+ 5,
141 VXGE_HW_BADCFG_INTR_MODE
= VXGE_HW_BASE_BADCFG
+ 6,
142 VXGE_HW_BADCFG_RTS_MAC_EN
= VXGE_HW_BASE_BADCFG
+ 7,
144 VXGE_HW_EOF_TRACE_BUF
= -1
148 * enum enum vxge_hw_device_link_state - Link state enumeration.
149 * @VXGE_HW_LINK_NONE: Invalid link state.
150 * @VXGE_HW_LINK_DOWN: Link is down.
151 * @VXGE_HW_LINK_UP: Link is up.
154 enum vxge_hw_device_link_state
{
161 * enum enum vxge_hw_fw_upgrade_code - FW upgrade return codes.
162 * @VXGE_HW_FW_UPGRADE_OK: All OK send next 16 bytes
163 * @VXGE_HW_FW_UPGRADE_DONE: upload completed
164 * @VXGE_HW_FW_UPGRADE_ERR: upload error
165 * @VXGE_FW_UPGRADE_BYTES2SKIP: skip bytes in the stream
168 enum vxge_hw_fw_upgrade_code
{
169 VXGE_HW_FW_UPGRADE_OK
= 0,
170 VXGE_HW_FW_UPGRADE_DONE
= 1,
171 VXGE_HW_FW_UPGRADE_ERR
= 2,
172 VXGE_FW_UPGRADE_BYTES2SKIP
= 3
176 * enum enum vxge_hw_fw_upgrade_err_code - FW upgrade error codes.
177 * @VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1: corrupt data
178 * @VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW: buffer overflow
179 * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3: invalid .ncf file
180 * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4: invalid .ncf file
181 * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5: invalid .ncf file
182 * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6: invalid .ncf file
183 * @VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7: corrupt data
184 * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8: invalid .ncf file
185 * @VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN: generic error unknown type
186 * @VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH: failed to flash image check failed
188 enum vxge_hw_fw_upgrade_err_code
{
189 VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1
= 1,
190 VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW
= 2,
191 VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3
= 3,
192 VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4
= 4,
193 VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5
= 5,
194 VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6
= 6,
195 VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7
= 7,
196 VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8
= 8,
197 VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN
= 9,
198 VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH
= 10
202 * struct vxge_hw_device_date - Date Format
206 * @date: Date in string format
208 * Structure for returning date
211 #define VXGE_HW_FW_STRLEN 32
212 struct vxge_hw_device_date
{
216 char date
[VXGE_HW_FW_STRLEN
];
219 struct vxge_hw_device_version
{
223 char version
[VXGE_HW_FW_STRLEN
];
227 * struct vxge_hw_fifo_config - Configuration of fifo.
228 * @enable: Is this fifo to be commissioned
229 * @fifo_blocks: Numbers of TxDL (that is, lists of Tx descriptors)
231 * @max_frags: Max number of Tx buffers per TxDL (that is, per single
232 * transmit operation).
233 * No more than 256 transmit buffers can be specified.
234 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
235 * bytes. Setting @memblock_size to page size ensures
236 * by-page allocation of descriptors. 128K bytes is the
237 * maximum supported block size.
238 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
239 * (e.g., to align on a cache line).
240 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL.
242 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
243 * which generally improves latency of the host bridge operation
244 * (see PCI specification). For valid values please refer
245 * to struct vxge_hw_fifo_config{} in the driver sources.
246 * Configuration of all Titan fifos.
247 * Note: Valid (min, max) range for each attribute is specified in the body of
248 * the struct vxge_hw_fifo_config{} structure.
250 struct vxge_hw_fifo_config
{
252 #define VXGE_HW_FIFO_ENABLE 1
253 #define VXGE_HW_FIFO_DISABLE 0
256 #define VXGE_HW_MIN_FIFO_BLOCKS 2
257 #define VXGE_HW_MAX_FIFO_BLOCKS 128
260 #define VXGE_HW_MIN_FIFO_FRAGS 1
261 #define VXGE_HW_MAX_FIFO_FRAGS 256
264 #define VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE VXGE_HW_BLOCK_SIZE
265 #define VXGE_HW_MAX_FIFO_MEMBLOCK_SIZE 131072
266 #define VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE 8096
269 #define VXGE_HW_MIN_FIFO_ALIGNMENT_SIZE 0
270 #define VXGE_HW_MAX_FIFO_ALIGNMENT_SIZE 65536
271 #define VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE VXGE_CACHE_LINE_SIZE
274 #define VXGE_HW_FIFO_QUEUE_INTR_ENABLE 1
275 #define VXGE_HW_FIFO_QUEUE_INTR_DISABLE 0
276 #define VXGE_HW_FIFO_QUEUE_INTR_DEFAULT 0
279 #define VXGE_HW_FIFO_NO_SNOOP_DISABLED 0
280 #define VXGE_HW_FIFO_NO_SNOOP_TXD 1
281 #define VXGE_HW_FIFO_NO_SNOOP_FRM 2
282 #define VXGE_HW_FIFO_NO_SNOOP_ALL 3
283 #define VXGE_HW_FIFO_NO_SNOOP_DEFAULT 0
287 * struct vxge_hw_ring_config - Ring configurations.
288 * @enable: Is this ring to be commissioned
289 * @ring_blocks: Numbers of RxD blocks in the ring
290 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer
291 * to Titan User Guide.
292 * @scatter_mode: Titan supports two receive scatter modes: A and B.
293 * For details please refer to Titan User Guide.
294 * @rx_timer_val: The number of 32ns periods that would be counted between two
296 * @greedy_return: If Set it forces the device to return absolutely all RxD
297 * that are consumed and still on board when a timer interrupt
298 * triggers. If Clear, then if the device has already returned
299 * RxD before current timer interrupt trigerred and after the
300 * previous timer interrupt triggered, then the device is not
301 * forced to returned the rest of the consumed RxD that it has
302 * on board which account for a byte count less than the one
303 * programmed into PRC_CFG6.RXD_CRXDT field
305 * @backoff_interval_us: Time (in microseconds), after which Titan
306 * tries to download RxDs posted by the host.
307 * Note that the "backoff" does not happen if host posts receive
308 * descriptors in the timely fashion.
309 * Ring configuration.
311 struct vxge_hw_ring_config
{
313 #define VXGE_HW_RING_ENABLE 1
314 #define VXGE_HW_RING_DISABLE 0
315 #define VXGE_HW_RING_DEFAULT 1
318 #define VXGE_HW_MIN_RING_BLOCKS 1
319 #define VXGE_HW_MAX_RING_BLOCKS 128
320 #define VXGE_HW_DEF_RING_BLOCKS 2
323 #define VXGE_HW_RING_RXD_BUFFER_MODE_1 1
324 #define VXGE_HW_RING_RXD_BUFFER_MODE_3 3
325 #define VXGE_HW_RING_RXD_BUFFER_MODE_5 5
326 #define VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT 1
329 #define VXGE_HW_RING_SCATTER_MODE_A 0
330 #define VXGE_HW_RING_SCATTER_MODE_B 1
331 #define VXGE_HW_RING_SCATTER_MODE_C 2
332 #define VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT 0xffffffff
335 #define VXGE_HW_DEF_RING_RXDS_LIMIT 44
339 * struct vxge_hw_vp_config - Configuration of virtual path
340 * @vp_id: Virtual Path Id
341 * @min_bandwidth: Minimum Guaranteed bandwidth
342 * @ring: See struct vxge_hw_ring_config{}.
343 * @fifo: See struct vxge_hw_fifo_config{}.
344 * @tti: Configuration of interrupt associated with Transmit.
345 * see struct vxge_hw_tim_intr_config();
346 * @rti: Configuration of interrupt associated with Receive.
347 * see struct vxge_hw_tim_intr_config();
348 * @mtu: mtu size used on this port.
349 * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to
350 * remove the VLAN tag from all received tagged frames that are not
351 * replicated at the internal L2 switch.
352 * 0 - Do not strip the VLAN tag.
353 * 1 - Strip the VLAN tag. Regardless of this setting, VLAN tags are
354 * always placed into the RxDMA descriptor.
356 * This structure is used by the driver to pass the configuration parameters to
357 * configure Virtual Path.
359 struct vxge_hw_vp_config
{
362 #define VXGE_HW_VPATH_PRIORITY_MIN 0
363 #define VXGE_HW_VPATH_PRIORITY_MAX 16
364 #define VXGE_HW_VPATH_PRIORITY_DEFAULT 0
367 #define VXGE_HW_VPATH_BANDWIDTH_MIN 0
368 #define VXGE_HW_VPATH_BANDWIDTH_MAX 100
369 #define VXGE_HW_VPATH_BANDWIDTH_DEFAULT 0
371 struct vxge_hw_ring_config ring
;
372 struct vxge_hw_fifo_config fifo
;
373 struct vxge_hw_tim_intr_config tti
;
374 struct vxge_hw_tim_intr_config rti
;
377 #define VXGE_HW_VPATH_MIN_INITIAL_MTU VXGE_HW_MIN_MTU
378 #define VXGE_HW_VPATH_MAX_INITIAL_MTU VXGE_HW_MAX_MTU
379 #define VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU 0xffffffff
381 u32 rpa_strip_vlan_tag
;
382 #define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE 1
383 #define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE 0
384 #define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT 0xffffffff
388 * struct vxge_hw_device_config - Device configuration.
389 * @dma_blockpool_initial: Initial size of DMA Pool
390 * @dma_blockpool_max: Maximum blocks in DMA pool
391 * @intr_mode: Line, or MSI-X interrupt.
393 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table).
394 * @rth_it_type: RTH IT table programming type
395 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address
396 * @vp_config: Configuration for virtual paths
397 * @device_poll_millis: Specify the interval (in mulliseconds)
398 * to wait for register reads
400 * Titan configuration.
401 * Contains per-device configuration parameters, including:
402 * - stats sampling interval, etc.
404 * In addition, struct vxge_hw_device_config{} includes "subordinate"
405 * configurations, including:
407 * - MAC (done at firmware level).
409 * See Titan User Guide for more details.
410 * Note: Valid (min, max) range for each attribute is specified in the body of
411 * the struct vxge_hw_device_config{} structure. Please refer to the
412 * corresponding include file.
413 * See also: struct vxge_hw_tim_intr_config{}.
415 struct vxge_hw_device_config
{
416 u32 device_poll_millis
;
417 #define VXGE_HW_MIN_DEVICE_POLL_MILLIS 1
418 #define VXGE_HW_MAX_DEVICE_POLL_MILLIS 100000
419 #define VXGE_HW_DEF_DEVICE_POLL_MILLIS 1000
421 u32 dma_blockpool_initial
;
422 u32 dma_blockpool_max
;
423 #define VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE 0
424 #define VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE 0
425 #define VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE 4
426 #define VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE 4096
428 #define VXGE_HW_MAX_PAYLOAD_SIZE_512 2
431 #define VXGE_HW_INTR_MODE_IRQLINE 0
432 #define VXGE_HW_INTR_MODE_MSIX 1
433 #define VXGE_HW_INTR_MODE_MSIX_ONE_SHOT 2
435 #define VXGE_HW_INTR_MODE_DEF 0
438 #define VXGE_HW_RTH_DISABLE 0
439 #define VXGE_HW_RTH_ENABLE 1
440 #define VXGE_HW_RTH_DEFAULT 0
443 #define VXGE_HW_RTH_IT_TYPE_SOLO_IT 0
444 #define VXGE_HW_RTH_IT_TYPE_MULTI_IT 1
445 #define VXGE_HW_RTH_IT_TYPE_DEFAULT 0
448 #define VXGE_HW_RTS_MAC_DISABLE 0
449 #define VXGE_HW_RTS_MAC_ENABLE 1
450 #define VXGE_HW_RTS_MAC_DEFAULT 0
453 #define VXGE_HW_HWTS_DISABLE 0
454 #define VXGE_HW_HWTS_ENABLE 1
455 #define VXGE_HW_HWTS_DEFAULT 1
457 struct vxge_hw_vp_config vp_config
[VXGE_HW_MAX_VIRTUAL_PATHS
];
461 * function vxge_uld_link_up_f - Link-Up callback provided by driver.
462 * @devh: HW device handle.
463 * Link-up notification callback provided by the driver.
464 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
466 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_down_f{},
467 * vxge_hw_driver_initialize().
471 * function vxge_uld_link_down_f - Link-Down callback provided by
473 * @devh: HW device handle.
475 * Link-Down notification callback provided by the driver.
476 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
478 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{},
479 * vxge_hw_driver_initialize().
483 * function vxge_uld_crit_err_f - Critical Error notification callback.
484 * @devh: HW device handle.
485 * (typically - at HW device iinitialization time).
486 * @type: Enumerated hw error, e.g.: double ECC.
487 * @serr_data: Titan status.
488 * @ext_data: Extended data. The contents depends on the @type.
490 * Link-Down notification callback provided by the driver.
491 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
493 * See also: struct vxge_hw_uld_cbs{}, enum vxge_hw_event{},
494 * vxge_hw_driver_initialize().
498 * struct vxge_hw_uld_cbs - driver "slow-path" callbacks.
499 * @link_up: See vxge_uld_link_up_f{}.
500 * @link_down: See vxge_uld_link_down_f{}.
501 * @crit_err: See vxge_uld_crit_err_f{}.
503 * Driver slow-path (per-driver) callbacks.
504 * Implemented by driver and provided to HW via
505 * vxge_hw_driver_initialize().
506 * Note that these callbacks are not mandatory: HW will not invoke
507 * a callback if NULL is specified.
509 * See also: vxge_hw_driver_initialize().
511 struct vxge_hw_uld_cbs
{
512 void (*link_up
)(struct __vxge_hw_device
*devh
);
513 void (*link_down
)(struct __vxge_hw_device
*devh
);
514 void (*crit_err
)(struct __vxge_hw_device
*devh
,
515 enum vxge_hw_event type
, u64 ext_data
);
519 * struct __vxge_hw_blockpool_entry - Block private data structure
520 * @item: List header used to link.
521 * @length: Length of the block
522 * @memblock: Virtual address block
523 * @dma_addr: DMA Address of the block.
524 * @dma_handle: DMA handle of the block.
525 * @acc_handle: DMA acc handle
527 * Block is allocated with a header to put the blocks into list.
530 struct __vxge_hw_blockpool_entry
{
531 struct list_head item
;
535 struct pci_dev
*dma_handle
;
536 struct pci_dev
*acc_handle
;
540 * struct __vxge_hw_blockpool - Block Pool
542 * @block_size: size of each block.
543 * @Pool_size: Number of blocks in the pool
544 * @pool_max: Maximum number of blocks above which to free additional blocks
545 * @req_out: Number of block requests with OS out standing
546 * @free_block_list: List of free blocks
548 * Block pool contains the DMA blocks preallocated.
551 struct __vxge_hw_blockpool
{
552 struct __vxge_hw_device
*hldev
;
557 struct list_head free_block_list
;
558 struct list_head free_entry_list
;
562 * enum enum __vxge_hw_channel_type - Enumerated channel types.
563 * @VXGE_HW_CHANNEL_TYPE_UNKNOWN: Unknown channel.
564 * @VXGE_HW_CHANNEL_TYPE_FIFO: fifo.
565 * @VXGE_HW_CHANNEL_TYPE_RING: ring.
566 * @VXGE_HW_CHANNEL_TYPE_MAX: Maximum number of HW-supported
567 * (and recognized) channel types. Currently: 2.
569 * Enumerated channel types. Currently there are only two link-layer
570 * channels - Titan fifo and Titan ring. In the future the list will grow.
572 enum __vxge_hw_channel_type
{
573 VXGE_HW_CHANNEL_TYPE_UNKNOWN
= 0,
574 VXGE_HW_CHANNEL_TYPE_FIFO
= 1,
575 VXGE_HW_CHANNEL_TYPE_RING
= 2,
576 VXGE_HW_CHANNEL_TYPE_MAX
= 3
580 * struct __vxge_hw_channel
581 * @item: List item; used to maintain a list of open channels.
582 * @type: Channel type. See enum vxge_hw_channel_type{}.
583 * @devh: Device handle. HW device object that contains _this_ channel.
584 * @vph: Virtual path handle. Virtual Path Object that contains _this_ channel.
585 * @length: Channel length. Currently allocated number of descriptors.
586 * The channel length "grows" when more descriptors get allocated.
587 * See _hw_mempool_grow.
588 * @reserve_arr: Reserve array. Contains descriptors that can be reserved
589 * by driver for the subsequent send or receive operation.
590 * See vxge_hw_fifo_txdl_reserve(),
591 * vxge_hw_ring_rxd_reserve().
592 * @reserve_ptr: Current pointer in the resrve array
593 * @reserve_top: Reserve top gives the maximum number of dtrs available in
595 * @work_arr: Work array. Contains descriptors posted to the channel.
596 * Note that at any point in time @work_arr contains 3 types of
598 * 1) posted but not yet consumed by Titan device;
599 * 2) consumed but not yet completed;
600 * 3) completed but not yet freed
601 * (via vxge_hw_fifo_txdl_free() or vxge_hw_ring_rxd_free())
602 * @post_index: Post index. At any point in time points on the
603 * position in the channel, which'll contain next to-be-posted
605 * @compl_index: Completion index. At any point in time points on the
606 * position in the channel, which will contain next
607 * to-be-completed descriptor.
608 * @free_arr: Free array. Contains completed descriptors that were freed
609 * (i.e., handed over back to HW) by driver.
610 * See vxge_hw_fifo_txdl_free(), vxge_hw_ring_rxd_free().
611 * @free_ptr: current pointer in free array
612 * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize
613 * to store per-operation control information.
614 * @stats: Pointer to common statistics
615 * @userdata: Per-channel opaque (void*) user-defined context, which may be
616 * driver object, ULP connection, etc.
617 * Once channel is open, @userdata is passed back to user via
618 * vxge_hw_channel_callback_f.
622 * See also: enum vxge_hw_channel_type{}, enum vxge_hw_channel_flag
624 struct __vxge_hw_channel
{
625 struct list_head item
;
626 enum __vxge_hw_channel_type type
;
627 struct __vxge_hw_device
*devh
;
628 struct __vxge_hw_vpath_handle
*vph
;
635 u32 post_index ____cacheline_aligned
;
636 u32 compl_index ____cacheline_aligned
;
642 struct vxge_hw_common_reg __iomem
*common_reg
;
644 struct vxge_hw_vpath_stats_sw_common_info
*stats
;
646 } ____cacheline_aligned
;
649 * struct __vxge_hw_virtualpath - Virtual Path
651 * @vp_id: Virtual path id
652 * @vp_open: This flag specifies if vxge_hw_vp_open is called from LL Driver
654 * @vp_config: Virtual Path Config
655 * @vp_reg: VPATH Register map address in BAR0
656 * @vpmgmt_reg: VPATH_MGMT register map address
657 * @max_mtu: Max mtu that can be supported
658 * @vsport_number: vsport attached to this vpath
659 * @max_kdfc_db: Maximum kernel mode doorbells
660 * @max_nofl_db: Maximum non offload doorbells
661 * @tx_intr_num: Interrupt Number associated with the TX
665 * @vpath_handles: Virtual Path handles list
666 * @stats_block: Memory for DMAing stats
667 * @stats: Vpath statistics
669 * Virtual path structure to encapsulate the data related to a virtual path.
670 * Virtual paths are allocated by the HW upon getting configuration from the
671 * driver and inserted into the list of virtual paths.
673 struct __vxge_hw_virtualpath
{
677 #define VXGE_HW_VP_NOT_OPEN 0
678 #define VXGE_HW_VP_OPEN 1
680 struct __vxge_hw_device
*hldev
;
681 struct vxge_hw_vp_config
*vp_config
;
682 struct vxge_hw_vpath_reg __iomem
*vp_reg
;
683 struct vxge_hw_vpmgmt_reg __iomem
*vpmgmt_reg
;
684 struct __vxge_hw_non_offload_db_wrapper __iomem
*nofl_db
;
690 u64 tim_tti_cfg1_saved
;
691 u64 tim_tti_cfg3_saved
;
692 u64 tim_rti_cfg1_saved
;
693 u64 tim_rti_cfg3_saved
;
695 struct __vxge_hw_ring
*____cacheline_aligned ringh
;
696 struct __vxge_hw_fifo
*____cacheline_aligned fifoh
;
697 struct list_head vpath_handles
;
698 struct __vxge_hw_blockpool_entry
*stats_block
;
699 struct vxge_hw_vpath_stats_hw_info
*hw_stats
;
700 struct vxge_hw_vpath_stats_hw_info
*hw_stats_sav
;
701 struct vxge_hw_vpath_stats_sw_info
*sw_stats
;
706 * struct __vxge_hw_vpath_handle - List item to store callback information
707 * @item: List head to keep the item in linked list
708 * @vpath: Virtual path to which this item belongs
710 * This structure is used to store the callback information.
712 struct __vxge_hw_vpath_handle
{
713 struct list_head item
;
714 struct __vxge_hw_virtualpath
*vpath
;
718 * struct __vxge_hw_device
723 * struct __vxge_hw_device - Hal device object
724 * @magic: Magic Number
725 * @bar0: BAR0 virtual address.
726 * @pdev: Physical device handle
727 * @config: Confguration passed by the LL driver at initialization
728 * @link_state: Link state
730 * HW device object. Represents Titan adapter
732 struct __vxge_hw_device
{
734 #define VXGE_HW_DEVICE_MAGIC 0x12345678
735 #define VXGE_HW_DEVICE_DEAD 0xDEADDEAD
737 struct pci_dev
*pdev
;
738 struct net_device
*ndev
;
739 struct vxge_hw_device_config config
;
740 enum vxge_hw_device_link_state link_state
;
742 struct vxge_hw_uld_cbs uld_callbacks
;
747 #define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH 0x1
748 #define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM 0x2
749 #define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM 0x4
750 struct vxge_hw_legacy_reg __iomem
*legacy_reg
;
751 struct vxge_hw_toc_reg __iomem
*toc_reg
;
752 struct vxge_hw_common_reg __iomem
*common_reg
;
753 struct vxge_hw_mrpcim_reg __iomem
*mrpcim_reg
;
754 struct vxge_hw_srpcim_reg __iomem
*srpcim_reg \
755 [VXGE_HW_TITAN_SRPCIM_REG_SPACES
];
756 struct vxge_hw_vpmgmt_reg __iomem
*vpmgmt_reg \
757 [VXGE_HW_TITAN_VPMGMT_REG_SPACES
];
758 struct vxge_hw_vpath_reg __iomem
*vpath_reg \
759 [VXGE_HW_TITAN_VPATH_REG_SPACES
];
762 struct __vxge_hw_virtualpath virtual_paths \
763 [VXGE_HW_MAX_VIRTUAL_PATHS
];
764 u64 vpath_assignments
;
767 u64 tim_int_mask0
[4];
768 u32 tim_int_mask1
[4];
770 struct __vxge_hw_blockpool block_pool
;
771 struct vxge_hw_device_stats stats
;
772 u32 debug_module_mask
;
776 u16 eprom_versions
[VXGE_HW_MAX_ROM_IMAGES
];
779 #define VXGE_HW_INFO_LEN 64
781 * struct vxge_hw_device_hw_info - Device information
782 * @host_type: Host Type
783 * @func_id: Function Id
784 * @vpath_mask: vpath bit mask
785 * @fw_version: Firmware version
786 * @fw_date: Firmware Date
787 * @flash_version: Firmware version
788 * @flash_date: Firmware Date
789 * @mac_addrs: Mac addresses for each vpath
790 * @mac_addr_masks: Mac address masks for each vpath
792 * Returns the vpath mask that has the bits set for each vpath allocated
793 * for the driver and the first mac address for each vpath
795 struct vxge_hw_device_hw_info
{
797 #define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION 0
798 #define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION 1
799 #define VXGE_HW_NO_MR_SR_VH0_FUNCTION0 2
800 #define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3
801 #define VXGE_HW_MR_SR_VH0_INVALID_CONFIG 4
802 #define VXGE_HW_SR_VH_FUNCTION0 5
803 #define VXGE_HW_SR_VH_VIRTUAL_FUNCTION 6
804 #define VXGE_HW_VH_NORMAL_FUNCTION 7
806 #define VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION 0
807 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION 1
808 #define VXGE_HW_FUNCTION_MODE_SRIOV 2
809 #define VXGE_HW_FUNCTION_MODE_MRIOV 3
810 #define VXGE_HW_FUNCTION_MODE_MRIOV_8 4
811 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_17 5
812 #define VXGE_HW_FUNCTION_MODE_SRIOV_8 6
813 #define VXGE_HW_FUNCTION_MODE_SRIOV_4 7
814 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_2 8
815 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_4 9
816 #define VXGE_HW_FUNCTION_MODE_MRIOV_4 10
820 struct vxge_hw_device_version fw_version
;
821 struct vxge_hw_device_date fw_date
;
822 struct vxge_hw_device_version flash_version
;
823 struct vxge_hw_device_date flash_date
;
824 u8 serial_number
[VXGE_HW_INFO_LEN
];
825 u8 part_number
[VXGE_HW_INFO_LEN
];
826 u8 product_desc
[VXGE_HW_INFO_LEN
];
827 u8 mac_addrs
[VXGE_HW_MAX_VIRTUAL_PATHS
][ETH_ALEN
];
828 u8 mac_addr_masks
[VXGE_HW_MAX_VIRTUAL_PATHS
][ETH_ALEN
];
832 * struct vxge_hw_device_attr - Device memory spaces.
833 * @bar0: BAR0 virtual address.
834 * @pdev: PCI device object.
836 * Device memory spaces. Includes configuration, BAR0 etc. per device
837 * mapped memories. Also, includes a pointer to OS-specific PCI device object.
839 struct vxge_hw_device_attr
{
841 struct pci_dev
*pdev
;
842 struct vxge_hw_uld_cbs uld_callbacks
;
845 #define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls) (hldev->link_state = ls)
847 #define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) { \
849 m0[0] |= vxge_vBIT(0x8, (i*4), 4); \
850 m0[1] |= vxge_vBIT(0x4, (i*4), 4); \
853 m1[0] = 0x80000000; \
854 m1[1] = 0x40000000; \
858 #define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) { \
860 m0[0] &= ~vxge_vBIT(0x8, (i*4), 4); \
861 m0[1] &= ~vxge_vBIT(0x4, (i*4), 4); \
869 #define VXGE_HW_DEVICE_STATS_PIO_READ(loc, offset) { \
870 status = vxge_hw_mrpcim_stats_access(hldev, \
871 VXGE_HW_STATS_OP_READ, \
875 if (status != VXGE_HW_OK) \
880 * struct __vxge_hw_ring - Ring channel.
881 * @channel: Channel "base" of this ring, the common part of all HW
883 * @mempool: Memory pool, the pool from which descriptors get allocated.
884 * (See vxge_hw_mm.h).
885 * @config: Ring configuration, part of device configuration
886 * (see struct vxge_hw_device_config{}).
887 * @ring_length: Length of the ring
888 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
889 * as per Titan User Guide.
890 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Titan spec,
891 * 1-buffer mode descriptor is 32 byte long, etc.
892 * @rxd_priv_size: Per RxD size reserved (by HW) for driver to keep
893 * per-descriptor data (e.g., DMA handle for Solaris)
894 * @per_rxd_space: Per rxd space requested by driver
895 * @rxds_per_block: Number of descriptors per hardware-defined RxD
896 * block. Depends on the (1-, 3-, 5-) buffer mode.
897 * @rxdblock_priv_size: Reserved at the end of each RxD block. HW internal
898 * usage. Not to confuse with @rxd_priv_size.
899 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
900 * @callback: Channel completion callback. HW invokes the callback when there
901 * are new completions on that channel. In many implementations
902 * the @callback executes in the hw interrupt context.
903 * @rxd_init: Channel's descriptor-initialize callback.
904 * See vxge_hw_ring_rxd_init_f{}.
905 * If not NULL, HW invokes the callback when opening
907 * @rxd_term: Channel's descriptor-terminate callback. If not NULL,
908 * HW invokes the callback when closing the corresponding channel.
909 * See also vxge_hw_channel_rxd_term_f{}.
910 * @stats: Statistics for ring
913 * Note: The structure is cache line aligned to better utilize
914 * CPU cache performance.
916 struct __vxge_hw_ring
{
917 struct __vxge_hw_channel channel
;
918 struct vxge_hw_mempool
*mempool
;
919 struct vxge_hw_vpath_reg __iomem
*vp_reg
;
920 struct vxge_hw_common_reg __iomem
*common_reg
;
927 u32 rxdblock_priv_size
;
934 u64 tim_rti_cfg1_saved
;
935 u64 tim_rti_cfg3_saved
;
937 enum vxge_hw_status (*callback
)(
938 struct __vxge_hw_ring
*ringh
,
943 enum vxge_hw_status (*rxd_init
)(
949 enum vxge_hw_rxd_state state
,
952 struct vxge_hw_vpath_stats_sw_ring_info
*stats ____cacheline_aligned
;
953 struct vxge_hw_ring_config
*config
;
954 } ____cacheline_aligned
;
957 * enum enum vxge_hw_txdl_state - Descriptor (TXDL) state.
958 * @VXGE_HW_TXDL_STATE_NONE: Invalid state.
959 * @VXGE_HW_TXDL_STATE_AVAIL: Descriptor is available for reservation.
960 * @VXGE_HW_TXDL_STATE_POSTED: Descriptor is posted for processing by the
962 * @VXGE_HW_TXDL_STATE_FREED: Descriptor is free and can be reused for
963 * filling-in and posting later.
965 * Titan/HW descriptor states.
968 enum vxge_hw_txdl_state
{
969 VXGE_HW_TXDL_STATE_NONE
= 0,
970 VXGE_HW_TXDL_STATE_AVAIL
= 1,
971 VXGE_HW_TXDL_STATE_POSTED
= 2,
972 VXGE_HW_TXDL_STATE_FREED
= 3
975 * struct __vxge_hw_fifo - Fifo.
976 * @channel: Channel "base" of this fifo, the common part of all HW
978 * @mempool: Memory pool, from which descriptors get allocated.
979 * @config: Fifo configuration, part of device configuration
980 * (see struct vxge_hw_device_config{}).
981 * @interrupt_type: Interrupt type to be used
982 * @no_snoop_bits: See struct vxge_hw_fifo_config{}.
983 * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
984 * on TxDL please refer to Titan UG.
985 * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
986 * per-TxDL HW private space (struct __vxge_hw_fifo_txdl_priv).
987 * @priv_size: Per-Tx descriptor space reserved for driver
989 * @per_txdl_space: Per txdl private space for the driver
990 * @callback: Fifo completion callback. HW invokes the callback when there
991 * are new completions on that fifo. In many implementations
992 * the @callback executes in the hw interrupt context.
993 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
994 * HW invokes the callback when closing the corresponding fifo.
995 * See also vxge_hw_fifo_txdl_term_f{}.
996 * @stats: Statistics of this fifo
999 * Note: The structure is cache line aligned.
1001 struct __vxge_hw_fifo
{
1002 struct __vxge_hw_channel channel
;
1003 struct vxge_hw_mempool
*mempool
;
1004 struct vxge_hw_fifo_config
*config
;
1005 struct vxge_hw_vpath_reg __iomem
*vp_reg
;
1006 struct __vxge_hw_non_offload_db_wrapper __iomem
*nofl_db
;
1009 u32 txdl_per_memblock
;
1016 u64 tim_tti_cfg1_saved
;
1017 u64 tim_tti_cfg3_saved
;
1019 enum vxge_hw_status (*callback
)(
1020 struct __vxge_hw_fifo
*fifo_handle
,
1022 enum vxge_hw_fifo_tcode t_code
,
1024 struct sk_buff
***skb_ptr
,
1030 enum vxge_hw_txdl_state state
,
1033 struct vxge_hw_vpath_stats_sw_fifo_info
*stats ____cacheline_aligned
;
1034 } ____cacheline_aligned
;
1037 * struct __vxge_hw_fifo_txdl_priv - Transmit descriptor HW-private data.
1038 * @dma_addr: DMA (mapped) address of _this_ descriptor.
1039 * @dma_handle: DMA handle used to map the descriptor onto device.
1040 * @dma_offset: Descriptor's offset in the memory block. HW allocates
1041 * descriptors in memory blocks (see struct vxge_hw_fifo_config{})
1042 * Each memblock is a contiguous block of DMA-able memory.
1043 * @frags: Total number of fragments (that is, contiguous data buffers)
1044 * carried by this TxDL.
1045 * @align_vaddr_start: Aligned virtual address start
1046 * @align_vaddr: Virtual address of the per-TxDL area in memory used for
1047 * alignement. Used to place one or more mis-aligned fragments
1048 * @align_dma_addr: DMA address translated from the @align_vaddr.
1049 * @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
1050 * @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
1051 * @align_dma_offset: The current offset into the @align_vaddr area.
1052 * Grows while filling the descriptor, gets reset.
1053 * @align_used_frags: Number of fragments used.
1054 * @alloc_frags: Total number of fragments allocated.
1056 * @next_txdl_priv: (TODO).
1057 * @first_txdp: (TODO).
1058 * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
1060 * @txdlh: Corresponding txdlh to this TxDL.
1061 * @memblock: Pointer to the TxDL memory block or memory page.
1062 * on the next send operation.
1063 * @dma_object: DMA address and handle of the memory block that contains
1064 * the descriptor. This member is used only in the "checked"
1065 * version of the HW (to enforce certain assertions);
1066 * otherwise it gets compiled out.
1067 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
1069 * Per-transmit decsriptor HW-private data. HW uses the space to keep DMA
1070 * information associated with the descriptor. Note that driver can ask HW
1071 * to allocate additional per-descriptor space for its own (driver-specific)
1074 * See also: struct vxge_hw_ring_rxd_priv{}.
1076 struct __vxge_hw_fifo_txdl_priv
{
1077 dma_addr_t dma_addr
;
1078 struct pci_dev
*dma_handle
;
1079 ptrdiff_t dma_offset
;
1081 u8
*align_vaddr_start
;
1083 dma_addr_t align_dma_addr
;
1084 struct pci_dev
*align_dma_handle
;
1085 struct pci_dev
*align_dma_acch
;
1086 ptrdiff_t align_dma_offset
;
1087 u32 align_used_frags
;
1090 struct __vxge_hw_fifo_txdl_priv
*next_txdl_priv
;
1091 struct vxge_hw_fifo_txd
*first_txdp
;
1096 * struct __vxge_hw_non_offload_db_wrapper - Non-offload Doorbell Wrapper
1097 * @control_0: Bits 0 to 7 - Doorbell type.
1098 * Bits 8 to 31 - Reserved.
1099 * Bits 32 to 39 - The highest TxD in this TxDL.
1100 * Bits 40 to 47 - Reserved.
1101 * Bits 48 to 55 - Reserved.
1102 * Bits 56 to 63 - No snoop flags.
1103 * @txdl_ptr: The starting location of the TxDL in host memory.
1105 * Created by the host and written to the adapter via PIO to a Kernel Doorbell
1106 * FIFO. All non-offload doorbell wrapper fields must be written by the host as
1107 * part of a doorbell write. Consumed by the adapter but is not written by the
1110 struct __vxge_hw_non_offload_db_wrapper
{
1112 #define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8)
1113 #define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8)
1114 #define VXGE_HW_NODBW_TYPE_NODBW 0
1116 #define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8)
1117 #define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8)
1119 #define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8)
1120 #define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8)
1121 #define VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE 0x2
1122 #define VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ 0x1
1132 * struct vxge_hw_fifo_txd - Transmit Descriptor
1133 * @control_0: Bits 0 to 6 - Reserved.
1134 * Bit 7 - List Ownership. This field should be initialized
1135 * to '1' by the driver before the transmit list pointer is
1136 * written to the adapter. This field will be set to '0' by the
1137 * adapter once it has completed transmitting the frame or frames in
1138 * the list. Note - This field is only valid in TxD0. Additionally,
1139 * for multi-list sequences, the driver should not release any
1140 * buffers until the ownership of the last list in the multi-list
1141 * sequence has been returned to the host.
1142 * Bits 8 to 11 - Reserved
1143 * Bits 12 to 15 - Transfer_Code. This field is only valid in
1144 * TxD0. It is used to describe the status of the transmit data
1145 * buffer transfer. This field is always overwritten by the
1146 * adapter, so this field may be initialized to any value.
1147 * Bits 16 to 17 - Host steering. This field allows the host to
1148 * override the selection of the physical transmit port.
1150 * Normal sounds as if learned from the switch rather than from
1151 * the aggregation algorythms.
1152 * 00: Normal. Use Destination/MAC Address
1153 * lookup to determine the transmit port.
1154 * 01: Send on physical Port1.
1155 * 10: Send on physical Port0.
1156 * 11: Send on both ports.
1157 * Bits 18 to 21 - Reserved
1158 * Bits 22 to 23 - Gather_Code. This field is set by the host and
1159 * is used to describe how individual buffers comprise a frame.
1160 * 10: First descriptor of a frame.
1161 * 00: Middle of a multi-descriptor frame.
1162 * 01: Last descriptor of a frame.
1163 * 11: First and last descriptor of a frame (the entire frame
1164 * resides in a single buffer).
1165 * For multi-descriptor frames, the only valid gather code sequence
1166 * is {10, [00], 01}. In other words, the descriptors must be placed
1167 * in the list in the correct order.
1168 * Bits 24 to 27 - Reserved
1169 * Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation
1170 * definition. Only valid in TxD0. This field allows the host to
1171 * indicate the Ethernet encapsulation of an outbound LSO packet.
1172 * 00 - classic mode (best guess)
1176 * If "classic mode" is selected, the adapter will attempt to
1177 * decode the frame's Ethernet encapsulation by examining the L/T
1179 * <= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine
1180 * if packet is IPv4 or IPv6.
1181 * 0x8870 Jumbo-SNAP encoding.
1182 * 0x0800 IPv4 DIX encoding
1183 * 0x86DD IPv6 DIX encoding
1184 * others illegal encapsulation
1185 * Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag.
1186 * Set to 1 to perform segmentation offload for TCP/UDP.
1187 * This field is valid only in TxD0.
1188 * Bits 31 to 33 - Reserved.
1189 * Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size
1190 * This field is meaningful only when LSO_Control is non-zero.
1191 * When LSO_Control is set to TCP_LSO, the single (possibly large)
1192 * TCP segment described by this TxDL will be sent as a series of
1193 * TCP segments each of which contains no more than LSO_MSS
1195 * When LSO_Control is set to UDP_LSO, the single (possibly large)
1196 * UDP datagram described by this TxDL will be sent as a series of
1197 * UDP datagrams each of which contains no more than LSO_MSS
1199 * All outgoing frames from this TxDL will have LSO_MSS bytes of UDP
1200 * or TCP payload, with the exception of the last, which will have
1201 * <= LSO_MSS bytes of payload.
1202 * Bits 48 to 63 - Buffer_Size. Number of valid bytes in the
1203 * buffer to be read by the adapter. This field is written by the
1204 * host. A value of 0 is illegal.
1205 * Bits 32 to 63 - This value is written by the adapter upon
1206 * completion of a UDP or TCP LSO operation and indicates the number
1207 * of UDP or TCP payload bytes that were transmitted. 0x0000 will be
1208 * returned for any non-LSO operation.
1209 * @control_1: Bits 0 to 4 - Reserved.
1210 * Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum
1211 * offload. This field is only valid in the first TxD of a frame.
1212 * Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload.
1213 * This field is only valid in the first TxD of a frame (the TxD's
1214 * gather code must be 10 or 11). The driver should only set this
1215 * bit if it can guarantee that TCP is present.
1216 * Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload.
1217 * This field is only valid in the first TxD of a frame (the TxD's
1218 * gather code must be 10 or 11). The driver should only set this
1219 * bit if it can guarantee that UDP is present.
1220 * Bits 8 to 14 - Reserved.
1221 * Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to
1222 * instruct the adapter to insert the VLAN tag specified by the
1223 * Tx_VLAN_Tag field. This field is only valid in the first TxD of
1225 * Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag
1226 * to be inserted into the frame by the adapter (the first two bytes
1227 * of a VLAN tag are always 0x8100). This field is only valid if the
1228 * Tx_VLAN_Enable field is set to '1'.
1229 * Bits 32 to 33 - Reserved.
1230 * Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt
1231 * number the frame associated with. This field is written by the
1232 * host. It is only valid in the first TxD of a frame.
1233 * Bits 40 to 42 - Reserved.
1234 * Bit 43 - Set to 1 to exclude the frame from bandwidth metering
1235 * functions. This field is valid only in the first TxD
1237 * Bits 44 to 45 - Reserved.
1238 * Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to
1239 * generate an interrupt as soon as all of the frames in the list
1240 * have been transmitted. In order to have per-frame interrupts,
1241 * the driver should place a maximum of one frame per list. This
1242 * field is only valid in the first TxD of a frame.
1243 * Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter
1244 * to count the frame toward the utilization interrupt specified in
1245 * the Tx_Int_Number field. This field is only valid in the first
1247 * Bits 48 to 63 - Reserved.
1248 * @buffer_pointer: Buffer start address.
1249 * @host_control: Host_Control.Opaque 64bit data stored by driver inside the
1250 * Titan descriptor prior to posting the latter on the fifo
1251 * via vxge_hw_fifo_txdl_post().The %host_control is returned as is
1252 * to the driver with each completed descriptor.
1254 * Transmit descriptor (TxD).Fifo descriptor contains configured number
1255 * (list) of TxDs. * For more details please refer to Titan User Guide,
1256 * Section 5.4.2 "Transmit Descriptor (TxD) Format".
1258 struct vxge_hw_fifo_txd
{
1260 #define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER vxge_mBIT(7)
1262 #define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4)
1263 #define VXGE_HW_FIFO_TXD_T_CODE(val) vxge_vBIT(val, 12, 4)
1264 #define VXGE_HW_FIFO_TXD_T_CODE_UNUSED VXGE_HW_FIFO_T_CODE_UNUSED
1267 #define VXGE_HW_FIFO_TXD_GATHER_CODE(val) vxge_vBIT(val, 22, 2)
1268 #define VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST VXGE_HW_FIFO_GATHER_CODE_FIRST
1269 #define VXGE_HW_FIFO_TXD_GATHER_CODE_LAST VXGE_HW_FIFO_GATHER_CODE_LAST
1272 #define VXGE_HW_FIFO_TXD_LSO_EN vxge_mBIT(30)
1274 #define VXGE_HW_FIFO_TXD_LSO_MSS(val) vxge_vBIT(val, 34, 14)
1276 #define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val) vxge_vBIT(val, 48, 16)
1279 #define VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN vxge_mBIT(5)
1280 #define VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN vxge_mBIT(6)
1281 #define VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN vxge_mBIT(7)
1282 #define VXGE_HW_FIFO_TXD_VLAN_ENABLE vxge_mBIT(15)
1284 #define VXGE_HW_FIFO_TXD_VLAN_TAG(val) vxge_vBIT(val, 16, 16)
1286 #define VXGE_HW_FIFO_TXD_INT_NUMBER(val) vxge_vBIT(val, 34, 6)
1288 #define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST vxge_mBIT(46)
1289 #define VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ vxge_mBIT(47)
1297 * struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
1298 * @host_control: This field is exclusively for host use and is "readonly"
1299 * from the adapter's perspective.
1300 * @control_0:Bits 0 to 6 - RTH_Bucket get
1301 * Bit 7 - Own Descriptor ownership bit. This bit is set to 1
1302 * by the host, and is set to 0 by the adapter.
1303 * 0 - Host owns RxD and buffer.
1304 * 1 - The adapter owns RxD and buffer.
1305 * Bit 8 - Fast_Path_Eligible When set, indicates that the
1306 * received frame meets all of the criteria for fast path processing.
1307 * The required criteria are as follows:
1309 * (Transfer_Code == "Transfer OK") &
1310 * (!Is_IP_Fragment) &
1311 * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) |
1313 * ((Is_TCP & computed_L4_checksum == 0xFFFF) |
1314 * (Is_UDP & (computed_L4_checksum == 0xFFFF |
1315 * computed _L4_checksum == 0x0000)))
1316 * (same meaning for all RxD buffer modes)
1317 * Bit 9 - L3 Checksum Correct
1318 * Bit 10 - L4 Checksum Correct
1320 * Bit 12 to 15 - This field is written by the adapter. It is
1321 * used to report the status of the frame transfer to the host.
1323 * 0x4 - RDA Failure During Transfer
1324 * 0x5 - Unparseable Packet, such as unknown IPv6 header.
1325 * 0x6 - Frame integrity error (FCS or ECC).
1326 * 0x7 - Buffer Size Error. The provided buffer(s) were not
1327 * appropriately sized and data loss occurred.
1328 * 0x8 - Internal ECC Error. RxD corrupted.
1329 * 0x9 - IPv4 Checksum error
1330 * 0xA - TCP/UDP Checksum error
1331 * 0xF - Unknown Error or Multiple Error. Indicates an
1332 * unknown problem or that more than one of transfer codes is set.
1333 * Bit 16 - SYN The adapter sets this field to indicate that
1334 * the incoming frame contained a TCP segment with its SYN bit
1335 * set and its ACK bit NOT set. (same meaning for all RxD buffer
1338 * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the
1339 * Socket Pair Direct Match Table and the frame was steered based
1341 * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the
1342 * Indirection Table and the frame was steered based on hash
1344 * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash
1345 * type) that was used to calculate the hash.
1346 * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN
1348 * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation
1349 * of the received frame.
1350 * 0x0 - Ethernet DIX
1352 * 0x2 - SNAP (includes Jumbo-SNAP)
1354 * Bit 27 - IS_IPV4 Set to '1' if the frame contains an IPv4 packet.
1355 * Bit 28 - IS_IPV6 Set to '1' if the frame contains an IPv6 packet.
1356 * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a fragmented
1358 * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment.
1359 * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message.
1360 * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that
1361 * arrived with the frame. If the resulting computed IPv4 header
1362 * checksum for the frame did not produce the expected 0xFFFF value,
1363 * then the transfer code would be set to 0x9.
1364 * Bit 48 to 63 - L4_Checksum[0:15] The TCP/UDP checksum value that
1365 * arrived with the frame. If the resulting computed TCP/UDP checksum
1366 * for the frame did not produce the expected 0xFFFF value, then the
1367 * transfer code would be set to 0xA.
1368 * @control_1:Bits 0 to 1 - Reserved
1369 * Bits 2 to 15 - Buffer0_Size.This field is set by the host and
1370 * eventually overwritten by the adapter. The host writes the
1371 * available buffer size in bytes when it passes the descriptor to
1372 * the adapter. When a frame is delivered the host, the adapter
1373 * populates this field with the number of bytes written into the
1374 * buffer. The largest supported buffer is 16, 383 bytes.
1375 * Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid if
1376 * RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero.
1377 * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable portion
1378 * of the VLAN tag, if one was detected by the adapter. This field is
1379 * populated even if VLAN-tag stripping is enabled.
1380 * @buffer0_ptr: Pointer to buffer. This field is populated by the driver.
1382 * One buffer mode RxD for ring structure
1384 struct vxge_hw_ring_rxd_1
{
1387 #define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7)
1389 #define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER vxge_mBIT(7)
1391 #define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1)
1393 #define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1)
1395 #define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1)
1397 #define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4)
1398 #define VXGE_HW_RING_RXD_T_CODE(val) vxge_vBIT(val, 12, 4)
1400 #define VXGE_HW_RING_RXD_T_CODE_UNUSED VXGE_HW_RING_T_CODE_UNUSED
1402 #define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1)
1404 #define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0) vxge_bVALn(ctrl0, 17, 1)
1406 #define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 18, 1)
1408 #define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 19, 1)
1410 #define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) vxge_bVALn(ctrl0, 20, 4)
1412 #define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0) vxge_bVALn(ctrl0, 24, 1)
1414 #define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0) vxge_bVALn(ctrl0, 25, 2)
1416 #define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0) vxge_bVALn(ctrl0, 27, 5)
1418 #define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 32, 16)
1420 #define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 48, 16)
1424 #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14)
1425 #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14)
1426 #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK vxge_vBIT(0x3FFF, 2, 14)
1428 #define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32)
1430 #define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16)
1435 enum vxge_hw_rth_algoritms
{
1436 RTH_ALG_JENKINS
= 0,
1442 * struct vxge_hw_rth_hash_types - RTH hash types.
1443 * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4
1444 * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4
1445 * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6
1446 * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6
1447 * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex
1448 * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex
1450 * Used to pass RTH hash types to rts_rts_set.
1452 * See also: vxge_hw_vpath_rts_rth_set(), vxge_hw_vpath_rts_rth_get().
1454 struct vxge_hw_rth_hash_types
{
1455 u8 hash_type_tcpipv4_en
:1,
1456 hash_type_ipv4_en
:1,
1457 hash_type_tcpipv6_en
:1,
1458 hash_type_ipv6_en
:1,
1459 hash_type_tcpipv6ex_en
:1,
1460 hash_type_ipv6ex_en
:1;
1463 void vxge_hw_device_debug_set(
1464 struct __vxge_hw_device
*devh
,
1465 enum vxge_debug_level level
,
1469 vxge_hw_device_error_level_get(struct __vxge_hw_device
*devh
);
1472 vxge_hw_device_trace_level_get(struct __vxge_hw_device
*devh
);
1475 * vxge_hw_ring_rxd_size_get - Get the size of ring descriptor.
1476 * @buf_mode: Buffer mode (1, 3 or 5)
1478 * This function returns the size of RxD for given buffer mode
1480 static inline u32
vxge_hw_ring_rxd_size_get(u32 buf_mode
)
1482 return sizeof(struct vxge_hw_ring_rxd_1
);
1486 * vxge_hw_ring_rxds_per_block_get - Get the number of rxds per block.
1487 * @buf_mode: Buffer mode (1 buffer mode only)
1489 * This function returns the number of RxD for RxD block for given buffer mode
1491 static inline u32
vxge_hw_ring_rxds_per_block_get(u32 buf_mode
)
1493 return (u32
)((VXGE_HW_BLOCK_SIZE
-16) /
1494 sizeof(struct vxge_hw_ring_rxd_1
));
1498 * vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
1499 * @rxdh: Descriptor handle.
1500 * @dma_pointer: DMA address of a single receive buffer this descriptor
1501 * should carry. Note that by the time vxge_hw_ring_rxd_1b_set is called,
1502 * the receive buffer should be already mapped to the device
1503 * @size: Size of the receive @dma_pointer buffer.
1505 * Prepare 1-buffer-mode Rx descriptor for posting
1506 * (via vxge_hw_ring_rxd_post()).
1508 * This inline helper-function does not return any parameters and always
1513 void vxge_hw_ring_rxd_1b_set(
1515 dma_addr_t dma_pointer
,
1518 struct vxge_hw_ring_rxd_1
*rxdp
= (struct vxge_hw_ring_rxd_1
*)rxdh
;
1519 rxdp
->buffer0_ptr
= dma_pointer
;
1520 rxdp
->control_1
&= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK
;
1521 rxdp
->control_1
|= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size
);
1525 * vxge_hw_ring_rxd_1b_get - Get data from the completed 1-buf
1527 * @vpath_handle: Virtual Path handle.
1528 * @rxdh: Descriptor handle.
1529 * @dma_pointer: DMA address of a single receive buffer this descriptor
1530 * carries. Returned by HW.
1531 * @pkt_length: Length (in bytes) of the data in the buffer pointed by
1533 * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor.
1534 * This inline helper-function uses completed descriptor to populate receive
1535 * buffer pointer and other "out" parameters. The function always succeeds.
1539 void vxge_hw_ring_rxd_1b_get(
1540 struct __vxge_hw_ring
*ring_handle
,
1544 struct vxge_hw_ring_rxd_1
*rxdp
= (struct vxge_hw_ring_rxd_1
*)rxdh
;
1547 (u32
)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp
->control_1
);
1551 * vxge_hw_ring_rxd_1b_info_get - Get extended information associated with
1552 * a completed receive descriptor for 1b mode.
1553 * @vpath_handle: Virtual Path handle.
1554 * @rxdh: Descriptor handle.
1555 * @rxd_info: Descriptor information
1557 * Retrieve extended information associated with a completed receive descriptor.
1561 void vxge_hw_ring_rxd_1b_info_get(
1562 struct __vxge_hw_ring
*ring_handle
,
1564 struct vxge_hw_ring_rxd_info
*rxd_info
)
1567 struct vxge_hw_ring_rxd_1
*rxdp
= (struct vxge_hw_ring_rxd_1
*)rxdh
;
1568 rxd_info
->syn_flag
=
1569 (u32
)VXGE_HW_RING_RXD_SYN_GET(rxdp
->control_0
);
1571 (u32
)VXGE_HW_RING_RXD_IS_ICMP_GET(rxdp
->control_0
);
1572 rxd_info
->fast_path_eligible
=
1573 (u32
)VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp
->control_0
);
1574 rxd_info
->l3_cksum_valid
=
1575 (u32
)VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp
->control_0
);
1576 rxd_info
->l3_cksum
=
1577 (u32
)VXGE_HW_RING_RXD_L3_CKSUM_GET(rxdp
->control_0
);
1578 rxd_info
->l4_cksum_valid
=
1579 (u32
)VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp
->control_0
);
1580 rxd_info
->l4_cksum
=
1581 (u32
)VXGE_HW_RING_RXD_L4_CKSUM_GET(rxdp
->control_0
);
1583 (u32
)VXGE_HW_RING_RXD_ETHER_ENCAP_GET(rxdp
->control_0
);
1585 (u32
)VXGE_HW_RING_RXD_FRAME_PROTO_GET(rxdp
->control_0
);
1587 (u32
)VXGE_HW_RING_RXD_IS_VLAN_GET(rxdp
->control_0
);
1589 (u32
)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp
->control_1
);
1590 rxd_info
->rth_bucket
=
1591 (u32
)VXGE_HW_RING_RXD_RTH_BUCKET_GET(rxdp
->control_0
);
1592 rxd_info
->rth_it_hit
=
1593 (u32
)VXGE_HW_RING_RXD_RTH_IT_HIT_GET(rxdp
->control_0
);
1594 rxd_info
->rth_spdm_hit
=
1595 (u32
)VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(rxdp
->control_0
);
1596 rxd_info
->rth_hash_type
=
1597 (u32
)VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(rxdp
->control_0
);
1598 rxd_info
->rth_value
=
1599 (u32
)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp
->control_1
);
1603 * vxge_hw_ring_rxd_private_get - Get driver private per-descriptor data
1604 * of 1b mode 3b mode ring.
1605 * @rxdh: Descriptor handle.
1607 * Returns: private driver info associated with the descriptor.
1608 * driver requests per-descriptor space via vxge_hw_ring_attr.
1611 static inline void *vxge_hw_ring_rxd_private_get(void *rxdh
)
1613 struct vxge_hw_ring_rxd_1
*rxdp
= (struct vxge_hw_ring_rxd_1
*)rxdh
;
1614 return (void *)(size_t)rxdp
->host_control
;
1618 * vxge_hw_fifo_txdl_cksum_set_bits - Offload checksum.
1619 * @txdlh: Descriptor handle.
1620 * @cksum_bits: Specifies which checksums are to be offloaded: IPv4,
1621 * and/or TCP and/or UDP.
1623 * Ask Titan to calculate IPv4 & transport checksums for _this_ transmit
1625 * This API is part of the preparation of the transmit descriptor for posting
1626 * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
1627 * vxge_hw_fifo_txdl_mss_set(), vxge_hw_fifo_txdl_buffer_set_aligned(),
1628 * and vxge_hw_fifo_txdl_buffer_set().
1629 * All these APIs fill in the fields of the fifo descriptor,
1630 * in accordance with the Titan specification.
1633 static inline void vxge_hw_fifo_txdl_cksum_set_bits(void *txdlh
, u64 cksum_bits
)
1635 struct vxge_hw_fifo_txd
*txdp
= (struct vxge_hw_fifo_txd
*)txdlh
;
1636 txdp
->control_1
|= cksum_bits
;
1640 * vxge_hw_fifo_txdl_mss_set - Set MSS.
1641 * @txdlh: Descriptor handle.
1642 * @mss: MSS size for _this_ TCP connection. Passed by TCP stack down to the
1643 * driver, which in turn inserts the MSS into the @txdlh.
1645 * This API is part of the preparation of the transmit descriptor for posting
1646 * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
1647 * vxge_hw_fifo_txdl_buffer_set(), vxge_hw_fifo_txdl_buffer_set_aligned(),
1648 * and vxge_hw_fifo_txdl_cksum_set_bits().
1649 * All these APIs fill in the fields of the fifo descriptor,
1650 * in accordance with the Titan specification.
1653 static inline void vxge_hw_fifo_txdl_mss_set(void *txdlh
, int mss
)
1655 struct vxge_hw_fifo_txd
*txdp
= (struct vxge_hw_fifo_txd
*)txdlh
;
1657 txdp
->control_0
|= VXGE_HW_FIFO_TXD_LSO_EN
;
1658 txdp
->control_0
|= VXGE_HW_FIFO_TXD_LSO_MSS(mss
);
1662 * vxge_hw_fifo_txdl_vlan_set - Set VLAN tag.
1663 * @txdlh: Descriptor handle.
1664 * @vlan_tag: 16bit VLAN tag.
1666 * Insert VLAN tag into specified transmit descriptor.
1667 * The actual insertion of the tag into outgoing frame is done by the hardware.
1669 static inline void vxge_hw_fifo_txdl_vlan_set(void *txdlh
, u16 vlan_tag
)
1671 struct vxge_hw_fifo_txd
*txdp
= (struct vxge_hw_fifo_txd
*)txdlh
;
1673 txdp
->control_1
|= VXGE_HW_FIFO_TXD_VLAN_ENABLE
;
1674 txdp
->control_1
|= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag
);
1678 * vxge_hw_fifo_txdl_private_get - Retrieve per-descriptor private data.
1679 * @txdlh: Descriptor handle.
1681 * Retrieve per-descriptor private data.
1682 * Note that driver requests per-descriptor space via
1683 * struct vxge_hw_fifo_attr passed to
1684 * vxge_hw_vpath_open().
1686 * Returns: private driver data associated with the descriptor.
1688 static inline void *vxge_hw_fifo_txdl_private_get(void *txdlh
)
1690 struct vxge_hw_fifo_txd
*txdp
= (struct vxge_hw_fifo_txd
*)txdlh
;
1692 return (void *)(size_t)txdp
->host_control
;
1696 * struct vxge_hw_ring_attr - Ring open "template".
1697 * @callback: Ring completion callback. HW invokes the callback when there
1698 * are new completions on that ring. In many implementations
1699 * the @callback executes in the hw interrupt context.
1700 * @rxd_init: Ring's descriptor-initialize callback.
1701 * See vxge_hw_ring_rxd_init_f{}.
1702 * If not NULL, HW invokes the callback when opening
1704 * @rxd_term: Ring's descriptor-terminate callback. If not NULL,
1705 * HW invokes the callback when closing the corresponding ring.
1706 * See also vxge_hw_ring_rxd_term_f{}.
1707 * @userdata: User-defined "context" of _that_ ring. Passed back to the
1708 * user as one of the @callback, @rxd_init, and @rxd_term arguments.
1709 * @per_rxd_space: If specified (i.e., greater than zero): extra space
1710 * reserved by HW per each receive descriptor.
1711 * Can be used to store
1712 * and retrieve on completion, information specific
1715 * Ring open "template". User fills the structure with ring
1716 * attributes and passes it to vxge_hw_vpath_open().
1718 struct vxge_hw_ring_attr
{
1719 enum vxge_hw_status (*callback
)(
1720 struct __vxge_hw_ring
*ringh
,
1725 enum vxge_hw_status (*rxd_init
)(
1731 enum vxge_hw_rxd_state state
,
1739 * function vxge_hw_fifo_callback_f - FIFO callback.
1740 * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed
1742 * @txdlh: First completed descriptor.
1743 * @txdl_priv: Pointer to per txdl space allocated
1744 * @t_code: Transfer code, as per Titan User Guide.
1746 * @host_control: Opaque 64bit data stored by driver inside the Titan
1747 * descriptor prior to posting the latter on the fifo
1748 * via vxge_hw_fifo_txdl_post(). The @host_control is returned
1749 * as is to the driver with each completed descriptor.
1750 * @userdata: Opaque per-fifo data specified at fifo open
1751 * time, via vxge_hw_vpath_open().
1753 * Fifo completion callback (type declaration). A single per-fifo
1754 * callback is specified at fifo open time, via
1755 * vxge_hw_vpath_open(). Typically gets called as part of the processing
1756 * of the Interrupt Service Routine.
1758 * Fifo callback gets called by HW if, and only if, there is at least
1759 * one new completion on a given fifo. Upon processing the first @txdlh driver
1760 * is _supposed_ to continue consuming completions using:
1761 * - vxge_hw_fifo_txdl_next_completed()
1763 * Note that failure to process new completions in a timely fashion
1764 * leads to VXGE_HW_INF_OUT_OF_DESCRIPTORS condition.
1766 * Non-zero @t_code means failure to process transmit descriptor.
1768 * In the "transmit" case the failure could happen, for instance, when the
1769 * link is down, in which case Titan completes the descriptor because it
1770 * is not able to send the data out.
1772 * For details please refer to Titan User Guide.
1774 * See also: vxge_hw_fifo_txdl_next_completed(), vxge_hw_fifo_txdl_term_f{}.
1777 * function vxge_hw_fifo_txdl_term_f - Terminate descriptor callback.
1778 * @txdlh: First completed descriptor.
1779 * @txdl_priv: Pointer to per txdl space allocated
1780 * @state: One of the enum vxge_hw_txdl_state{} enumerated states.
1781 * @userdata: Per-fifo user data (a.k.a. context) specified at
1782 * fifo open time, via vxge_hw_vpath_open().
1784 * Terminate descriptor callback. Unless NULL is specified in the
1785 * struct vxge_hw_fifo_attr{} structure passed to vxge_hw_vpath_open()),
1786 * HW invokes the callback as part of closing fifo, prior to
1787 * de-allocating the ring and associated data structures
1788 * (including descriptors).
1789 * driver should utilize the callback to (for instance) unmap
1790 * and free DMA data buffers associated with the posted (state =
1791 * VXGE_HW_TXDL_STATE_POSTED) descriptors,
1792 * as well as other relevant cleanup functions.
1794 * See also: struct vxge_hw_fifo_attr{}
1797 * struct vxge_hw_fifo_attr - Fifo open "template".
1798 * @callback: Fifo completion callback. HW invokes the callback when there
1799 * are new completions on that fifo. In many implementations
1800 * the @callback executes in the hw interrupt context.
1801 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
1802 * HW invokes the callback when closing the corresponding fifo.
1803 * See also vxge_hw_fifo_txdl_term_f{}.
1804 * @userdata: User-defined "context" of _that_ fifo. Passed back to the
1805 * user as one of the @callback, and @txdl_term arguments.
1806 * @per_txdl_space: If specified (i.e., greater than zero): extra space
1807 * reserved by HW per each transmit descriptor. Can be used to
1808 * store, and retrieve on completion, information specific
1811 * Fifo open "template". User fills the structure with fifo
1812 * attributes and passes it to vxge_hw_vpath_open().
1814 struct vxge_hw_fifo_attr
{
1816 enum vxge_hw_status (*callback
)(
1817 struct __vxge_hw_fifo
*fifo_handle
,
1819 enum vxge_hw_fifo_tcode t_code
,
1821 struct sk_buff
***skb_ptr
,
1822 int nr_skb
, int *more
);
1826 enum vxge_hw_txdl_state state
,
1834 * struct vxge_hw_vpath_attr - Attributes of virtual path
1835 * @vp_id: Identifier of Virtual Path
1836 * @ring_attr: Attributes of ring for non-offload receive
1837 * @fifo_attr: Attributes of fifo for non-offload transmit
1839 * Attributes of virtual path. This structure is passed as parameter
1840 * to the vxge_hw_vpath_open() routine to set the attributes of ring and fifo.
1842 struct vxge_hw_vpath_attr
{
1844 struct vxge_hw_ring_attr ring_attr
;
1845 struct vxge_hw_fifo_attr fifo_attr
;
1848 enum vxge_hw_status __devinit
vxge_hw_device_hw_info_get(
1850 struct vxge_hw_device_hw_info
*hw_info
);
1852 enum vxge_hw_status __devinit
vxge_hw_device_config_default_get(
1853 struct vxge_hw_device_config
*device_config
);
1856 * vxge_hw_device_link_state_get - Get link state.
1857 * @devh: HW device handle.
1860 * Returns: link state.
1863 enum vxge_hw_device_link_state
vxge_hw_device_link_state_get(
1864 struct __vxge_hw_device
*devh
)
1866 return devh
->link_state
;
1869 void vxge_hw_device_terminate(struct __vxge_hw_device
*devh
);
1872 vxge_hw_device_serial_number_get(struct __vxge_hw_device
*devh
);
1874 u16
vxge_hw_device_link_width_get(struct __vxge_hw_device
*devh
);
1877 vxge_hw_device_product_name_get(struct __vxge_hw_device
*devh
);
1879 enum vxge_hw_status __devinit
vxge_hw_device_initialize(
1880 struct __vxge_hw_device
**devh
,
1881 struct vxge_hw_device_attr
*attr
,
1882 struct vxge_hw_device_config
*device_config
);
1884 enum vxge_hw_status
vxge_hw_device_getpause_data(
1885 struct __vxge_hw_device
*devh
,
1890 enum vxge_hw_status
vxge_hw_device_setpause_data(
1891 struct __vxge_hw_device
*devh
,
1896 static inline void *vxge_os_dma_malloc(struct pci_dev
*pdev
,
1898 struct pci_dev
**p_dmah
,
1899 struct pci_dev
**p_dma_acch
)
1903 unsigned long misaligned
= 0;
1904 int realloc_flag
= 0;
1905 *p_dma_acch
= *p_dmah
= NULL
;
1908 flags
= GFP_ATOMIC
| GFP_DMA
;
1910 flags
= GFP_KERNEL
| GFP_DMA
;
1912 vaddr
= kmalloc((size
), flags
);
1915 misaligned
= (unsigned long)VXGE_ALIGN((unsigned long)vaddr
,
1916 VXGE_CACHE_LINE_SIZE
);
1921 /* misaligned, free current one and try allocating
1922 * size + VXGE_CACHE_LINE_SIZE memory
1924 kfree((void *) vaddr
);
1925 size
+= VXGE_CACHE_LINE_SIZE
;
1930 *(unsigned long *)p_dma_acch
= misaligned
;
1931 vaddr
= (void *)((u8
*)vaddr
+ misaligned
);
1935 static inline void vxge_os_dma_free(struct pci_dev
*pdev
, const void *vaddr
,
1936 struct pci_dev
**p_dma_acch
)
1938 unsigned long misaligned
= *(unsigned long *)p_dma_acch
;
1939 u8
*tmp
= (u8
*)vaddr
;
1945 * __vxge_hw_mempool_item_priv - will return pointer on per item private space
1948 __vxge_hw_mempool_item_priv(
1949 struct vxge_hw_mempool
*mempool
,
1952 u32
*memblock_item_idx
)
1955 void *memblock
= mempool
->memblocks_arr
[memblock_idx
];
1958 offset
= (u32
)((u8
*)item
- (u8
*)memblock
);
1959 vxge_assert(offset
>= 0 && (u32
)offset
< mempool
->memblock_size
);
1961 (*memblock_item_idx
) = (u32
) offset
/ mempool
->item_size
;
1962 vxge_assert((*memblock_item_idx
) < mempool
->items_per_memblock
);
1964 return (u8
*)mempool
->memblocks_priv_arr
[memblock_idx
] +
1965 (*memblock_item_idx
) * mempool
->items_priv_size
;
1969 * __vxge_hw_fifo_txdl_priv - Return the max fragments allocated
1972 * @txdp: Poniter to a TxD
1974 static inline struct __vxge_hw_fifo_txdl_priv
*
1975 __vxge_hw_fifo_txdl_priv(
1976 struct __vxge_hw_fifo
*fifo
,
1977 struct vxge_hw_fifo_txd
*txdp
)
1979 return (struct __vxge_hw_fifo_txdl_priv
*)
1980 (((char *)((ulong
)txdp
->host_control
)) +
1981 fifo
->per_txdl_space
);
1984 enum vxge_hw_status
vxge_hw_vpath_open(
1985 struct __vxge_hw_device
*devh
,
1986 struct vxge_hw_vpath_attr
*attr
,
1987 struct __vxge_hw_vpath_handle
**vpath_handle
);
1989 enum vxge_hw_status
vxge_hw_vpath_close(
1990 struct __vxge_hw_vpath_handle
*vpath_handle
);
1993 vxge_hw_vpath_reset(
1994 struct __vxge_hw_vpath_handle
*vpath_handle
);
1997 vxge_hw_vpath_recover_from_reset(
1998 struct __vxge_hw_vpath_handle
*vpath_handle
);
2001 vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle
*vp
);
2004 vxge_hw_vpath_check_leak(struct __vxge_hw_ring
*ringh
);
2006 enum vxge_hw_status
vxge_hw_vpath_mtu_set(
2007 struct __vxge_hw_vpath_handle
*vpath_handle
,
2011 vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle
*vp
);
2014 static inline u64
readq(void __iomem
*addr
)
2017 ret
= readl(addr
+ 4);
2026 static inline void writeq(u64 val
, void __iomem
*addr
)
2028 writel((u32
) (val
), addr
);
2029 writel((u32
) (val
>> 32), (addr
+ 4));
2033 static inline void __vxge_hw_pio_mem_write32_upper(u32 val
, void __iomem
*addr
)
2035 writel(val
, addr
+ 4);
2038 static inline void __vxge_hw_pio_mem_write32_lower(u32 val
, void __iomem
*addr
)
2044 vxge_hw_device_flick_link_led(struct __vxge_hw_device
*devh
, u64 on_off
);
2047 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device
*hldev
, u64 vpath_mask
);
2051 * @level: level of debug verbosity.
2052 * @mask: mask for the debug
2053 * @buf: Circular buffer for tracing
2054 * @fmt: printf like format string
2056 * Provides logging facilities. Can be customized on per-module
2057 * basis or/and with debug levels. Input parameters, except
2058 * module and level, are the same as posix printf. This function
2059 * may be compiled out if DEBUG macro was never defined.
2060 * See also: enum vxge_debug_level{}.
2062 #if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
2063 #define vxge_debug_ll(level, mask, fmt, ...) do { \
2064 if ((level >= VXGE_ERR && VXGE_COMPONENT_LL & VXGE_DEBUG_ERR_MASK) || \
2065 (level >= VXGE_TRACE && VXGE_COMPONENT_LL & VXGE_DEBUG_TRACE_MASK))\
2066 if ((mask & VXGE_DEBUG_MASK) == mask) \
2067 printk(fmt "\n", __VA_ARGS__); \
2070 #define vxge_debug_ll(level, mask, fmt, ...)
2073 enum vxge_hw_status
vxge_hw_vpath_rts_rth_itable_set(
2074 struct __vxge_hw_vpath_handle
**vpath_handles
,
2080 enum vxge_hw_status
vxge_hw_vpath_rts_rth_set(
2081 struct __vxge_hw_vpath_handle
*vpath_handle
,
2082 enum vxge_hw_rth_algoritms algorithm
,
2083 struct vxge_hw_rth_hash_types
*hash_type
,
2087 __vxge_hw_device_is_privilaged(u32 host_type
, u32 func_id
);
2089 #define VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT 5
2090 #define VXGE_HW_MAX_POLLING_COUNT 100
2093 vxge_hw_device_wait_receive_idle(struct __vxge_hw_device
*hldev
);
2096 vxge_hw_upgrade_read_version(struct __vxge_hw_device
*hldev
, u32
*major
,
2097 u32
*minor
, u32
*build
);
2099 enum vxge_hw_status
vxge_hw_flash_fw(struct __vxge_hw_device
*hldev
);
2102 vxge_update_fw_image(struct __vxge_hw_device
*hldev
, const u8
*filebuf
,
2106 vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device
*hldev
,
2107 struct eprom_image
*eprom_image_data
);
2109 int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device
*hldev
, u32 vp_id
);