2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/version.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/types.h>
30 #include <linux/errno.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/list.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
43 #include <linux/ipv6.h>
44 #include <linux/udp.h>
45 #include <linux/mii.h>
47 #include <linux/vmalloc.h>
48 #include <linux/pagemap.h>
49 #include <linux/tcp.h>
50 #include <linux/ethtool.h>
51 #include <linux/if_vlan.h>
52 #include <linux/workqueue.h>
53 #include <net/checksum.h>
54 #include <net/ip6_checksum.h>
58 #define PCI_REG_COMMAND 0x04 /* PCI Command Register */
59 #define CMD_IO_SPACE 0x0001
60 #define CMD_MEMORY_SPACE 0x0002
61 #define CMD_BUS_MASTER 0x0004
67 /* Wake Up Filter Control */
68 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
69 #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
70 #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
71 #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
72 #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
74 #define SPEED_0 0xffff
79 #define AT_ERR_EEPROM 1
81 #define AT_ERR_CONFIG 3
82 #define AT_ERR_PARAM 4
83 #define AT_ERR_MAC_TYPE 5
84 #define AT_ERR_PHY_TYPE 6
85 #define AT_ERR_PHY_SPEED 7
86 #define AT_ERR_PHY_RES 8
87 #define AT_ERR_TIMEOUT 9
89 #define MAX_JUMBO_FRAME_SIZE 0x2000
91 #define AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd) \
92 _tpd = (((_vlan) << (4)) | (((_vlan) >> 13) & 7) |\
95 #define AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan) \
96 _vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\
97 (((_tdp) & 0x88) << 5))
99 #define AT_MAX_RECEIVE_QUEUE 4
100 #define AT_PAGE_NUM_PER_QUEUE 2
102 #define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
103 #define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
105 #define AT_TX_WATCHDOG (5 * HZ)
106 #define AT_MAX_INT_WORK 10
107 #define AT_TWSI_EEPROM_TIMEOUT 100
108 #define AT_HW_MAX_IDLE_DELAY 10
109 #define AT_SUSPEND_LINK_TIMEOUT 28
111 #define AT_REGS_LEN 75
112 #define AT_EEPROM_LEN 512
113 #define AT_ADV_MASK (ADVERTISE_10_HALF |\
115 ADVERTISE_100_HALF |\
116 ADVERTISE_100_FULL |\
120 #define TPD_BUFLEN_MASK 0x3FFF
121 #define TPD_BUFLEN_SHIFT 0
122 #define TPD_DMAINT_MASK 0x0001
123 #define TPD_DMAINT_SHIFT 14
124 #define TPD_PKTNT_MASK 0x0001
125 #define TPD_PKTINT_SHIFT 15
126 #define TPD_VLANTAG_MASK 0xFFFF
127 #define TPD_VLAN_SHIFT 16
129 /* tpd word 3 bits 0:4 */
130 #define TPD_EOP_MASK 0x0001
131 #define TPD_EOP_SHIFT 0
132 #define TPD_IP_VERSION_MASK 0x0001
133 #define TPD_IP_VERSION_SHIFT 1 /* 0 : IPV4, 1 : IPV6 */
134 #define TPD_INS_VL_TAG_MASK 0x0001
135 #define TPD_INS_VL_TAG_SHIFT 2
136 #define TPD_CC_SEGMENT_EN_MASK 0x0001
137 #define TPD_CC_SEGMENT_EN_SHIFT 3
138 #define TPD_SEGMENT_EN_MASK 0x0001
139 #define TPD_SEGMENT_EN_SHIFT 4
141 /* tdp word 3 bits 5:7 if ip version is 0 */
142 #define TPD_IP_CSUM_MASK 0x0001
143 #define TPD_IP_CSUM_SHIFT 5
144 #define TPD_TCP_CSUM_MASK 0x0001
145 #define TPD_TCP_CSUM_SHIFT 6
146 #define TPD_UDP_CSUM_MASK 0x0001
147 #define TPD_UDP_CSUM_SHIFT 7
149 /* tdp word 3 bits 5:7 if ip version is 1 */
150 #define TPD_V6_IPHLLO_MASK 0x0007
151 #define TPD_V6_IPHLLO_SHIFT 7
153 /* tpd word 3 bits 8:9 bit */
154 #define TPD_VL_TAGGED_MASK 0x0001
155 #define TPD_VL_TAGGED_SHIFT 8
156 #define TPD_ETHTYPE_MASK 0x0001
157 #define TPD_ETHTYPE_SHIFT 9
159 /* tdp word 3 bits 10:13 if ip version is 0 */
160 #define TDP_V4_IPHL_MASK 0x000F
161 #define TPD_V4_IPHL_SHIFT 10
163 /* tdp word 3 bits 10:13 if ip version is 1 */
164 #define TPD_V6_IPHLHI_MASK 0x000F
165 #define TPD_V6_IPHLHI_SHIFT 10
167 /* tpd word 3 bit 14:31 if segment enabled */
168 #define TPD_TCPHDRLEN_MASK 0x000F
169 #define TPD_TCPHDRLEN_SHIFT 14
170 #define TPD_HDRFLAG_MASK 0x0001
171 #define TPD_HDRFLAG_SHIFT 18
172 #define TPD_MSS_MASK 0x1FFF
173 #define TPD_MSS_SHIFT 19
175 /* tdp word 3 bit 16:31 if custom csum enabled */
176 #define TPD_PLOADOFFSET_MASK 0x00FF
177 #define TPD_PLOADOFFSET_SHIFT 16
178 #define TPD_CCSUMOFFSET_MASK 0x00FF
179 #define TPD_CCSUMOFFSET_SHIFT 24
181 struct atl1e_tpd_desc
{
187 /* how about 0x2000 */
188 #define MAX_TX_BUF_LEN 0x2000
189 #define MAX_TX_BUF_SHIFT 13
190 /*#define MAX_TX_BUF_LEN 0x3000 */
192 /* rrs word 1 bit 0:31 */
193 #define RRS_RX_CSUM_MASK 0xFFFF
194 #define RRS_RX_CSUM_SHIFT 0
195 #define RRS_PKT_SIZE_MASK 0x3FFF
196 #define RRS_PKT_SIZE_SHIFT 16
197 #define RRS_CPU_NUM_MASK 0x0003
198 #define RRS_CPU_NUM_SHIFT 30
200 #define RRS_IS_RSS_IPV4 0x0001
201 #define RRS_IS_RSS_IPV4_TCP 0x0002
202 #define RRS_IS_RSS_IPV6 0x0004
203 #define RRS_IS_RSS_IPV6_TCP 0x0008
204 #define RRS_IS_IPV6 0x0010
205 #define RRS_IS_IP_FRAG 0x0020
206 #define RRS_IS_IP_DF 0x0040
207 #define RRS_IS_802_3 0x0080
208 #define RRS_IS_VLAN_TAG 0x0100
209 #define RRS_IS_ERR_FRAME 0x0200
210 #define RRS_IS_IPV4 0x0400
211 #define RRS_IS_UDP 0x0800
212 #define RRS_IS_TCP 0x1000
213 #define RRS_IS_BCAST 0x2000
214 #define RRS_IS_MCAST 0x4000
215 #define RRS_IS_PAUSE 0x8000
217 #define RRS_ERR_BAD_CRC 0x0001
218 #define RRS_ERR_CODE 0x0002
219 #define RRS_ERR_DRIBBLE 0x0004
220 #define RRS_ERR_RUNT 0x0008
221 #define RRS_ERR_RX_OVERFLOW 0x0010
222 #define RRS_ERR_TRUNC 0x0020
223 #define RRS_ERR_IP_CSUM 0x0040
224 #define RRS_ERR_L4_CSUM 0x0080
225 #define RRS_ERR_LENGTH 0x0100
226 #define RRS_ERR_DES_ADDR 0x0200
228 struct atl1e_recv_ret_status
{
238 enum atl1e_dma_req_block
{
239 atl1e_dma_req_128
= 0,
240 atl1e_dma_req_256
= 1,
241 atl1e_dma_req_512
= 2,
242 atl1e_dma_req_1024
= 3,
243 atl1e_dma_req_2048
= 4,
244 atl1e_dma_req_4096
= 5
247 enum atl1e_rrs_type
{
248 atl1e_rrs_disable
= 0,
250 atl1e_rrs_ipv4_tcp
= 2,
252 atl1e_rrs_ipv6_tcp
= 8
255 enum atl1e_nic_type
{
261 struct atl1e_hw_stats
{
263 unsigned long rx_ok
; /* The number of good packet received. */
264 unsigned long rx_bcast
; /* The number of good broadcast packet received. */
265 unsigned long rx_mcast
; /* The number of good multicast packet received. */
266 unsigned long rx_pause
; /* The number of Pause packet received. */
267 unsigned long rx_ctrl
; /* The number of Control packet received other than Pause frame. */
268 unsigned long rx_fcs_err
; /* The number of packets with bad FCS. */
269 unsigned long rx_len_err
; /* The number of packets with mismatch of length field and actual size. */
270 unsigned long rx_byte_cnt
; /* The number of bytes of good packet received. FCS is NOT included. */
271 unsigned long rx_runt
; /* The number of packets received that are less than 64 byte long and with good FCS. */
272 unsigned long rx_frag
; /* The number of packets received that are less than 64 byte long and with bad FCS. */
273 unsigned long rx_sz_64
; /* The number of good and bad packets received that are 64 byte long. */
274 unsigned long rx_sz_65_127
; /* The number of good and bad packets received that are between 65 and 127-byte long. */
275 unsigned long rx_sz_128_255
; /* The number of good and bad packets received that are between 128 and 255-byte long. */
276 unsigned long rx_sz_256_511
; /* The number of good and bad packets received that are between 256 and 511-byte long. */
277 unsigned long rx_sz_512_1023
; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
278 unsigned long rx_sz_1024_1518
; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
279 unsigned long rx_sz_1519_max
; /* The number of good and bad packets received that are between 1519-byte and MTU. */
280 unsigned long rx_sz_ov
; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
281 unsigned long rx_rxf_ov
; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
282 unsigned long rx_rrd_ov
; /* The number of frame dropped due to occurrence of RRD overflow. */
283 unsigned long rx_align_err
; /* Alignment Error */
284 unsigned long rx_bcast_byte_cnt
; /* The byte count of broadcast packet received, excluding FCS. */
285 unsigned long rx_mcast_byte_cnt
; /* The byte count of multicast packet received, excluding FCS. */
286 unsigned long rx_err_addr
; /* The number of packets dropped due to address filtering. */
289 unsigned long tx_ok
; /* The number of good packet transmitted. */
290 unsigned long tx_bcast
; /* The number of good broadcast packet transmitted. */
291 unsigned long tx_mcast
; /* The number of good multicast packet transmitted. */
292 unsigned long tx_pause
; /* The number of Pause packet transmitted. */
293 unsigned long tx_exc_defer
; /* The number of packets transmitted with excessive deferral. */
294 unsigned long tx_ctrl
; /* The number of packets transmitted is a control frame, excluding Pause frame. */
295 unsigned long tx_defer
; /* The number of packets transmitted that is deferred. */
296 unsigned long tx_byte_cnt
; /* The number of bytes of data transmitted. FCS is NOT included. */
297 unsigned long tx_sz_64
; /* The number of good and bad packets transmitted that are 64 byte long. */
298 unsigned long tx_sz_65_127
; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
299 unsigned long tx_sz_128_255
; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
300 unsigned long tx_sz_256_511
; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
301 unsigned long tx_sz_512_1023
; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
302 unsigned long tx_sz_1024_1518
; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
303 unsigned long tx_sz_1519_max
; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
304 unsigned long tx_1_col
; /* The number of packets subsequently transmitted successfully with a single prior collision. */
305 unsigned long tx_2_col
; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
306 unsigned long tx_late_col
; /* The number of packets transmitted with late collisions. */
307 unsigned long tx_abort_col
; /* The number of transmit packets aborted due to excessive collisions. */
308 unsigned long tx_underrun
; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
309 unsigned long tx_rd_eop
; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
310 unsigned long tx_len_err
; /* The number of transmit packets with length field does NOT match the actual frame size. */
311 unsigned long tx_trunc
; /* The number of transmit packets truncated due to size exceeding MTU. */
312 unsigned long tx_bcast_byte
; /* The byte count of broadcast packet transmitted, excluding FCS. */
313 unsigned long tx_mcast_byte
; /* The byte count of multicast packet transmitted, excluding FCS. */
317 u8 __iomem
*hw_addr
; /* inner register address */
318 resource_size_t mem_rang
;
319 struct atl1e_adapter
*adapter
;
320 enum atl1e_nic_type nic_type
;
324 u16 subsystem_vendor_id
;
327 u8 mac_addr
[ETH_ALEN
];
328 u8 perm_mac_addr
[ETH_ALEN
];
335 #define MEDIA_TYPE_AUTO_SENSOR 0
336 #define MEDIA_TYPE_100M_FULL 1
337 #define MEDIA_TYPE_100M_HALF 2
338 #define MEDIA_TYPE_10M_FULL 3
339 #define MEDIA_TYPE_10M_HALF 4
341 u16 autoneg_advertised
;
342 #define ADVERTISE_10_HALF 0x0001
343 #define ADVERTISE_10_FULL 0x0002
344 #define ADVERTISE_100_HALF 0x0004
345 #define ADVERTISE_100_FULL 0x0008
346 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
347 #define ADVERTISE_1000_FULL 0x0020
348 u16 mii_autoneg_adv_reg
;
349 u16 mii_1000t_ctrl_reg
;
351 u16 imt
; /* Interrupt Moderator timer ( 2us resolution) */
352 u16 ict
; /* Interrupt Clear timer (2us resolution) */
354 u16 rrd_thresh
; /* Threshold of number of RRD produced to trigger
357 u16 rx_count_down
; /* 2us resolution */
360 u8 tpd_burst
; /* Number of TPD to prefetch in cache-aligned burst. */
361 enum atl1e_rrs_type rrs_type
;
365 enum atl1e_dma_req_block dmar_block
;
366 enum atl1e_dma_req_block dmaw_block
;
376 * wrapper around a pointer to a socket buffer,
377 * so a DMA handle can be stored along with the buffer
379 struct atl1e_tx_buffer
{
382 #define ATL1E_TX_PCIMAP_SINGLE 0x0001
383 #define ATL1E_TX_PCIMAP_PAGE 0x0002
384 #define ATL1E_TX_PCIMAP_TYPE_MASK 0x0003
389 #define ATL1E_SET_PCIMAP_TYPE(tx_buff, type) do { \
390 ((tx_buff)->flags) &= ~ATL1E_TX_PCIMAP_TYPE_MASK; \
391 ((tx_buff)->flags) |= (type); \
394 struct atl1e_rx_page
{
395 dma_addr_t dma
; /* receive rage DMA address */
396 u8
*addr
; /* receive rage virtual address */
397 dma_addr_t write_offset_dma
; /* the DMA address which contain the
398 receive data offset in the page */
399 u32
*write_offset_addr
; /* the virtaul address which contain
400 the receive data offset in the page */
401 u32 read_offset
; /* the offset where we have read */
404 struct atl1e_rx_page_desc
{
405 struct atl1e_rx_page rx_page
[AT_PAGE_NUM_PER_QUEUE
];
410 /* transmit packet descriptor (tpd) ring */
411 struct atl1e_tx_ring
{
412 struct atl1e_tpd_desc
*desc
; /* descriptor ring virtual address */
413 dma_addr_t dma
; /* descriptor ring physical address */
414 u16 count
; /* the count of transmit rings */
417 atomic_t next_to_clean
;
418 struct atl1e_tx_buffer
*tx_buffer
;
423 /* receive packet descriptor ring */
424 struct atl1e_rx_ring
{
428 u32 page_size
; /* bytes length of rxf page */
429 u32 real_page_size
; /* real_page_size = page_size + jumbo + aliagn */
430 struct atl1e_rx_page_desc rx_page_desc
[AT_MAX_RECEIVE_QUEUE
];
433 /* board specific private data structure */
434 struct atl1e_adapter
{
435 struct net_device
*netdev
;
436 struct pci_dev
*pdev
;
437 struct vlan_group
*vlgrp
;
438 struct napi_struct napi
;
439 struct mii_if_info mii
; /* MII interface info */
441 struct atl1e_hw_stats hw_stats
;
448 spinlock_t mdio_lock
;
452 struct work_struct reset_task
;
453 struct work_struct link_chg_task
;
454 struct timer_list watchdog_timer
;
455 struct timer_list phy_config_timer
;
457 /* All Descriptor memory */
462 struct atl1e_tx_ring tx_ring
;
463 struct atl1e_rx_ring rx_ring
;
466 #define __AT_TESTING 0x0001
467 #define __AT_RESETTING 0x0002
468 #define __AT_DOWN 0x0003
470 u32 bd_number
; /* board number;*/
475 #define AT_WRITE_REG(a, reg, value) ( \
476 writel((value), ((a)->hw_addr + reg)))
478 #define AT_WRITE_FLUSH(a) (\
481 #define AT_READ_REG(a, reg) ( \
482 readl((a)->hw_addr + reg))
484 #define AT_WRITE_REGB(a, reg, value) (\
485 writeb((value), ((a)->hw_addr + reg)))
487 #define AT_READ_REGB(a, reg) (\
488 readb((a)->hw_addr + reg))
490 #define AT_WRITE_REGW(a, reg, value) (\
491 writew((value), ((a)->hw_addr + reg)))
493 #define AT_READ_REGW(a, reg) (\
494 readw((a)->hw_addr + reg))
496 #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
497 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
499 #define AT_READ_REG_ARRAY(a, reg, offset) ( \
500 readl(((a)->hw_addr + reg) + ((offset) << 2)))
502 extern char atl1e_driver_name
[];
503 extern char atl1e_driver_version
[];
505 extern void atl1e_check_options(struct atl1e_adapter
*adapter
);
506 extern int atl1e_up(struct atl1e_adapter
*adapter
);
507 extern void atl1e_down(struct atl1e_adapter
*adapter
);
508 extern void atl1e_reinit_locked(struct atl1e_adapter
*adapter
);
509 extern s32
atl1e_reset_hw(struct atl1e_hw
*hw
);
510 extern void atl1e_set_ethtool_ops(struct net_device
*netdev
);
511 #endif /* _ATL1_E_H_ */