drivers/spi/xilinx_spi.c

   1 /*
   2  * xilinx_spi.c
   3  *
   4  * Xilinx SPI controller driver (master mode only)
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *      source@mvista.com
   8  *
   9  * 2002-2007 (c) MontaVista Software, Inc.  This file is licensed under the
  10  * terms of the GNU General Public License version 2.  This program is licensed
  11  * "as is" without any warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17
  18 #include <linux/spi/spi.h>
  19 #include <linux/spi/spi_bitbang.h>
  20 #include <linux/io.h>
  21
  22 #include "xilinx_spi.h"
  23 #include <linux/spi/xilinx_spi.h>
  24
  25 #define XILINX_SPI_NAME "xilinx_spi"
  26
  27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
  28  * Product Specification", DS464
  29  */
  30 #define XSPI_CR_OFFSET          0x60    /* Control Register */
  31
  32 #define XSPI_CR_ENABLE          0x02
  33 #define XSPI_CR_MASTER_MODE     0x04
  34 #define XSPI_CR_CPOL            0x08
  35 #define XSPI_CR_CPHA            0x10
  36 #define XSPI_CR_MODE_MASK       (XSPI_CR_CPHA | XSPI_CR_CPOL)
  37 #define XSPI_CR_TXFIFO_RESET    0x20
  38 #define XSPI_CR_RXFIFO_RESET    0x40
  39 #define XSPI_CR_MANUAL_SSELECT  0x80
  40 #define XSPI_CR_TRANS_INHIBIT   0x100
  41 #define XSPI_CR_LSB_FIRST       0x200
  42
  43 #define XSPI_SR_OFFSET          0x64    /* Status Register */
  44
  45 #define XSPI_SR_RX_EMPTY_MASK   0x01    /* Receive FIFO is empty */
  46 #define XSPI_SR_RX_FULL_MASK    0x02    /* Receive FIFO is full */
  47 #define XSPI_SR_TX_EMPTY_MASK   0x04    /* Transmit FIFO is empty */
  48 #define XSPI_SR_TX_FULL_MASK    0x08    /* Transmit FIFO is full */
  49 #define XSPI_SR_MODE_FAULT_MASK 0x10    /* Mode fault error */
  50
  51 #define XSPI_TXD_OFFSET         0x68    /* Data Transmit Register */
  52 #define XSPI_RXD_OFFSET         0x6c    /* Data Receive Register */
  53
  54 #define XSPI_SSR_OFFSET         0x70    /* 32-bit Slave Select Register */
  55
  56 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
  57  * IPIF registers are 32 bit
  58  */
  59 #define XIPIF_V123B_DGIER_OFFSET        0x1c    /* IPIF global int enable reg */
  60 #define XIPIF_V123B_GINTR_ENABLE        0x80000000
  61
  62 #define XIPIF_V123B_IISR_OFFSET         0x20    /* IPIF interrupt status reg */
  63 #define XIPIF_V123B_IIER_OFFSET         0x28    /* IPIF interrupt enable reg */
  64
  65 #define XSPI_INTR_MODE_FAULT            0x01    /* Mode fault error */
  66 #define XSPI_INTR_SLAVE_MODE_FAULT      0x02    /* Selected as slave while
  67                                                  * disabled */
  68 #define XSPI_INTR_TX_EMPTY              0x04    /* TxFIFO is empty */
  69 #define XSPI_INTR_TX_UNDERRUN           0x08    /* TxFIFO was underrun */
  70 #define XSPI_INTR_RX_FULL               0x10    /* RxFIFO is full */
  71 #define XSPI_INTR_RX_OVERRUN            0x20    /* RxFIFO was overrun */
  72 #define XSPI_INTR_TX_HALF_EMPTY         0x40    /* TxFIFO is half empty */
  73
  74 #define XIPIF_V123B_RESETR_OFFSET       0x40    /* IPIF reset register */
  75 #define XIPIF_V123B_RESET_MASK          0x0a    /* the value to write */
  76
  77 struct xilinx_spi {
  78         /* bitbang has to be first */
  79         struct spi_bitbang bitbang;
  80         struct completion done;
  81         struct resource mem; /* phys mem */
  82         void __iomem    *regs;  /* virt. address of the control registers */
  83
  84         u32             irq;
  85
  86         u8 *rx_ptr;             /* pointer in the Tx buffer */
  87         const u8 *tx_ptr;       /* pointer in the Rx buffer */
  88         int remaining_bytes;    /* the number of bytes left to transfer */
  89         u8 bits_per_word;
  90         unsigned int (*read_fn) (void __iomem *);
  91         void (*write_fn) (u32, void __iomem *);
  92         void (*tx_fn) (struct xilinx_spi *);
  93         void (*rx_fn) (struct xilinx_spi *);
  94 };
  95
  96 static void xspi_write32(u32 val, void __iomem *addr)
  97 {
  98         iowrite32(val, addr);
  99 }
 100
 101 static unsigned int xspi_read32(void __iomem *addr)
 102 {
 103         return ioread32(addr);
 104 }
 105
 106 static void xspi_write32_be(u32 val, void __iomem *addr)
 107 {
 108         iowrite32be(val, addr);
 109 }
 110
 111 static unsigned int xspi_read32_be(void __iomem *addr)
 112 {
 113         return ioread32be(addr);
 114 }
 115
 116 static void xspi_tx8(struct xilinx_spi *xspi)
 117 {
 118         xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
 119         xspi->tx_ptr++;
 120 }
 121
 122 static void xspi_tx16(struct xilinx_spi *xspi)
 123 {
 124         xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
 125         xspi->tx_ptr += 2;
 126 }
 127
 128 static void xspi_tx32(struct xilinx_spi *xspi)
 129 {
 130         xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
 131         xspi->tx_ptr += 4;
 132 }
 133
 134 static void xspi_rx8(struct xilinx_spi *xspi)
 135 {
 136         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
 137         if (xspi->rx_ptr) {
 138                 *xspi->rx_ptr = data & 0xff;
 139                 xspi->rx_ptr++;
 140         }
 141 }
 142
 143 static void xspi_rx16(struct xilinx_spi *xspi)
 144 {
 145         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
 146         if (xspi->rx_ptr) {
 147                 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
 148                 xspi->rx_ptr += 2;
 149         }
 150 }
 151
 152 static void xspi_rx32(struct xilinx_spi *xspi)
 153 {
 154         u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
 155         if (xspi->rx_ptr) {
 156                 *(u32 *)(xspi->rx_ptr) = data;
 157                 xspi->rx_ptr += 4;
 158         }
 159 }
 160
 161 static void xspi_init_hw(struct xilinx_spi *xspi)
 162 {
 163         void __iomem *regs_base = xspi->regs;
 164
 165         /* Reset the SPI device */
 166         xspi->write_fn(XIPIF_V123B_RESET_MASK,
 167                 regs_base + XIPIF_V123B_RESETR_OFFSET);
 168         /* Disable all the interrupts just in case */
 169         xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
 170         /* Enable the global IPIF interrupt */
 171         xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
 172                 regs_base + XIPIF_V123B_DGIER_OFFSET);
 173         /* Deselect the slave on the SPI bus */
 174         xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
 175         /* Disable the transmitter, enable Manual Slave Select Assertion,
 176          * put SPI controller into master mode, and enable it */
 177         xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
 178                 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
 179                 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
 180 }
 181
 182 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
 183 {
 184         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
 185
 186         if (is_on == BITBANG_CS_INACTIVE) {
 187                 /* Deselect the slave on the SPI bus */
 188                 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
 189         } else if (is_on == BITBANG_CS_ACTIVE) {
 190                 /* Set the SPI clock phase and polarity */
 191                 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
 192                          & ~XSPI_CR_MODE_MASK;
 193                 if (spi->mode & SPI_CPHA)
 194                         cr |= XSPI_CR_CPHA;
 195                 if (spi->mode & SPI_CPOL)
 196                         cr |= XSPI_CR_CPOL;
 197                 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
 198
 199                 /* We do not check spi->max_speed_hz here as the SPI clock
 200                  * frequency is not software programmable (the IP block design
 201                  * parameter)
 202                  */
 203
 204                 /* Activate the chip select */
 205                 xspi->write_fn(~(0x0001 << spi->chip_select),
 206                         xspi->regs + XSPI_SSR_OFFSET);
 207         }
 208 }
 209
 210 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
 211  * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
 212  * supports 8 or 16 bits per word which cannot be changed in software.
 213  * SPI clock can't be changed in software either.
 214  * Check for correct bits per word. Chip select delay calculations could be
 215  * added here as soon as bitbang_work() can be made aware of the delay value.
 216  */
 217 static int xilinx_spi_setup_transfer(struct spi_device *spi,
 218                 struct spi_transfer *t)
 219 {
 220         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
 221         u8 bits_per_word;
 222
 223         bits_per_word = (t && t->bits_per_word)
 224                          ? t->bits_per_word : spi->bits_per_word;
 225         if (bits_per_word != xspi->bits_per_word) {
 226                 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 227                         __func__, bits_per_word);
 228                 return -EINVAL;
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int xilinx_spi_setup(struct spi_device *spi)
 235 {
 236         /* always return 0, we can not check the number of bits.
 237          * There are cases when SPI setup is called before any driver is
 238          * there, in that case the SPI core defaults to 8 bits, which we
 239          * do not support in some cases. But if we return an error, the
 240          * SPI device would not be registered and no driver can get hold of it
 241          * When the driver is there, it will call SPI setup again with the
 242          * correct number of bits per transfer.
 243          * If a driver setups with the wrong bit number, it will fail when
 244          * it tries to do a transfer
 245          */
 246         return 0;
 247 }
 248
 249 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
 250 {
 251         u8 sr;
 252
 253         /* Fill the Tx FIFO with as many bytes as possible */
 254         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 255         while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
 256                 if (xspi->tx_ptr)
 257                         xspi->tx_fn(xspi);
 258                 else
 259                         xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
 260                 xspi->remaining_bytes -= xspi->bits_per_word / 8;
 261                 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 262         }
 263 }
 264
 265 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 266 {
 267         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
 268         u32 ipif_ier;
 269         u16 cr;
 270
 271         /* We get here with transmitter inhibited */
 272
 273         xspi->tx_ptr = t->tx_buf;
 274         xspi->rx_ptr = t->rx_buf;
 275         xspi->remaining_bytes = t->len;
 276         INIT_COMPLETION(xspi->done);
 277
 278         xilinx_spi_fill_tx_fifo(xspi);
 279
 280         /* Enable the transmit empty interrupt, which we use to determine
 281          * progress on the transmission.
 282          */
 283         ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
 284         xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
 285                 xspi->regs + XIPIF_V123B_IIER_OFFSET);
 286
 287         /* Start the transfer by not inhibiting the transmitter any longer */
 288         cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
 289                 ~XSPI_CR_TRANS_INHIBIT;
 290         xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
 291
 292         wait_for_completion(&xspi->done);
 293
 294         /* Disable the transmit empty interrupt */
 295         xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
 296
 297         return t->len - xspi->remaining_bytes;
 298 }
 299
 300
 301 /* This driver supports single master mode only. Hence Tx FIFO Empty
 302  * is the only interrupt we care about.
 303  * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
 304  * Fault are not to happen.
 305  */
 306 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
 307 {
 308         struct xilinx_spi *xspi = dev_id;
 309         u32 ipif_isr;
 310
 311         /* Get the IPIF interrupts, and clear them immediately */
 312         ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
 313         xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
 314
 315         if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
 316                 u16 cr;
 317                 u8 sr;
 318
 319                 /* A transmit has just completed. Process received data and
 320                  * check for more data to transmit. Always inhibit the
 321                  * transmitter while the Isr refills the transmit register/FIFO,
 322                  * or make sure it is stopped if we're done.
 323                  */
 324                 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
 325                 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
 326                         xspi->regs + XSPI_CR_OFFSET);
 327
 328                 /* Read out all the data from the Rx FIFO */
 329                 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 330                 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
 331                         xspi->rx_fn(xspi);
 332                         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
 333                 }
 334
 335                 /* See if there is more data to send */
 336                 if (xspi->remaining_bytes > 0) {
 337                         xilinx_spi_fill_tx_fifo(xspi);
 338                         /* Start the transfer by not inhibiting the
 339                          * transmitter any longer
 340                          */
 341                         xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
 342                 } else {
 343                         /* No more data to send.
 344                          * Indicate the transfer is completed.
 345                          */
 346                         complete(&xspi->done);
 347                 }
 348         }
 349
 350         return IRQ_HANDLED;
 351 }
 352
 353 struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
 354         u32 irq, s16 bus_num)
 355 {
 356         struct spi_master *master;
 357         struct xilinx_spi *xspi;
 358         struct xspi_platform_data *pdata = dev->platform_data;
 359         int ret;
 360
 361         if (!pdata) {
 362                 dev_err(dev, "No platform data attached\n");
 363                 return NULL;
 364         }
 365
 366         master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
 367         if (!master)
 368                 return NULL;
 369
 370         /* the spi->mode bits understood by this driver: */
 371         master->mode_bits = SPI_CPOL | SPI_CPHA;
 372
 373         xspi = spi_master_get_devdata(master);
 374         xspi->bitbang.master = spi_master_get(master);
 375         xspi->bitbang.chipselect = xilinx_spi_chipselect;
 376         xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
 377         xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
 378         xspi->bitbang.master->setup = xilinx_spi_setup;
 379         init_completion(&xspi->done);
 380
 381         if (!request_mem_region(mem->start, resource_size(mem),
 382                 XILINX_SPI_NAME))
 383                 goto put_master;
 384
 385         xspi->regs = ioremap(mem->start, resource_size(mem));
 386         if (xspi->regs == NULL) {
 387                 dev_warn(dev, "ioremap failure\n");
 388                 goto map_failed;
 389         }
 390
 391         master->bus_num = bus_num;
 392         master->num_chipselect = pdata->num_chipselect;
 393
 394         xspi->mem = *mem;
 395         xspi->irq = irq;
 396         if (pdata->little_endian) {
 397                 xspi->read_fn = xspi_read32;
 398                 xspi->write_fn = xspi_write32;
 399         } else {
 400                 xspi->read_fn = xspi_read32_be;
 401                 xspi->write_fn = xspi_write32_be;
 402         }
 403         xspi->bits_per_word = pdata->bits_per_word;
 404         if (xspi->bits_per_word == 8) {
 405                 xspi->tx_fn = xspi_tx8;
 406                 xspi->rx_fn = xspi_rx8;
 407         } else if (xspi->bits_per_word == 16) {
 408                 xspi->tx_fn = xspi_tx16;
 409                 xspi->rx_fn = xspi_rx16;
 410         } else if (xspi->bits_per_word == 32) {
 411                 xspi->tx_fn = xspi_tx32;
 412                 xspi->rx_fn = xspi_rx32;
 413         } else
 414                 goto unmap_io;
 415
 416
 417         /* SPI controller initializations */
 418         xspi_init_hw(xspi);
 419
 420         /* Register for SPI Interrupt */
 421         ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
 422         if (ret)
 423                 goto unmap_io;
 424
 425         ret = spi_bitbang_start(&xspi->bitbang);
 426         if (ret) {
 427                 dev_err(dev, "spi_bitbang_start FAILED\n");
 428                 goto free_irq;
 429         }
 430
 431         dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
 432                 (unsigned long long)mem->start, xspi->regs, xspi->irq);
 433         return master;
 434
 435 free_irq:
 436         free_irq(xspi->irq, xspi);
 437 unmap_io:
 438         iounmap(xspi->regs);
 439 map_failed:
 440         release_mem_region(mem->start, resource_size(mem));
 441 put_master:
 442         spi_master_put(master);
 443         return NULL;
 444 }
 445 EXPORT_SYMBOL(xilinx_spi_init);
 446
 447 void xilinx_spi_deinit(struct spi_master *master)
 448 {
 449         struct xilinx_spi *xspi;
 450
 451         xspi = spi_master_get_devdata(master);
 452
 453         spi_bitbang_stop(&xspi->bitbang);
 454         free_irq(xspi->irq, xspi);
 455         iounmap(xspi->regs);
 456
 457         release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
 458         spi_master_put(xspi->bitbang.master);
 459 }
 460 EXPORT_SYMBOL(xilinx_spi_deinit);
 461
 462 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
 463 MODULE_DESCRIPTION("Xilinx SPI driver");
 464 MODULE_LICENSE("GPL");