drm/radeon/kms: fix DP after DPMS cycle
[linux-2.6.git] / drivers / spi / spi_bitbang.c
blob5265330a528fb2a367f164465fefb0b496e25c31
1 /*
2 * spi_bitbang.c - polling/bitbanging SPI master controller driver utilities
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/workqueue.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
32 /*----------------------------------------------------------------------*/
35 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
36 * Use this for GPIO or shift-register level hardware APIs.
38 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
39 * to glue code. These bitbang setup() and cleanup() routines are always
40 * used, though maybe they're called from controller-aware code.
42 * chipselect() and friends may use use spi_device->controller_data and
43 * controller registers as appropriate.
46 * NOTE: SPI controller pins can often be used as GPIO pins instead,
47 * which means you could use a bitbang driver either to get hardware
48 * working quickly, or testing for differences that aren't speed related.
51 struct spi_bitbang_cs {
52 unsigned nsecs; /* (clock cycle time)/2 */
53 u32 (*txrx_word)(struct spi_device *spi, unsigned nsecs,
54 u32 word, u8 bits);
55 unsigned (*txrx_bufs)(struct spi_device *,
56 u32 (*txrx_word)(
57 struct spi_device *spi,
58 unsigned nsecs,
59 u32 word, u8 bits),
60 unsigned, struct spi_transfer *);
63 static unsigned bitbang_txrx_8(
64 struct spi_device *spi,
65 u32 (*txrx_word)(struct spi_device *spi,
66 unsigned nsecs,
67 u32 word, u8 bits),
68 unsigned ns,
69 struct spi_transfer *t
70 ) {
71 unsigned bits = spi->bits_per_word;
72 unsigned count = t->len;
73 const u8 *tx = t->tx_buf;
74 u8 *rx = t->rx_buf;
76 while (likely(count > 0)) {
77 u8 word = 0;
79 if (tx)
80 word = *tx++;
81 word = txrx_word(spi, ns, word, bits);
82 if (rx)
83 *rx++ = word;
84 count -= 1;
86 return t->len - count;
89 static unsigned bitbang_txrx_16(
90 struct spi_device *spi,
91 u32 (*txrx_word)(struct spi_device *spi,
92 unsigned nsecs,
93 u32 word, u8 bits),
94 unsigned ns,
95 struct spi_transfer *t
96 ) {
97 unsigned bits = spi->bits_per_word;
98 unsigned count = t->len;
99 const u16 *tx = t->tx_buf;
100 u16 *rx = t->rx_buf;
102 while (likely(count > 1)) {
103 u16 word = 0;
105 if (tx)
106 word = *tx++;
107 word = txrx_word(spi, ns, word, bits);
108 if (rx)
109 *rx++ = word;
110 count -= 2;
112 return t->len - count;
115 static unsigned bitbang_txrx_32(
116 struct spi_device *spi,
117 u32 (*txrx_word)(struct spi_device *spi,
118 unsigned nsecs,
119 u32 word, u8 bits),
120 unsigned ns,
121 struct spi_transfer *t
123 unsigned bits = spi->bits_per_word;
124 unsigned count = t->len;
125 const u32 *tx = t->tx_buf;
126 u32 *rx = t->rx_buf;
128 while (likely(count > 3)) {
129 u32 word = 0;
131 if (tx)
132 word = *tx++;
133 word = txrx_word(spi, ns, word, bits);
134 if (rx)
135 *rx++ = word;
136 count -= 4;
138 return t->len - count;
141 int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
143 struct spi_bitbang_cs *cs = spi->controller_state;
144 u8 bits_per_word;
145 u32 hz;
147 if (t) {
148 bits_per_word = t->bits_per_word;
149 hz = t->speed_hz;
150 } else {
151 bits_per_word = 0;
152 hz = 0;
155 /* spi_transfer level calls that work per-word */
156 if (!bits_per_word)
157 bits_per_word = spi->bits_per_word;
158 if (bits_per_word <= 8)
159 cs->txrx_bufs = bitbang_txrx_8;
160 else if (bits_per_word <= 16)
161 cs->txrx_bufs = bitbang_txrx_16;
162 else if (bits_per_word <= 32)
163 cs->txrx_bufs = bitbang_txrx_32;
164 else
165 return -EINVAL;
167 /* nsecs = (clock period)/2 */
168 if (!hz)
169 hz = spi->max_speed_hz;
170 if (hz) {
171 cs->nsecs = (1000000000/2) / hz;
172 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
173 return -EINVAL;
176 return 0;
178 EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
181 * spi_bitbang_setup - default setup for per-word I/O loops
183 int spi_bitbang_setup(struct spi_device *spi)
185 struct spi_bitbang_cs *cs = spi->controller_state;
186 struct spi_bitbang *bitbang;
187 int retval;
188 unsigned long flags;
190 bitbang = spi_master_get_devdata(spi->master);
192 if (!cs) {
193 cs = kzalloc(sizeof *cs, GFP_KERNEL);
194 if (!cs)
195 return -ENOMEM;
196 spi->controller_state = cs;
199 /* per-word shift register access, in hardware or bitbanging */
200 cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
201 if (!cs->txrx_word)
202 return -EINVAL;
204 retval = bitbang->setup_transfer(spi, NULL);
205 if (retval < 0)
206 return retval;
208 dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
210 /* NOTE we _need_ to call chipselect() early, ideally with adapter
211 * setup, unless the hardware defaults cooperate to avoid confusion
212 * between normal (active low) and inverted chipselects.
215 /* deselect chip (low or high) */
216 spin_lock_irqsave(&bitbang->lock, flags);
217 if (!bitbang->busy) {
218 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
219 ndelay(cs->nsecs);
221 spin_unlock_irqrestore(&bitbang->lock, flags);
223 return 0;
225 EXPORT_SYMBOL_GPL(spi_bitbang_setup);
228 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
230 void spi_bitbang_cleanup(struct spi_device *spi)
232 kfree(spi->controller_state);
234 EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
236 static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
238 struct spi_bitbang_cs *cs = spi->controller_state;
239 unsigned nsecs = cs->nsecs;
241 return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
244 /*----------------------------------------------------------------------*/
247 * SECOND PART ... simple transfer queue runner.
249 * This costs a task context per controller, running the queue by
250 * performing each transfer in sequence. Smarter hardware can queue
251 * several DMA transfers at once, and process several controller queues
252 * in parallel; this driver doesn't match such hardware very well.
254 * Drivers can provide word-at-a-time i/o primitives, or provide
255 * transfer-at-a-time ones to leverage dma or fifo hardware.
257 static void bitbang_work(struct work_struct *work)
259 struct spi_bitbang *bitbang =
260 container_of(work, struct spi_bitbang, work);
261 unsigned long flags;
262 int do_setup = -1;
263 int (*setup_transfer)(struct spi_device *,
264 struct spi_transfer *);
266 setup_transfer = bitbang->setup_transfer;
268 spin_lock_irqsave(&bitbang->lock, flags);
269 bitbang->busy = 1;
270 while (!list_empty(&bitbang->queue)) {
271 struct spi_message *m;
272 struct spi_device *spi;
273 unsigned nsecs;
274 struct spi_transfer *t = NULL;
275 unsigned tmp;
276 unsigned cs_change;
277 int status;
279 m = container_of(bitbang->queue.next, struct spi_message,
280 queue);
281 list_del_init(&m->queue);
282 spin_unlock_irqrestore(&bitbang->lock, flags);
284 /* FIXME this is made-up ... the correct value is known to
285 * word-at-a-time bitbang code, and presumably chipselect()
286 * should enforce these requirements too?
288 nsecs = 100;
290 spi = m->spi;
291 tmp = 0;
292 cs_change = 1;
293 status = 0;
295 list_for_each_entry (t, &m->transfers, transfer_list) {
297 /* override speed or wordsize? */
298 if (t->speed_hz || t->bits_per_word)
299 do_setup = 1;
301 /* init (-1) or override (1) transfer params */
302 if (do_setup != 0) {
303 if (!setup_transfer) {
304 status = -ENOPROTOOPT;
305 break;
307 status = setup_transfer(spi, t);
308 if (status < 0)
309 break;
312 /* set up default clock polarity, and activate chip;
313 * this implicitly updates clock and spi modes as
314 * previously recorded for this device via setup().
315 * (and also deselects any other chip that might be
316 * selected ...)
318 if (cs_change) {
319 bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
320 ndelay(nsecs);
322 cs_change = t->cs_change;
323 if (!t->tx_buf && !t->rx_buf && t->len) {
324 status = -EINVAL;
325 break;
328 /* transfer data. the lower level code handles any
329 * new dma mappings it needs. our caller always gave
330 * us dma-safe buffers.
332 if (t->len) {
333 /* REVISIT dma API still needs a designated
334 * DMA_ADDR_INVALID; ~0 might be better.
336 if (!m->is_dma_mapped)
337 t->rx_dma = t->tx_dma = 0;
338 status = bitbang->txrx_bufs(spi, t);
340 if (status > 0)
341 m->actual_length += status;
342 if (status != t->len) {
343 /* always report some kind of error */
344 if (status >= 0)
345 status = -EREMOTEIO;
346 break;
348 status = 0;
350 /* protocol tweaks before next transfer */
351 if (t->delay_usecs)
352 udelay(t->delay_usecs);
354 if (!cs_change)
355 continue;
356 if (t->transfer_list.next == &m->transfers)
357 break;
359 /* sometimes a short mid-message deselect of the chip
360 * may be needed to terminate a mode or command
362 ndelay(nsecs);
363 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
364 ndelay(nsecs);
367 m->status = status;
368 m->complete(m->context);
370 /* restore speed and wordsize if it was overridden */
371 if (do_setup == 1)
372 setup_transfer(spi, NULL);
373 do_setup = 0;
375 /* normally deactivate chipselect ... unless no error and
376 * cs_change has hinted that the next message will probably
377 * be for this chip too.
379 if (!(status == 0 && cs_change)) {
380 ndelay(nsecs);
381 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
382 ndelay(nsecs);
385 spin_lock_irqsave(&bitbang->lock, flags);
387 bitbang->busy = 0;
388 spin_unlock_irqrestore(&bitbang->lock, flags);
392 * spi_bitbang_transfer - default submit to transfer queue
394 int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
396 struct spi_bitbang *bitbang;
397 unsigned long flags;
398 int status = 0;
400 m->actual_length = 0;
401 m->status = -EINPROGRESS;
403 bitbang = spi_master_get_devdata(spi->master);
405 spin_lock_irqsave(&bitbang->lock, flags);
406 if (!spi->max_speed_hz)
407 status = -ENETDOWN;
408 else {
409 list_add_tail(&m->queue, &bitbang->queue);
410 queue_work(bitbang->workqueue, &bitbang->work);
412 spin_unlock_irqrestore(&bitbang->lock, flags);
414 return status;
416 EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
418 /*----------------------------------------------------------------------*/
421 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
422 * @bitbang: driver handle
424 * Caller should have zero-initialized all parts of the structure, and then
425 * provided callbacks for chip selection and I/O loops. If the master has
426 * a transfer method, its final step should call spi_bitbang_transfer; or,
427 * that's the default if the transfer routine is not initialized. It should
428 * also set up the bus number and number of chipselects.
430 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
431 * hardware that basically exposes a shift register) or per-spi_transfer
432 * (which takes better advantage of hardware like fifos or DMA engines).
434 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
435 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
436 * master methods. Those methods are the defaults if the bitbang->txrx_bufs
437 * routine isn't initialized.
439 * This routine registers the spi_master, which will process requests in a
440 * dedicated task, keeping IRQs unblocked most of the time. To stop
441 * processing those requests, call spi_bitbang_stop().
443 int spi_bitbang_start(struct spi_bitbang *bitbang)
445 int status;
447 if (!bitbang->master || !bitbang->chipselect)
448 return -EINVAL;
450 INIT_WORK(&bitbang->work, bitbang_work);
451 spin_lock_init(&bitbang->lock);
452 INIT_LIST_HEAD(&bitbang->queue);
454 if (!bitbang->master->mode_bits)
455 bitbang->master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;
457 if (!bitbang->master->transfer)
458 bitbang->master->transfer = spi_bitbang_transfer;
459 if (!bitbang->txrx_bufs) {
460 bitbang->use_dma = 0;
461 bitbang->txrx_bufs = spi_bitbang_bufs;
462 if (!bitbang->master->setup) {
463 if (!bitbang->setup_transfer)
464 bitbang->setup_transfer =
465 spi_bitbang_setup_transfer;
466 bitbang->master->setup = spi_bitbang_setup;
467 bitbang->master->cleanup = spi_bitbang_cleanup;
469 } else if (!bitbang->master->setup)
470 return -EINVAL;
472 /* this task is the only thing to touch the SPI bits */
473 bitbang->busy = 0;
474 bitbang->workqueue = create_singlethread_workqueue(
475 dev_name(bitbang->master->dev.parent));
476 if (bitbang->workqueue == NULL) {
477 status = -EBUSY;
478 goto err1;
481 /* driver may get busy before register() returns, especially
482 * if someone registered boardinfo for devices
484 status = spi_register_master(bitbang->master);
485 if (status < 0)
486 goto err2;
488 return status;
490 err2:
491 destroy_workqueue(bitbang->workqueue);
492 err1:
493 return status;
495 EXPORT_SYMBOL_GPL(spi_bitbang_start);
498 * spi_bitbang_stop - stops the task providing spi communication
500 int spi_bitbang_stop(struct spi_bitbang *bitbang)
502 spi_unregister_master(bitbang->master);
504 WARN_ON(!list_empty(&bitbang->queue));
506 destroy_workqueue(bitbang->workqueue);
508 return 0;
510 EXPORT_SYMBOL_GPL(spi_bitbang_stop);
512 MODULE_LICENSE("GPL");