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ixgbe: Add ability to double reset on failure to clear master enable
[linux-2.6.git] / drivers / net / via-rhine.c
blob5e7f069eab533e75cf950294648a7967da104bb0
1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2 /*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
29
30 */
31
32 #define DRV_NAME "via-rhine"
33 #define DRV_VERSION "1.5.0"
34 #define DRV_RELDATE "2010-10-09"
35
36
37 /* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
39
40 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41 static int max_interrupt_work = 20;
42
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
45 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
46 defined(CONFIG_SPARC) || defined(__ia64__) || \
47 defined(__sh__) || defined(__mips__)
48 static int rx_copybreak = 1518;
49 #else
50 static int rx_copybreak;
51 #endif
52
53 /* Work-around for broken BIOSes: they are unable to get the chip back out of
54 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
55 static int avoid_D3;
56
57 /*
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
60 */
61
62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 The Rhine has a 64 element 8390-like hash table. */
64 static const int multicast_filter_limit = 32;
65
66
67 /* Operational parameters that are set at compile time. */
68
69 /* Keep the ring sizes a power of two for compile efficiency.
70 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71 Making the Tx ring too large decreases the effectiveness of channel
72 bonding and packet priority.
73 There are no ill effects from too-large receive rings. */
74 #define TX_RING_SIZE 16
75 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
76 #define RX_RING_SIZE 64
77
78 /* Operational parameters that usually are not changed. */
79
80 /* Time in jiffies before concluding the transmitter is hung. */
81 #define TX_TIMEOUT (2*HZ)
82
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85 #include <linux/module.h>
86 #include <linux/moduleparam.h>
87 #include <linux/kernel.h>
88 #include <linux/string.h>
89 #include <linux/timer.h>
90 #include <linux/errno.h>
91 #include <linux/ioport.h>
92 #include <linux/interrupt.h>
93 #include <linux/pci.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/netdevice.h>
96 #include <linux/etherdevice.h>
97 #include <linux/skbuff.h>
98 #include <linux/init.h>
99 #include <linux/delay.h>
100 #include <linux/mii.h>
101 #include <linux/ethtool.h>
102 #include <linux/crc32.h>
103 #include <linux/if_vlan.h>
104 #include <linux/bitops.h>
105 #include <linux/workqueue.h>
106 #include <asm/processor.h> /* Processor type for cache alignment. */
107 #include <asm/io.h>
108 #include <asm/irq.h>
109 #include <asm/uaccess.h>
110 #include <linux/dmi.h>
111
112 /* These identify the driver base version and may not be removed. */
113 static const char version[] __devinitconst =
114 KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE
115 " Written by Donald Becker\n";
116
117 /* This driver was written to use PCI memory space. Some early versions
118 of the Rhine may only work correctly with I/O space accesses. */
119 #ifdef CONFIG_VIA_RHINE_MMIO
120 #define USE_MMIO
121 #else
122 #endif
123
124 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
125 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
126 MODULE_LICENSE("GPL");
127
128 module_param(max_interrupt_work, int, 0);
129 module_param(debug, int, 0);
130 module_param(rx_copybreak, int, 0);
131 module_param(avoid_D3, bool, 0);
132 MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
133 MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
134 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
135 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
136
137 #define MCAM_SIZE 32
138 #define VCAM_SIZE 32
139
140 /*
141 Theory of Operation
142
143 I. Board Compatibility
144
145 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
146 controller.
147
148 II. Board-specific settings
149
150 Boards with this chip are functional only in a bus-master PCI slot.
151
152 Many operational settings are loaded from the EEPROM to the Config word at
153 offset 0x78. For most of these settings, this driver assumes that they are
154 correct.
155 If this driver is compiled to use PCI memory space operations the EEPROM
156 must be configured to enable memory ops.
157
158 III. Driver operation
159
160 IIIa. Ring buffers
161
162 This driver uses two statically allocated fixed-size descriptor lists
163 formed into rings by a branch from the final descriptor to the beginning of
164 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
165
166 IIIb/c. Transmit/Receive Structure
167
168 This driver attempts to use a zero-copy receive and transmit scheme.
169
170 Alas, all data buffers are required to start on a 32 bit boundary, so
171 the driver must often copy transmit packets into bounce buffers.
172
173 The driver allocates full frame size skbuffs for the Rx ring buffers at
174 open() time and passes the skb->data field to the chip as receive data
175 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
176 a fresh skbuff is allocated and the frame is copied to the new skbuff.
177 When the incoming frame is larger, the skbuff is passed directly up the
178 protocol stack. Buffers consumed this way are replaced by newly allocated
179 skbuffs in the last phase of rhine_rx().
180
181 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
182 using a full-sized skbuff for small frames vs. the copying costs of larger
183 frames. New boards are typically used in generously configured machines
184 and the underfilled buffers have negligible impact compared to the benefit of
185 a single allocation size, so the default value of zero results in never
186 copying packets. When copying is done, the cost is usually mitigated by using
187 a combined copy/checksum routine. Copying also preloads the cache, which is
188 most useful with small frames.
189
190 Since the VIA chips are only able to transfer data to buffers on 32 bit
191 boundaries, the IP header at offset 14 in an ethernet frame isn't
192 longword aligned for further processing. Copying these unaligned buffers
193 has the beneficial effect of 16-byte aligning the IP header.
194
195 IIId. Synchronization
196
197 The driver runs as two independent, single-threaded flows of control. One
198 is the send-packet routine, which enforces single-threaded use by the
199 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
200 which is single threaded by the hardware and interrupt handling software.
201
202 The send packet thread has partial control over the Tx ring. It locks the
203 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
204 the ring is not available it stops the transmit queue by
205 calling netif_stop_queue.
206
207 The interrupt handler has exclusive control over the Rx ring and records stats
208 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
209 empty by incrementing the dirty_tx mark. If at least half of the entries in
210 the Rx ring are available the transmit queue is woken up if it was stopped.
211
212 IV. Notes
213
214 IVb. References
215
216 Preliminary VT86C100A manual from http://www.via.com.tw/
217 http://www.scyld.com/expert/100mbps.html
218 http://www.scyld.com/expert/NWay.html
219 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
220 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
221
222
223 IVc. Errata
224
225 The VT86C100A manual is not reliable information.
226 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
227 in significant performance degradation for bounce buffer copies on transmit
228 and unaligned IP headers on receive.
229 The chip does not pad to minimum transmit length.
230
231 */
232
233
234 /* This table drives the PCI probe routines. It's mostly boilerplate in all
235 of the drivers, and will likely be provided by some future kernel.
236 Note the matching code -- the first table entry matchs all 56** cards but
237 second only the 1234 card.
238 */
239
240 enum rhine_revs {
241 VT86C100A = 0x00,
242 VTunknown0 = 0x20,
243 VT6102 = 0x40,
244 VT8231 = 0x50, /* Integrated MAC */
245 VT8233 = 0x60, /* Integrated MAC */
246 VT8235 = 0x74, /* Integrated MAC */
247 VT8237 = 0x78, /* Integrated MAC */
248 VTunknown1 = 0x7C,
249 VT6105 = 0x80,
250 VT6105_B0 = 0x83,
251 VT6105L = 0x8A,
252 VT6107 = 0x8C,
253 VTunknown2 = 0x8E,
254 VT6105M = 0x90, /* Management adapter */
255 };
256
257 enum rhine_quirks {
258 rqWOL = 0x0001, /* Wake-On-LAN support */
259 rqForceReset = 0x0002,
260 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
261 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
262 rqRhineI = 0x0100, /* See comment below */
263 };
264 /*
265 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
266 * MMIO as well as for the collision counter and the Tx FIFO underflow
267 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
268 */
269
270 /* Beware of PCI posted writes */
271 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
272
273 static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {
274 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
275 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
276 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
277 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
278 { } /* terminate list */
279 };
280 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
281
282
283 /* Offsets to the device registers. */
284 enum register_offsets {
285 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
286 ChipCmd1=0x09, TQWake=0x0A,
287 IntrStatus=0x0C, IntrEnable=0x0E,
288 MulticastFilter0=0x10, MulticastFilter1=0x14,
289 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
290 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
291 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
292 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
293 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
294 StickyHW=0x83, IntrStatus2=0x84,
295 CamMask=0x88, CamCon=0x92, CamAddr=0x93,
296 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
297 WOLcrClr1=0xA6, WOLcgClr=0xA7,
298 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
299 };
300
301 /* Bits in ConfigD */
302 enum backoff_bits {
303 BackOptional=0x01, BackModify=0x02,
304 BackCaptureEffect=0x04, BackRandom=0x08
305 };
306
307 /* Bits in the TxConfig (TCR) register */
308 enum tcr_bits {
309 TCR_PQEN=0x01,
310 TCR_LB0=0x02, /* loopback[0] */
311 TCR_LB1=0x04, /* loopback[1] */
312 TCR_OFSET=0x08,
313 TCR_RTGOPT=0x10,
314 TCR_RTFT0=0x20,
315 TCR_RTFT1=0x40,
316 TCR_RTSF=0x80,
317 };
318
319 /* Bits in the CamCon (CAMC) register */
320 enum camcon_bits {
321 CAMC_CAMEN=0x01,
322 CAMC_VCAMSL=0x02,
323 CAMC_CAMWR=0x04,
324 CAMC_CAMRD=0x08,
325 };
326
327 /* Bits in the PCIBusConfig1 (BCR1) register */
328 enum bcr1_bits {
329 BCR1_POT0=0x01,
330 BCR1_POT1=0x02,
331 BCR1_POT2=0x04,
332 BCR1_CTFT0=0x08,
333 BCR1_CTFT1=0x10,
334 BCR1_CTSF=0x20,
335 BCR1_TXQNOBK=0x40, /* for VT6105 */
336 BCR1_VIDFR=0x80, /* for VT6105 */
337 BCR1_MED0=0x40, /* for VT6102 */
338 BCR1_MED1=0x80, /* for VT6102 */
339 };
340
341 #ifdef USE_MMIO
342 /* Registers we check that mmio and reg are the same. */
343 static const int mmio_verify_registers[] = {
344 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
345 0
346 };
347 #endif
348
349 /* Bits in the interrupt status/mask registers. */
350 enum intr_status_bits {
351 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
352 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
353 IntrPCIErr=0x0040,
354 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
355 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
356 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
357 IntrRxWakeUp=0x8000,
358 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
359 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
360 IntrTxErrSummary=0x082218,
361 };
362
363 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
364 enum wol_bits {
365 WOLucast = 0x10,
366 WOLmagic = 0x20,
367 WOLbmcast = 0x30,
368 WOLlnkon = 0x40,
369 WOLlnkoff = 0x80,
370 };
371
372 /* The Rx and Tx buffer descriptors. */
373 struct rx_desc {
374 __le32 rx_status;
375 __le32 desc_length; /* Chain flag, Buffer/frame length */
376 __le32 addr;
377 __le32 next_desc;
378 };
379 struct tx_desc {
380 __le32 tx_status;
381 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
382 __le32 addr;
383 __le32 next_desc;
384 };
385
386 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
387 #define TXDESC 0x00e08000
388
389 enum rx_status_bits {
390 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
391 };
392
393 /* Bits in *_desc.*_status */
394 enum desc_status_bits {
395 DescOwn=0x80000000
396 };
397
398 /* Bits in *_desc.*_length */
399 enum desc_length_bits {
400 DescTag=0x00010000
401 };
402
403 /* Bits in ChipCmd. */
404 enum chip_cmd_bits {
405 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
406 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
407 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
408 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
409 };
410
411 struct rhine_private {
412 /* Bit mask for configured VLAN ids */
413 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
414
415 /* Descriptor rings */
416 struct rx_desc *rx_ring;
417 struct tx_desc *tx_ring;
418 dma_addr_t rx_ring_dma;
419 dma_addr_t tx_ring_dma;
420
421 /* The addresses of receive-in-place skbuffs. */
422 struct sk_buff *rx_skbuff[RX_RING_SIZE];
423 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
424
425 /* The saved address of a sent-in-place packet/buffer, for later free(). */
426 struct sk_buff *tx_skbuff[TX_RING_SIZE];
427 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
428
429 /* Tx bounce buffers (Rhine-I only) */
430 unsigned char *tx_buf[TX_RING_SIZE];
431 unsigned char *tx_bufs;
432 dma_addr_t tx_bufs_dma;
433
434 struct pci_dev *pdev;
435 long pioaddr;
436 struct net_device *dev;
437 struct napi_struct napi;
438 spinlock_t lock;
439 struct work_struct reset_task;
440
441 /* Frequently used values: keep some adjacent for cache effect. */
442 u32 quirks;
443 struct rx_desc *rx_head_desc;
444 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
445 unsigned int cur_tx, dirty_tx;
446 unsigned int rx_buf_sz; /* Based on MTU+slack. */
447 u8 wolopts;
448
449 u8 tx_thresh, rx_thresh;
450
451 struct mii_if_info mii_if;
452 void __iomem *base;
453 };
454
455 #define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
456 #define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
457 #define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
458
459 #define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))
460 #define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))
461 #define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))
462
463 #define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
464 #define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
465 #define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
466
467 #define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
468 #define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
469 #define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
470
471
472 static int mdio_read(struct net_device *dev, int phy_id, int location);
473 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
474 static int rhine_open(struct net_device *dev);
475 static void rhine_reset_task(struct work_struct *work);
476 static void rhine_tx_timeout(struct net_device *dev);
477 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
478 struct net_device *dev);
479 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
480 static void rhine_tx(struct net_device *dev);
481 static int rhine_rx(struct net_device *dev, int limit);
482 static void rhine_error(struct net_device *dev, int intr_status);
483 static void rhine_set_rx_mode(struct net_device *dev);
484 static struct net_device_stats *rhine_get_stats(struct net_device *dev);
485 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
486 static const struct ethtool_ops netdev_ethtool_ops;
487 static int rhine_close(struct net_device *dev);
488 static void rhine_shutdown (struct pci_dev *pdev);
489 static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
490 static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
491 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);
492 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);
493 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);
494 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);
495 static void rhine_init_cam_filter(struct net_device *dev);
496 static void rhine_update_vcam(struct net_device *dev);
497
498 #define RHINE_WAIT_FOR(condition) do { \
499 int i=1024; \
500 while (!(condition) && --i) \
501 ; \
502 if (debug > 1 && i < 512) \
503 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
504 DRV_NAME, 1024-i, __func__, __LINE__); \
505 } while(0)
506
507 static inline u32 get_intr_status(struct net_device *dev)
508 {
509 struct rhine_private *rp = netdev_priv(dev);
510 void __iomem *ioaddr = rp->base;
511 u32 intr_status;
512
513 intr_status = ioread16(ioaddr + IntrStatus);
514 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
515 if (rp->quirks & rqStatusWBRace)
516 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
517 return intr_status;
518 }
519
520 /*
521 * Get power related registers into sane state.
522 * Notify user about past WOL event.
523 */
524 static void rhine_power_init(struct net_device *dev)
525 {
526 struct rhine_private *rp = netdev_priv(dev);
527 void __iomem *ioaddr = rp->base;
528 u16 wolstat;
529
530 if (rp->quirks & rqWOL) {
531 /* Make sure chip is in power state D0 */
532 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
533
534 /* Disable "force PME-enable" */
535 iowrite8(0x80, ioaddr + WOLcgClr);
536
537 /* Clear power-event config bits (WOL) */
538 iowrite8(0xFF, ioaddr + WOLcrClr);
539 /* More recent cards can manage two additional patterns */
540 if (rp->quirks & rq6patterns)
541 iowrite8(0x03, ioaddr + WOLcrClr1);
542
543 /* Save power-event status bits */
544 wolstat = ioread8(ioaddr + PwrcsrSet);
545 if (rp->quirks & rq6patterns)
546 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
547
548 /* Clear power-event status bits */
549 iowrite8(0xFF, ioaddr + PwrcsrClr);
550 if (rp->quirks & rq6patterns)
551 iowrite8(0x03, ioaddr + PwrcsrClr1);
552
553 if (wolstat) {
554 char *reason;
555 switch (wolstat) {
556 case WOLmagic:
557 reason = "Magic packet";
558 break;
559 case WOLlnkon:
560 reason = "Link went up";
561 break;
562 case WOLlnkoff:
563 reason = "Link went down";
564 break;
565 case WOLucast:
566 reason = "Unicast packet";
567 break;
568 case WOLbmcast:
569 reason = "Multicast/broadcast packet";
570 break;
571 default:
572 reason = "Unknown";
573 }
574 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
575 DRV_NAME, reason);
576 }
577 }
578 }
579
580 static void rhine_chip_reset(struct net_device *dev)
581 {
582 struct rhine_private *rp = netdev_priv(dev);
583 void __iomem *ioaddr = rp->base;
584
585 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
586 IOSYNC;
587
588 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
589 printk(KERN_INFO "%s: Reset not complete yet. "
590 "Trying harder.\n", DRV_NAME);
591
592 /* Force reset */
593 if (rp->quirks & rqForceReset)
594 iowrite8(0x40, ioaddr + MiscCmd);
595
596 /* Reset can take somewhat longer (rare) */
597 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
598 }
599
600 if (debug > 1)
601 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
602 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
603 "failed" : "succeeded");
604 }
605
606 #ifdef USE_MMIO
607 static void enable_mmio(long pioaddr, u32 quirks)
608 {
609 int n;
610 if (quirks & rqRhineI) {
611 /* More recent docs say that this bit is reserved ... */
612 n = inb(pioaddr + ConfigA) | 0x20;
613 outb(n, pioaddr + ConfigA);
614 } else {
615 n = inb(pioaddr + ConfigD) | 0x80;
616 outb(n, pioaddr + ConfigD);
617 }
618 }
619 #endif
620
621 /*
622 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
623 * (plus 0x6C for Rhine-I/II)
624 */
625 static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
626 {
627 struct rhine_private *rp = netdev_priv(dev);
628 void __iomem *ioaddr = rp->base;
629
630 outb(0x20, pioaddr + MACRegEEcsr);
631 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
632
633 #ifdef USE_MMIO
634 /*
635 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
636 * MMIO. If reloading EEPROM was done first this could be avoided, but
637 * it is not known if that still works with the "win98-reboot" problem.
638 */
639 enable_mmio(pioaddr, rp->quirks);
640 #endif
641
642 /* Turn off EEPROM-controlled wake-up (magic packet) */
643 if (rp->quirks & rqWOL)
644 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
645
646 }
647
648 #ifdef CONFIG_NET_POLL_CONTROLLER
649 static void rhine_poll(struct net_device *dev)
650 {
651 disable_irq(dev->irq);
652 rhine_interrupt(dev->irq, (void *)dev);
653 enable_irq(dev->irq);
654 }
655 #endif
656
657 static int rhine_napipoll(struct napi_struct *napi, int budget)
658 {
659 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
660 struct net_device *dev = rp->dev;
661 void __iomem *ioaddr = rp->base;
662 int work_done;
663
664 work_done = rhine_rx(dev, budget);
665
666 if (work_done < budget) {
667 napi_complete(napi);
668
669 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
670 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
671 IntrTxDone | IntrTxError | IntrTxUnderrun |
672 IntrPCIErr | IntrStatsMax | IntrLinkChange,
673 ioaddr + IntrEnable);
674 }
675 return work_done;
676 }
677
678 static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
679 {
680 struct rhine_private *rp = netdev_priv(dev);
681
682 /* Reset the chip to erase previous misconfiguration. */
683 rhine_chip_reset(dev);
684
685 /* Rhine-I needs extra time to recuperate before EEPROM reload */
686 if (rp->quirks & rqRhineI)
687 msleep(5);
688
689 /* Reload EEPROM controlled bytes cleared by soft reset */
690 rhine_reload_eeprom(pioaddr, dev);
691 }
692
693 static const struct net_device_ops rhine_netdev_ops = {
694 .ndo_open = rhine_open,
695 .ndo_stop = rhine_close,
696 .ndo_start_xmit = rhine_start_tx,
697 .ndo_get_stats = rhine_get_stats,
698 .ndo_set_multicast_list = rhine_set_rx_mode,
699 .ndo_change_mtu = eth_change_mtu,
700 .ndo_validate_addr = eth_validate_addr,
701 .ndo_set_mac_address = eth_mac_addr,
702 .ndo_do_ioctl = netdev_ioctl,
703 .ndo_tx_timeout = rhine_tx_timeout,
704 .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,
705 .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,
706 #ifdef CONFIG_NET_POLL_CONTROLLER
707 .ndo_poll_controller = rhine_poll,
708 #endif
709 };
710
711 static int __devinit rhine_init_one(struct pci_dev *pdev,
712 const struct pci_device_id *ent)
713 {
714 struct net_device *dev;
715 struct rhine_private *rp;
716 int i, rc;
717 u32 quirks;
718 long pioaddr;
719 long memaddr;
720 void __iomem *ioaddr;
721 int io_size, phy_id;
722 const char *name;
723 #ifdef USE_MMIO
724 int bar = 1;
725 #else
726 int bar = 0;
727 #endif
728
729 /* when built into the kernel, we only print version if device is found */
730 #ifndef MODULE
731 static int printed_version;
732 if (!printed_version++)
733 printk(version);
734 #endif
735
736 io_size = 256;
737 phy_id = 0;
738 quirks = 0;
739 name = "Rhine";
740 if (pdev->revision < VTunknown0) {
741 quirks = rqRhineI;
742 io_size = 128;
743 }
744 else if (pdev->revision >= VT6102) {
745 quirks = rqWOL | rqForceReset;
746 if (pdev->revision < VT6105) {
747 name = "Rhine II";
748 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
749 }
750 else {
751 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
752 if (pdev->revision >= VT6105_B0)
753 quirks |= rq6patterns;
754 if (pdev->revision < VT6105M)
755 name = "Rhine III";
756 else
757 name = "Rhine III (Management Adapter)";
758 }
759 }
760
761 rc = pci_enable_device(pdev);
762 if (rc)
763 goto err_out;
764
765 /* this should always be supported */
766 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
767 if (rc) {
768 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
769 "the card!?\n");
770 goto err_out;
771 }
772
773 /* sanity check */
774 if ((pci_resource_len(pdev, 0) < io_size) ||
775 (pci_resource_len(pdev, 1) < io_size)) {
776 rc = -EIO;
777 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
778 goto err_out;
779 }
780
781 pioaddr = pci_resource_start(pdev, 0);
782 memaddr = pci_resource_start(pdev, 1);
783
784 pci_set_master(pdev);
785
786 dev = alloc_etherdev(sizeof(struct rhine_private));
787 if (!dev) {
788 rc = -ENOMEM;
789 printk(KERN_ERR "alloc_etherdev failed\n");
790 goto err_out;
791 }
792 SET_NETDEV_DEV(dev, &pdev->dev);
793
794 rp = netdev_priv(dev);
795 rp->dev = dev;
796 rp->quirks = quirks;
797 rp->pioaddr = pioaddr;
798 rp->pdev = pdev;
799
800 rc = pci_request_regions(pdev, DRV_NAME);
801 if (rc)
802 goto err_out_free_netdev;
803
804 ioaddr = pci_iomap(pdev, bar, io_size);
805 if (!ioaddr) {
806 rc = -EIO;
807 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
808 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
809 goto err_out_free_res;
810 }
811
812 #ifdef USE_MMIO
813 enable_mmio(pioaddr, quirks);
814
815 /* Check that selected MMIO registers match the PIO ones */
816 i = 0;
817 while (mmio_verify_registers[i]) {
818 int reg = mmio_verify_registers[i++];
819 unsigned char a = inb(pioaddr+reg);
820 unsigned char b = readb(ioaddr+reg);
821 if (a != b) {
822 rc = -EIO;
823 printk(KERN_ERR "MMIO do not match PIO [%02x] "
824 "(%02x != %02x)\n", reg, a, b);
825 goto err_out_unmap;
826 }
827 }
828 #endif /* USE_MMIO */
829
830 dev->base_addr = (unsigned long)ioaddr;
831 rp->base = ioaddr;
832
833 /* Get chip registers into a sane state */
834 rhine_power_init(dev);
835 rhine_hw_init(dev, pioaddr);
836
837 for (i = 0; i < 6; i++)
838 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
839 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
840
841 if (!is_valid_ether_addr(dev->perm_addr)) {
842 rc = -EIO;
843 printk(KERN_ERR "Invalid MAC address\n");
844 goto err_out_unmap;
845 }
846
847 /* For Rhine-I/II, phy_id is loaded from EEPROM */
848 if (!phy_id)
849 phy_id = ioread8(ioaddr + 0x6C);
850
851 dev->irq = pdev->irq;
852
853 spin_lock_init(&rp->lock);
854 INIT_WORK(&rp->reset_task, rhine_reset_task);
855
856 rp->mii_if.dev = dev;
857 rp->mii_if.mdio_read = mdio_read;
858 rp->mii_if.mdio_write = mdio_write;
859 rp->mii_if.phy_id_mask = 0x1f;
860 rp->mii_if.reg_num_mask = 0x1f;
861
862 /* The chip-specific entries in the device structure. */
863 dev->netdev_ops = &rhine_netdev_ops;
864 dev->ethtool_ops = &netdev_ethtool_ops,
865 dev->watchdog_timeo = TX_TIMEOUT;
866
867 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
868
869 if (rp->quirks & rqRhineI)
870 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
871
872 if (pdev->revision >= VT6105M)
873 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
874 NETIF_F_HW_VLAN_FILTER;
875
876 /* dev->name not defined before register_netdev()! */
877 rc = register_netdev(dev);
878 if (rc)
879 goto err_out_unmap;
880
881 printk(KERN_INFO "%s: VIA %s at 0x%lx, %pM, IRQ %d.\n",
882 dev->name, name,
883 #ifdef USE_MMIO
884 memaddr,
885 #else
886 (long)ioaddr,
887 #endif
888 dev->dev_addr, pdev->irq);
889
890 pci_set_drvdata(pdev, dev);
891
892 {
893 u16 mii_cmd;
894 int mii_status = mdio_read(dev, phy_id, 1);
895 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
896 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
897 if (mii_status != 0xffff && mii_status != 0x0000) {
898 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
899 printk(KERN_INFO "%s: MII PHY found at address "
900 "%d, status 0x%4.4x advertising %4.4x "
901 "Link %4.4x.\n", dev->name, phy_id,
902 mii_status, rp->mii_if.advertising,
903 mdio_read(dev, phy_id, 5));
904
905 /* set IFF_RUNNING */
906 if (mii_status & BMSR_LSTATUS)
907 netif_carrier_on(dev);
908 else
909 netif_carrier_off(dev);
910
911 }
912 }
913 rp->mii_if.phy_id = phy_id;
914 if (debug > 1 && avoid_D3)
915 printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
916 dev->name);
917
918 return 0;
919
920 err_out_unmap:
921 pci_iounmap(pdev, ioaddr);
922 err_out_free_res:
923 pci_release_regions(pdev);
924 err_out_free_netdev:
925 free_netdev(dev);
926 err_out:
927 return rc;
928 }
929
930 static int alloc_ring(struct net_device* dev)
931 {
932 struct rhine_private *rp = netdev_priv(dev);
933 void *ring;
934 dma_addr_t ring_dma;
935
936 ring = pci_alloc_consistent(rp->pdev,
937 RX_RING_SIZE * sizeof(struct rx_desc) +
938 TX_RING_SIZE * sizeof(struct tx_desc),
939 &ring_dma);
940 if (!ring) {
941 printk(KERN_ERR "Could not allocate DMA memory.\n");
942 return -ENOMEM;
943 }
944 if (rp->quirks & rqRhineI) {
945 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
946 PKT_BUF_SZ * TX_RING_SIZE,
947 &rp->tx_bufs_dma);
948 if (rp->tx_bufs == NULL) {
949 pci_free_consistent(rp->pdev,
950 RX_RING_SIZE * sizeof(struct rx_desc) +
951 TX_RING_SIZE * sizeof(struct tx_desc),
952 ring, ring_dma);
953 return -ENOMEM;
954 }
955 }
956
957 rp->rx_ring = ring;
958 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
959 rp->rx_ring_dma = ring_dma;
960 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
961
962 return 0;
963 }
964
965 static void free_ring(struct net_device* dev)
966 {
967 struct rhine_private *rp = netdev_priv(dev);
968
969 pci_free_consistent(rp->pdev,
970 RX_RING_SIZE * sizeof(struct rx_desc) +
971 TX_RING_SIZE * sizeof(struct tx_desc),
972 rp->rx_ring, rp->rx_ring_dma);
973 rp->tx_ring = NULL;
974
975 if (rp->tx_bufs)
976 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
977 rp->tx_bufs, rp->tx_bufs_dma);
978
979 rp->tx_bufs = NULL;
980
981 }
982
983 static void alloc_rbufs(struct net_device *dev)
984 {
985 struct rhine_private *rp = netdev_priv(dev);
986 dma_addr_t next;
987 int i;
988
989 rp->dirty_rx = rp->cur_rx = 0;
990
991 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
992 rp->rx_head_desc = &rp->rx_ring[0];
993 next = rp->rx_ring_dma;
994
995 /* Init the ring entries */
996 for (i = 0; i < RX_RING_SIZE; i++) {
997 rp->rx_ring[i].rx_status = 0;
998 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
999 next += sizeof(struct rx_desc);
1000 rp->rx_ring[i].next_desc = cpu_to_le32(next);
1001 rp->rx_skbuff[i] = NULL;
1002 }
1003 /* Mark the last entry as wrapping the ring. */
1004 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
1005
1006 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1007 for (i = 0; i < RX_RING_SIZE; i++) {
1008 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1009 rp->rx_skbuff[i] = skb;
1010 if (skb == NULL)
1011 break;
1012 skb->dev = dev; /* Mark as being used by this device. */
1013
1014 rp->rx_skbuff_dma[i] =
1015 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
1016 PCI_DMA_FROMDEVICE);
1017
1018 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
1019 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1020 }
1021 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1022 }
1023
1024 static void free_rbufs(struct net_device* dev)
1025 {
1026 struct rhine_private *rp = netdev_priv(dev);
1027 int i;
1028
1029 /* Free all the skbuffs in the Rx queue. */
1030 for (i = 0; i < RX_RING_SIZE; i++) {
1031 rp->rx_ring[i].rx_status = 0;
1032 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1033 if (rp->rx_skbuff[i]) {
1034 pci_unmap_single(rp->pdev,
1035 rp->rx_skbuff_dma[i],
1036 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1037 dev_kfree_skb(rp->rx_skbuff[i]);
1038 }
1039 rp->rx_skbuff[i] = NULL;
1040 }
1041 }
1042
1043 static void alloc_tbufs(struct net_device* dev)
1044 {
1045 struct rhine_private *rp = netdev_priv(dev);
1046 dma_addr_t next;
1047 int i;
1048
1049 rp->dirty_tx = rp->cur_tx = 0;
1050 next = rp->tx_ring_dma;
1051 for (i = 0; i < TX_RING_SIZE; i++) {
1052 rp->tx_skbuff[i] = NULL;
1053 rp->tx_ring[i].tx_status = 0;
1054 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1055 next += sizeof(struct tx_desc);
1056 rp->tx_ring[i].next_desc = cpu_to_le32(next);
1057 if (rp->quirks & rqRhineI)
1058 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1059 }
1060 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1061
1062 }
1063
1064 static void free_tbufs(struct net_device* dev)
1065 {
1066 struct rhine_private *rp = netdev_priv(dev);
1067 int i;
1068
1069 for (i = 0; i < TX_RING_SIZE; i++) {
1070 rp->tx_ring[i].tx_status = 0;
1071 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1072 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1073 if (rp->tx_skbuff[i]) {
1074 if (rp->tx_skbuff_dma[i]) {
1075 pci_unmap_single(rp->pdev,
1076 rp->tx_skbuff_dma[i],
1077 rp->tx_skbuff[i]->len,
1078 PCI_DMA_TODEVICE);
1079 }
1080 dev_kfree_skb(rp->tx_skbuff[i]);
1081 }
1082 rp->tx_skbuff[i] = NULL;
1083 rp->tx_buf[i] = NULL;
1084 }
1085 }
1086
1087 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1088 {
1089 struct rhine_private *rp = netdev_priv(dev);
1090 void __iomem *ioaddr = rp->base;
1091
1092 mii_check_media(&rp->mii_if, debug, init_media);
1093
1094 if (rp->mii_if.full_duplex)
1095 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1096 ioaddr + ChipCmd1);
1097 else
1098 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1099 ioaddr + ChipCmd1);
1100 if (debug > 1)
1101 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1102 rp->mii_if.force_media, netif_carrier_ok(dev));
1103 }
1104
1105 /* Called after status of force_media possibly changed */
1106 static void rhine_set_carrier(struct mii_if_info *mii)
1107 {
1108 if (mii->force_media) {
1109 /* autoneg is off: Link is always assumed to be up */
1110 if (!netif_carrier_ok(mii->dev))
1111 netif_carrier_on(mii->dev);
1112 }
1113 else /* Let MMI library update carrier status */
1114 rhine_check_media(mii->dev, 0);
1115 if (debug > 1)
1116 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1117 mii->dev->name, mii->force_media,
1118 netif_carrier_ok(mii->dev));
1119 }
1120
1121 /**
1122 * rhine_set_cam - set CAM multicast filters
1123 * @ioaddr: register block of this Rhine
1124 * @idx: multicast CAM index [0..MCAM_SIZE-1]
1125 * @addr: multicast address (6 bytes)
1126 *
1127 * Load addresses into multicast filters.
1128 */
1129 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
1130 {
1131 int i;
1132
1133 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1134 wmb();
1135
1136 /* Paranoid -- idx out of range should never happen */
1137 idx &= (MCAM_SIZE - 1);
1138
1139 iowrite8((u8) idx, ioaddr + CamAddr);
1140
1141 for (i = 0; i < 6; i++, addr++)
1142 iowrite8(*addr, ioaddr + MulticastFilter0 + i);
1143 udelay(10);
1144 wmb();
1145
1146 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1147 udelay(10);
1148
1149 iowrite8(0, ioaddr + CamCon);
1150 }
1151
1152 /**
1153 * rhine_set_vlan_cam - set CAM VLAN filters
1154 * @ioaddr: register block of this Rhine
1155 * @idx: VLAN CAM index [0..VCAM_SIZE-1]
1156 * @addr: VLAN ID (2 bytes)
1157 *
1158 * Load addresses into VLAN filters.
1159 */
1160 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
1161 {
1162 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1163 wmb();
1164
1165 /* Paranoid -- idx out of range should never happen */
1166 idx &= (VCAM_SIZE - 1);
1167
1168 iowrite8((u8) idx, ioaddr + CamAddr);
1169
1170 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
1171 udelay(10);
1172 wmb();
1173
1174 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1175 udelay(10);
1176
1177 iowrite8(0, ioaddr + CamCon);
1178 }
1179
1180 /**
1181 * rhine_set_cam_mask - set multicast CAM mask
1182 * @ioaddr: register block of this Rhine
1183 * @mask: multicast CAM mask
1184 *
1185 * Mask sets multicast filters active/inactive.
1186 */
1187 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
1188 {
1189 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1190 wmb();
1191
1192 /* write mask */
1193 iowrite32(mask, ioaddr + CamMask);
1194
1195 /* disable CAMEN */
1196 iowrite8(0, ioaddr + CamCon);
1197 }
1198
1199 /**
1200 * rhine_set_vlan_cam_mask - set VLAN CAM mask
1201 * @ioaddr: register block of this Rhine
1202 * @mask: VLAN CAM mask
1203 *
1204 * Mask sets VLAN filters active/inactive.
1205 */
1206 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
1207 {
1208 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1209 wmb();
1210
1211 /* write mask */
1212 iowrite32(mask, ioaddr + CamMask);
1213
1214 /* disable CAMEN */
1215 iowrite8(0, ioaddr + CamCon);
1216 }
1217
1218 /**
1219 * rhine_init_cam_filter - initialize CAM filters
1220 * @dev: network device
1221 *
1222 * Initialize (disable) hardware VLAN and multicast support on this
1223 * Rhine.
1224 */
1225 static void rhine_init_cam_filter(struct net_device *dev)
1226 {
1227 struct rhine_private *rp = netdev_priv(dev);
1228 void __iomem *ioaddr = rp->base;
1229
1230 /* Disable all CAMs */
1231 rhine_set_vlan_cam_mask(ioaddr, 0);
1232 rhine_set_cam_mask(ioaddr, 0);
1233
1234 /* disable hardware VLAN support */
1235 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
1236 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
1237 }
1238
1239 /**
1240 * rhine_update_vcam - update VLAN CAM filters
1241 * @rp: rhine_private data of this Rhine
1242 *
1243 * Update VLAN CAM filters to match configuration change.
1244 */
1245 static void rhine_update_vcam(struct net_device *dev)
1246 {
1247 struct rhine_private *rp = netdev_priv(dev);
1248 void __iomem *ioaddr = rp->base;
1249 u16 vid;
1250 u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */
1251 unsigned int i = 0;
1252
1253 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
1254 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
1255 vCAMmask |= 1 << i;
1256 if (++i >= VCAM_SIZE)
1257 break;
1258 }
1259 rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
1260 }
1261
1262 static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
1263 {
1264 struct rhine_private *rp = netdev_priv(dev);
1265
1266 spin_lock_irq(&rp->lock);
1267 set_bit(vid, rp->active_vlans);
1268 rhine_update_vcam(dev);
1269 spin_unlock_irq(&rp->lock);
1270 }
1271
1272 static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1273 {
1274 struct rhine_private *rp = netdev_priv(dev);
1275
1276 spin_lock_irq(&rp->lock);
1277 clear_bit(vid, rp->active_vlans);
1278 rhine_update_vcam(dev);
1279 spin_unlock_irq(&rp->lock);
1280 }
1281
1282 static void init_registers(struct net_device *dev)
1283 {
1284 struct rhine_private *rp = netdev_priv(dev);
1285 void __iomem *ioaddr = rp->base;
1286 int i;
1287
1288 for (i = 0; i < 6; i++)
1289 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1290
1291 /* Initialize other registers. */
1292 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1293 /* Configure initial FIFO thresholds. */
1294 iowrite8(0x20, ioaddr + TxConfig);
1295 rp->tx_thresh = 0x20;
1296 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1297
1298 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1299 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1300
1301 rhine_set_rx_mode(dev);
1302
1303 if (rp->pdev->revision >= VT6105M)
1304 rhine_init_cam_filter(dev);
1305
1306 napi_enable(&rp->napi);
1307
1308 /* Enable interrupts by setting the interrupt mask. */
1309 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1310 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1311 IntrTxDone | IntrTxError | IntrTxUnderrun |
1312 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1313 ioaddr + IntrEnable);
1314
1315 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1316 ioaddr + ChipCmd);
1317 rhine_check_media(dev, 1);
1318 }
1319
1320 /* Enable MII link status auto-polling (required for IntrLinkChange) */
1321 static void rhine_enable_linkmon(void __iomem *ioaddr)
1322 {
1323 iowrite8(0, ioaddr + MIICmd);
1324 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1325 iowrite8(0x80, ioaddr + MIICmd);
1326
1327 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1328
1329 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1330 }
1331
1332 /* Disable MII link status auto-polling (required for MDIO access) */
1333 static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1334 {
1335 iowrite8(0, ioaddr + MIICmd);
1336
1337 if (quirks & rqRhineI) {
1338 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1339
1340 /* Can be called from ISR. Evil. */
1341 mdelay(1);
1342
1343 /* 0x80 must be set immediately before turning it off */
1344 iowrite8(0x80, ioaddr + MIICmd);
1345
1346 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1347
1348 /* Heh. Now clear 0x80 again. */
1349 iowrite8(0, ioaddr + MIICmd);
1350 }
1351 else
1352 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1353 }
1354
1355 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1356
1357 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1358 {
1359 struct rhine_private *rp = netdev_priv(dev);
1360 void __iomem *ioaddr = rp->base;
1361 int result;
1362
1363 rhine_disable_linkmon(ioaddr, rp->quirks);
1364
1365 /* rhine_disable_linkmon already cleared MIICmd */
1366 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1367 iowrite8(regnum, ioaddr + MIIRegAddr);
1368 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1369 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1370 result = ioread16(ioaddr + MIIData);
1371
1372 rhine_enable_linkmon(ioaddr);
1373 return result;
1374 }
1375
1376 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1377 {
1378 struct rhine_private *rp = netdev_priv(dev);
1379 void __iomem *ioaddr = rp->base;
1380
1381 rhine_disable_linkmon(ioaddr, rp->quirks);
1382
1383 /* rhine_disable_linkmon already cleared MIICmd */
1384 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1385 iowrite8(regnum, ioaddr + MIIRegAddr);
1386 iowrite16(value, ioaddr + MIIData);
1387 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1388 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1389
1390 rhine_enable_linkmon(ioaddr);
1391 }
1392
1393 static int rhine_open(struct net_device *dev)
1394 {
1395 struct rhine_private *rp = netdev_priv(dev);
1396 void __iomem *ioaddr = rp->base;
1397 int rc;
1398
1399 rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,
1400 dev);
1401 if (rc)
1402 return rc;
1403
1404 if (debug > 1)
1405 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1406 dev->name, rp->pdev->irq);
1407
1408 rc = alloc_ring(dev);
1409 if (rc) {
1410 free_irq(rp->pdev->irq, dev);
1411 return rc;
1412 }
1413 alloc_rbufs(dev);
1414 alloc_tbufs(dev);
1415 rhine_chip_reset(dev);
1416 init_registers(dev);
1417 if (debug > 2)
1418 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1419 "MII status: %4.4x.\n",
1420 dev->name, ioread16(ioaddr + ChipCmd),
1421 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1422
1423 netif_start_queue(dev);
1424
1425 return 0;
1426 }
1427
1428 static void rhine_reset_task(struct work_struct *work)
1429 {
1430 struct rhine_private *rp = container_of(work, struct rhine_private,
1431 reset_task);
1432 struct net_device *dev = rp->dev;
1433
1434 /* protect against concurrent rx interrupts */
1435 disable_irq(rp->pdev->irq);
1436
1437 napi_disable(&rp->napi);
1438
1439 spin_lock_bh(&rp->lock);
1440
1441 /* clear all descriptors */
1442 free_tbufs(dev);
1443 free_rbufs(dev);
1444 alloc_tbufs(dev);
1445 alloc_rbufs(dev);
1446
1447 /* Reinitialize the hardware. */
1448 rhine_chip_reset(dev);
1449 init_registers(dev);
1450
1451 spin_unlock_bh(&rp->lock);
1452 enable_irq(rp->pdev->irq);
1453
1454 dev->trans_start = jiffies; /* prevent tx timeout */
1455 dev->stats.tx_errors++;
1456 netif_wake_queue(dev);
1457 }
1458
1459 static void rhine_tx_timeout(struct net_device *dev)
1460 {
1461 struct rhine_private *rp = netdev_priv(dev);
1462 void __iomem *ioaddr = rp->base;
1463
1464 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1465 "%4.4x, resetting...\n",
1466 dev->name, ioread16(ioaddr + IntrStatus),
1467 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1468
1469 schedule_work(&rp->reset_task);
1470 }
1471
1472 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
1473 struct net_device *dev)
1474 {
1475 struct rhine_private *rp = netdev_priv(dev);
1476 void __iomem *ioaddr = rp->base;
1477 unsigned entry;
1478 unsigned long flags;
1479
1480 /* Caution: the write order is important here, set the field
1481 with the "ownership" bits last. */
1482
1483 /* Calculate the next Tx descriptor entry. */
1484 entry = rp->cur_tx % TX_RING_SIZE;
1485
1486 if (skb_padto(skb, ETH_ZLEN))
1487 return NETDEV_TX_OK;
1488
1489 rp->tx_skbuff[entry] = skb;
1490
1491 if ((rp->quirks & rqRhineI) &&
1492 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1493 /* Must use alignment buffer. */
1494 if (skb->len > PKT_BUF_SZ) {
1495 /* packet too long, drop it */
1496 dev_kfree_skb(skb);
1497 rp->tx_skbuff[entry] = NULL;
1498 dev->stats.tx_dropped++;
1499 return NETDEV_TX_OK;
1500 }
1501
1502 /* Padding is not copied and so must be redone. */
1503 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1504 if (skb->len < ETH_ZLEN)
1505 memset(rp->tx_buf[entry] + skb->len, 0,
1506 ETH_ZLEN - skb->len);
1507 rp->tx_skbuff_dma[entry] = 0;
1508 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1509 (rp->tx_buf[entry] -
1510 rp->tx_bufs));
1511 } else {
1512 rp->tx_skbuff_dma[entry] =
1513 pci_map_single(rp->pdev, skb->data, skb->len,
1514 PCI_DMA_TODEVICE);
1515 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1516 }
1517
1518 rp->tx_ring[entry].desc_length =
1519 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1520
1521 if (unlikely(vlan_tx_tag_present(skb))) {
1522 rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
1523 /* request tagging */
1524 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
1525 }
1526 else
1527 rp->tx_ring[entry].tx_status = 0;
1528
1529 /* lock eth irq */
1530 spin_lock_irqsave(&rp->lock, flags);
1531 wmb();
1532 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
1533 wmb();
1534
1535 rp->cur_tx++;
1536
1537 /* Non-x86 Todo: explicitly flush cache lines here. */
1538
1539 if (vlan_tx_tag_present(skb))
1540 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1541 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1542
1543 /* Wake the potentially-idle transmit channel */
1544 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1545 ioaddr + ChipCmd1);
1546 IOSYNC;
1547
1548 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1549 netif_stop_queue(dev);
1550
1551 spin_unlock_irqrestore(&rp->lock, flags);
1552
1553 if (debug > 4) {
1554 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1555 dev->name, rp->cur_tx-1, entry);
1556 }
1557 return NETDEV_TX_OK;
1558 }
1559
1560 /* The interrupt handler does all of the Rx thread work and cleans up
1561 after the Tx thread. */
1562 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1563 {
1564 struct net_device *dev = dev_instance;
1565 struct rhine_private *rp = netdev_priv(dev);
1566 void __iomem *ioaddr = rp->base;
1567 u32 intr_status;
1568 int boguscnt = max_interrupt_work;
1569 int handled = 0;
1570
1571 while ((intr_status = get_intr_status(dev))) {
1572 handled = 1;
1573
1574 /* Acknowledge all of the current interrupt sources ASAP. */
1575 if (intr_status & IntrTxDescRace)
1576 iowrite8(0x08, ioaddr + IntrStatus2);
1577 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1578 IOSYNC;
1579
1580 if (debug > 4)
1581 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1582 dev->name, intr_status);
1583
1584 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1585 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1586 iowrite16(IntrTxAborted |
1587 IntrTxDone | IntrTxError | IntrTxUnderrun |
1588 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1589 ioaddr + IntrEnable);
1590
1591 napi_schedule(&rp->napi);
1592 }
1593
1594 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1595 if (intr_status & IntrTxErrSummary) {
1596 /* Avoid scavenging before Tx engine turned off */
1597 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1598 if (debug > 2 &&
1599 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1600 printk(KERN_WARNING "%s: "
1601 "rhine_interrupt() Tx engine "
1602 "still on.\n", dev->name);
1603 }
1604 rhine_tx(dev);
1605 }
1606
1607 /* Abnormal error summary/uncommon events handlers. */
1608 if (intr_status & (IntrPCIErr | IntrLinkChange |
1609 IntrStatsMax | IntrTxError | IntrTxAborted |
1610 IntrTxUnderrun | IntrTxDescRace))
1611 rhine_error(dev, intr_status);
1612
1613 if (--boguscnt < 0) {
1614 printk(KERN_WARNING "%s: Too much work at interrupt, "
1615 "status=%#8.8x.\n",
1616 dev->name, intr_status);
1617 break;
1618 }
1619 }
1620
1621 if (debug > 3)
1622 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1623 dev->name, ioread16(ioaddr + IntrStatus));
1624 return IRQ_RETVAL(handled);
1625 }
1626
1627 /* This routine is logically part of the interrupt handler, but isolated
1628 for clarity. */
1629 static void rhine_tx(struct net_device *dev)
1630 {
1631 struct rhine_private *rp = netdev_priv(dev);
1632 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1633
1634 spin_lock(&rp->lock);
1635
1636 /* find and cleanup dirty tx descriptors */
1637 while (rp->dirty_tx != rp->cur_tx) {
1638 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1639 if (debug > 6)
1640 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
1641 entry, txstatus);
1642 if (txstatus & DescOwn)
1643 break;
1644 if (txstatus & 0x8000) {
1645 if (debug > 1)
1646 printk(KERN_DEBUG "%s: Transmit error, "
1647 "Tx status %8.8x.\n",
1648 dev->name, txstatus);
1649 dev->stats.tx_errors++;
1650 if (txstatus & 0x0400)
1651 dev->stats.tx_carrier_errors++;
1652 if (txstatus & 0x0200)
1653 dev->stats.tx_window_errors++;
1654 if (txstatus & 0x0100)
1655 dev->stats.tx_aborted_errors++;
1656 if (txstatus & 0x0080)
1657 dev->stats.tx_heartbeat_errors++;
1658 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1659 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1660 dev->stats.tx_fifo_errors++;
1661 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1662 break; /* Keep the skb - we try again */
1663 }
1664 /* Transmitter restarted in 'abnormal' handler. */
1665 } else {
1666 if (rp->quirks & rqRhineI)
1667 dev->stats.collisions += (txstatus >> 3) & 0x0F;
1668 else
1669 dev->stats.collisions += txstatus & 0x0F;
1670 if (debug > 6)
1671 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1672 (txstatus >> 3) & 0xF,
1673 txstatus & 0xF);
1674 dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1675 dev->stats.tx_packets++;
1676 }
1677 /* Free the original skb. */
1678 if (rp->tx_skbuff_dma[entry]) {
1679 pci_unmap_single(rp->pdev,
1680 rp->tx_skbuff_dma[entry],
1681 rp->tx_skbuff[entry]->len,
1682 PCI_DMA_TODEVICE);
1683 }
1684 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1685 rp->tx_skbuff[entry] = NULL;
1686 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1687 }
1688 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1689 netif_wake_queue(dev);
1690
1691 spin_unlock(&rp->lock);
1692 }
1693
1694 /**
1695 * rhine_get_vlan_tci - extract TCI from Rx data buffer
1696 * @skb: pointer to sk_buff
1697 * @data_size: used data area of the buffer including CRC
1698 *
1699 * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
1700 * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
1701 * aligned following the CRC.
1702 */
1703 static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
1704 {
1705 u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
1706 return ntohs(*(u16 *)trailer);
1707 }
1708
1709 /* Process up to limit frames from receive ring */
1710 static int rhine_rx(struct net_device *dev, int limit)
1711 {
1712 struct rhine_private *rp = netdev_priv(dev);
1713 int count;
1714 int entry = rp->cur_rx % RX_RING_SIZE;
1715
1716 if (debug > 4) {
1717 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1718 dev->name, entry,
1719 le32_to_cpu(rp->rx_head_desc->rx_status));
1720 }
1721
1722 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1723 for (count = 0; count < limit; ++count) {
1724 struct rx_desc *desc = rp->rx_head_desc;
1725 u32 desc_status = le32_to_cpu(desc->rx_status);
1726 u32 desc_length = le32_to_cpu(desc->desc_length);
1727 int data_size = desc_status >> 16;
1728
1729 if (desc_status & DescOwn)
1730 break;
1731
1732 if (debug > 4)
1733 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
1734 desc_status);
1735
1736 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1737 if ((desc_status & RxWholePkt) != RxWholePkt) {
1738 printk(KERN_WARNING "%s: Oversized Ethernet "
1739 "frame spanned multiple buffers, entry "
1740 "%#x length %d status %8.8x!\n",
1741 dev->name, entry, data_size,
1742 desc_status);
1743 printk(KERN_WARNING "%s: Oversized Ethernet "
1744 "frame %p vs %p.\n", dev->name,
1745 rp->rx_head_desc, &rp->rx_ring[entry]);
1746 dev->stats.rx_length_errors++;
1747 } else if (desc_status & RxErr) {
1748 /* There was a error. */
1749 if (debug > 2)
1750 printk(KERN_DEBUG "rhine_rx() Rx "
1751 "error was %8.8x.\n",
1752 desc_status);
1753 dev->stats.rx_errors++;
1754 if (desc_status & 0x0030)
1755 dev->stats.rx_length_errors++;
1756 if (desc_status & 0x0048)
1757 dev->stats.rx_fifo_errors++;
1758 if (desc_status & 0x0004)
1759 dev->stats.rx_frame_errors++;
1760 if (desc_status & 0x0002) {
1761 /* this can also be updated outside the interrupt handler */
1762 spin_lock(&rp->lock);
1763 dev->stats.rx_crc_errors++;
1764 spin_unlock(&rp->lock);
1765 }
1766 }
1767 } else {
1768 struct sk_buff *skb = NULL;
1769 /* Length should omit the CRC */
1770 int pkt_len = data_size - 4;
1771 u16 vlan_tci = 0;
1772
1773 /* Check if the packet is long enough to accept without
1774 copying to a minimally-sized skbuff. */
1775 if (pkt_len < rx_copybreak)
1776 skb = netdev_alloc_skb_ip_align(dev, pkt_len);
1777 if (skb) {
1778 pci_dma_sync_single_for_cpu(rp->pdev,
1779 rp->rx_skbuff_dma[entry],
1780 rp->rx_buf_sz,
1781 PCI_DMA_FROMDEVICE);
1782
1783 skb_copy_to_linear_data(skb,
1784 rp->rx_skbuff[entry]->data,
1785 pkt_len);
1786 skb_put(skb, pkt_len);
1787 pci_dma_sync_single_for_device(rp->pdev,
1788 rp->rx_skbuff_dma[entry],
1789 rp->rx_buf_sz,
1790 PCI_DMA_FROMDEVICE);
1791 } else {
1792 skb = rp->rx_skbuff[entry];
1793 if (skb == NULL) {
1794 printk(KERN_ERR "%s: Inconsistent Rx "
1795 "descriptor chain.\n",
1796 dev->name);
1797 break;
1798 }
1799 rp->rx_skbuff[entry] = NULL;
1800 skb_put(skb, pkt_len);
1801 pci_unmap_single(rp->pdev,
1802 rp->rx_skbuff_dma[entry],
1803 rp->rx_buf_sz,
1804 PCI_DMA_FROMDEVICE);
1805 }
1806
1807 if (unlikely(desc_length & DescTag))
1808 vlan_tci = rhine_get_vlan_tci(skb, data_size);
1809
1810 skb->protocol = eth_type_trans(skb, dev);
1811
1812 if (unlikely(desc_length & DescTag))
1813 __vlan_hwaccel_put_tag(skb, vlan_tci);
1814 netif_receive_skb(skb);
1815 dev->stats.rx_bytes += pkt_len;
1816 dev->stats.rx_packets++;
1817 }
1818 entry = (++rp->cur_rx) % RX_RING_SIZE;
1819 rp->rx_head_desc = &rp->rx_ring[entry];
1820 }
1821
1822 /* Refill the Rx ring buffers. */
1823 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1824 struct sk_buff *skb;
1825 entry = rp->dirty_rx % RX_RING_SIZE;
1826 if (rp->rx_skbuff[entry] == NULL) {
1827 skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1828 rp->rx_skbuff[entry] = skb;
1829 if (skb == NULL)
1830 break; /* Better luck next round. */
1831 skb->dev = dev; /* Mark as being used by this device. */
1832 rp->rx_skbuff_dma[entry] =
1833 pci_map_single(rp->pdev, skb->data,
1834 rp->rx_buf_sz,
1835 PCI_DMA_FROMDEVICE);
1836 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1837 }
1838 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1839 }
1840
1841 return count;
1842 }
1843
1844 /*
1845 * Clears the "tally counters" for CRC errors and missed frames(?).
1846 * It has been reported that some chips need a write of 0 to clear
1847 * these, for others the counters are set to 1 when written to and
1848 * instead cleared when read. So we clear them both ways ...
1849 */
1850 static inline void clear_tally_counters(void __iomem *ioaddr)
1851 {
1852 iowrite32(0, ioaddr + RxMissed);
1853 ioread16(ioaddr + RxCRCErrs);
1854 ioread16(ioaddr + RxMissed);
1855 }
1856
1857 static void rhine_restart_tx(struct net_device *dev) {
1858 struct rhine_private *rp = netdev_priv(dev);
1859 void __iomem *ioaddr = rp->base;
1860 int entry = rp->dirty_tx % TX_RING_SIZE;
1861 u32 intr_status;
1862
1863 /*
1864 * If new errors occured, we need to sort them out before doing Tx.
1865 * In that case the ISR will be back here RSN anyway.
1866 */
1867 intr_status = get_intr_status(dev);
1868
1869 if ((intr_status & IntrTxErrSummary) == 0) {
1870
1871 /* We know better than the chip where it should continue. */
1872 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1873 ioaddr + TxRingPtr);
1874
1875 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1876 ioaddr + ChipCmd);
1877
1878 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
1879 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1880 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1881
1882 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1883 ioaddr + ChipCmd1);
1884 IOSYNC;
1885 }
1886 else {
1887 /* This should never happen */
1888 if (debug > 1)
1889 printk(KERN_WARNING "%s: rhine_restart_tx() "
1890 "Another error occured %8.8x.\n",
1891 dev->name, intr_status);
1892 }
1893
1894 }
1895
1896 static void rhine_error(struct net_device *dev, int intr_status)
1897 {
1898 struct rhine_private *rp = netdev_priv(dev);
1899 void __iomem *ioaddr = rp->base;
1900
1901 spin_lock(&rp->lock);
1902
1903 if (intr_status & IntrLinkChange)
1904 rhine_check_media(dev, 0);
1905 if (intr_status & IntrStatsMax) {
1906 dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1907 dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1908 clear_tally_counters(ioaddr);
1909 }
1910 if (intr_status & IntrTxAborted) {
1911 if (debug > 1)
1912 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1913 dev->name, intr_status);
1914 }
1915 if (intr_status & IntrTxUnderrun) {
1916 if (rp->tx_thresh < 0xE0)
1917 BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
1918 if (debug > 1)
1919 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1920 "threshold now %2.2x.\n",
1921 dev->name, rp->tx_thresh);
1922 }
1923 if (intr_status & IntrTxDescRace) {
1924 if (debug > 2)
1925 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1926 dev->name);
1927 }
1928 if ((intr_status & IntrTxError) &&
1929 (intr_status & (IntrTxAborted |
1930 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1931 if (rp->tx_thresh < 0xE0) {
1932 BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
1933 }
1934 if (debug > 1)
1935 printk(KERN_INFO "%s: Unspecified error. Tx "
1936 "threshold now %2.2x.\n",
1937 dev->name, rp->tx_thresh);
1938 }
1939 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1940 IntrTxError))
1941 rhine_restart_tx(dev);
1942
1943 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1944 IntrTxError | IntrTxAborted | IntrNormalSummary |
1945 IntrTxDescRace)) {
1946 if (debug > 1)
1947 printk(KERN_ERR "%s: Something Wicked happened! "
1948 "%8.8x.\n", dev->name, intr_status);
1949 }
1950
1951 spin_unlock(&rp->lock);
1952 }
1953
1954 static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1955 {
1956 struct rhine_private *rp = netdev_priv(dev);
1957 void __iomem *ioaddr = rp->base;
1958 unsigned long flags;
1959
1960 spin_lock_irqsave(&rp->lock, flags);
1961 dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1962 dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1963 clear_tally_counters(ioaddr);
1964 spin_unlock_irqrestore(&rp->lock, flags);
1965
1966 return &dev->stats;
1967 }
1968
1969 static void rhine_set_rx_mode(struct net_device *dev)
1970 {
1971 struct rhine_private *rp = netdev_priv(dev);
1972 void __iomem *ioaddr = rp->base;
1973 u32 mc_filter[2]; /* Multicast hash filter */
1974 u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */
1975 struct netdev_hw_addr *ha;
1976
1977 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1978 rx_mode = 0x1C;
1979 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1980 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1981 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1982 (dev->flags & IFF_ALLMULTI)) {
1983 /* Too many to match, or accept all multicasts. */
1984 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1985 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1986 } else if (rp->pdev->revision >= VT6105M) {
1987 int i = 0;
1988 u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */
1989 netdev_for_each_mc_addr(ha, dev) {
1990 if (i == MCAM_SIZE)
1991 break;
1992 rhine_set_cam(ioaddr, i, ha->addr);
1993 mCAMmask |= 1 << i;
1994 i++;
1995 }
1996 rhine_set_cam_mask(ioaddr, mCAMmask);
1997 } else {
1998 memset(mc_filter, 0, sizeof(mc_filter));
1999 netdev_for_each_mc_addr(ha, dev) {
2000 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2001
2002 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2003 }
2004 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
2005 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
2006 }
2007 /* enable/disable VLAN receive filtering */
2008 if (rp->pdev->revision >= VT6105M) {
2009 if (dev->flags & IFF_PROMISC)
2010 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2011 else
2012 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2013 }
2014 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
2015 }
2016
2017 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2018 {
2019 struct rhine_private *rp = netdev_priv(dev);
2020
2021 strcpy(info->driver, DRV_NAME);
2022 strcpy(info->version, DRV_VERSION);
2023 strcpy(info->bus_info, pci_name(rp->pdev));
2024 }
2025
2026 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2027 {
2028 struct rhine_private *rp = netdev_priv(dev);
2029 int rc;
2030
2031 spin_lock_irq(&rp->lock);
2032 rc = mii_ethtool_gset(&rp->mii_if, cmd);
2033 spin_unlock_irq(&rp->lock);
2034
2035 return rc;
2036 }
2037
2038 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2039 {
2040 struct rhine_private *rp = netdev_priv(dev);
2041 int rc;
2042
2043 spin_lock_irq(&rp->lock);
2044 rc = mii_ethtool_sset(&rp->mii_if, cmd);
2045 spin_unlock_irq(&rp->lock);
2046 rhine_set_carrier(&rp->mii_if);
2047
2048 return rc;
2049 }
2050
2051 static int netdev_nway_reset(struct net_device *dev)
2052 {
2053 struct rhine_private *rp = netdev_priv(dev);
2054
2055 return mii_nway_restart(&rp->mii_if);
2056 }
2057
2058 static u32 netdev_get_link(struct net_device *dev)
2059 {
2060 struct rhine_private *rp = netdev_priv(dev);
2061
2062 return mii_link_ok(&rp->mii_if);
2063 }
2064
2065 static u32 netdev_get_msglevel(struct net_device *dev)
2066 {
2067 return debug;
2068 }
2069
2070 static void netdev_set_msglevel(struct net_device *dev, u32 value)
2071 {
2072 debug = value;
2073 }
2074
2075 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2076 {
2077 struct rhine_private *rp = netdev_priv(dev);
2078
2079 if (!(rp->quirks & rqWOL))
2080 return;
2081
2082 spin_lock_irq(&rp->lock);
2083 wol->supported = WAKE_PHY | WAKE_MAGIC |
2084 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2085 wol->wolopts = rp->wolopts;
2086 spin_unlock_irq(&rp->lock);
2087 }
2088
2089 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2090 {
2091 struct rhine_private *rp = netdev_priv(dev);
2092 u32 support = WAKE_PHY | WAKE_MAGIC |
2093 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2094
2095 if (!(rp->quirks & rqWOL))
2096 return -EINVAL;
2097
2098 if (wol->wolopts & ~support)
2099 return -EINVAL;
2100
2101 spin_lock_irq(&rp->lock);
2102 rp->wolopts = wol->wolopts;
2103 spin_unlock_irq(&rp->lock);
2104
2105 return 0;
2106 }
2107
2108 static const struct ethtool_ops netdev_ethtool_ops = {
2109 .get_drvinfo = netdev_get_drvinfo,
2110 .get_settings = netdev_get_settings,
2111 .set_settings = netdev_set_settings,
2112 .nway_reset = netdev_nway_reset,
2113 .get_link = netdev_get_link,
2114 .get_msglevel = netdev_get_msglevel,
2115 .set_msglevel = netdev_set_msglevel,
2116 .get_wol = rhine_get_wol,
2117 .set_wol = rhine_set_wol,
2118 };
2119
2120 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2121 {
2122 struct rhine_private *rp = netdev_priv(dev);
2123 int rc;
2124
2125 if (!netif_running(dev))
2126 return -EINVAL;
2127
2128 spin_lock_irq(&rp->lock);
2129 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
2130 spin_unlock_irq(&rp->lock);
2131 rhine_set_carrier(&rp->mii_if);
2132
2133 return rc;
2134 }
2135
2136 static int rhine_close(struct net_device *dev)
2137 {
2138 struct rhine_private *rp = netdev_priv(dev);
2139 void __iomem *ioaddr = rp->base;
2140
2141 napi_disable(&rp->napi);
2142 cancel_work_sync(&rp->reset_task);
2143 netif_stop_queue(dev);
2144
2145 spin_lock_irq(&rp->lock);
2146
2147 if (debug > 1)
2148 printk(KERN_DEBUG "%s: Shutting down ethercard, "
2149 "status was %4.4x.\n",
2150 dev->name, ioread16(ioaddr + ChipCmd));
2151
2152 /* Switch to loopback mode to avoid hardware races. */
2153 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2154
2155 /* Disable interrupts by clearing the interrupt mask. */
2156 iowrite16(0x0000, ioaddr + IntrEnable);
2157
2158 /* Stop the chip's Tx and Rx processes. */
2159 iowrite16(CmdStop, ioaddr + ChipCmd);
2160
2161 spin_unlock_irq(&rp->lock);
2162
2163 free_irq(rp->pdev->irq, dev);
2164 free_rbufs(dev);
2165 free_tbufs(dev);
2166 free_ring(dev);
2167
2168 return 0;
2169 }
2170
2171
2172 static void __devexit rhine_remove_one(struct pci_dev *pdev)
2173 {
2174 struct net_device *dev = pci_get_drvdata(pdev);
2175 struct rhine_private *rp = netdev_priv(dev);
2176
2177 unregister_netdev(dev);
2178
2179 pci_iounmap(pdev, rp->base);
2180 pci_release_regions(pdev);
2181
2182 free_netdev(dev);
2183 pci_disable_device(pdev);
2184 pci_set_drvdata(pdev, NULL);
2185 }
2186
2187 static void rhine_shutdown (struct pci_dev *pdev)
2188 {
2189 struct net_device *dev = pci_get_drvdata(pdev);
2190 struct rhine_private *rp = netdev_priv(dev);
2191 void __iomem *ioaddr = rp->base;
2192
2193 if (!(rp->quirks & rqWOL))
2194 return; /* Nothing to do for non-WOL adapters */
2195
2196 rhine_power_init(dev);
2197
2198 /* Make sure we use pattern 0, 1 and not 4, 5 */
2199 if (rp->quirks & rq6patterns)
2200 iowrite8(0x04, ioaddr + WOLcgClr);
2201
2202 if (rp->wolopts & WAKE_MAGIC) {
2203 iowrite8(WOLmagic, ioaddr + WOLcrSet);
2204 /*
2205 * Turn EEPROM-controlled wake-up back on -- some hardware may
2206 * not cooperate otherwise.
2207 */
2208 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
2209 }
2210
2211 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
2212 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
2213
2214 if (rp->wolopts & WAKE_PHY)
2215 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
2216
2217 if (rp->wolopts & WAKE_UCAST)
2218 iowrite8(WOLucast, ioaddr + WOLcrSet);
2219
2220 if (rp->wolopts) {
2221 /* Enable legacy WOL (for old motherboards) */
2222 iowrite8(0x01, ioaddr + PwcfgSet);
2223 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
2224 }
2225
2226 /* Hit power state D3 (sleep) */
2227 if (!avoid_D3)
2228 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
2229
2230 /* TODO: Check use of pci_enable_wake() */
2231
2232 }
2233
2234 #ifdef CONFIG_PM
2235 static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
2236 {
2237 struct net_device *dev = pci_get_drvdata(pdev);
2238 struct rhine_private *rp = netdev_priv(dev);
2239 unsigned long flags;
2240
2241 if (!netif_running(dev))
2242 return 0;
2243
2244 napi_disable(&rp->napi);
2245
2246 netif_device_detach(dev);
2247 pci_save_state(pdev);
2248
2249 spin_lock_irqsave(&rp->lock, flags);
2250 rhine_shutdown(pdev);
2251 spin_unlock_irqrestore(&rp->lock, flags);
2252
2253 free_irq(dev->irq, dev);
2254 return 0;
2255 }
2256
2257 static int rhine_resume(struct pci_dev *pdev)
2258 {
2259 struct net_device *dev = pci_get_drvdata(pdev);
2260 struct rhine_private *rp = netdev_priv(dev);
2261 unsigned long flags;
2262 int ret;
2263
2264 if (!netif_running(dev))
2265 return 0;
2266
2267 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
2268 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
2269
2270 ret = pci_set_power_state(pdev, PCI_D0);
2271 if (debug > 1)
2272 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
2273 dev->name, ret ? "failed" : "succeeded", ret);
2274
2275 pci_restore_state(pdev);
2276
2277 spin_lock_irqsave(&rp->lock, flags);
2278 #ifdef USE_MMIO
2279 enable_mmio(rp->pioaddr, rp->quirks);
2280 #endif
2281 rhine_power_init(dev);
2282 free_tbufs(dev);
2283 free_rbufs(dev);
2284 alloc_tbufs(dev);
2285 alloc_rbufs(dev);
2286 init_registers(dev);
2287 spin_unlock_irqrestore(&rp->lock, flags);
2288
2289 netif_device_attach(dev);
2290
2291 return 0;
2292 }
2293 #endif /* CONFIG_PM */
2294
2295 static struct pci_driver rhine_driver = {
2296 .name = DRV_NAME,
2297 .id_table = rhine_pci_tbl,
2298 .probe = rhine_init_one,
2299 .remove = __devexit_p(rhine_remove_one),
2300 #ifdef CONFIG_PM
2301 .suspend = rhine_suspend,
2302 .resume = rhine_resume,
2303 #endif /* CONFIG_PM */
2304 .shutdown = rhine_shutdown,
2305 };
2306
2307 static struct dmi_system_id __initdata rhine_dmi_table[] = {
2308 {
2309 .ident = "EPIA-M",
2310 .matches = {
2311 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2312 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2313 },
2314 },
2315 {
2316 .ident = "KV7",
2317 .matches = {
2318 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2319 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2320 },
2321 },
2322 { NULL }
2323 };
2324
2325 static int __init rhine_init(void)
2326 {
2327 /* when a module, this is printed whether or not devices are found in probe */
2328 #ifdef MODULE
2329 printk(version);
2330 #endif
2331 if (dmi_check_system(rhine_dmi_table)) {
2332 /* these BIOSes fail at PXE boot if chip is in D3 */
2333 avoid_D3 = 1;
2334 printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 "
2335 "enabled.\n",
2336 DRV_NAME);
2337 }
2338 else if (avoid_D3)
2339 printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME);
2340
2341 return pci_register_driver(&rhine_driver);
2342 }
2343
2344
2345 static void __exit rhine_cleanup(void)
2346 {
2347 pci_unregister_driver(&rhine_driver);
2348 }
2349
2350
2351 module_init(rhine_init);
2352 module_exit(rhine_cleanup);
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