1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
41 static s32
ixgbe_setup_copper_link_82598(struct ixgbe_hw
*hw
,
42 ixgbe_link_speed speed
,
44 bool autoneg_wait_to_complete
);
45 static s32
ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw
*hw
, u8 byte_offset
,
49 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
50 * @hw: pointer to the HW structure
52 * The defaults for 82598 should be in the range of 50us to 50ms,
53 * however the hardware default for these parts is 500us to 1ms which is less
54 * than the 10ms recommended by the pci-e spec. To address this we need to
55 * increase the value to either 10ms to 250ms for capability version 1 config,
56 * or 16ms to 55ms for version 2.
58 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw
*hw
)
60 struct ixgbe_adapter
*adapter
= hw
->back
;
61 u32 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR
);
64 /* only take action if timeout value is defaulted to 0 */
65 if (gcr
& IXGBE_GCR_CMPL_TMOUT_MASK
)
69 * if capababilities version is type 1 we can write the
70 * timeout of 10ms to 250ms through the GCR register
72 if (!(gcr
& IXGBE_GCR_CAP_VER2
)) {
73 gcr
|= IXGBE_GCR_CMPL_TMOUT_10ms
;
78 * for version 2 capabilities we need to write the config space
79 * directly in order to set the completion timeout value for
82 pci_read_config_word(adapter
->pdev
,
83 IXGBE_PCI_DEVICE_CONTROL2
, &pcie_devctl2
);
84 pcie_devctl2
|= IXGBE_PCI_DEVICE_CONTROL2_16ms
;
85 pci_write_config_word(adapter
->pdev
,
86 IXGBE_PCI_DEVICE_CONTROL2
, pcie_devctl2
);
88 /* disable completion timeout resend */
89 gcr
&= ~IXGBE_GCR_CMPL_TMOUT_RESEND
;
90 IXGBE_WRITE_REG(hw
, IXGBE_GCR
, gcr
);
94 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
95 * @hw: pointer to hardware structure
97 * Read PCIe configuration space, and get the MSI-X vector count from
98 * the capabilities table.
100 static u16
ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw
*hw
)
102 struct ixgbe_adapter
*adapter
= hw
->back
;
104 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82598_CAPS
,
106 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
108 /* MSI-X count is zero-based in HW, so increment to give proper value */
116 static s32
ixgbe_get_invariants_82598(struct ixgbe_hw
*hw
)
118 struct ixgbe_mac_info
*mac
= &hw
->mac
;
120 /* Call PHY identify routine to get the phy type */
121 ixgbe_identify_phy_generic(hw
);
123 mac
->mcft_size
= IXGBE_82598_MC_TBL_SIZE
;
124 mac
->vft_size
= IXGBE_82598_VFT_TBL_SIZE
;
125 mac
->num_rar_entries
= IXGBE_82598_RAR_ENTRIES
;
126 mac
->max_rx_queues
= IXGBE_82598_MAX_RX_QUEUES
;
127 mac
->max_tx_queues
= IXGBE_82598_MAX_TX_QUEUES
;
128 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_82598(hw
);
134 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
135 * @hw: pointer to hardware structure
137 * Initialize any function pointers that were not able to be
138 * set during get_invariants because the PHY/SFP type was
139 * not known. Perform the SFP init if necessary.
142 static s32
ixgbe_init_phy_ops_82598(struct ixgbe_hw
*hw
)
144 struct ixgbe_mac_info
*mac
= &hw
->mac
;
145 struct ixgbe_phy_info
*phy
= &hw
->phy
;
147 u16 list_offset
, data_offset
;
149 /* Identify the PHY */
150 phy
->ops
.identify(hw
);
152 /* Overwrite the link function pointers if copper PHY */
153 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
154 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82598
;
155 mac
->ops
.get_link_capabilities
=
156 &ixgbe_get_copper_link_capabilities_generic
;
159 switch (hw
->phy
.type
) {
161 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
162 phy
->ops
.get_firmware_version
=
163 &ixgbe_get_phy_firmware_version_tnx
;
166 phy
->ops
.reset
= &ixgbe_reset_phy_nl
;
168 /* Call SFP+ identify routine to get the SFP+ module type */
169 ret_val
= phy
->ops
.identify_sfp(hw
);
172 else if (hw
->phy
.sfp_type
== ixgbe_sfp_type_unknown
) {
173 ret_val
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
177 /* Check to see if SFP+ module is supported */
178 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
,
182 ret_val
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
195 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
196 * @hw: pointer to hardware structure
198 * Starts the hardware using the generic start_hw function.
199 * Then set pcie completion timeout
201 static s32
ixgbe_start_hw_82598(struct ixgbe_hw
*hw
)
205 ret_val
= ixgbe_start_hw_generic(hw
);
207 /* set the completion timeout for interface */
209 ixgbe_set_pcie_completion_timeout(hw
);
215 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
216 * @hw: pointer to hardware structure
217 * @speed: pointer to link speed
218 * @autoneg: boolean auto-negotiation value
220 * Determines the link capabilities by reading the AUTOC register.
222 static s32
ixgbe_get_link_capabilities_82598(struct ixgbe_hw
*hw
,
223 ixgbe_link_speed
*speed
,
230 * Determine link capabilities based on the stored value of AUTOC,
231 * which represents EEPROM defaults. If AUTOC value has not been
232 * stored, use the current register value.
234 if (hw
->mac
.orig_link_settings_stored
)
235 autoc
= hw
->mac
.orig_autoc
;
237 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
239 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
240 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
241 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
245 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
246 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
250 case IXGBE_AUTOC_LMS_1G_AN
:
251 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
255 case IXGBE_AUTOC_LMS_KX4_AN
:
256 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN
:
257 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
258 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
259 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
260 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
261 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
266 status
= IXGBE_ERR_LINK_SETUP
;
274 * ixgbe_get_media_type_82598 - Determines media type
275 * @hw: pointer to hardware structure
277 * Returns the media type (fiber, copper, backplane)
279 static enum ixgbe_media_type
ixgbe_get_media_type_82598(struct ixgbe_hw
*hw
)
281 enum ixgbe_media_type media_type
;
283 /* Media type for I82598 is based on device ID */
284 switch (hw
->device_id
) {
285 case IXGBE_DEV_ID_82598
:
286 case IXGBE_DEV_ID_82598_BX
:
287 media_type
= ixgbe_media_type_backplane
;
289 case IXGBE_DEV_ID_82598AF_DUAL_PORT
:
290 case IXGBE_DEV_ID_82598AF_SINGLE_PORT
:
291 case IXGBE_DEV_ID_82598_DA_DUAL_PORT
:
292 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
:
293 case IXGBE_DEV_ID_82598EB_XF_LR
:
294 case IXGBE_DEV_ID_82598EB_SFP_LOM
:
295 media_type
= ixgbe_media_type_fiber
;
297 case IXGBE_DEV_ID_82598EB_CX4
:
298 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT
:
299 media_type
= ixgbe_media_type_cx4
;
301 case IXGBE_DEV_ID_82598AT
:
302 case IXGBE_DEV_ID_82598AT2
:
303 media_type
= ixgbe_media_type_copper
;
306 media_type
= ixgbe_media_type_unknown
;
314 * ixgbe_fc_enable_82598 - Enable flow control
315 * @hw: pointer to hardware structure
316 * @packetbuf_num: packet buffer number (0-7)
318 * Enable flow control according to the current settings.
320 static s32
ixgbe_fc_enable_82598(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
331 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
)
334 #endif /* CONFIG_DCB */
336 * On 82598 having Rx FC on causes resets while doing 1G
337 * so if it's on turn it off once we know link_speed. For
338 * more details see 82598 Specification update.
340 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
341 if (link_up
&& link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) {
342 switch (hw
->fc
.requested_mode
) {
344 hw
->fc
.requested_mode
= ixgbe_fc_tx_pause
;
346 case ixgbe_fc_rx_pause
:
347 hw
->fc
.requested_mode
= ixgbe_fc_none
;
355 /* Negotiate the fc mode to use */
356 ret_val
= ixgbe_fc_autoneg(hw
);
360 /* Disable any previous flow control settings */
361 fctrl_reg
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
362 fctrl_reg
&= ~(IXGBE_FCTRL_RFCE
| IXGBE_FCTRL_RPFCE
);
364 rmcs_reg
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
365 rmcs_reg
&= ~(IXGBE_RMCS_TFCE_PRIORITY
| IXGBE_RMCS_TFCE_802_3X
);
368 * The possible values of fc.current_mode are:
369 * 0: Flow control is completely disabled
370 * 1: Rx flow control is enabled (we can receive pause frames,
371 * but not send pause frames).
372 * 2: Tx flow control is enabled (we can send pause frames but
373 * we do not support receiving pause frames).
374 * 3: Both Rx and Tx flow control (symmetric) are enabled.
377 * 4: Priority Flow Control is enabled.
380 switch (hw
->fc
.current_mode
) {
383 * Flow control is disabled by software override or autoneg.
384 * The code below will actually disable it in the HW.
387 case ixgbe_fc_rx_pause
:
389 * Rx Flow control is enabled and Tx Flow control is
390 * disabled by software override. Since there really
391 * isn't a way to advertise that we are capable of RX
392 * Pause ONLY, we will advertise that we support both
393 * symmetric and asymmetric Rx PAUSE. Later, we will
394 * disable the adapter's ability to send PAUSE frames.
396 fctrl_reg
|= IXGBE_FCTRL_RFCE
;
398 case ixgbe_fc_tx_pause
:
400 * Tx Flow control is enabled, and Rx Flow control is
401 * disabled by software override.
403 rmcs_reg
|= IXGBE_RMCS_TFCE_802_3X
;
406 /* Flow control (both Rx and Tx) is enabled by SW override. */
407 fctrl_reg
|= IXGBE_FCTRL_RFCE
;
408 rmcs_reg
|= IXGBE_RMCS_TFCE_802_3X
;
414 #endif /* CONFIG_DCB */
416 hw_dbg(hw
, "Flow control param set incorrectly\n");
417 ret_val
= IXGBE_ERR_CONFIG
;
422 /* Set 802.3x based flow control settings. */
423 fctrl_reg
|= IXGBE_FCTRL_DPF
;
424 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl_reg
);
425 IXGBE_WRITE_REG(hw
, IXGBE_RMCS
, rmcs_reg
);
427 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
428 if (hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) {
429 rx_pba_size
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(packetbuf_num
));
430 rx_pba_size
>>= IXGBE_RXPBSIZE_SHIFT
;
432 reg
= (rx_pba_size
- hw
->fc
.low_water
) << 6;
434 reg
|= IXGBE_FCRTL_XONE
;
435 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL(packetbuf_num
), reg
);
437 reg
= (rx_pba_size
- hw
->fc
.high_water
) << 10;
438 reg
|= IXGBE_FCRTH_FCEN
;
440 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH(packetbuf_num
), reg
);
443 /* Configure pause time (2 TCs per register) */
444 reg
= IXGBE_READ_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2));
445 if ((packetbuf_num
& 1) == 0)
446 reg
= (reg
& 0xFFFF0000) | hw
->fc
.pause_time
;
448 reg
= (reg
& 0x0000FFFF) | (hw
->fc
.pause_time
<< 16);
449 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2), reg
);
451 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, (hw
->fc
.pause_time
>> 1));
458 * ixgbe_start_mac_link_82598 - Configures MAC link settings
459 * @hw: pointer to hardware structure
461 * Configures link settings based on values in the ixgbe_hw struct.
462 * Restarts the link. Performs autonegotiation if needed.
464 static s32
ixgbe_start_mac_link_82598(struct ixgbe_hw
*hw
,
465 bool autoneg_wait_to_complete
)
473 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
474 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
475 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
477 /* Only poll for autoneg to complete if specified to do so */
478 if (autoneg_wait_to_complete
) {
479 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
480 IXGBE_AUTOC_LMS_KX4_AN
||
481 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
482 IXGBE_AUTOC_LMS_KX4_AN_1G_AN
) {
483 links_reg
= 0; /* Just in case Autoneg time = 0 */
484 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
485 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
486 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
490 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
491 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
492 hw_dbg(hw
, "Autonegotiation did not complete.\n");
497 /* Add delay to filter out noises during initial link setup */
504 * ixgbe_validate_link_ready - Function looks for phy link
505 * @hw: pointer to hardware structure
507 * Function indicates success when phy link is available. If phy is not ready
508 * within 5 seconds of MAC indicating link, the function returns error.
510 static s32
ixgbe_validate_link_ready(struct ixgbe_hw
*hw
)
515 if (hw
->device_id
!= IXGBE_DEV_ID_82598AT2
)
519 timeout
< IXGBE_VALIDATE_LINK_READY_TIMEOUT
; timeout
++) {
520 hw
->phy
.ops
.read_reg(hw
, MDIO_STAT1
, MDIO_MMD_AN
, &an_reg
);
522 if ((an_reg
& MDIO_AN_STAT1_COMPLETE
) &&
523 (an_reg
& MDIO_STAT1_LSTATUS
))
529 if (timeout
== IXGBE_VALIDATE_LINK_READY_TIMEOUT
) {
530 hw_dbg(hw
, "Link was indicated but link is down\n");
531 return IXGBE_ERR_LINK_SETUP
;
538 * ixgbe_check_mac_link_82598 - Get link/speed status
539 * @hw: pointer to hardware structure
540 * @speed: pointer to link speed
541 * @link_up: true is link is up, false otherwise
542 * @link_up_wait_to_complete: bool used to wait for link up or not
544 * Reads the links register to determine if link is up and the current speed
546 static s32
ixgbe_check_mac_link_82598(struct ixgbe_hw
*hw
,
547 ixgbe_link_speed
*speed
, bool *link_up
,
548 bool link_up_wait_to_complete
)
552 u16 link_reg
, adapt_comp_reg
;
555 * SERDES PHY requires us to read link status from register 0xC79F.
556 * Bit 0 set indicates link is up/ready; clear indicates link down.
557 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
558 * clear indicates active; set indicates inactive.
560 if (hw
->phy
.type
== ixgbe_phy_nl
) {
561 hw
->phy
.ops
.read_reg(hw
, 0xC79F, MDIO_MMD_PMAPMD
, &link_reg
);
562 hw
->phy
.ops
.read_reg(hw
, 0xC79F, MDIO_MMD_PMAPMD
, &link_reg
);
563 hw
->phy
.ops
.read_reg(hw
, 0xC00C, MDIO_MMD_PMAPMD
,
565 if (link_up_wait_to_complete
) {
566 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
567 if ((link_reg
& 1) &&
568 ((adapt_comp_reg
& 1) == 0)) {
575 hw
->phy
.ops
.read_reg(hw
, 0xC79F,
578 hw
->phy
.ops
.read_reg(hw
, 0xC00C,
583 if ((link_reg
& 1) && ((adapt_comp_reg
& 1) == 0))
589 if (*link_up
== false)
593 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
594 if (link_up_wait_to_complete
) {
595 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
596 if (links_reg
& IXGBE_LINKS_UP
) {
603 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
606 if (links_reg
& IXGBE_LINKS_UP
)
612 if (links_reg
& IXGBE_LINKS_SPEED
)
613 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
615 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
617 if ((hw
->device_id
== IXGBE_DEV_ID_82598AT2
) && (*link_up
== true) &&
618 (ixgbe_validate_link_ready(hw
) != 0))
621 /* if link is down, zero out the current_mode */
622 if (*link_up
== false) {
623 hw
->fc
.current_mode
= ixgbe_fc_none
;
624 hw
->fc
.fc_was_autonegged
= false;
632 * ixgbe_setup_mac_link_82598 - Set MAC link speed
633 * @hw: pointer to hardware structure
634 * @speed: new link speed
635 * @autoneg: true if auto-negotiation enabled
636 * @autoneg_wait_to_complete: true if waiting is needed to complete
638 * Set the link speed in the AUTOC register and restarts link.
640 static s32
ixgbe_setup_mac_link_82598(struct ixgbe_hw
*hw
,
641 ixgbe_link_speed speed
, bool autoneg
,
642 bool autoneg_wait_to_complete
)
645 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
646 u32 curr_autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
647 u32 autoc
= curr_autoc
;
648 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
650 /* Check to see if speed passed in is supported. */
651 ixgbe_get_link_capabilities_82598(hw
, &link_capabilities
, &autoneg
);
652 speed
&= link_capabilities
;
654 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
)
655 status
= IXGBE_ERR_LINK_SETUP
;
657 /* Set KX4/KX support according to speed requested */
658 else if (link_mode
== IXGBE_AUTOC_LMS_KX4_AN
||
659 link_mode
== IXGBE_AUTOC_LMS_KX4_AN_1G_AN
) {
660 autoc
&= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK
;
661 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
662 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
663 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
664 autoc
|= IXGBE_AUTOC_KX_SUPP
;
665 if (autoc
!= curr_autoc
)
666 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
671 * Setup and restart the link based on the new values in
672 * ixgbe_hw This will write the AUTOC register based on the new
675 status
= ixgbe_start_mac_link_82598(hw
, autoneg_wait_to_complete
);
683 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
684 * @hw: pointer to hardware structure
685 * @speed: new link speed
686 * @autoneg: true if autonegotiation enabled
687 * @autoneg_wait_to_complete: true if waiting is needed to complete
689 * Sets the link speed in the AUTOC register in the MAC and restarts link.
691 static s32
ixgbe_setup_copper_link_82598(struct ixgbe_hw
*hw
,
692 ixgbe_link_speed speed
,
694 bool autoneg_wait_to_complete
)
698 /* Setup the PHY according to input speed */
699 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
700 autoneg_wait_to_complete
);
703 ixgbe_start_mac_link_82598(hw
, autoneg_wait_to_complete
);
709 * ixgbe_reset_hw_82598 - Performs hardware reset
710 * @hw: pointer to hardware structure
712 * Resets the hardware by resetting the transmit and receive units, masks and
713 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
716 static s32
ixgbe_reset_hw_82598(struct ixgbe_hw
*hw
)
726 /* Call adapter stop to disable tx/rx and clear interrupts */
727 hw
->mac
.ops
.stop_adapter(hw
);
730 * Power up the Atlas Tx lanes if they are currently powered down.
731 * Atlas Tx lanes are powered down for MAC loopback tests, but
732 * they are not automatically restored on reset.
734 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_LPBK
, &analog_val
);
735 if (analog_val
& IXGBE_ATLAS_PDN_TX_REG_EN
) {
736 /* Enable Tx Atlas so packets can be transmitted again */
737 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_LPBK
,
739 analog_val
&= ~IXGBE_ATLAS_PDN_TX_REG_EN
;
740 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_LPBK
,
743 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_10G
,
745 analog_val
&= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL
;
746 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_10G
,
749 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_1G
,
751 analog_val
&= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL
;
752 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_1G
,
755 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_AN
,
757 analog_val
&= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL
;
758 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_AN
,
763 if (hw
->phy
.reset_disable
== false) {
764 /* PHY ops must be identified and initialized prior to reset */
766 /* Init PHY and function pointers, perform SFP setup */
767 phy_status
= hw
->phy
.ops
.init(hw
);
768 if (phy_status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
770 else if (phy_status
== IXGBE_ERR_SFP_NOT_PRESENT
)
773 hw
->phy
.ops
.reset(hw
);
778 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
779 * access and verify no pending requests before reset
781 ixgbe_disable_pcie_master(hw
);
785 * Issue global reset to the MAC. This needs to be a SW reset.
786 * If link reset is used, it might reset the MAC when mng is using it
788 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
789 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
790 IXGBE_WRITE_FLUSH(hw
);
792 /* Poll for reset bit to self-clear indicating reset is complete */
793 for (i
= 0; i
< 10; i
++) {
795 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
796 if (!(ctrl
& IXGBE_CTRL_RST
))
799 if (ctrl
& IXGBE_CTRL_RST
) {
800 status
= IXGBE_ERR_RESET_FAILED
;
801 hw_dbg(hw
, "Reset polling failed to complete.\n");
805 * Double resets are required for recovery from certain error
806 * conditions. Between resets, it is necessary to stall to allow time
807 * for any pending HW events to complete. We use 1usec since that is
808 * what is needed for ixgbe_disable_pcie_master(). The second reset
809 * then clears out any effects of those events.
811 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
812 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
819 gheccr
= IXGBE_READ_REG(hw
, IXGBE_GHECCR
);
820 gheccr
&= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
821 IXGBE_WRITE_REG(hw
, IXGBE_GHECCR
, gheccr
);
824 * Store the original AUTOC value if it has not been
825 * stored off yet. Otherwise restore the stored original
826 * AUTOC value since the reset operation sets back to deaults.
828 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
829 if (hw
->mac
.orig_link_settings_stored
== false) {
830 hw
->mac
.orig_autoc
= autoc
;
831 hw
->mac
.orig_link_settings_stored
= true;
832 } else if (autoc
!= hw
->mac
.orig_autoc
) {
833 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, hw
->mac
.orig_autoc
);
837 * Store MAC address from RAR0, clear receive address registers, and
838 * clear the multicast table
840 hw
->mac
.ops
.init_rx_addrs(hw
);
842 /* Store the permanent mac address */
843 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
853 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
854 * @hw: pointer to hardware struct
855 * @rar: receive address register index to associate with a VMDq index
856 * @vmdq: VMDq set index
858 static s32
ixgbe_set_vmdq_82598(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
862 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(rar
));
863 rar_high
&= ~IXGBE_RAH_VIND_MASK
;
864 rar_high
|= ((vmdq
<< IXGBE_RAH_VIND_SHIFT
) & IXGBE_RAH_VIND_MASK
);
865 IXGBE_WRITE_REG(hw
, IXGBE_RAH(rar
), rar_high
);
870 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
871 * @hw: pointer to hardware struct
872 * @rar: receive address register index to associate with a VMDq index
873 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
875 static s32
ixgbe_clear_vmdq_82598(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
878 u32 rar_entries
= hw
->mac
.num_rar_entries
;
880 if (rar
< rar_entries
) {
881 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(rar
));
882 if (rar_high
& IXGBE_RAH_VIND_MASK
) {
883 rar_high
&= ~IXGBE_RAH_VIND_MASK
;
884 IXGBE_WRITE_REG(hw
, IXGBE_RAH(rar
), rar_high
);
887 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
894 * ixgbe_set_vfta_82598 - Set VLAN filter table
895 * @hw: pointer to hardware structure
896 * @vlan: VLAN id to write to VLAN filter
897 * @vind: VMDq output index that maps queue to VLAN id in VFTA
898 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
900 * Turn on/off specified VLAN in the VLAN filter table.
902 static s32
ixgbe_set_vfta_82598(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
911 return IXGBE_ERR_PARAM
;
913 /* Determine 32-bit word position in array */
914 regindex
= (vlan
>> 5) & 0x7F; /* upper seven bits */
916 /* Determine the location of the (VMD) queue index */
917 vftabyte
= ((vlan
>> 3) & 0x03); /* bits (4:3) indicating byte array */
918 bitindex
= (vlan
& 0x7) << 2; /* lower 3 bits indicate nibble */
920 /* Set the nibble for VMD queue index */
921 bits
= IXGBE_READ_REG(hw
, IXGBE_VFTAVIND(vftabyte
, regindex
));
922 bits
&= (~(0x0F << bitindex
));
923 bits
|= (vind
<< bitindex
);
924 IXGBE_WRITE_REG(hw
, IXGBE_VFTAVIND(vftabyte
, regindex
), bits
);
926 /* Determine the location of the bit for this VLAN id */
927 bitindex
= vlan
& 0x1F; /* lower five bits */
929 bits
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
931 /* Turn on this VLAN id */
932 bits
|= (1 << bitindex
);
934 /* Turn off this VLAN id */
935 bits
&= ~(1 << bitindex
);
936 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), bits
);
942 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
943 * @hw: pointer to hardware structure
945 * Clears the VLAN filer table, and the VMDq index associated with the filter
947 static s32
ixgbe_clear_vfta_82598(struct ixgbe_hw
*hw
)
952 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
953 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
955 for (vlanbyte
= 0; vlanbyte
< 4; vlanbyte
++)
956 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
957 IXGBE_WRITE_REG(hw
, IXGBE_VFTAVIND(vlanbyte
, offset
),
964 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
965 * @hw: pointer to hardware structure
966 * @reg: analog register to read
969 * Performs read operation to Atlas analog register specified.
971 static s32
ixgbe_read_analog_reg8_82598(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
975 IXGBE_WRITE_REG(hw
, IXGBE_ATLASCTL
,
976 IXGBE_ATLASCTL_WRITE_CMD
| (reg
<< 8));
977 IXGBE_WRITE_FLUSH(hw
);
979 atlas_ctl
= IXGBE_READ_REG(hw
, IXGBE_ATLASCTL
);
980 *val
= (u8
)atlas_ctl
;
986 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
987 * @hw: pointer to hardware structure
988 * @reg: atlas register to write
989 * @val: value to write
991 * Performs write operation to Atlas analog register specified.
993 static s32
ixgbe_write_analog_reg8_82598(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
997 atlas_ctl
= (reg
<< 8) | val
;
998 IXGBE_WRITE_REG(hw
, IXGBE_ATLASCTL
, atlas_ctl
);
999 IXGBE_WRITE_FLUSH(hw
);
1006 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
1007 * over I2C interface through an intermediate phy.
1008 * @hw: pointer to hardware structure
1009 * @byte_offset: EEPROM byte offset to read
1010 * @eeprom_data: value read
1012 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1014 static s32
ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw
*hw
, u8 byte_offset
,
1023 if (hw
->phy
.type
== ixgbe_phy_nl
) {
1025 * phy SDA/SCL registers are at addresses 0xC30A to
1026 * 0xC30D. These registers are used to talk to the SFP+
1027 * module's EEPROM through the SDA/SCL (I2C) interface.
1029 sfp_addr
= (IXGBE_I2C_EEPROM_DEV_ADDR
<< 8) + byte_offset
;
1030 sfp_addr
= (sfp_addr
| IXGBE_I2C_EEPROM_READ_MASK
);
1031 hw
->phy
.ops
.write_reg(hw
,
1032 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR
,
1037 for (i
= 0; i
< 100; i
++) {
1038 hw
->phy
.ops
.read_reg(hw
,
1039 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT
,
1042 sfp_stat
= sfp_stat
& IXGBE_I2C_EEPROM_STATUS_MASK
;
1043 if (sfp_stat
!= IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS
)
1048 if (sfp_stat
!= IXGBE_I2C_EEPROM_STATUS_PASS
) {
1049 hw_dbg(hw
, "EEPROM read did not pass.\n");
1050 status
= IXGBE_ERR_SFP_NOT_PRESENT
;
1055 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA
,
1056 MDIO_MMD_PMAPMD
, &sfp_data
);
1058 *eeprom_data
= (u8
)(sfp_data
>> 8);
1060 status
= IXGBE_ERR_PHY
;
1069 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1070 * @hw: pointer to hardware structure
1072 * Determines physical layer capabilities of the current configuration.
1074 static u32
ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw
*hw
)
1076 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1077 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1078 u32 pma_pmd_10g
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1079 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1080 u16 ext_ability
= 0;
1082 hw
->phy
.ops
.identify(hw
);
1084 /* Copper PHY must be checked before AUTOC LMS to determine correct
1085 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1086 if (hw
->phy
.type
== ixgbe_phy_tn
||
1087 hw
->phy
.type
== ixgbe_phy_cu_unknown
) {
1088 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1090 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1091 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1092 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1093 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1094 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1095 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1099 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1100 case IXGBE_AUTOC_LMS_1G_AN
:
1101 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1102 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX
)
1103 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1105 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1107 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1108 if (pma_pmd_10g
== IXGBE_AUTOC_10G_CX4
)
1109 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1110 else if (pma_pmd_10g
== IXGBE_AUTOC_10G_KX4
)
1111 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1113 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1115 case IXGBE_AUTOC_LMS_KX4_AN
:
1116 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN
:
1117 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1118 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1119 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1120 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1126 if (hw
->phy
.type
== ixgbe_phy_nl
) {
1127 hw
->phy
.ops
.identify_sfp(hw
);
1129 switch (hw
->phy
.sfp_type
) {
1130 case ixgbe_sfp_type_da_cu
:
1131 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1133 case ixgbe_sfp_type_sr
:
1134 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1136 case ixgbe_sfp_type_lr
:
1137 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1140 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1145 switch (hw
->device_id
) {
1146 case IXGBE_DEV_ID_82598_DA_DUAL_PORT
:
1147 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1149 case IXGBE_DEV_ID_82598AF_DUAL_PORT
:
1150 case IXGBE_DEV_ID_82598AF_SINGLE_PORT
:
1151 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
:
1152 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1154 case IXGBE_DEV_ID_82598EB_XF_LR
:
1155 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1162 return physical_layer
;
1165 static struct ixgbe_mac_operations mac_ops_82598
= {
1166 .init_hw
= &ixgbe_init_hw_generic
,
1167 .reset_hw
= &ixgbe_reset_hw_82598
,
1168 .start_hw
= &ixgbe_start_hw_82598
,
1169 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
1170 .get_media_type
= &ixgbe_get_media_type_82598
,
1171 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82598
,
1172 .enable_rx_dma
= &ixgbe_enable_rx_dma_generic
,
1173 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
1174 .stop_adapter
= &ixgbe_stop_adapter_generic
,
1175 .get_bus_info
= &ixgbe_get_bus_info_generic
,
1176 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
1177 .read_analog_reg8
= &ixgbe_read_analog_reg8_82598
,
1178 .write_analog_reg8
= &ixgbe_write_analog_reg8_82598
,
1179 .setup_link
= &ixgbe_setup_mac_link_82598
,
1180 .check_link
= &ixgbe_check_mac_link_82598
,
1181 .get_link_capabilities
= &ixgbe_get_link_capabilities_82598
,
1182 .led_on
= &ixgbe_led_on_generic
,
1183 .led_off
= &ixgbe_led_off_generic
,
1184 .blink_led_start
= &ixgbe_blink_led_start_generic
,
1185 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
1186 .set_rar
= &ixgbe_set_rar_generic
,
1187 .clear_rar
= &ixgbe_clear_rar_generic
,
1188 .set_vmdq
= &ixgbe_set_vmdq_82598
,
1189 .clear_vmdq
= &ixgbe_clear_vmdq_82598
,
1190 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
1191 .update_uc_addr_list
= &ixgbe_update_uc_addr_list_generic
,
1192 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
1193 .enable_mc
= &ixgbe_enable_mc_generic
,
1194 .disable_mc
= &ixgbe_disable_mc_generic
,
1195 .clear_vfta
= &ixgbe_clear_vfta_82598
,
1196 .set_vfta
= &ixgbe_set_vfta_82598
,
1197 .fc_enable
= &ixgbe_fc_enable_82598
,
1200 static struct ixgbe_eeprom_operations eeprom_ops_82598
= {
1201 .init_params
= &ixgbe_init_eeprom_params_generic
,
1202 .read
= &ixgbe_read_eerd_generic
,
1203 .calc_checksum
= &ixgbe_calc_eeprom_checksum_generic
,
1204 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
1205 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
1208 static struct ixgbe_phy_operations phy_ops_82598
= {
1209 .identify
= &ixgbe_identify_phy_generic
,
1210 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
1211 .init
= &ixgbe_init_phy_ops_82598
,
1212 .reset
= &ixgbe_reset_phy_generic
,
1213 .read_reg
= &ixgbe_read_phy_reg_generic
,
1214 .write_reg
= &ixgbe_write_phy_reg_generic
,
1215 .setup_link
= &ixgbe_setup_phy_link_generic
,
1216 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
1217 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_82598
,
1218 .check_overtemp
= &ixgbe_tn_check_overtemp
,
1221 struct ixgbe_info ixgbe_82598_info
= {
1222 .mac
= ixgbe_mac_82598EB
,
1223 .get_invariants
= &ixgbe_get_invariants_82598
,
1224 .mac_ops
= &mac_ops_82598
,
1225 .eeprom_ops
= &eeprom_ops_82598
,
1226 .phy_ops
= &phy_ops_82598
,