drivers/net/wireless/wl12xx/boot.h

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2009 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #ifndef __BOOT_H__
  25 #define __BOOT_H__
  26
  27 #include "wl12xx.h"
  28
  29 int wl1271_boot(struct wl1271 *wl);
  30 int wl1271_load_firmware(struct wl1271 *wl);
  31
  32 #define WL1271_NO_SUBBANDS 8
  33 #define WL1271_NO_POWER_LEVELS 4
  34 #define WL1271_FW_VERSION_MAX_LEN 20
  35
  36 struct wl1271_static_data {
  37         u8 mac_address[ETH_ALEN];
  38         u8 padding[2];
  39         u8 fw_version[WL1271_FW_VERSION_MAX_LEN];
  40         u32 hw_version;
  41         u8 tx_power_table[WL1271_NO_SUBBANDS][WL1271_NO_POWER_LEVELS];
  42 };
  43
  44 /* number of times we try to read the INIT interrupt */
  45 #define INIT_LOOP 20000
  46
  47 /* delay between retries */
  48 #define INIT_LOOP_DELAY 50
  49
  50 #define WU_COUNTER_PAUSE_VAL 0x3FF
  51 #define WELP_ARM_COMMAND_VAL 0x4
  52
  53 #define OCP_REG_POLARITY     0x0064
  54 #define OCP_REG_CLK_TYPE     0x0448
  55 #define OCP_REG_CLK_POLARITY 0x0cb2
  56 #define OCP_REG_CLK_PULL     0x0cb4
  57
  58 #define REG_FUSE_DATA_2_1    0x050a
  59 #define PG_VER_MASK          0x3c
  60 #define PG_VER_OFFSET        2
  61
  62 #define PG_MAJOR_VER_MASK    0x3
  63 #define PG_MAJOR_VER_OFFSET  0x0
  64 #define PG_MINOR_VER_MASK    0xc
  65 #define PG_MINOR_VER_OFFSET  0x2
  66
  67 #define CMD_MBOX_ADDRESS     0x407B4
  68
  69 #define POLARITY_LOW         BIT(1)
  70 #define NO_PULL              (BIT(14) | BIT(15))
  71
  72 #define FREF_CLK_TYPE_BITS     0xfffffe7f
  73 #define CLK_REQ_PRCM           0x100
  74 #define FREF_CLK_POLARITY_BITS 0xfffff8ff
  75 #define CLK_REQ_OUTN_SEL       0x700
  76
  77 /* PLL configuration algorithm for wl128x */
  78 #define SYS_CLK_CFG_REG              0x2200
  79 /* Bit[0]   -  0-TCXO,  1-FREF */
  80 #define MCS_PLL_CLK_SEL_FREF         BIT(0)
  81 /* Bit[3:2] - 01-TCXO, 10-FREF */
  82 #define WL_CLK_REQ_TYPE_FREF         BIT(3)
  83 #define WL_CLK_REQ_TYPE_PG2          (BIT(3) | BIT(2))
  84 /* Bit[4]   -  0-TCXO,  1-FREF */
  85 #define PRCM_CM_EN_MUX_WLAN_FREF     BIT(4)
  86
  87 #define TCXO_ILOAD_INT_REG           0x2264
  88 #define TCXO_CLK_DETECT_REG          0x2266
  89
  90 #define TCXO_DET_FAILED              BIT(4)
  91
  92 #define FREF_ILOAD_INT_REG           0x2084
  93 #define FREF_CLK_DETECT_REG          0x2086
  94 #define FREF_CLK_DETECT_FAIL         BIT(4)
  95
  96 /* Use this reg for masking during driver access */
  97 #define WL_SPARE_REG                 0x2320
  98 #define WL_SPARE_VAL                 BIT(2)
  99 /* Bit[6:5:3] -  mask wl write SYS_CLK_CFG[8:5:2:4] */
 100 #define WL_SPARE_MASK_8526           (BIT(6) | BIT(5) | BIT(3))
 101
 102 #define PLL_LOCK_COUNTERS_REG        0xD8C
 103 #define PLL_LOCK_COUNTERS_COEX       0x0F
 104 #define PLL_LOCK_COUNTERS_MCS        0xF0
 105 #define MCS_PLL_OVERRIDE_REG         0xD90
 106 #define MCS_PLL_CONFIG_REG           0xD92
 107 #define MCS_SEL_IN_FREQ_MASK         0x0070
 108 #define MCS_SEL_IN_FREQ_SHIFT        4
 109 #define MCS_PLL_CONFIG_REG_VAL       0x73
 110 #define MCS_PLL_ENABLE_HP            (BIT(0) | BIT(1))
 111
 112 #define MCS_PLL_M_REG                0xD94
 113 #define MCS_PLL_N_REG                0xD96
 114 #define MCS_PLL_M_REG_VAL            0xC8
 115 #define MCS_PLL_N_REG_VAL            0x07
 116
 117 #define SDIO_IO_DS                   0xd14
 118
 119 /* SDIO/wSPI DS configuration values */
 120 enum {
 121         HCI_IO_DS_8MA = 0,
 122         HCI_IO_DS_4MA = 1, /* default */
 123         HCI_IO_DS_6MA = 2,
 124         HCI_IO_DS_2MA = 3,
 125 };
 126
 127 /* end PLL configuration algorithm for wl128x */
 128
 129 #endif