2 * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
4 * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
18 #include <linux/miscdevice.h>
19 #include <linux/init.h>
20 #include <linux/ioport.h>
21 #include <linux/watchdog.h>
23 #include <linux/uaccess.h>
25 #include <linux/of_device.h>
26 #include <linux/of_address.h>
28 /* Register offsets for the Wdt device */
29 #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
30 #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
31 #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
33 /* Control/Status Register Masks */
34 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */
35 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */
36 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
38 /* Control/Status Register 0/1 bits */
39 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
41 /* SelfTest constants */
42 #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
43 #define XWT_TIMER_FAILED 0xFFFFFFFF
45 #define WATCHDOG_NAME "Xilinx Watchdog"
46 #define PFX WATCHDOG_NAME ": "
56 static struct xwdt_device xdev
;
59 static u32 control_status_reg
;
60 static u8 expect_close
;
62 static unsigned long driver_open
;
64 static DEFINE_SPINLOCK(spinlock
);
66 static void xwdt_start(void)
70 /* Clean previous status and enable the watchdog timer */
71 control_status_reg
= ioread32(xdev
.base
+ XWT_TWCSR0_OFFSET
);
72 control_status_reg
|= (XWT_CSR0_WRS_MASK
| XWT_CSR0_WDS_MASK
);
74 iowrite32((control_status_reg
| XWT_CSR0_EWDT1_MASK
),
75 xdev
.base
+ XWT_TWCSR0_OFFSET
);
77 iowrite32(XWT_CSRX_EWDT2_MASK
, xdev
.base
+ XWT_TWCSR1_OFFSET
);
79 spin_unlock(&spinlock
);
82 static void xwdt_stop(void)
86 control_status_reg
= ioread32(xdev
.base
+ XWT_TWCSR0_OFFSET
);
88 iowrite32((control_status_reg
& ~XWT_CSR0_EWDT1_MASK
),
89 xdev
.base
+ XWT_TWCSR0_OFFSET
);
91 iowrite32(0, xdev
.base
+ XWT_TWCSR1_OFFSET
);
93 spin_unlock(&spinlock
);
94 pr_info("Stopped!\n");
97 static void xwdt_keepalive(void)
101 control_status_reg
= ioread32(xdev
.base
+ XWT_TWCSR0_OFFSET
);
102 control_status_reg
|= (XWT_CSR0_WRS_MASK
| XWT_CSR0_WDS_MASK
);
103 iowrite32(control_status_reg
, xdev
.base
+ XWT_TWCSR0_OFFSET
);
105 spin_unlock(&spinlock
);
108 static void xwdt_get_status(int *status
)
112 spin_lock(&spinlock
);
114 control_status_reg
= ioread32(xdev
.base
+ XWT_TWCSR0_OFFSET
);
115 new_status
= ((control_status_reg
&
116 (XWT_CSR0_WRS_MASK
| XWT_CSR0_WDS_MASK
)) != 0);
117 spin_unlock(&spinlock
);
121 *status
|= WDIOF_CARDRESET
;
124 static u32
xwdt_selftest(void)
130 spin_lock(&spinlock
);
132 timer_value1
= ioread32(xdev
.base
+ XWT_TBR_OFFSET
);
133 timer_value2
= ioread32(xdev
.base
+ XWT_TBR_OFFSET
);
136 ((i
<= XWT_MAX_SELFTEST_LOOP_COUNT
) &&
137 (timer_value2
== timer_value1
)); i
++) {
138 timer_value2
= ioread32(xdev
.base
+ XWT_TBR_OFFSET
);
141 spin_unlock(&spinlock
);
143 if (timer_value2
!= timer_value1
)
144 return ~XWT_TIMER_FAILED
;
146 return XWT_TIMER_FAILED
;
149 static int xwdt_open(struct inode
*inode
, struct file
*file
)
151 /* Only one process can handle the wdt at a time */
152 if (test_and_set_bit(0, &driver_open
))
155 /* Make sure that the module are always loaded...*/
157 __module_get(THIS_MODULE
);
160 pr_info("Started...\n");
162 return nonseekable_open(inode
, file
);
165 static int xwdt_release(struct inode
*inode
, struct file
*file
)
167 if (expect_close
== 42) {
170 pr_crit("Unexpected close, not stopping watchdog!\n");
174 clear_bit(0, &driver_open
);
181 * @file: file handle to the watchdog
182 * @buf: buffer to write (unused as data does not matter here
183 * @count: count of bytes
184 * @ppos: pointer to the position to write. No seeks allowed
186 * A write to a watchdog device is defined as a keepalive signal. Any
187 * write of data will do, as we don't define content meaning.
189 static ssize_t
xwdt_write(struct file
*file
, const char __user
*buf
,
190 size_t len
, loff_t
*ppos
)
193 if (!xdev
.nowayout
) {
196 /* In case it was set long ago */
199 for (i
= 0; i
!= len
; i
++) {
202 if (get_user(c
, buf
+ i
))
213 static const struct watchdog_info ident
= {
214 .options
= WDIOF_MAGICCLOSE
|
216 .firmware_version
= 1,
217 .identity
= WATCHDOG_NAME
,
222 * @file: file handle to the device
223 * @cmd: watchdog command
224 * @arg: argument pointer
226 * The watchdog API defines a common set of functions for all watchdogs
227 * according to their available features.
229 static long xwdt_ioctl(struct file
*file
, unsigned int cmd
, unsigned long arg
)
234 struct watchdog_info __user
*ident
;
238 uarg
.i
= (int __user
*)arg
;
241 case WDIOC_GETSUPPORT
:
242 return copy_to_user(uarg
.ident
, &ident
,
243 sizeof(ident
)) ? -EFAULT
: 0;
245 case WDIOC_GETBOOTSTATUS
:
246 return put_user(xdev
.boot_status
, uarg
.i
);
248 case WDIOC_GETSTATUS
:
249 xwdt_get_status(&status
);
250 return put_user(status
, uarg
.i
);
252 case WDIOC_KEEPALIVE
:
256 case WDIOC_GETTIMEOUT
:
260 return put_user(timeout
, uarg
.i
);
267 static const struct file_operations xwdt_fops
= {
268 .owner
= THIS_MODULE
,
272 .release
= xwdt_release
,
273 .unlocked_ioctl
= xwdt_ioctl
,
276 static struct miscdevice xwdt_miscdev
= {
277 .minor
= WATCHDOG_MINOR
,
282 static int xwdt_probe(struct platform_device
*pdev
)
290 pfreq
= (u32
*)of_get_property(pdev
->dev
.of_node
,
291 "clock-frequency", NULL
);
294 pr_warn("The watchdog clock frequency cannot be obtained!\n");
298 rc
= of_address_to_resource(pdev
->dev
.of_node
, 0, &xdev
.res
);
300 pr_warn("invalid address!\n");
304 tmptr
= (u32
*)of_get_property(pdev
->dev
.of_node
,
305 "xlnx,wdt-interval", NULL
);
307 pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
310 xdev
.wdt_interval
= *tmptr
;
313 tmptr
= (u32
*)of_get_property(pdev
->dev
.of_node
,
314 "xlnx,wdt-enable-once", NULL
);
316 pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
317 xdev
.nowayout
= WATCHDOG_NOWAYOUT
;
321 * Twice of the 2^wdt_interval / freq because the first wdt overflow is
322 * ignored (interrupt), reset is only generated at second wdt overflow
325 timeout
= 2 * ((1<<xdev
.wdt_interval
) / *pfreq
);
327 if (!request_mem_region(xdev
.res
.start
,
328 xdev
.res
.end
- xdev
.res
.start
+ 1, WATCHDOG_NAME
)) {
330 pr_err("memory request failure!\n");
334 xdev
.base
= ioremap(xdev
.res
.start
, xdev
.res
.end
- xdev
.res
.start
+ 1);
335 if (xdev
.base
== NULL
) {
337 pr_err("ioremap failure!\n");
341 rc
= xwdt_selftest();
342 if (rc
== XWT_TIMER_FAILED
) {
343 pr_err("SelfTest routine error!\n");
347 xwdt_get_status(&xdev
.boot_status
);
349 rc
= misc_register(&xwdt_miscdev
);
351 pr_err("cannot register miscdev on minor=%d (err=%d)\n",
352 xwdt_miscdev
.minor
, rc
);
357 pr_info("driver loaded (timeout=? sec, nowayout=%d)\n",
360 pr_info("driver loaded (timeout=%d sec, nowayout=%d)\n",
361 timeout
, xdev
.nowayout
);
364 clear_bit(0, &driver_open
);
371 release_mem_region(xdev
.res
.start
, resource_size(&xdev
.res
));
376 static int xwdt_remove(struct platform_device
*dev
)
378 misc_deregister(&xwdt_miscdev
);
380 release_mem_region(xdev
.res
.start
, resource_size(&xdev
.res
));
385 /* Match table for of_platform binding */
386 static struct of_device_id xwdt_of_match
[] = {
387 { .compatible
= "xlnx,xps-timebase-wdt-1.00.a", },
388 { .compatible
= "xlnx,xps-timebase-wdt-1.01.a", },
391 MODULE_DEVICE_TABLE(of
, xwdt_of_match
);
393 static struct platform_driver xwdt_driver
= {
395 .remove
= xwdt_remove
,
397 .owner
= THIS_MODULE
,
398 .name
= WATCHDOG_NAME
,
399 .of_match_table
= xwdt_of_match
,
403 module_platform_driver(xwdt_driver
);
405 MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
406 MODULE_DESCRIPTION("Xilinx Watchdog driver");
407 MODULE_LICENSE("GPL v2");