2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 #include <linux/types.h>
12 #include <linux/kconfig.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 #include <linux/acpi.h>
19 #include <linux/dmi.h>
20 #include "pci-quirks.h"
21 #include "xhci-ext-caps.h"
24 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
25 #define UHCI_USBCMD 0 /* command register */
26 #define UHCI_USBINTR 4 /* interrupt register */
27 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
28 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
29 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
30 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
31 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
32 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
33 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
35 #define OHCI_CONTROL 0x04
36 #define OHCI_CMDSTATUS 0x08
37 #define OHCI_INTRSTATUS 0x0c
38 #define OHCI_INTRENABLE 0x10
39 #define OHCI_INTRDISABLE 0x14
40 #define OHCI_FMINTERVAL 0x34
41 #define OHCI_HCFS (3 << 6) /* hc functional state */
42 #define OHCI_HCR (1 << 0) /* host controller reset */
43 #define OHCI_OCR (1 << 3) /* ownership change request */
44 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
45 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
46 #define OHCI_INTR_OC (1 << 30) /* ownership change */
48 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
49 #define EHCI_USBCMD 0 /* command register */
50 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
51 #define EHCI_USBSTS 4 /* status register */
52 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
53 #define EHCI_USBINTR 8 /* interrupt register */
54 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */
55 #define EHCI_USBLEGSUP 0 /* legacy support register */
56 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
57 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
58 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
59 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
62 #define AB_REG_BAR_LOW 0xe0
63 #define AB_REG_BAR_HIGH 0xe1
64 #define AB_REG_BAR_SB700 0xf0
65 #define AB_INDX(addr) ((addr) + 0x00)
66 #define AB_DATA(addr) ((addr) + 0x04)
70 #define NB_PCIE_INDX_ADDR 0xe0
71 #define NB_PCIE_INDX_DATA 0xe4
72 #define PCIE_P_CNTL 0x10040
73 #define BIF_NB 0x10002
74 #define NB_PIF0_PWRDOWN_0 0x01100012
75 #define NB_PIF0_PWRDOWN_1 0x01100013
77 #define USB_INTEL_XUSB2PR 0xD0
78 #define USB_INTEL_USB2PRM 0xD4
79 #define USB_INTEL_USB3_PSSEN 0xD8
80 #define USB_INTEL_USB3PRM 0xDC
83 * amd_chipset_gen values represent AMD different chipset generations
85 enum amd_chipset_gen
{
96 struct amd_chipset_type
{
97 enum amd_chipset_gen gen
;
101 static struct amd_chipset_info
{
102 struct pci_dev
*nb_dev
;
103 struct pci_dev
*smbus_dev
;
105 struct amd_chipset_type sb_type
;
111 static DEFINE_SPINLOCK(amd_lock
);
114 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
116 * AMD FCH/SB generation and revision is identified by SMBus controller
117 * vendor, device and revision IDs.
119 * Returns: 1 if it is an AMD chipset, 0 otherwise.
121 static int amd_chipset_sb_type_init(struct amd_chipset_info
*pinfo
)
124 pinfo
->sb_type
.gen
= AMD_CHIPSET_UNKNOWN
;
126 pinfo
->smbus_dev
= pci_get_device(PCI_VENDOR_ID_ATI
,
127 PCI_DEVICE_ID_ATI_SBX00_SMBUS
, NULL
);
128 if (pinfo
->smbus_dev
) {
129 rev
= pinfo
->smbus_dev
->revision
;
130 if (rev
>= 0x10 && rev
<= 0x1f)
131 pinfo
->sb_type
.gen
= AMD_CHIPSET_SB600
;
132 else if (rev
>= 0x30 && rev
<= 0x3f)
133 pinfo
->sb_type
.gen
= AMD_CHIPSET_SB700
;
134 else if (rev
>= 0x40 && rev
<= 0x4f)
135 pinfo
->sb_type
.gen
= AMD_CHIPSET_SB800
;
137 pinfo
->smbus_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
138 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
, NULL
);
140 if (!pinfo
->smbus_dev
) {
141 pinfo
->sb_type
.gen
= NOT_AMD_CHIPSET
;
145 rev
= pinfo
->smbus_dev
->revision
;
146 if (rev
>= 0x11 && rev
<= 0x14)
147 pinfo
->sb_type
.gen
= AMD_CHIPSET_HUDSON2
;
148 else if (rev
>= 0x15 && rev
<= 0x18)
149 pinfo
->sb_type
.gen
= AMD_CHIPSET_BOLTON
;
150 else if (rev
>= 0x39 && rev
<= 0x3a)
151 pinfo
->sb_type
.gen
= AMD_CHIPSET_YANGTZE
;
154 pinfo
->sb_type
.rev
= rev
;
158 void sb800_prefetch(struct device
*dev
, int on
)
161 struct pci_dev
*pdev
= to_pci_dev(dev
);
163 pci_read_config_word(pdev
, 0x50, &misc
);
165 pci_write_config_word(pdev
, 0x50, misc
& 0xfcff);
167 pci_write_config_word(pdev
, 0x50, misc
| 0x0300);
169 EXPORT_SYMBOL_GPL(sb800_prefetch
);
171 int usb_amd_find_chipset_info(void)
174 struct amd_chipset_info info
;
177 spin_lock_irqsave(&amd_lock
, flags
);
179 /* probe only once */
180 if (amd_chipset
.probe_count
> 0) {
181 amd_chipset
.probe_count
++;
182 spin_unlock_irqrestore(&amd_lock
, flags
);
183 return amd_chipset
.probe_result
;
185 memset(&info
, 0, sizeof(info
));
186 spin_unlock_irqrestore(&amd_lock
, flags
);
188 if (!amd_chipset_sb_type_init(&info
)) {
193 /* Below chipset generations needn't enable AMD PLL quirk */
194 if (info
.sb_type
.gen
== AMD_CHIPSET_UNKNOWN
||
195 info
.sb_type
.gen
== AMD_CHIPSET_SB600
||
196 info
.sb_type
.gen
== AMD_CHIPSET_YANGTZE
||
197 (info
.sb_type
.gen
== AMD_CHIPSET_SB700
&&
198 info
.sb_type
.rev
> 0x3b)) {
199 if (info
.smbus_dev
) {
200 pci_dev_put(info
.smbus_dev
);
201 info
.smbus_dev
= NULL
;
207 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
, 0x9601, NULL
);
211 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
, 0x1510, NULL
);
215 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
222 ret
= info
.probe_result
= 1;
223 printk(KERN_DEBUG
"QUIRK: Enable AMD PLL fix\n");
227 spin_lock_irqsave(&amd_lock
, flags
);
228 if (amd_chipset
.probe_count
> 0) {
229 /* race - someone else was faster - drop devices */
231 /* Mark that we where here */
232 amd_chipset
.probe_count
++;
233 ret
= amd_chipset
.probe_result
;
235 spin_unlock_irqrestore(&amd_lock
, flags
);
238 pci_dev_put(info
.nb_dev
);
240 pci_dev_put(info
.smbus_dev
);
243 /* no race - commit the result */
246 spin_unlock_irqrestore(&amd_lock
, flags
);
251 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info
);
253 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev
*pdev
)
255 /* Make sure amd chipset type has already been initialized */
256 usb_amd_find_chipset_info();
257 if (amd_chipset
.sb_type
.gen
!= AMD_CHIPSET_YANGTZE
)
260 dev_dbg(&pdev
->dev
, "QUIRK: Enable AMD remote wakeup fix\n");
263 EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk
);
265 bool usb_amd_hang_symptom_quirk(void)
269 usb_amd_find_chipset_info();
270 rev
= amd_chipset
.sb_type
.rev
;
271 /* SB600 and old version of SB700 have hang symptom bug */
272 return amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB600
||
273 (amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB700
&&
274 rev
>= 0x3a && rev
<= 0x3b);
276 EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk
);
278 bool usb_amd_prefetch_quirk(void)
280 usb_amd_find_chipset_info();
281 /* SB800 needs pre-fetch fix */
282 return amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB800
;
284 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk
);
287 * The hardware normally enables the A-link power management feature, which
288 * lets the system lower the power consumption in idle states.
290 * This USB quirk prevents the link going into that lower power state
291 * during isochronous transfers.
293 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
294 * some AMD platforms may stutter or have breaks occasionally.
296 static void usb_amd_quirk_pll(int disable
)
298 u32 addr
, addr_low
, addr_high
, val
;
299 u32 bit
= disable
? 0 : 1;
302 spin_lock_irqsave(&amd_lock
, flags
);
305 amd_chipset
.isoc_reqs
++;
306 if (amd_chipset
.isoc_reqs
> 1) {
307 spin_unlock_irqrestore(&amd_lock
, flags
);
311 amd_chipset
.isoc_reqs
--;
312 if (amd_chipset
.isoc_reqs
> 0) {
313 spin_unlock_irqrestore(&amd_lock
, flags
);
318 if (amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB800
||
319 amd_chipset
.sb_type
.gen
== AMD_CHIPSET_HUDSON2
||
320 amd_chipset
.sb_type
.gen
== AMD_CHIPSET_BOLTON
) {
321 outb_p(AB_REG_BAR_LOW
, 0xcd6);
322 addr_low
= inb_p(0xcd7);
323 outb_p(AB_REG_BAR_HIGH
, 0xcd6);
324 addr_high
= inb_p(0xcd7);
325 addr
= addr_high
<< 8 | addr_low
;
327 outl_p(0x30, AB_INDX(addr
));
328 outl_p(0x40, AB_DATA(addr
));
329 outl_p(0x34, AB_INDX(addr
));
330 val
= inl_p(AB_DATA(addr
));
331 } else if (amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB700
&&
332 amd_chipset
.sb_type
.rev
<= 0x3b) {
333 pci_read_config_dword(amd_chipset
.smbus_dev
,
334 AB_REG_BAR_SB700
, &addr
);
335 outl(AX_INDXC
, AB_INDX(addr
));
336 outl(0x40, AB_DATA(addr
));
337 outl(AX_DATAC
, AB_INDX(addr
));
338 val
= inl(AB_DATA(addr
));
340 spin_unlock_irqrestore(&amd_lock
, flags
);
346 val
|= (1 << 4) | (1 << 9);
349 val
&= ~((1 << 4) | (1 << 9));
351 outl_p(val
, AB_DATA(addr
));
353 if (!amd_chipset
.nb_dev
) {
354 spin_unlock_irqrestore(&amd_lock
, flags
);
358 if (amd_chipset
.nb_type
== 1 || amd_chipset
.nb_type
== 3) {
360 pci_write_config_dword(amd_chipset
.nb_dev
,
361 NB_PCIE_INDX_ADDR
, addr
);
362 pci_read_config_dword(amd_chipset
.nb_dev
,
363 NB_PCIE_INDX_DATA
, &val
);
365 val
&= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
366 val
|= bit
| (bit
<< 3) | (bit
<< 12);
367 val
|= ((!bit
) << 4) | ((!bit
) << 9);
368 pci_write_config_dword(amd_chipset
.nb_dev
,
369 NB_PCIE_INDX_DATA
, val
);
372 pci_write_config_dword(amd_chipset
.nb_dev
,
373 NB_PCIE_INDX_ADDR
, addr
);
374 pci_read_config_dword(amd_chipset
.nb_dev
,
375 NB_PCIE_INDX_DATA
, &val
);
379 pci_write_config_dword(amd_chipset
.nb_dev
,
380 NB_PCIE_INDX_DATA
, val
);
381 } else if (amd_chipset
.nb_type
== 2) {
382 addr
= NB_PIF0_PWRDOWN_0
;
383 pci_write_config_dword(amd_chipset
.nb_dev
,
384 NB_PCIE_INDX_ADDR
, addr
);
385 pci_read_config_dword(amd_chipset
.nb_dev
,
386 NB_PCIE_INDX_DATA
, &val
);
392 pci_write_config_dword(amd_chipset
.nb_dev
,
393 NB_PCIE_INDX_DATA
, val
);
395 addr
= NB_PIF0_PWRDOWN_1
;
396 pci_write_config_dword(amd_chipset
.nb_dev
,
397 NB_PCIE_INDX_ADDR
, addr
);
398 pci_read_config_dword(amd_chipset
.nb_dev
,
399 NB_PCIE_INDX_DATA
, &val
);
405 pci_write_config_dword(amd_chipset
.nb_dev
,
406 NB_PCIE_INDX_DATA
, val
);
409 spin_unlock_irqrestore(&amd_lock
, flags
);
413 void usb_amd_quirk_pll_disable(void)
415 usb_amd_quirk_pll(1);
417 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable
);
419 void usb_amd_quirk_pll_enable(void)
421 usb_amd_quirk_pll(0);
423 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable
);
425 void usb_amd_dev_put(void)
427 struct pci_dev
*nb
, *smbus
;
430 spin_lock_irqsave(&amd_lock
, flags
);
432 amd_chipset
.probe_count
--;
433 if (amd_chipset
.probe_count
> 0) {
434 spin_unlock_irqrestore(&amd_lock
, flags
);
438 /* save them to pci_dev_put outside of spinlock */
439 nb
= amd_chipset
.nb_dev
;
440 smbus
= amd_chipset
.smbus_dev
;
442 amd_chipset
.nb_dev
= NULL
;
443 amd_chipset
.smbus_dev
= NULL
;
444 amd_chipset
.nb_type
= 0;
445 memset(&amd_chipset
.sb_type
, 0, sizeof(amd_chipset
.sb_type
));
446 amd_chipset
.isoc_reqs
= 0;
447 amd_chipset
.probe_result
= 0;
449 spin_unlock_irqrestore(&amd_lock
, flags
);
456 EXPORT_SYMBOL_GPL(usb_amd_dev_put
);
459 * Make sure the controller is completely inactive, unable to
460 * generate interrupts or do DMA.
462 void uhci_reset_hc(struct pci_dev
*pdev
, unsigned long base
)
464 /* Turn off PIRQ enable and SMI enable. (This also turns off the
465 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
467 pci_write_config_word(pdev
, UHCI_USBLEGSUP
, UHCI_USBLEGSUP_RWC
);
469 /* Reset the HC - this will force us to get a
470 * new notification of any already connected
471 * ports due to the virtual disconnect that it
474 outw(UHCI_USBCMD_HCRESET
, base
+ UHCI_USBCMD
);
477 if (inw(base
+ UHCI_USBCMD
) & UHCI_USBCMD_HCRESET
)
478 dev_warn(&pdev
->dev
, "HCRESET not completed yet!\n");
480 /* Just to be safe, disable interrupt requests and
481 * make sure the controller is stopped.
483 outw(0, base
+ UHCI_USBINTR
);
484 outw(0, base
+ UHCI_USBCMD
);
486 EXPORT_SYMBOL_GPL(uhci_reset_hc
);
489 * Initialize a controller that was newly discovered or has just been
490 * resumed. In either case we can't be sure of its previous state.
492 * Returns: 1 if the controller was reset, 0 otherwise.
494 int uhci_check_and_reset_hc(struct pci_dev
*pdev
, unsigned long base
)
497 unsigned int cmd
, intr
;
500 * When restarting a suspended controller, we expect all the
501 * settings to be the same as we left them:
503 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
504 * Controller is stopped and configured with EGSM set;
505 * No interrupts enabled except possibly Resume Detect.
507 * If any of these conditions are violated we do a complete reset.
509 pci_read_config_word(pdev
, UHCI_USBLEGSUP
, &legsup
);
510 if (legsup
& ~(UHCI_USBLEGSUP_RO
| UHCI_USBLEGSUP_RWC
)) {
511 dev_dbg(&pdev
->dev
, "%s: legsup = 0x%04x\n",
516 cmd
= inw(base
+ UHCI_USBCMD
);
517 if ((cmd
& UHCI_USBCMD_RUN
) || !(cmd
& UHCI_USBCMD_CONFIGURE
) ||
518 !(cmd
& UHCI_USBCMD_EGSM
)) {
519 dev_dbg(&pdev
->dev
, "%s: cmd = 0x%04x\n",
524 intr
= inw(base
+ UHCI_USBINTR
);
525 if (intr
& (~UHCI_USBINTR_RESUME
)) {
526 dev_dbg(&pdev
->dev
, "%s: intr = 0x%04x\n",
533 dev_dbg(&pdev
->dev
, "Performing full reset\n");
534 uhci_reset_hc(pdev
, base
);
537 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc
);
539 static inline int io_type_enabled(struct pci_dev
*pdev
, unsigned int mask
)
542 return !pci_read_config_word(pdev
, PCI_COMMAND
, &cmd
) && (cmd
& mask
);
545 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
546 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
548 static void quirk_usb_handoff_uhci(struct pci_dev
*pdev
)
550 unsigned long base
= 0;
553 if (!pio_enabled(pdev
))
556 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++)
557 if ((pci_resource_flags(pdev
, i
) & IORESOURCE_IO
)) {
558 base
= pci_resource_start(pdev
, i
);
563 uhci_check_and_reset_hc(pdev
, base
);
566 static int mmio_resource_enabled(struct pci_dev
*pdev
, int idx
)
568 return pci_resource_start(pdev
, idx
) && mmio_enabled(pdev
);
571 static void quirk_usb_handoff_ohci(struct pci_dev
*pdev
)
578 if (!mmio_resource_enabled(pdev
, 0))
581 base
= pci_ioremap_bar(pdev
, 0);
585 control
= readl(base
+ OHCI_CONTROL
);
587 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
589 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
591 #define OHCI_CTRL_MASK OHCI_CTRL_RWC
593 if (control
& OHCI_CTRL_IR
) {
594 int wait_time
= 500; /* arbitrary; 5 seconds */
595 writel(OHCI_INTR_OC
, base
+ OHCI_INTRENABLE
);
596 writel(OHCI_OCR
, base
+ OHCI_CMDSTATUS
);
597 while (wait_time
> 0 &&
598 readl(base
+ OHCI_CONTROL
) & OHCI_CTRL_IR
) {
603 dev_warn(&pdev
->dev
, "OHCI: BIOS handoff failed"
604 " (BIOS bug?) %08x\n",
605 readl(base
+ OHCI_CONTROL
));
609 /* disable interrupts */
610 writel((u32
) ~0, base
+ OHCI_INTRDISABLE
);
612 /* Reset the USB bus, if the controller isn't already in RESET */
613 if (control
& OHCI_HCFS
) {
614 /* Go into RESET, preserving RWC (and possibly IR) */
615 writel(control
& OHCI_CTRL_MASK
, base
+ OHCI_CONTROL
);
616 readl(base
+ OHCI_CONTROL
);
618 /* drive bus reset for at least 50 ms (7.1.7.5) */
622 /* software reset of the controller, preserving HcFmInterval */
623 fminterval
= readl(base
+ OHCI_FMINTERVAL
);
624 writel(OHCI_HCR
, base
+ OHCI_CMDSTATUS
);
626 /* reset requires max 10 us delay */
627 for (cnt
= 30; cnt
> 0; --cnt
) { /* ... allow extra time */
628 if ((readl(base
+ OHCI_CMDSTATUS
) & OHCI_HCR
) == 0)
632 writel(fminterval
, base
+ OHCI_FMINTERVAL
);
634 /* Now the controller is safely in SUSPEND and nothing can wake it up */
638 static const struct dmi_system_id ehci_dmi_nohandoff_table
[] = {
640 /* Pegatron Lucid (ExoPC) */
642 DMI_MATCH(DMI_BOARD_NAME
, "EXOPG06411"),
643 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-CE-133"),
647 /* Pegatron Lucid (Ordissimo AIRIS) */
649 DMI_MATCH(DMI_BOARD_NAME
, "M11JB"),
650 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-"),
654 /* Pegatron Lucid (Ordissimo) */
656 DMI_MATCH(DMI_BOARD_NAME
, "Ordissimo"),
657 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-"),
663 static void ehci_bios_handoff(struct pci_dev
*pdev
,
664 void __iomem
*op_reg_base
,
667 int try_handoff
= 1, tried_handoff
= 0;
669 /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
670 * the handoff on its unused controller. Skip it. */
671 if (pdev
->vendor
== 0x8086 && pdev
->device
== 0x283a) {
672 if (dmi_check_system(ehci_dmi_nohandoff_table
))
676 if (try_handoff
&& (cap
& EHCI_USBLEGSUP_BIOS
)) {
677 dev_dbg(&pdev
->dev
, "EHCI: BIOS handoff\n");
680 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
681 * but that seems dubious in general (the BIOS left it off intentionally)
682 * and is known to prevent some systems from booting. so we won't do this
683 * unless maybe we can determine when we're on a system that needs SMI forced.
685 /* BIOS workaround (?): be sure the pre-Linux code
688 pci_read_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
, &val
);
689 pci_write_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
,
690 val
| EHCI_USBLEGCTLSTS_SOOE
);
693 /* some systems get upset if this semaphore is
694 * set for any other reason than forcing a BIOS
697 pci_write_config_byte(pdev
, offset
+ 3, 1);
700 /* if boot firmware now owns EHCI, spin till it hands it over. */
703 while ((cap
& EHCI_USBLEGSUP_BIOS
) && (msec
> 0)) {
707 pci_read_config_dword(pdev
, offset
, &cap
);
711 if (cap
& EHCI_USBLEGSUP_BIOS
) {
712 /* well, possibly buggy BIOS... try to shut it down,
713 * and hope nothing goes too wrong
716 dev_warn(&pdev
->dev
, "EHCI: BIOS handoff failed"
717 " (BIOS bug?) %08x\n", cap
);
718 pci_write_config_byte(pdev
, offset
+ 2, 0);
721 /* just in case, always disable EHCI SMIs */
722 pci_write_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
, 0);
724 /* If the BIOS ever owned the controller then we can't expect
725 * any power sessions to remain intact.
728 writel(0, op_reg_base
+ EHCI_CONFIGFLAG
);
731 static void quirk_usb_disable_ehci(struct pci_dev
*pdev
)
733 void __iomem
*base
, *op_reg_base
;
734 u32 hcc_params
, cap
, val
;
735 u8 offset
, cap_length
;
736 int wait_time
, count
= 256/4;
738 if (!mmio_resource_enabled(pdev
, 0))
741 base
= pci_ioremap_bar(pdev
, 0);
745 cap_length
= readb(base
);
746 op_reg_base
= base
+ cap_length
;
748 /* EHCI 0.96 and later may have "extended capabilities"
749 * spec section 5.1 explains the bios handoff, e.g. for
750 * booting from USB disk or using a usb keyboard
752 hcc_params
= readl(base
+ EHCI_HCC_PARAMS
);
753 offset
= (hcc_params
>> 8) & 0xff;
754 while (offset
&& --count
) {
755 pci_read_config_dword(pdev
, offset
, &cap
);
757 switch (cap
& 0xff) {
759 ehci_bios_handoff(pdev
, op_reg_base
, cap
, offset
);
761 case 0: /* Illegal reserved cap, set cap=0 so we exit */
762 cap
= 0; /* then fallthrough... */
764 dev_warn(&pdev
->dev
, "EHCI: unrecognized capability "
765 "%02x\n", cap
& 0xff);
767 offset
= (cap
>> 8) & 0xff;
770 dev_printk(KERN_DEBUG
, &pdev
->dev
, "EHCI: capability loop?\n");
773 * halt EHCI & disable its interrupts in any case
775 val
= readl(op_reg_base
+ EHCI_USBSTS
);
776 if ((val
& EHCI_USBSTS_HALTED
) == 0) {
777 val
= readl(op_reg_base
+ EHCI_USBCMD
);
778 val
&= ~EHCI_USBCMD_RUN
;
779 writel(val
, op_reg_base
+ EHCI_USBCMD
);
783 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
786 val
= readl(op_reg_base
+ EHCI_USBSTS
);
787 if ((val
== ~(u32
)0) || (val
& EHCI_USBSTS_HALTED
)) {
790 } while (wait_time
> 0);
792 writel(0, op_reg_base
+ EHCI_USBINTR
);
793 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
799 * handshake - spin reading a register until handshake completes
800 * @ptr: address of hc register to be read
801 * @mask: bits to look at in result of read
802 * @done: value of those bits when handshake succeeds
803 * @wait_usec: timeout in microseconds
804 * @delay_usec: delay in microseconds to wait between polling
806 * Polls a register every delay_usec microseconds.
807 * Returns 0 when the mask bits have the value done.
808 * Returns -ETIMEDOUT if this condition is not true after
809 * wait_usec microseconds have passed.
811 static int handshake(void __iomem
*ptr
, u32 mask
, u32 done
,
812 int wait_usec
, int delay_usec
)
822 wait_usec
-= delay_usec
;
823 } while (wait_usec
> 0);
828 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
829 * share some number of ports. These ports can be switched between either
830 * controller. Not all of the ports under the EHCI host controller may be
833 * The ports should be switched over to xHCI before PCI probes for any device
834 * start. This avoids active devices under EHCI being disconnected during the
835 * port switchover, which could cause loss of data on USB storage devices, or
836 * failed boot when the root file system is on a USB mass storage device and is
837 * enumerated under EHCI first.
839 * We write into the xHC's PCI configuration space in some Intel-specific
840 * registers to switch the ports over. The USB 3.0 terminations and the USB
841 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
842 * terminations before switching the USB 2.0 wires over, so that USB 3.0
843 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
845 void usb_enable_intel_xhci_ports(struct pci_dev
*xhci_pdev
)
848 bool ehci_found
= false;
849 struct pci_dev
*companion
= NULL
;
851 /* make sure an intel EHCI controller exists */
852 for_each_pci_dev(companion
) {
853 if (companion
->class == PCI_CLASS_SERIAL_USB_EHCI
&&
854 companion
->vendor
== PCI_VENDOR_ID_INTEL
) {
863 /* Don't switchover the ports if the user hasn't compiled the xHCI
864 * driver. Otherwise they will see "dead" USB ports that don't power
867 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD
)) {
868 dev_warn(&xhci_pdev
->dev
,
869 "CONFIG_USB_XHCI_HCD is turned off, "
870 "defaulting to EHCI.\n");
871 dev_warn(&xhci_pdev
->dev
,
872 "USB 3.0 devices will work at USB 2.0 speeds.\n");
873 usb_disable_xhci_ports(xhci_pdev
);
877 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
878 * Indicate the ports that can be changed from OS.
880 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB3PRM
,
883 dev_dbg(&xhci_pdev
->dev
, "Configurable ports to enable SuperSpeed: 0x%x\n",
886 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
887 * Register, to turn on SuperSpeed terminations for the
890 pci_write_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
,
893 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
,
895 dev_dbg(&xhci_pdev
->dev
, "USB 3.0 ports that are now enabled "
896 "under xHCI: 0x%x\n", ports_available
);
898 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
899 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
902 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB2PRM
,
905 dev_dbg(&xhci_pdev
->dev
, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
908 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
909 * switch the USB 2.0 power and data lines over to the xHCI
912 pci_write_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
,
915 pci_read_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
,
917 dev_dbg(&xhci_pdev
->dev
, "USB 2.0 ports that are now switched over "
918 "to xHCI: 0x%x\n", ports_available
);
920 EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports
);
922 void usb_disable_xhci_ports(struct pci_dev
*xhci_pdev
)
924 pci_write_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
, 0x0);
925 pci_write_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
, 0x0);
927 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports
);
930 * PCI Quirks for xHCI.
932 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
933 * It signals to the BIOS that the OS wants control of the host controller,
934 * and then waits 5 seconds for the BIOS to hand over control.
935 * If we timeout, assume the BIOS is broken and take control anyway.
937 static void quirk_usb_handoff_xhci(struct pci_dev
*pdev
)
941 void __iomem
*op_reg_base
;
944 int len
= pci_resource_len(pdev
, 0);
946 if (!mmio_resource_enabled(pdev
, 0))
949 base
= ioremap_nocache(pci_resource_start(pdev
, 0), len
);
954 * Find the Legacy Support Capability register -
955 * this is optional for xHCI host controllers.
957 ext_cap_offset
= xhci_find_next_cap_offset(base
, XHCI_HCC_PARAMS_OFFSET
);
959 if ((ext_cap_offset
+ sizeof(val
)) > len
) {
960 /* We're reading garbage from the controller */
962 "xHCI controller failing to respond");
967 /* We've reached the end of the extended capabilities */
970 val
= readl(base
+ ext_cap_offset
);
971 if (XHCI_EXT_CAPS_ID(val
) == XHCI_EXT_CAPS_LEGACY
)
973 ext_cap_offset
= xhci_find_next_cap_offset(base
, ext_cap_offset
);
976 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
977 if (val
& XHCI_HC_BIOS_OWNED
) {
978 writel(val
| XHCI_HC_OS_OWNED
, base
+ ext_cap_offset
);
980 /* Wait for 5 seconds with 10 microsecond polling interval */
981 timeout
= handshake(base
+ ext_cap_offset
, XHCI_HC_BIOS_OWNED
,
984 /* Assume a buggy BIOS and take HC ownership anyway */
986 dev_warn(&pdev
->dev
, "xHCI BIOS handoff failed"
987 " (BIOS bug ?) %08x\n", val
);
988 writel(val
& ~XHCI_HC_BIOS_OWNED
, base
+ ext_cap_offset
);
992 val
= readl(base
+ ext_cap_offset
+ XHCI_LEGACY_CONTROL_OFFSET
);
993 /* Mask off (turn off) any enabled SMIs */
994 val
&= XHCI_LEGACY_DISABLE_SMI
;
995 /* Mask all SMI events bits, RW1C */
996 val
|= XHCI_LEGACY_SMI_EVENTS
;
997 /* Disable any BIOS SMIs and clear all SMI events*/
998 writel(val
, base
+ ext_cap_offset
+ XHCI_LEGACY_CONTROL_OFFSET
);
1001 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
)
1002 usb_enable_intel_xhci_ports(pdev
);
1004 op_reg_base
= base
+ XHCI_HC_LENGTH(readl(base
));
1006 /* Wait for the host controller to be ready before writing any
1007 * operational or runtime registers. Wait 5 seconds and no more.
1009 timeout
= handshake(op_reg_base
+ XHCI_STS_OFFSET
, XHCI_STS_CNR
, 0,
1011 /* Assume a buggy HC and start HC initialization anyway */
1013 val
= readl(op_reg_base
+ XHCI_STS_OFFSET
);
1014 dev_warn(&pdev
->dev
,
1015 "xHCI HW not ready after 5 sec (HC bug?) "
1016 "status = 0x%x\n", val
);
1019 /* Send the halt and disable interrupts command */
1020 val
= readl(op_reg_base
+ XHCI_CMD_OFFSET
);
1021 val
&= ~(XHCI_CMD_RUN
| XHCI_IRQS
);
1022 writel(val
, op_reg_base
+ XHCI_CMD_OFFSET
);
1024 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
1025 timeout
= handshake(op_reg_base
+ XHCI_STS_OFFSET
, XHCI_STS_HALT
, 1,
1026 XHCI_MAX_HALT_USEC
, 125);
1028 val
= readl(op_reg_base
+ XHCI_STS_OFFSET
);
1029 dev_warn(&pdev
->dev
,
1030 "xHCI HW did not halt within %d usec "
1031 "status = 0x%x\n", XHCI_MAX_HALT_USEC
, val
);
1037 static void quirk_usb_early_handoff(struct pci_dev
*pdev
)
1039 /* Skip Netlogic mips SoC's internal PCI USB controller.
1040 * This device does not need/support EHCI/OHCI handoff
1042 if (pdev
->vendor
== 0x184e) /* vendor Netlogic */
1044 if (pdev
->class != PCI_CLASS_SERIAL_USB_UHCI
&&
1045 pdev
->class != PCI_CLASS_SERIAL_USB_OHCI
&&
1046 pdev
->class != PCI_CLASS_SERIAL_USB_EHCI
&&
1047 pdev
->class != PCI_CLASS_SERIAL_USB_XHCI
)
1050 if (pci_enable_device(pdev
) < 0) {
1051 dev_warn(&pdev
->dev
, "Can't enable PCI device, "
1052 "BIOS handoff failed.\n");
1055 if (pdev
->class == PCI_CLASS_SERIAL_USB_UHCI
)
1056 quirk_usb_handoff_uhci(pdev
);
1057 else if (pdev
->class == PCI_CLASS_SERIAL_USB_OHCI
)
1058 quirk_usb_handoff_ohci(pdev
);
1059 else if (pdev
->class == PCI_CLASS_SERIAL_USB_EHCI
)
1060 quirk_usb_disable_ehci(pdev
);
1061 else if (pdev
->class == PCI_CLASS_SERIAL_USB_XHCI
)
1062 quirk_usb_handoff_xhci(pdev
);
1063 pci_disable_device(pdev
);
1065 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1066 PCI_CLASS_SERIAL_USB
, 8, quirk_usb_early_handoff
);