2 * pinctrl pads, groups, functions for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/pinctrl/pinctrl.h>
10 #include <linux/bitops.h>
12 #include "pinctrl-sirf.h"
15 * pad list for the pinmux subsystem
16 * refer to CS-131858-DC-6A.xls
18 static const struct pinctrl_pin_desc sirfsoc_pads
[] = {
19 PINCTRL_PIN(0, "gpio0-0"),
20 PINCTRL_PIN(1, "gpio0-1"),
21 PINCTRL_PIN(2, "gpio0-2"),
22 PINCTRL_PIN(3, "gpio0-3"),
23 PINCTRL_PIN(4, "pwm0"),
24 PINCTRL_PIN(5, "pwm1"),
25 PINCTRL_PIN(6, "pwm2"),
26 PINCTRL_PIN(7, "pwm3"),
27 PINCTRL_PIN(8, "warm_rst_b"),
28 PINCTRL_PIN(9, "odo_0"),
29 PINCTRL_PIN(10, "odo_1"),
30 PINCTRL_PIN(11, "dr_dir"),
31 PINCTRL_PIN(12, "viprom_fa"),
32 PINCTRL_PIN(13, "scl_1"),
33 PINCTRL_PIN(14, "ntrst"),
34 PINCTRL_PIN(15, "sda_1"),
35 PINCTRL_PIN(16, "x_ldd[16]"),
36 PINCTRL_PIN(17, "x_ldd[17]"),
37 PINCTRL_PIN(18, "x_ldd[18]"),
38 PINCTRL_PIN(19, "x_ldd[19]"),
39 PINCTRL_PIN(20, "x_ldd[20]"),
40 PINCTRL_PIN(21, "x_ldd[21]"),
41 PINCTRL_PIN(22, "x_ldd[22]"),
42 PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
43 PINCTRL_PIN(24, "gps_sgn"),
44 PINCTRL_PIN(25, "gps_mag"),
45 PINCTRL_PIN(26, "gps_clk"),
46 PINCTRL_PIN(27, "sd_cd_b_1"),
47 PINCTRL_PIN(28, "sd_vcc_on_1"),
48 PINCTRL_PIN(29, "sd_wp_b_1"),
49 PINCTRL_PIN(30, "sd_clk_3"),
50 PINCTRL_PIN(31, "sd_cmd_3"),
52 PINCTRL_PIN(32, "x_sd_dat_3[0]"),
53 PINCTRL_PIN(33, "x_sd_dat_3[1]"),
54 PINCTRL_PIN(34, "x_sd_dat_3[2]"),
55 PINCTRL_PIN(35, "x_sd_dat_3[3]"),
56 PINCTRL_PIN(36, "x_sd_clk_4"),
57 PINCTRL_PIN(37, "x_sd_cmd_4"),
58 PINCTRL_PIN(38, "x_sd_dat_4[0]"),
59 PINCTRL_PIN(39, "x_sd_dat_4[1]"),
60 PINCTRL_PIN(40, "x_sd_dat_4[2]"),
61 PINCTRL_PIN(41, "x_sd_dat_4[3]"),
62 PINCTRL_PIN(42, "x_cko_1"),
63 PINCTRL_PIN(43, "x_ac97_bit_clk"),
64 PINCTRL_PIN(44, "x_ac97_dout"),
65 PINCTRL_PIN(45, "x_ac97_din"),
66 PINCTRL_PIN(46, "x_ac97_sync"),
67 PINCTRL_PIN(47, "x_txd_1"),
68 PINCTRL_PIN(48, "x_txd_2"),
69 PINCTRL_PIN(49, "x_rxd_1"),
70 PINCTRL_PIN(50, "x_rxd_2"),
71 PINCTRL_PIN(51, "x_usclk_0"),
72 PINCTRL_PIN(52, "x_utxd_0"),
73 PINCTRL_PIN(53, "x_urxd_0"),
74 PINCTRL_PIN(54, "x_utfs_0"),
75 PINCTRL_PIN(55, "x_urfs_0"),
76 PINCTRL_PIN(56, "x_usclk_1"),
77 PINCTRL_PIN(57, "x_utxd_1"),
78 PINCTRL_PIN(58, "x_urxd_1"),
79 PINCTRL_PIN(59, "x_utfs_1"),
80 PINCTRL_PIN(60, "x_urfs_1"),
81 PINCTRL_PIN(61, "x_usclk_2"),
82 PINCTRL_PIN(62, "x_utxd_2"),
83 PINCTRL_PIN(63, "x_urxd_2"),
85 PINCTRL_PIN(64, "x_utfs_2"),
86 PINCTRL_PIN(65, "x_urfs_2"),
87 PINCTRL_PIN(66, "x_df_we_b"),
88 PINCTRL_PIN(67, "x_df_re_b"),
89 PINCTRL_PIN(68, "x_txd_0"),
90 PINCTRL_PIN(69, "x_rxd_0"),
91 PINCTRL_PIN(78, "x_cko_0"),
92 PINCTRL_PIN(79, "x_vip_pxd[7]"),
93 PINCTRL_PIN(80, "x_vip_pxd[6]"),
94 PINCTRL_PIN(81, "x_vip_pxd[5]"),
95 PINCTRL_PIN(82, "x_vip_pxd[4]"),
96 PINCTRL_PIN(83, "x_vip_pxd[3]"),
97 PINCTRL_PIN(84, "x_vip_pxd[2]"),
98 PINCTRL_PIN(85, "x_vip_pxd[1]"),
99 PINCTRL_PIN(86, "x_vip_pxd[0]"),
100 PINCTRL_PIN(87, "x_vip_vsync"),
101 PINCTRL_PIN(88, "x_vip_hsync"),
102 PINCTRL_PIN(89, "x_vip_pxclk"),
103 PINCTRL_PIN(90, "x_sda_0"),
104 PINCTRL_PIN(91, "x_scl_0"),
105 PINCTRL_PIN(92, "x_df_ry_by"),
106 PINCTRL_PIN(93, "x_df_cs_b[1]"),
107 PINCTRL_PIN(94, "x_df_cs_b[0]"),
108 PINCTRL_PIN(95, "x_l_pclk"),
110 PINCTRL_PIN(96, "x_l_lck"),
111 PINCTRL_PIN(97, "x_l_fck"),
112 PINCTRL_PIN(98, "x_l_de"),
113 PINCTRL_PIN(99, "x_ldd[0]"),
114 PINCTRL_PIN(100, "x_ldd[1]"),
115 PINCTRL_PIN(101, "x_ldd[2]"),
116 PINCTRL_PIN(102, "x_ldd[3]"),
117 PINCTRL_PIN(103, "x_ldd[4]"),
118 PINCTRL_PIN(104, "x_ldd[5]"),
119 PINCTRL_PIN(105, "x_ldd[6]"),
120 PINCTRL_PIN(106, "x_ldd[7]"),
121 PINCTRL_PIN(107, "x_ldd[8]"),
122 PINCTRL_PIN(108, "x_ldd[9]"),
123 PINCTRL_PIN(109, "x_ldd[10]"),
124 PINCTRL_PIN(110, "x_ldd[11]"),
125 PINCTRL_PIN(111, "x_ldd[12]"),
126 PINCTRL_PIN(112, "x_ldd[13]"),
127 PINCTRL_PIN(113, "x_ldd[14]"),
128 PINCTRL_PIN(114, "x_ldd[15]"),
130 PINCTRL_PIN(115, "x_usb1_dp"),
131 PINCTRL_PIN(116, "x_usb1_dn"),
134 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask
[] = {
137 .mask
= BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
138 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
146 static const struct sirfsoc_padmux lcd_16bits_padmux
= {
147 .muxmask_counts
= ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask
),
148 .muxmask
= lcd_16bits_sirfsoc_muxmask
,
149 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
154 static const unsigned lcd_16bits_pins
[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
155 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
157 static const struct sirfsoc_muxmask lcd_18bits_muxmask
[] = {
160 .mask
= BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
161 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
168 .mask
= BIT(16) | BIT(17),
172 static const struct sirfsoc_padmux lcd_18bits_padmux
= {
173 .muxmask_counts
= ARRAY_SIZE(lcd_18bits_muxmask
),
174 .muxmask
= lcd_18bits_muxmask
,
175 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
180 static const unsigned lcd_18bits_pins
[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
181 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
183 static const struct sirfsoc_muxmask lcd_24bits_muxmask
[] = {
186 .mask
= BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
187 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
194 .mask
= BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
198 static const struct sirfsoc_padmux lcd_24bits_padmux
= {
199 .muxmask_counts
= ARRAY_SIZE(lcd_24bits_muxmask
),
200 .muxmask
= lcd_24bits_muxmask
,
201 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
206 static const unsigned lcd_24bits_pins
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
207 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
209 static const struct sirfsoc_muxmask lcdrom_muxmask
[] = {
212 .mask
= BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
213 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
224 static const struct sirfsoc_padmux lcdrom_padmux
= {
225 .muxmask_counts
= ARRAY_SIZE(lcdrom_muxmask
),
226 .muxmask
= lcdrom_muxmask
,
227 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
232 static const unsigned lcdrom_pins
[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
233 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
235 static const struct sirfsoc_muxmask uart0_muxmask
[] = {
238 .mask
= BIT(4) | BIT(5),
241 .mask
= BIT(23) | BIT(28),
245 static const struct sirfsoc_padmux uart0_padmux
= {
246 .muxmask_counts
= ARRAY_SIZE(uart0_muxmask
),
247 .muxmask
= uart0_muxmask
,
248 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
253 static const unsigned uart0_pins
[] = { 55, 60, 68, 69 };
255 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask
[] = {
258 .mask
= BIT(4) | BIT(5),
262 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux
= {
263 .muxmask_counts
= ARRAY_SIZE(uart0_nostreamctrl_muxmask
),
264 .muxmask
= uart0_nostreamctrl_muxmask
,
267 static const unsigned uart0_nostreamctrl_pins
[] = { 68, 69 };
269 static const struct sirfsoc_muxmask uart1_muxmask
[] = {
272 .mask
= BIT(15) | BIT(17),
276 static const struct sirfsoc_padmux uart1_padmux
= {
277 .muxmask_counts
= ARRAY_SIZE(uart1_muxmask
),
278 .muxmask
= uart1_muxmask
,
281 static const unsigned uart1_pins
[] = { 47, 49 };
283 static const struct sirfsoc_muxmask uart2_muxmask
[] = {
286 .mask
= BIT(16) | BIT(18) | BIT(24) | BIT(27),
290 static const struct sirfsoc_padmux uart2_padmux
= {
291 .muxmask_counts
= ARRAY_SIZE(uart2_muxmask
),
292 .muxmask
= uart2_muxmask
,
293 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
298 static const unsigned uart2_pins
[] = { 48, 50, 56, 59 };
300 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask
[] = {
303 .mask
= BIT(16) | BIT(18),
307 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux
= {
308 .muxmask_counts
= ARRAY_SIZE(uart2_nostreamctrl_muxmask
),
309 .muxmask
= uart2_nostreamctrl_muxmask
,
312 static const unsigned uart2_nostreamctrl_pins
[] = { 48, 50 };
314 static const struct sirfsoc_muxmask sdmmc3_muxmask
[] = {
317 .mask
= BIT(30) | BIT(31),
320 .mask
= BIT(0) | BIT(1) | BIT(2) | BIT(3),
324 static const struct sirfsoc_padmux sdmmc3_padmux
= {
325 .muxmask_counts
= ARRAY_SIZE(sdmmc3_muxmask
),
326 .muxmask
= sdmmc3_muxmask
,
327 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
332 static const unsigned sdmmc3_pins
[] = { 30, 31, 32, 33, 34, 35 };
334 static const struct sirfsoc_muxmask spi0_muxmask
[] = {
337 .mask
= BIT(0) | BIT(1) | BIT(2) | BIT(3),
341 static const struct sirfsoc_padmux spi0_padmux
= {
342 .muxmask_counts
= ARRAY_SIZE(spi0_muxmask
),
343 .muxmask
= spi0_muxmask
,
344 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
349 static const unsigned spi0_pins
[] = { 32, 33, 34, 35 };
351 static const struct sirfsoc_muxmask sdmmc4_muxmask
[] = {
354 .mask
= BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
358 static const struct sirfsoc_padmux sdmmc4_padmux
= {
359 .muxmask_counts
= ARRAY_SIZE(sdmmc4_muxmask
),
360 .muxmask
= sdmmc4_muxmask
,
363 static const unsigned sdmmc4_pins
[] = { 36, 37, 38, 39, 40, 41 };
365 static const struct sirfsoc_muxmask cko1_muxmask
[] = {
372 static const struct sirfsoc_padmux cko1_padmux
= {
373 .muxmask_counts
= ARRAY_SIZE(cko1_muxmask
),
374 .muxmask
= cko1_muxmask
,
375 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
380 static const unsigned cko1_pins
[] = { 42 };
382 static const struct sirfsoc_muxmask i2s_muxmask
[] = {
386 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
391 static const struct sirfsoc_padmux i2s_padmux
= {
392 .muxmask_counts
= ARRAY_SIZE(i2s_muxmask
),
393 .muxmask
= i2s_muxmask
,
394 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
395 .funcmask
= BIT(3) | BIT(9),
399 static const unsigned i2s_pins
[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
401 static const struct sirfsoc_muxmask ac97_muxmask
[] = {
404 .mask
= BIT(11) | BIT(12) | BIT(13) | BIT(14),
408 static const struct sirfsoc_padmux ac97_padmux
= {
409 .muxmask_counts
= ARRAY_SIZE(ac97_muxmask
),
410 .muxmask
= ac97_muxmask
,
411 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
416 static const unsigned ac97_pins
[] = { 33, 34, 35, 36 };
418 static const struct sirfsoc_muxmask spi1_muxmask
[] = {
421 .mask
= BIT(11) | BIT(12) | BIT(13) | BIT(14),
425 static const struct sirfsoc_padmux spi1_padmux
= {
426 .muxmask_counts
= ARRAY_SIZE(spi1_muxmask
),
427 .muxmask
= spi1_muxmask
,
428 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
433 static const unsigned spi1_pins
[] = { 43, 44, 45, 46 };
435 static const struct sirfsoc_muxmask sdmmc1_muxmask
[] = {
438 .mask
= BIT(27) | BIT(28) | BIT(29),
442 static const struct sirfsoc_padmux sdmmc1_padmux
= {
443 .muxmask_counts
= ARRAY_SIZE(sdmmc1_muxmask
),
444 .muxmask
= sdmmc1_muxmask
,
447 static const unsigned sdmmc1_pins
[] = { 27, 28, 29 };
449 static const struct sirfsoc_muxmask gps_muxmask
[] = {
452 .mask
= BIT(24) | BIT(25) | BIT(26),
456 static const struct sirfsoc_padmux gps_padmux
= {
457 .muxmask_counts
= ARRAY_SIZE(gps_muxmask
),
458 .muxmask
= gps_muxmask
,
459 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
460 .funcmask
= BIT(12) | BIT(13) | BIT(14),
464 static const unsigned gps_pins
[] = { 24, 25, 26 };
466 static const struct sirfsoc_muxmask sdmmc5_muxmask
[] = {
469 .mask
= BIT(24) | BIT(25) | BIT(26),
475 .mask
= BIT(0) | BIT(1),
479 static const struct sirfsoc_padmux sdmmc5_padmux
= {
480 .muxmask_counts
= ARRAY_SIZE(sdmmc5_muxmask
),
481 .muxmask
= sdmmc5_muxmask
,
482 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
483 .funcmask
= BIT(13) | BIT(14),
484 .funcval
= BIT(13) | BIT(14),
487 static const unsigned sdmmc5_pins
[] = { 24, 25, 26, 61, 64, 65 };
489 static const struct sirfsoc_muxmask usp0_muxmask
[] = {
492 .mask
= BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
496 static const struct sirfsoc_padmux usp0_padmux
= {
497 .muxmask_counts
= ARRAY_SIZE(usp0_muxmask
),
498 .muxmask
= usp0_muxmask
,
499 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
500 .funcmask
= BIT(1) | BIT(2) | BIT(6) | BIT(9),
504 static const unsigned usp0_pins
[] = { 51, 52, 53, 54, 55 };
506 static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask
[] = {
509 .mask
= BIT(20) | BIT(21),
513 static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux
= {
514 .muxmask_counts
= ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask
),
515 .muxmask
= usp0_uart_nostreamctrl_muxmask
,
518 static const unsigned usp0_uart_nostreamctrl_pins
[] = { 52, 53 };
520 static const struct sirfsoc_muxmask usp1_muxmask
[] = {
523 .mask
= BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
527 static const struct sirfsoc_padmux usp1_padmux
= {
528 .muxmask_counts
= ARRAY_SIZE(usp1_muxmask
),
529 .muxmask
= usp1_muxmask
,
530 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
531 .funcmask
= BIT(1) | BIT(9) | BIT(10) | BIT(11),
535 static const unsigned usp1_pins
[] = { 56, 57, 58, 59, 60 };
537 static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask
[] = {
540 .mask
= BIT(25) | BIT(26),
544 static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux
= {
545 .muxmask_counts
= ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask
),
546 .muxmask
= usp1_uart_nostreamctrl_muxmask
,
549 static const unsigned usp1_uart_nostreamctrl_pins
[] = { 57, 58 };
551 static const struct sirfsoc_muxmask usp2_muxmask
[] = {
554 .mask
= BIT(29) | BIT(30) | BIT(31),
557 .mask
= BIT(0) | BIT(1),
561 static const struct sirfsoc_padmux usp2_padmux
= {
562 .muxmask_counts
= ARRAY_SIZE(usp2_muxmask
),
563 .muxmask
= usp2_muxmask
,
564 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
565 .funcmask
= BIT(13) | BIT(14),
569 static const unsigned usp2_pins
[] = { 61, 62, 63, 64, 65 };
571 static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask
[] = {
574 .mask
= BIT(30) | BIT(31),
578 static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux
= {
579 .muxmask_counts
= ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask
),
580 .muxmask
= usp2_uart_nostreamctrl_muxmask
,
583 static const unsigned usp2_uart_nostreamctrl_pins
[] = { 62, 63 };
585 static const struct sirfsoc_muxmask nand_muxmask
[] = {
588 .mask
= BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
592 static const struct sirfsoc_padmux nand_padmux
= {
593 .muxmask_counts
= ARRAY_SIZE(nand_muxmask
),
594 .muxmask
= nand_muxmask
,
595 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
600 static const unsigned nand_pins
[] = { 64, 65, 92, 93, 94 };
602 static const struct sirfsoc_padmux sdmmc0_padmux
= {
604 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
609 static const unsigned sdmmc0_pins
[] = { };
611 static const struct sirfsoc_muxmask sdmmc2_muxmask
[] = {
614 .mask
= BIT(2) | BIT(3),
618 static const struct sirfsoc_padmux sdmmc2_padmux
= {
619 .muxmask_counts
= ARRAY_SIZE(sdmmc2_muxmask
),
620 .muxmask
= sdmmc2_muxmask
,
621 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
626 static const unsigned sdmmc2_pins
[] = { 66, 67 };
628 static const struct sirfsoc_muxmask cko0_muxmask
[] = {
635 static const struct sirfsoc_padmux cko0_padmux
= {
636 .muxmask_counts
= ARRAY_SIZE(cko0_muxmask
),
637 .muxmask
= cko0_muxmask
,
640 static const unsigned cko0_pins
[] = { 78 };
642 static const struct sirfsoc_muxmask vip_muxmask
[] = {
645 .mask
= BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
646 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
651 static const struct sirfsoc_padmux vip_padmux
= {
652 .muxmask_counts
= ARRAY_SIZE(vip_muxmask
),
653 .muxmask
= vip_muxmask
,
654 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
659 static const unsigned vip_pins
[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
661 static const struct sirfsoc_muxmask i2c0_muxmask
[] = {
664 .mask
= BIT(26) | BIT(27),
668 static const struct sirfsoc_padmux i2c0_padmux
= {
669 .muxmask_counts
= ARRAY_SIZE(i2c0_muxmask
),
670 .muxmask
= i2c0_muxmask
,
673 static const unsigned i2c0_pins
[] = { 90, 91 };
675 static const struct sirfsoc_muxmask i2c1_muxmask
[] = {
678 .mask
= BIT(13) | BIT(15),
682 static const struct sirfsoc_padmux i2c1_padmux
= {
683 .muxmask_counts
= ARRAY_SIZE(i2c1_muxmask
),
684 .muxmask
= i2c1_muxmask
,
687 static const unsigned i2c1_pins
[] = { 13, 15 };
689 static const struct sirfsoc_muxmask viprom_muxmask
[] = {
692 .mask
= BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
693 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
701 static const struct sirfsoc_padmux viprom_padmux
= {
702 .muxmask_counts
= ARRAY_SIZE(viprom_muxmask
),
703 .muxmask
= viprom_muxmask
,
704 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
709 static const unsigned viprom_pins
[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
711 static const struct sirfsoc_muxmask pwm0_muxmask
[] = {
718 static const struct sirfsoc_padmux pwm0_padmux
= {
719 .muxmask_counts
= ARRAY_SIZE(pwm0_muxmask
),
720 .muxmask
= pwm0_muxmask
,
721 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
726 static const unsigned pwm0_pins
[] = { 4 };
728 static const struct sirfsoc_muxmask pwm1_muxmask
[] = {
735 static const struct sirfsoc_padmux pwm1_padmux
= {
736 .muxmask_counts
= ARRAY_SIZE(pwm1_muxmask
),
737 .muxmask
= pwm1_muxmask
,
740 static const unsigned pwm1_pins
[] = { 5 };
742 static const struct sirfsoc_muxmask pwm2_muxmask
[] = {
749 static const struct sirfsoc_padmux pwm2_padmux
= {
750 .muxmask_counts
= ARRAY_SIZE(pwm2_muxmask
),
751 .muxmask
= pwm2_muxmask
,
754 static const unsigned pwm2_pins
[] = { 6 };
756 static const struct sirfsoc_muxmask pwm3_muxmask
[] = {
763 static const struct sirfsoc_padmux pwm3_padmux
= {
764 .muxmask_counts
= ARRAY_SIZE(pwm3_muxmask
),
765 .muxmask
= pwm3_muxmask
,
768 static const unsigned pwm3_pins
[] = { 7 };
770 static const struct sirfsoc_muxmask warm_rst_muxmask
[] = {
777 static const struct sirfsoc_padmux warm_rst_padmux
= {
778 .muxmask_counts
= ARRAY_SIZE(warm_rst_muxmask
),
779 .muxmask
= warm_rst_muxmask
,
782 static const unsigned warm_rst_pins
[] = { 8 };
784 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask
[] = {
790 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux
= {
791 .muxmask_counts
= ARRAY_SIZE(usb0_utmi_drvbus_muxmask
),
792 .muxmask
= usb0_utmi_drvbus_muxmask
,
793 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
795 .funcval
= BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
798 static const unsigned usb0_utmi_drvbus_pins
[] = { 54 };
800 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask
[] = {
807 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux
= {
808 .muxmask_counts
= ARRAY_SIZE(usb1_utmi_drvbus_muxmask
),
809 .muxmask
= usb1_utmi_drvbus_muxmask
,
810 .ctrlreg
= SIRFSOC_RSC_PIN_MUX
,
812 .funcval
= BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
815 static const unsigned usb1_utmi_drvbus_pins
[] = { 59 };
817 static const struct sirfsoc_padmux usb1_dp_dn_padmux
= {
819 .ctrlreg
= SIRFSOC_RSC_USB_UART_SHARE
,
824 static const unsigned usb1_dp_dn_pins
[] = { 115, 116 };
826 static const struct sirfsoc_padmux uart1_route_io_usb1_padmux
= {
828 .ctrlreg
= SIRFSOC_RSC_USB_UART_SHARE
,
833 static const unsigned uart1_route_io_usb1_pins
[] = { 115, 116 };
835 static const struct sirfsoc_muxmask pulse_count_muxmask
[] = {
838 .mask
= BIT(9) | BIT(10) | BIT(11),
842 static const struct sirfsoc_padmux pulse_count_padmux
= {
843 .muxmask_counts
= ARRAY_SIZE(pulse_count_muxmask
),
844 .muxmask
= pulse_count_muxmask
,
847 static const unsigned pulse_count_pins
[] = { 9, 10, 11 };
849 static const struct sirfsoc_pin_group sirfsoc_pin_groups
[] = {
850 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins
),
851 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins
),
852 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins
),
853 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins
),
854 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins
),
855 SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins
),
856 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins
),
857 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins
),
858 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins
),
859 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins
),
860 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
861 usp0_uart_nostreamctrl_pins
),
862 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins
),
863 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
864 usp1_uart_nostreamctrl_pins
),
865 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins
),
866 SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
867 usp2_uart_nostreamctrl_pins
),
868 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins
),
869 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins
),
870 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins
),
871 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins
),
872 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins
),
873 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins
),
874 SIRFSOC_PIN_GROUP("vipgrp", vip_pins
),
875 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins
),
876 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins
),
877 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins
),
878 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins
),
879 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins
),
880 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins
),
881 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins
),
882 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins
),
883 SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins
),
884 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins
),
885 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins
),
886 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins
),
887 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins
),
888 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins
),
889 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins
),
890 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins
),
891 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins
),
892 SIRFSOC_PIN_GROUP("nandgrp", nand_pins
),
893 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins
),
894 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins
),
895 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins
),
898 static const char * const lcd_16bitsgrp
[] = { "lcd_16bitsgrp" };
899 static const char * const lcd_18bitsgrp
[] = { "lcd_18bitsgrp" };
900 static const char * const lcd_24bitsgrp
[] = { "lcd_24bitsgrp" };
901 static const char * const lcdromgrp
[] = { "lcdromgrp" };
902 static const char * const uart0grp
[] = { "uart0grp" };
903 static const char * const uart0_nostreamctrlgrp
[] = { "uart0_nostreamctrlgrp" };
904 static const char * const uart1grp
[] = { "uart1grp" };
905 static const char * const uart2grp
[] = { "uart2grp" };
906 static const char * const uart2_nostreamctrlgrp
[] = { "uart2_nostreamctrlgrp" };
907 static const char * const usp0grp
[] = { "usp0grp" };
908 static const char * const usp0_uart_nostreamctrl_grp
[] =
909 { "usp0_uart_nostreamctrl_grp" };
910 static const char * const usp1grp
[] = { "usp1grp" };
911 static const char * const usp1_uart_nostreamctrl_grp
[] =
912 { "usp1_uart_nostreamctrl_grp" };
913 static const char * const usp2grp
[] = { "usp2grp" };
914 static const char * const usp2_uart_nostreamctrl_grp
[] =
915 { "usp2_uart_nostreamctrl_grp" };
916 static const char * const i2c0grp
[] = { "i2c0grp" };
917 static const char * const i2c1grp
[] = { "i2c1grp" };
918 static const char * const pwm0grp
[] = { "pwm0grp" };
919 static const char * const pwm1grp
[] = { "pwm1grp" };
920 static const char * const pwm2grp
[] = { "pwm2grp" };
921 static const char * const pwm3grp
[] = { "pwm3grp" };
922 static const char * const vipgrp
[] = { "vipgrp" };
923 static const char * const vipromgrp
[] = { "vipromgrp" };
924 static const char * const warm_rstgrp
[] = { "warm_rstgrp" };
925 static const char * const cko0grp
[] = { "cko0grp" };
926 static const char * const cko1grp
[] = { "cko1grp" };
927 static const char * const sdmmc0grp
[] = { "sdmmc0grp" };
928 static const char * const sdmmc1grp
[] = { "sdmmc1grp" };
929 static const char * const sdmmc2grp
[] = { "sdmmc2grp" };
930 static const char * const sdmmc3grp
[] = { "sdmmc3grp" };
931 static const char * const sdmmc4grp
[] = { "sdmmc4grp" };
932 static const char * const sdmmc5grp
[] = { "sdmmc5grp" };
933 static const char * const usb0_utmi_drvbusgrp
[] = { "usb0_utmi_drvbusgrp" };
934 static const char * const usb1_utmi_drvbusgrp
[] = { "usb1_utmi_drvbusgrp" };
935 static const char * const usb1_dp_dngrp
[] = { "usb1_dp_dngrp" };
936 static const char * const uart1_route_io_usb1grp
[] = { "uart1_route_io_usb1grp" };
937 static const char * const pulse_countgrp
[] = { "pulse_countgrp" };
938 static const char * const i2sgrp
[] = { "i2sgrp" };
939 static const char * const ac97grp
[] = { "ac97grp" };
940 static const char * const nandgrp
[] = { "nandgrp" };
941 static const char * const spi0grp
[] = { "spi0grp" };
942 static const char * const spi1grp
[] = { "spi1grp" };
943 static const char * const gpsgrp
[] = { "gpsgrp" };
945 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions
[] = {
946 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp
, lcd_16bits_padmux
),
947 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp
, lcd_18bits_padmux
),
948 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp
, lcd_24bits_padmux
),
949 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp
, lcdrom_padmux
),
950 SIRFSOC_PMX_FUNCTION("uart0", uart0grp
, uart0_padmux
),
951 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp
, uart0_nostreamctrl_padmux
),
952 SIRFSOC_PMX_FUNCTION("uart1", uart1grp
, uart1_padmux
),
953 SIRFSOC_PMX_FUNCTION("uart2", uart2grp
, uart2_padmux
),
954 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp
, uart2_nostreamctrl_padmux
),
955 SIRFSOC_PMX_FUNCTION("usp0", usp0grp
, usp0_padmux
),
956 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
957 usp0_uart_nostreamctrl_grp
, usp0_uart_nostreamctrl_padmux
),
958 SIRFSOC_PMX_FUNCTION("usp1", usp1grp
, usp1_padmux
),
959 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
960 usp1_uart_nostreamctrl_grp
, usp1_uart_nostreamctrl_padmux
),
961 SIRFSOC_PMX_FUNCTION("usp2", usp2grp
, usp2_padmux
),
962 SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
963 usp2_uart_nostreamctrl_grp
, usp2_uart_nostreamctrl_padmux
),
964 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp
, i2c0_padmux
),
965 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp
, i2c1_padmux
),
966 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp
, pwm0_padmux
),
967 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp
, pwm1_padmux
),
968 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp
, pwm2_padmux
),
969 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp
, pwm3_padmux
),
970 SIRFSOC_PMX_FUNCTION("vip", vipgrp
, vip_padmux
),
971 SIRFSOC_PMX_FUNCTION("viprom", vipromgrp
, viprom_padmux
),
972 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp
, warm_rst_padmux
),
973 SIRFSOC_PMX_FUNCTION("cko0", cko0grp
, cko0_padmux
),
974 SIRFSOC_PMX_FUNCTION("cko1", cko1grp
, cko1_padmux
),
975 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp
, sdmmc0_padmux
),
976 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp
, sdmmc1_padmux
),
977 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp
, sdmmc2_padmux
),
978 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp
, sdmmc3_padmux
),
979 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp
, sdmmc4_padmux
),
980 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp
, sdmmc5_padmux
),
981 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp
, usb0_utmi_drvbus_padmux
),
982 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp
, usb1_utmi_drvbus_padmux
),
983 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp
, usb1_dp_dn_padmux
),
984 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp
, uart1_route_io_usb1_padmux
),
985 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp
, pulse_count_padmux
),
986 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp
, i2s_padmux
),
987 SIRFSOC_PMX_FUNCTION("ac97", ac97grp
, ac97_padmux
),
988 SIRFSOC_PMX_FUNCTION("nand", nandgrp
, nand_padmux
),
989 SIRFSOC_PMX_FUNCTION("spi0", spi0grp
, spi0_padmux
),
990 SIRFSOC_PMX_FUNCTION("spi1", spi1grp
, spi1_padmux
),
991 SIRFSOC_PMX_FUNCTION("gps", gpsgrp
, gps_padmux
),
994 struct sirfsoc_pinctrl_data prima2_pinctrl_data
= {
995 (struct pinctrl_pin_desc
*)sirfsoc_pads
,
996 ARRAY_SIZE(sirfsoc_pads
),
997 (struct sirfsoc_pin_group
*)sirfsoc_pin_groups
,
998 ARRAY_SIZE(sirfsoc_pin_groups
),
999 (struct sirfsoc_pmx_func
*)sirfsoc_pmx_functions
,
1000 ARRAY_SIZE(sirfsoc_pmx_functions
),