Merge tag 'gpio-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[linux-2.6.git] / drivers / net / ethernet / sfc / siena.c
blobd034bcd124ef1e777f9d19dfba868e9275e6eae2
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
18 #include "bitfield.h"
19 #include "efx.h"
20 #include "nic.h"
21 #include "farch_regs.h"
22 #include "io.h"
23 #include "phy.h"
24 #include "workarounds.h"
25 #include "mcdi.h"
26 #include "mcdi_pcol.h"
27 #include "selftest.h"
29 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31 static void siena_init_wol(struct efx_nic *efx);
34 static void siena_push_irq_moderation(struct efx_channel *channel)
36 efx_dword_t timer_cmd;
38 if (channel->irq_moderation)
39 EFX_POPULATE_DWORD_2(timer_cmd,
40 FRF_CZ_TC_TIMER_MODE,
41 FFE_CZ_TIMER_MODE_INT_HLDOFF,
42 FRF_CZ_TC_TIMER_VAL,
43 channel->irq_moderation - 1);
44 else
45 EFX_POPULATE_DWORD_2(timer_cmd,
46 FRF_CZ_TC_TIMER_MODE,
47 FFE_CZ_TIMER_MODE_DIS,
48 FRF_CZ_TC_TIMER_VAL, 0);
49 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
50 channel->channel);
53 void siena_prepare_flush(struct efx_nic *efx)
55 if (efx->fc_disable++ == 0)
56 efx_mcdi_set_mac(efx);
59 void siena_finish_flush(struct efx_nic *efx)
61 if (--efx->fc_disable == 0)
62 efx_mcdi_set_mac(efx);
65 static const struct efx_farch_register_test siena_register_tests[] = {
66 { FR_AZ_ADR_REGION,
67 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
68 { FR_CZ_USR_EV_CFG,
69 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
70 { FR_AZ_RX_CFG,
71 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
72 { FR_AZ_TX_CFG,
73 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
74 { FR_AZ_TX_RESERVED,
75 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
76 { FR_AZ_SRM_TX_DC_CFG,
77 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
78 { FR_AZ_RX_DC_CFG,
79 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
80 { FR_AZ_RX_DC_PF_WM,
81 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
82 { FR_BZ_DP_CTRL,
83 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
84 { FR_BZ_RX_RSS_TKEY,
85 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
86 { FR_CZ_RX_RSS_IPV6_REG1,
87 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
88 { FR_CZ_RX_RSS_IPV6_REG2,
89 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
90 { FR_CZ_RX_RSS_IPV6_REG3,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
94 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
96 enum reset_type reset_method = RESET_TYPE_ALL;
97 int rc, rc2;
99 efx_reset_down(efx, reset_method);
101 /* Reset the chip immediately so that it is completely
102 * quiescent regardless of what any VF driver does.
104 rc = efx_mcdi_reset(efx, reset_method);
105 if (rc)
106 goto out;
108 tests->registers =
109 efx_farch_test_registers(efx, siena_register_tests,
110 ARRAY_SIZE(siena_register_tests))
111 ? -1 : 1;
113 rc = efx_mcdi_reset(efx, reset_method);
114 out:
115 rc2 = efx_reset_up(efx, reset_method, rc == 0);
116 return rc ? rc : rc2;
119 /**************************************************************************
121 * Device reset
123 **************************************************************************
126 static int siena_map_reset_flags(u32 *flags)
128 enum {
129 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
130 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
131 ETH_RESET_PHY),
132 SIENA_RESET_MC = (SIENA_RESET_PORT |
133 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
136 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
137 *flags &= ~SIENA_RESET_MC;
138 return RESET_TYPE_WORLD;
141 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
142 *flags &= ~SIENA_RESET_PORT;
143 return RESET_TYPE_ALL;
146 /* no invisible reset implemented */
148 return -EINVAL;
151 #ifdef CONFIG_EEH
152 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
153 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
154 * was written to minimise MMIO read (for latency) then a periodic call to check
155 * the EEH status of the device is required so that device recovery can happen
156 * in a timely fashion.
158 static void siena_monitor(struct efx_nic *efx)
160 struct eeh_dev *eehdev =
161 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
163 eeh_dev_check_failure(eehdev);
165 #endif
167 static int siena_probe_nvconfig(struct efx_nic *efx)
169 u32 caps = 0;
170 int rc;
172 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
174 efx->timer_quantum_ns =
175 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
176 3072 : 6144; /* 768 cycles */
177 return rc;
180 static int siena_dimension_resources(struct efx_nic *efx)
182 /* Each port has a small block of internal SRAM dedicated to
183 * the buffer table and descriptor caches. In theory we can
184 * map both blocks to one port, but we don't.
186 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
187 return 0;
190 static unsigned int siena_mem_map_size(struct efx_nic *efx)
192 return FR_CZ_MC_TREG_SMEM +
193 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
196 static int siena_probe_nic(struct efx_nic *efx)
198 struct siena_nic_data *nic_data;
199 efx_oword_t reg;
200 int rc;
202 /* Allocate storage for hardware specific data */
203 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
204 if (!nic_data)
205 return -ENOMEM;
206 efx->nic_data = nic_data;
208 if (efx_farch_fpga_ver(efx) != 0) {
209 netif_err(efx, probe, efx->net_dev,
210 "Siena FPGA not supported\n");
211 rc = -ENODEV;
212 goto fail1;
215 efx->max_channels = EFX_MAX_CHANNELS;
217 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
218 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
220 rc = efx_mcdi_init(efx);
221 if (rc)
222 goto fail1;
224 /* Now we can reset the NIC */
225 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
226 if (rc) {
227 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
228 goto fail3;
231 siena_init_wol(efx);
233 /* Allocate memory for INT_KER */
234 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
235 GFP_KERNEL);
236 if (rc)
237 goto fail4;
238 BUG_ON(efx->irq_status.dma_addr & 0x0f);
240 netif_dbg(efx, probe, efx->net_dev,
241 "INT_KER at %llx (virt %p phys %llx)\n",
242 (unsigned long long)efx->irq_status.dma_addr,
243 efx->irq_status.addr,
244 (unsigned long long)virt_to_phys(efx->irq_status.addr));
246 /* Read in the non-volatile configuration */
247 rc = siena_probe_nvconfig(efx);
248 if (rc == -EINVAL) {
249 netif_err(efx, probe, efx->net_dev,
250 "NVRAM is invalid therefore using defaults\n");
251 efx->phy_type = PHY_TYPE_NONE;
252 efx->mdio.prtad = MDIO_PRTAD_NONE;
253 } else if (rc) {
254 goto fail5;
257 rc = efx_mcdi_mon_probe(efx);
258 if (rc)
259 goto fail5;
261 efx_sriov_probe(efx);
262 efx_ptp_probe(efx);
264 return 0;
266 fail5:
267 efx_nic_free_buffer(efx, &efx->irq_status);
268 fail4:
269 fail3:
270 efx_mcdi_fini(efx);
271 fail1:
272 kfree(efx->nic_data);
273 return rc;
276 /* This call performs hardware-specific global initialisation, such as
277 * defining the descriptor cache sizes and number of RSS channels.
278 * It does not set up any buffers, descriptor rings or event queues.
280 static int siena_init_nic(struct efx_nic *efx)
282 efx_oword_t temp;
283 int rc;
285 /* Recover from a failed assertion post-reset */
286 rc = efx_mcdi_handle_assertion(efx);
287 if (rc)
288 return rc;
290 /* Squash TX of packets of 16 bytes or less */
291 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
292 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
293 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
295 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
296 * descriptors (which is bad).
298 efx_reado(efx, &temp, FR_AZ_TX_CFG);
299 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
300 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
301 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
303 efx_reado(efx, &temp, FR_AZ_RX_CFG);
304 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
305 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
306 /* Enable hash insertion. This is broken for the 'Falcon' hash
307 * if IPv6 hashing is also enabled, so also select Toeplitz
308 * TCP/IPv4 and IPv4 hashes. */
309 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
310 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
311 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
312 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
313 EFX_RX_USR_BUF_SIZE >> 5);
314 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
316 /* Set hash key for IPv4 */
317 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
318 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
320 /* Enable IPv6 RSS */
321 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
322 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
323 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
324 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
325 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
326 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
327 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
328 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
329 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
330 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
331 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
332 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
334 /* Enable event logging */
335 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
336 if (rc)
337 return rc;
339 /* Set destination of both TX and RX Flush events */
340 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
341 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
343 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
344 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
346 efx_farch_init_common(efx);
347 return 0;
350 static void siena_remove_nic(struct efx_nic *efx)
352 efx_mcdi_mon_remove(efx);
354 efx_nic_free_buffer(efx, &efx->irq_status);
356 efx_mcdi_reset(efx, RESET_TYPE_ALL);
358 efx_mcdi_fini(efx);
360 /* Tear down the private nic state */
361 kfree(efx->nic_data);
362 efx->nic_data = NULL;
365 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
366 [SIENA_STAT_ ## ext_name] = \
367 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
368 #define SIENA_OTHER_STAT(ext_name) \
369 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
371 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
372 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
373 SIENA_OTHER_STAT(tx_good_bytes),
374 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
375 SIENA_DMA_STAT(tx_packets, TX_PKTS),
376 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
377 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
378 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
379 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
380 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
381 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
382 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
383 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
384 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
385 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
386 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
387 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
388 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
389 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
390 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
391 SIENA_OTHER_STAT(tx_collision),
392 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
393 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
394 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
395 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
396 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
397 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
398 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
399 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
400 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
401 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
402 SIENA_OTHER_STAT(rx_good_bytes),
403 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
404 SIENA_DMA_STAT(rx_packets, RX_PKTS),
405 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
406 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
407 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
408 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
409 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
410 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
411 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
412 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
413 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
414 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
415 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
416 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
417 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
418 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
419 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
420 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
421 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
422 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
423 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
424 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
425 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
426 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
427 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
428 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
430 static const unsigned long siena_stat_mask[] = {
431 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
434 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
436 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
437 siena_stat_mask, names);
440 static int siena_try_update_nic_stats(struct efx_nic *efx)
442 struct siena_nic_data *nic_data = efx->nic_data;
443 u64 *stats = nic_data->stats;
444 __le64 *dma_stats;
445 __le64 generation_start, generation_end;
447 dma_stats = efx->stats_buffer.addr;
449 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
450 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
451 return 0;
452 rmb();
453 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
454 stats, efx->stats_buffer.addr, false);
455 rmb();
456 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
457 if (generation_end != generation_start)
458 return -EAGAIN;
460 /* Update derived statistics */
461 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
462 stats[SIENA_STAT_tx_bytes] -
463 stats[SIENA_STAT_tx_bad_bytes]);
464 stats[SIENA_STAT_tx_collision] =
465 stats[SIENA_STAT_tx_single_collision] +
466 stats[SIENA_STAT_tx_multiple_collision] +
467 stats[SIENA_STAT_tx_excessive_collision] +
468 stats[SIENA_STAT_tx_late_collision];
469 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
470 stats[SIENA_STAT_rx_bytes] -
471 stats[SIENA_STAT_rx_bad_bytes]);
472 return 0;
475 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
476 struct rtnl_link_stats64 *core_stats)
478 struct siena_nic_data *nic_data = efx->nic_data;
479 u64 *stats = nic_data->stats;
480 int retry;
482 /* If we're unlucky enough to read statistics wduring the DMA, wait
483 * up to 10ms for it to finish (typically takes <500us) */
484 for (retry = 0; retry < 100; ++retry) {
485 if (siena_try_update_nic_stats(efx) == 0)
486 break;
487 udelay(100);
490 if (full_stats)
491 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
493 if (core_stats) {
494 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
495 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
496 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
497 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
498 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt];
499 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
500 core_stats->collisions = stats[SIENA_STAT_tx_collision];
501 core_stats->rx_length_errors =
502 stats[SIENA_STAT_rx_gtjumbo] +
503 stats[SIENA_STAT_rx_length_error];
504 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
505 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
506 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
507 core_stats->tx_window_errors =
508 stats[SIENA_STAT_tx_late_collision];
510 core_stats->rx_errors = (core_stats->rx_length_errors +
511 core_stats->rx_crc_errors +
512 core_stats->rx_frame_errors +
513 stats[SIENA_STAT_rx_symbol_error]);
514 core_stats->tx_errors = (core_stats->tx_window_errors +
515 stats[SIENA_STAT_tx_bad]);
518 return SIENA_STAT_COUNT;
521 static int siena_mac_reconfigure(struct efx_nic *efx)
523 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
524 int rc;
526 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
527 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
528 sizeof(efx->multicast_hash));
530 efx_farch_filter_sync_rx_mode(efx);
532 WARN_ON(!mutex_is_locked(&efx->mac_lock));
534 rc = efx_mcdi_set_mac(efx);
535 if (rc != 0)
536 return rc;
538 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
539 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
540 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
541 inbuf, sizeof(inbuf), NULL, 0, NULL);
544 /**************************************************************************
546 * Wake on LAN
548 **************************************************************************
551 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
553 struct siena_nic_data *nic_data = efx->nic_data;
555 wol->supported = WAKE_MAGIC;
556 if (nic_data->wol_filter_id != -1)
557 wol->wolopts = WAKE_MAGIC;
558 else
559 wol->wolopts = 0;
560 memset(&wol->sopass, 0, sizeof(wol->sopass));
564 static int siena_set_wol(struct efx_nic *efx, u32 type)
566 struct siena_nic_data *nic_data = efx->nic_data;
567 int rc;
569 if (type & ~WAKE_MAGIC)
570 return -EINVAL;
572 if (type & WAKE_MAGIC) {
573 if (nic_data->wol_filter_id != -1)
574 efx_mcdi_wol_filter_remove(efx,
575 nic_data->wol_filter_id);
576 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
577 &nic_data->wol_filter_id);
578 if (rc)
579 goto fail;
581 pci_wake_from_d3(efx->pci_dev, true);
582 } else {
583 rc = efx_mcdi_wol_filter_reset(efx);
584 nic_data->wol_filter_id = -1;
585 pci_wake_from_d3(efx->pci_dev, false);
586 if (rc)
587 goto fail;
590 return 0;
591 fail:
592 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
593 __func__, type, rc);
594 return rc;
598 static void siena_init_wol(struct efx_nic *efx)
600 struct siena_nic_data *nic_data = efx->nic_data;
601 int rc;
603 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
605 if (rc != 0) {
606 /* If it failed, attempt to get into a synchronised
607 * state with MC by resetting any set WoL filters */
608 efx_mcdi_wol_filter_reset(efx);
609 nic_data->wol_filter_id = -1;
610 } else if (nic_data->wol_filter_id != -1) {
611 pci_wake_from_d3(efx->pci_dev, true);
615 /**************************************************************************
617 * MCDI
619 **************************************************************************
622 #define MCDI_PDU(efx) \
623 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
624 #define MCDI_DOORBELL(efx) \
625 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
626 #define MCDI_STATUS(efx) \
627 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
629 static void siena_mcdi_request(struct efx_nic *efx,
630 const efx_dword_t *hdr, size_t hdr_len,
631 const efx_dword_t *sdu, size_t sdu_len)
633 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
634 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
635 unsigned int i;
636 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
638 EFX_BUG_ON_PARANOID(hdr_len != 4);
640 efx_writed(efx, hdr, pdu);
642 for (i = 0; i < inlen_dw; i++)
643 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
645 /* Ensure the request is written out before the doorbell */
646 wmb();
648 /* ring the doorbell with a distinctive value */
649 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
652 static bool siena_mcdi_poll_response(struct efx_nic *efx)
654 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
655 efx_dword_t hdr;
657 efx_readd(efx, &hdr, pdu);
659 /* All 1's indicates that shared memory is in reset (and is
660 * not a valid hdr). Wait for it to come out reset before
661 * completing the command
663 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
664 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
667 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
668 size_t offset, size_t outlen)
670 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
671 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
672 int i;
674 for (i = 0; i < outlen_dw; i++)
675 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
678 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
680 struct siena_nic_data *nic_data = efx->nic_data;
681 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
682 efx_dword_t reg;
683 u32 value;
685 efx_readd(efx, &reg, addr);
686 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
688 if (value == 0)
689 return 0;
691 EFX_ZERO_DWORD(reg);
692 efx_writed(efx, &reg, addr);
694 /* MAC statistics have been cleared on the NIC; clear the local
695 * copies that we update with efx_update_diff_stat().
697 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
698 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
700 if (value == MC_STATUS_DWORD_ASSERT)
701 return -EINTR;
702 else
703 return -EIO;
706 /**************************************************************************
708 * MTD
710 **************************************************************************
713 #ifdef CONFIG_SFC_MTD
715 struct siena_nvram_type_info {
716 int port;
717 const char *name;
720 static const struct siena_nvram_type_info siena_nvram_types[] = {
721 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
722 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
723 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
724 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
725 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
726 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
727 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
728 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
729 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
730 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
731 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
732 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
733 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
736 static int siena_mtd_probe_partition(struct efx_nic *efx,
737 struct efx_mcdi_mtd_partition *part,
738 unsigned int type)
740 const struct siena_nvram_type_info *info;
741 size_t size, erase_size;
742 bool protected;
743 int rc;
745 if (type >= ARRAY_SIZE(siena_nvram_types) ||
746 siena_nvram_types[type].name == NULL)
747 return -ENODEV;
749 info = &siena_nvram_types[type];
751 if (info->port != efx_port_num(efx))
752 return -ENODEV;
754 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
755 if (rc)
756 return rc;
757 if (protected)
758 return -ENODEV; /* hide it */
760 part->nvram_type = type;
761 part->common.dev_type_name = "Siena NVRAM manager";
762 part->common.type_name = info->name;
764 part->common.mtd.type = MTD_NORFLASH;
765 part->common.mtd.flags = MTD_CAP_NORFLASH;
766 part->common.mtd.size = size;
767 part->common.mtd.erasesize = erase_size;
769 return 0;
772 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
773 struct efx_mcdi_mtd_partition *parts,
774 size_t n_parts)
776 uint16_t fw_subtype_list[
777 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
778 size_t i;
779 int rc;
781 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
782 if (rc)
783 return rc;
785 for (i = 0; i < n_parts; i++)
786 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
788 return 0;
791 static int siena_mtd_probe(struct efx_nic *efx)
793 struct efx_mcdi_mtd_partition *parts;
794 u32 nvram_types;
795 unsigned int type;
796 size_t n_parts;
797 int rc;
799 ASSERT_RTNL();
801 rc = efx_mcdi_nvram_types(efx, &nvram_types);
802 if (rc)
803 return rc;
805 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
806 if (!parts)
807 return -ENOMEM;
809 type = 0;
810 n_parts = 0;
812 while (nvram_types != 0) {
813 if (nvram_types & 1) {
814 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
815 type);
816 if (rc == 0)
817 n_parts++;
818 else if (rc != -ENODEV)
819 goto fail;
821 type++;
822 nvram_types >>= 1;
825 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
826 if (rc)
827 goto fail;
829 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
830 fail:
831 if (rc)
832 kfree(parts);
833 return rc;
836 #endif /* CONFIG_SFC_MTD */
838 /**************************************************************************
840 * PTP
842 **************************************************************************
845 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
847 _efx_writed(efx, cpu_to_le32(host_time),
848 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
851 /**************************************************************************
853 * Revision-dependent attributes used by efx.c and nic.c
855 **************************************************************************
858 const struct efx_nic_type siena_a0_nic_type = {
859 .mem_map_size = siena_mem_map_size,
860 .probe = siena_probe_nic,
861 .remove = siena_remove_nic,
862 .init = siena_init_nic,
863 .dimension_resources = siena_dimension_resources,
864 .fini = efx_port_dummy_op_void,
865 #ifdef CONFIG_EEH
866 .monitor = siena_monitor,
867 #else
868 .monitor = NULL,
869 #endif
870 .map_reset_reason = efx_mcdi_map_reset_reason,
871 .map_reset_flags = siena_map_reset_flags,
872 .reset = efx_mcdi_reset,
873 .probe_port = efx_mcdi_port_probe,
874 .remove_port = efx_mcdi_port_remove,
875 .fini_dmaq = efx_farch_fini_dmaq,
876 .prepare_flush = siena_prepare_flush,
877 .finish_flush = siena_finish_flush,
878 .describe_stats = siena_describe_nic_stats,
879 .update_stats = siena_update_nic_stats,
880 .start_stats = efx_mcdi_mac_start_stats,
881 .stop_stats = efx_mcdi_mac_stop_stats,
882 .set_id_led = efx_mcdi_set_id_led,
883 .push_irq_moderation = siena_push_irq_moderation,
884 .reconfigure_mac = siena_mac_reconfigure,
885 .check_mac_fault = efx_mcdi_mac_check_fault,
886 .reconfigure_port = efx_mcdi_port_reconfigure,
887 .get_wol = siena_get_wol,
888 .set_wol = siena_set_wol,
889 .resume_wol = siena_init_wol,
890 .test_chip = siena_test_chip,
891 .test_nvram = efx_mcdi_nvram_test_all,
892 .mcdi_request = siena_mcdi_request,
893 .mcdi_poll_response = siena_mcdi_poll_response,
894 .mcdi_read_response = siena_mcdi_read_response,
895 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
896 .irq_enable_master = efx_farch_irq_enable_master,
897 .irq_test_generate = efx_farch_irq_test_generate,
898 .irq_disable_non_ev = efx_farch_irq_disable_master,
899 .irq_handle_msi = efx_farch_msi_interrupt,
900 .irq_handle_legacy = efx_farch_legacy_interrupt,
901 .tx_probe = efx_farch_tx_probe,
902 .tx_init = efx_farch_tx_init,
903 .tx_remove = efx_farch_tx_remove,
904 .tx_write = efx_farch_tx_write,
905 .rx_push_indir_table = efx_farch_rx_push_indir_table,
906 .rx_probe = efx_farch_rx_probe,
907 .rx_init = efx_farch_rx_init,
908 .rx_remove = efx_farch_rx_remove,
909 .rx_write = efx_farch_rx_write,
910 .rx_defer_refill = efx_farch_rx_defer_refill,
911 .ev_probe = efx_farch_ev_probe,
912 .ev_init = efx_farch_ev_init,
913 .ev_fini = efx_farch_ev_fini,
914 .ev_remove = efx_farch_ev_remove,
915 .ev_process = efx_farch_ev_process,
916 .ev_read_ack = efx_farch_ev_read_ack,
917 .ev_test_generate = efx_farch_ev_test_generate,
918 .filter_table_probe = efx_farch_filter_table_probe,
919 .filter_table_restore = efx_farch_filter_table_restore,
920 .filter_table_remove = efx_farch_filter_table_remove,
921 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
922 .filter_insert = efx_farch_filter_insert,
923 .filter_remove_safe = efx_farch_filter_remove_safe,
924 .filter_get_safe = efx_farch_filter_get_safe,
925 .filter_clear_rx = efx_farch_filter_clear_rx,
926 .filter_count_rx_used = efx_farch_filter_count_rx_used,
927 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
928 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
929 #ifdef CONFIG_RFS_ACCEL
930 .filter_rfs_insert = efx_farch_filter_rfs_insert,
931 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
932 #endif
933 #ifdef CONFIG_SFC_MTD
934 .mtd_probe = siena_mtd_probe,
935 .mtd_rename = efx_mcdi_mtd_rename,
936 .mtd_read = efx_mcdi_mtd_read,
937 .mtd_erase = efx_mcdi_mtd_erase,
938 .mtd_write = efx_mcdi_mtd_write,
939 .mtd_sync = efx_mcdi_mtd_sync,
940 #endif
941 .ptp_write_host_time = siena_ptp_write_host_time,
943 .revision = EFX_REV_SIENA_A0,
944 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
945 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
946 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
947 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
948 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
949 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
950 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
951 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
952 .rx_buffer_padding = 0,
953 .can_rx_scatter = true,
954 .max_interrupt_mode = EFX_INT_MODE_MSIX,
955 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
956 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
957 NETIF_F_RXHASH | NETIF_F_NTUPLE),
958 .mcdi_max_ver = 1,
959 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,