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Merge tag 'gpio-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[linux-2.6.git] / drivers / net / ethernet / myricom / myri10ge / myri10ge.c
blob68026f7e8ba308d62c66570fb5ac7c19eb9f8994
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2011 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
43 #include <linux/tcp.h>
44 #include <linux/netdevice.h>
45 #include <linux/skbuff.h>
46 #include <linux/string.h>
47 #include <linux/module.h>
48 #include <linux/pci.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/etherdevice.h>
51 #include <linux/if_ether.h>
52 #include <linux/if_vlan.h>
53 #include <linux/dca.h>
54 #include <linux/ip.h>
55 #include <linux/inet.h>
56 #include <linux/in.h>
57 #include <linux/ethtool.h>
58 #include <linux/firmware.h>
59 #include <linux/delay.h>
60 #include <linux/timer.h>
61 #include <linux/vmalloc.h>
62 #include <linux/crc32.h>
63 #include <linux/moduleparam.h>
64 #include <linux/io.h>
65 #include <linux/log2.h>
66 #include <linux/slab.h>
67 #include <linux/prefetch.h>
68 #include <net/checksum.h>
69 #include <net/ip.h>
70 #include <net/tcp.h>
71 #include <asm/byteorder.h>
72 #include <asm/io.h>
73 #include <asm/processor.h>
74 #ifdef CONFIG_MTRR
75 #include <asm/mtrr.h>
76 #endif
77 #include <net/busy_poll.h>
78
79 #include "myri10ge_mcp.h"
80 #include "myri10ge_mcp_gen_header.h"
81
82 #define MYRI10GE_VERSION_STR "1.5.3-1.534"
83
84 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
85 MODULE_AUTHOR("Maintainer: help@myri.com");
86 MODULE_VERSION(MYRI10GE_VERSION_STR);
87 MODULE_LICENSE("Dual BSD/GPL");
88
89 #define MYRI10GE_MAX_ETHER_MTU 9014
90
91 #define MYRI10GE_ETH_STOPPED 0
92 #define MYRI10GE_ETH_STOPPING 1
93 #define MYRI10GE_ETH_STARTING 2
94 #define MYRI10GE_ETH_RUNNING 3
95 #define MYRI10GE_ETH_OPEN_FAILED 4
96
97 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
98 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
99
100 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
101 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
102
103 #define MYRI10GE_ALLOC_ORDER 0
104 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
105 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
106
107 #define MYRI10GE_MAX_SLICES 32
108
109 struct myri10ge_rx_buffer_state {
110 struct page *page;
111 int page_offset;
112 DEFINE_DMA_UNMAP_ADDR(bus);
113 DEFINE_DMA_UNMAP_LEN(len);
114 };
115
116 struct myri10ge_tx_buffer_state {
117 struct sk_buff *skb;
118 int last;
119 DEFINE_DMA_UNMAP_ADDR(bus);
120 DEFINE_DMA_UNMAP_LEN(len);
121 };
122
123 struct myri10ge_cmd {
124 u32 data0;
125 u32 data1;
126 u32 data2;
127 };
128
129 struct myri10ge_rx_buf {
130 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
131 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
132 struct myri10ge_rx_buffer_state *info;
133 struct page *page;
134 dma_addr_t bus;
135 int page_offset;
136 int cnt;
137 int fill_cnt;
138 int alloc_fail;
139 int mask; /* number of rx slots -1 */
140 int watchdog_needed;
141 };
142
143 struct myri10ge_tx_buf {
144 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
145 __be32 __iomem *send_go; /* "go" doorbell ptr */
146 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
147 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
148 char *req_bytes;
149 struct myri10ge_tx_buffer_state *info;
150 int mask; /* number of transmit slots -1 */
151 int req ____cacheline_aligned; /* transmit slots submitted */
152 int pkt_start; /* packets started */
153 int stop_queue;
154 int linearized;
155 int done ____cacheline_aligned; /* transmit slots completed */
156 int pkt_done; /* packets completed */
157 int wake_queue;
158 int queue_active;
159 };
160
161 struct myri10ge_rx_done {
162 struct mcp_slot *entry;
163 dma_addr_t bus;
164 int cnt;
165 int idx;
166 };
167
168 struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175 };
176
177 struct myri10ge_slice_state {
178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
191 int watchdog_rx_done;
192 int stuck;
193 #ifdef CONFIG_MYRI10GE_DCA
194 int cached_dca_tag;
195 int cpu;
196 __be32 __iomem *dca_tag;
197 #endif
198 #ifdef CONFIG_NET_RX_BUSY_POLL
199 unsigned int state;
200 #define SLICE_STATE_IDLE 0
201 #define SLICE_STATE_NAPI 1 /* NAPI owns this slice */
202 #define SLICE_STATE_POLL 2 /* poll owns this slice */
203 #define SLICE_LOCKED (SLICE_STATE_NAPI | SLICE_STATE_POLL)
204 #define SLICE_STATE_NAPI_YIELD 4 /* NAPI yielded this slice */
205 #define SLICE_STATE_POLL_YIELD 8 /* poll yielded this slice */
206 #define SLICE_USER_PEND (SLICE_STATE_POLL | SLICE_STATE_POLL_YIELD)
207 spinlock_t lock;
208 unsigned long lock_napi_yield;
209 unsigned long lock_poll_yield;
210 unsigned long busy_poll_miss;
211 unsigned long busy_poll_cnt;
212 #endif /* CONFIG_NET_RX_BUSY_POLL */
213 char irq_desc[32];
214 };
215
216 struct myri10ge_priv {
217 struct myri10ge_slice_state *ss;
218 int tx_boundary; /* boundary transmits cannot cross */
219 int num_slices;
220 int running; /* running? */
221 int small_bytes;
222 int big_bytes;
223 int max_intr_slots;
224 struct net_device *dev;
225 u8 __iomem *sram;
226 int sram_size;
227 unsigned long board_span;
228 unsigned long iomem_base;
229 __be32 __iomem *irq_deassert;
230 char *mac_addr_string;
231 struct mcp_cmd_response *cmd;
232 dma_addr_t cmd_bus;
233 struct pci_dev *pdev;
234 int msi_enabled;
235 int msix_enabled;
236 struct msix_entry *msix_vectors;
237 #ifdef CONFIG_MYRI10GE_DCA
238 int dca_enabled;
239 int relaxed_order;
240 #endif
241 u32 link_state;
242 unsigned int rdma_tags_available;
243 int intr_coal_delay;
244 __be32 __iomem *intr_coal_delay_ptr;
245 int mtrr;
246 int wc_enabled;
247 int down_cnt;
248 wait_queue_head_t down_wq;
249 struct work_struct watchdog_work;
250 struct timer_list watchdog_timer;
251 int watchdog_resets;
252 int watchdog_pause;
253 int pause;
254 bool fw_name_allocated;
255 char *fw_name;
256 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
257 char *product_code_string;
258 char fw_version[128];
259 int fw_ver_major;
260 int fw_ver_minor;
261 int fw_ver_tiny;
262 int adopted_rx_filter_bug;
263 u8 mac_addr[ETH_ALEN]; /* eeprom mac address */
264 unsigned long serial_number;
265 int vendor_specific_offset;
266 int fw_multicast_support;
267 u32 features;
268 u32 max_tso6;
269 u32 read_dma;
270 u32 write_dma;
271 u32 read_write_dma;
272 u32 link_changes;
273 u32 msg_enable;
274 unsigned int board_number;
275 int rebooted;
276 };
277
278 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
279 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
280 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
281 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
282 MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
283 MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
284 MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
285 MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
286
287 /* Careful: must be accessed under kparam_block_sysfs_write */
288 static char *myri10ge_fw_name = NULL;
289 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
290 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
291
292 #define MYRI10GE_MAX_BOARDS 8
293 static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
294 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
295 module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
296 0444);
297 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
298
299 static int myri10ge_ecrc_enable = 1;
300 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
301 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
302
303 static int myri10ge_small_bytes = -1; /* -1 == auto */
304 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
305 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
306
307 static int myri10ge_msi = 1; /* enable msi by default */
308 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
309 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
310
311 static int myri10ge_intr_coal_delay = 75;
312 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
313 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
314
315 static int myri10ge_flow_control = 1;
316 module_param(myri10ge_flow_control, int, S_IRUGO);
317 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
318
319 static int myri10ge_deassert_wait = 1;
320 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
321 MODULE_PARM_DESC(myri10ge_deassert_wait,
322 "Wait when deasserting legacy interrupts");
323
324 static int myri10ge_force_firmware = 0;
325 module_param(myri10ge_force_firmware, int, S_IRUGO);
326 MODULE_PARM_DESC(myri10ge_force_firmware,
327 "Force firmware to assume aligned completions");
328
329 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
330 module_param(myri10ge_initial_mtu, int, S_IRUGO);
331 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
332
333 static int myri10ge_napi_weight = 64;
334 module_param(myri10ge_napi_weight, int, S_IRUGO);
335 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
336
337 static int myri10ge_watchdog_timeout = 1;
338 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
339 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
340
341 static int myri10ge_max_irq_loops = 1048576;
342 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
343 MODULE_PARM_DESC(myri10ge_max_irq_loops,
344 "Set stuck legacy IRQ detection threshold");
345
346 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
347
348 static int myri10ge_debug = -1; /* defaults above */
349 module_param(myri10ge_debug, int, 0);
350 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
351
352 static int myri10ge_fill_thresh = 256;
353 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
354 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
355
356 static int myri10ge_reset_recover = 1;
357
358 static int myri10ge_max_slices = 1;
359 module_param(myri10ge_max_slices, int, S_IRUGO);
360 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
361
362 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
363 module_param(myri10ge_rss_hash, int, S_IRUGO);
364 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
365
366 static int myri10ge_dca = 1;
367 module_param(myri10ge_dca, int, S_IRUGO);
368 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
369
370 #define MYRI10GE_FW_OFFSET 1024*1024
371 #define MYRI10GE_HIGHPART_TO_U32(X) \
372 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
373 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
374
375 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
376
377 static void myri10ge_set_multicast_list(struct net_device *dev);
378 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
379 struct net_device *dev);
380
381 static inline void put_be32(__be32 val, __be32 __iomem * p)
382 {
383 __raw_writel((__force __u32) val, (__force void __iomem *)p);
384 }
385
386 static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
387 struct rtnl_link_stats64 *stats);
388
389 static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
390 {
391 if (mgp->fw_name_allocated)
392 kfree(mgp->fw_name);
393 mgp->fw_name = name;
394 mgp->fw_name_allocated = allocated;
395 }
396
397 static int
398 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
399 struct myri10ge_cmd *data, int atomic)
400 {
401 struct mcp_cmd *buf;
402 char buf_bytes[sizeof(*buf) + 8];
403 struct mcp_cmd_response *response = mgp->cmd;
404 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
405 u32 dma_low, dma_high, result, value;
406 int sleep_total = 0;
407
408 /* ensure buf is aligned to 8 bytes */
409 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
410
411 buf->data0 = htonl(data->data0);
412 buf->data1 = htonl(data->data1);
413 buf->data2 = htonl(data->data2);
414 buf->cmd = htonl(cmd);
415 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
416 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
417
418 buf->response_addr.low = htonl(dma_low);
419 buf->response_addr.high = htonl(dma_high);
420 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
421 mb();
422 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
423
424 /* wait up to 15ms. Longest command is the DMA benchmark,
425 * which is capped at 5ms, but runs from a timeout handler
426 * that runs every 7.8ms. So a 15ms timeout leaves us with
427 * a 2.2ms margin
428 */
429 if (atomic) {
430 /* if atomic is set, do not sleep,
431 * and try to get the completion quickly
432 * (1ms will be enough for those commands) */
433 for (sleep_total = 0;
434 sleep_total < 1000 &&
435 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
436 sleep_total += 10) {
437 udelay(10);
438 mb();
439 }
440 } else {
441 /* use msleep for most command */
442 for (sleep_total = 0;
443 sleep_total < 15 &&
444 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
445 sleep_total++)
446 msleep(1);
447 }
448
449 result = ntohl(response->result);
450 value = ntohl(response->data);
451 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
452 if (result == 0) {
453 data->data0 = value;
454 return 0;
455 } else if (result == MXGEFW_CMD_UNKNOWN) {
456 return -ENOSYS;
457 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
458 return -E2BIG;
459 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
460 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
461 (data->
462 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
463 0) {
464 return -ERANGE;
465 } else {
466 dev_err(&mgp->pdev->dev,
467 "command %d failed, result = %d\n",
468 cmd, result);
469 return -ENXIO;
470 }
471 }
472
473 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
474 cmd, result);
475 return -EAGAIN;
476 }
477
478 /*
479 * The eeprom strings on the lanaiX have the format
480 * SN=x\0
481 * MAC=x:x:x:x:x:x\0
482 * PT:ddd mmm xx xx:xx:xx xx\0
483 * PV:ddd mmm xx xx:xx:xx xx\0
484 */
485 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
486 {
487 char *ptr, *limit;
488 int i;
489
490 ptr = mgp->eeprom_strings;
491 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
492
493 while (*ptr != '\0' && ptr < limit) {
494 if (memcmp(ptr, "MAC=", 4) == 0) {
495 ptr += 4;
496 mgp->mac_addr_string = ptr;
497 for (i = 0; i < 6; i++) {
498 if ((ptr + 2) > limit)
499 goto abort;
500 mgp->mac_addr[i] =
501 simple_strtoul(ptr, &ptr, 16);
502 ptr += 1;
503 }
504 }
505 if (memcmp(ptr, "PC=", 3) == 0) {
506 ptr += 3;
507 mgp->product_code_string = ptr;
508 }
509 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
510 ptr += 3;
511 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
512 }
513 while (ptr < limit && *ptr++) ;
514 }
515
516 return 0;
517
518 abort:
519 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
520 return -ENXIO;
521 }
522
523 /*
524 * Enable or disable periodic RDMAs from the host to make certain
525 * chipsets resend dropped PCIe messages
526 */
527
528 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
529 {
530 char __iomem *submit;
531 __be32 buf[16] __attribute__ ((__aligned__(8)));
532 u32 dma_low, dma_high;
533 int i;
534
535 /* clear confirmation addr */
536 mgp->cmd->data = 0;
537 mb();
538
539 /* send a rdma command to the PCIe engine, and wait for the
540 * response in the confirmation address. The firmware should
541 * write a -1 there to indicate it is alive and well
542 */
543 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
544 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
545
546 buf[0] = htonl(dma_high); /* confirm addr MSW */
547 buf[1] = htonl(dma_low); /* confirm addr LSW */
548 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
549 buf[3] = htonl(dma_high); /* dummy addr MSW */
550 buf[4] = htonl(dma_low); /* dummy addr LSW */
551 buf[5] = htonl(enable); /* enable? */
552
553 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
554
555 myri10ge_pio_copy(submit, &buf, sizeof(buf));
556 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
557 msleep(1);
558 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
559 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
560 (enable ? "enable" : "disable"));
561 }
562
563 static int
564 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
565 struct mcp_gen_header *hdr)
566 {
567 struct device *dev = &mgp->pdev->dev;
568
569 /* check firmware type */
570 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
571 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
572 return -EINVAL;
573 }
574
575 /* save firmware version for ethtool */
576 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
577
578 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
579 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
580
581 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
582 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
583 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
584 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
585 MXGEFW_VERSION_MINOR);
586 return -EINVAL;
587 }
588 return 0;
589 }
590
591 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
592 {
593 unsigned crc, reread_crc;
594 const struct firmware *fw;
595 struct device *dev = &mgp->pdev->dev;
596 unsigned char *fw_readback;
597 struct mcp_gen_header *hdr;
598 size_t hdr_offset;
599 int status;
600 unsigned i;
601
602 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
603 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
604 mgp->fw_name);
605 status = -EINVAL;
606 goto abort_with_nothing;
607 }
608
609 /* check size */
610
611 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
612 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
613 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
614 status = -EINVAL;
615 goto abort_with_fw;
616 }
617
618 /* check id */
619 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
620 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
621 dev_err(dev, "Bad firmware file\n");
622 status = -EINVAL;
623 goto abort_with_fw;
624 }
625 hdr = (void *)(fw->data + hdr_offset);
626
627 status = myri10ge_validate_firmware(mgp, hdr);
628 if (status != 0)
629 goto abort_with_fw;
630
631 crc = crc32(~0, fw->data, fw->size);
632 for (i = 0; i < fw->size; i += 256) {
633 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
634 fw->data + i,
635 min(256U, (unsigned)(fw->size - i)));
636 mb();
637 readb(mgp->sram);
638 }
639 fw_readback = vmalloc(fw->size);
640 if (!fw_readback) {
641 status = -ENOMEM;
642 goto abort_with_fw;
643 }
644 /* corruption checking is good for parity recovery and buggy chipset */
645 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
646 reread_crc = crc32(~0, fw_readback, fw->size);
647 vfree(fw_readback);
648 if (crc != reread_crc) {
649 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
650 (unsigned)fw->size, reread_crc, crc);
651 status = -EIO;
652 goto abort_with_fw;
653 }
654 *size = (u32) fw->size;
655
656 abort_with_fw:
657 release_firmware(fw);
658
659 abort_with_nothing:
660 return status;
661 }
662
663 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
664 {
665 struct mcp_gen_header *hdr;
666 struct device *dev = &mgp->pdev->dev;
667 const size_t bytes = sizeof(struct mcp_gen_header);
668 size_t hdr_offset;
669 int status;
670
671 /* find running firmware header */
672 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
673
674 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
675 dev_err(dev, "Running firmware has bad header offset (%d)\n",
676 (int)hdr_offset);
677 return -EIO;
678 }
679
680 /* copy header of running firmware from SRAM to host memory to
681 * validate firmware */
682 hdr = kmalloc(bytes, GFP_KERNEL);
683 if (hdr == NULL)
684 return -ENOMEM;
685
686 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
687 status = myri10ge_validate_firmware(mgp, hdr);
688 kfree(hdr);
689
690 /* check to see if adopted firmware has bug where adopting
691 * it will cause broadcasts to be filtered unless the NIC
692 * is kept in ALLMULTI mode */
693 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
694 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
695 mgp->adopted_rx_filter_bug = 1;
696 dev_warn(dev, "Adopting fw %d.%d.%d: "
697 "working around rx filter bug\n",
698 mgp->fw_ver_major, mgp->fw_ver_minor,
699 mgp->fw_ver_tiny);
700 }
701 return status;
702 }
703
704 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
705 {
706 struct myri10ge_cmd cmd;
707 int status;
708
709 /* probe for IPv6 TSO support */
710 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
711 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
712 &cmd, 0);
713 if (status == 0) {
714 mgp->max_tso6 = cmd.data0;
715 mgp->features |= NETIF_F_TSO6;
716 }
717
718 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
719 if (status != 0) {
720 dev_err(&mgp->pdev->dev,
721 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
722 return -ENXIO;
723 }
724
725 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
726
727 return 0;
728 }
729
730 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
731 {
732 char __iomem *submit;
733 __be32 buf[16] __attribute__ ((__aligned__(8)));
734 u32 dma_low, dma_high, size;
735 int status, i;
736
737 size = 0;
738 status = myri10ge_load_hotplug_firmware(mgp, &size);
739 if (status) {
740 if (!adopt)
741 return status;
742 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
743
744 /* Do not attempt to adopt firmware if there
745 * was a bad crc */
746 if (status == -EIO)
747 return status;
748
749 status = myri10ge_adopt_running_firmware(mgp);
750 if (status != 0) {
751 dev_err(&mgp->pdev->dev,
752 "failed to adopt running firmware\n");
753 return status;
754 }
755 dev_info(&mgp->pdev->dev,
756 "Successfully adopted running firmware\n");
757 if (mgp->tx_boundary == 4096) {
758 dev_warn(&mgp->pdev->dev,
759 "Using firmware currently running on NIC"
760 ". For optimal\n");
761 dev_warn(&mgp->pdev->dev,
762 "performance consider loading optimized "
763 "firmware\n");
764 dev_warn(&mgp->pdev->dev, "via hotplug\n");
765 }
766
767 set_fw_name(mgp, "adopted", false);
768 mgp->tx_boundary = 2048;
769 myri10ge_dummy_rdma(mgp, 1);
770 status = myri10ge_get_firmware_capabilities(mgp);
771 return status;
772 }
773
774 /* clear confirmation addr */
775 mgp->cmd->data = 0;
776 mb();
777
778 /* send a reload command to the bootstrap MCP, and wait for the
779 * response in the confirmation address. The firmware should
780 * write a -1 there to indicate it is alive and well
781 */
782 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
783 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
784
785 buf[0] = htonl(dma_high); /* confirm addr MSW */
786 buf[1] = htonl(dma_low); /* confirm addr LSW */
787 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
788
789 /* FIX: All newest firmware should un-protect the bottom of
790 * the sram before handoff. However, the very first interfaces
791 * do not. Therefore the handoff copy must skip the first 8 bytes
792 */
793 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
794 buf[4] = htonl(size - 8); /* length of code */
795 buf[5] = htonl(8); /* where to copy to */
796 buf[6] = htonl(0); /* where to jump to */
797
798 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
799
800 myri10ge_pio_copy(submit, &buf, sizeof(buf));
801 mb();
802 msleep(1);
803 mb();
804 i = 0;
805 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
806 msleep(1 << i);
807 i++;
808 }
809 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
810 dev_err(&mgp->pdev->dev, "handoff failed\n");
811 return -ENXIO;
812 }
813 myri10ge_dummy_rdma(mgp, 1);
814 status = myri10ge_get_firmware_capabilities(mgp);
815
816 return status;
817 }
818
819 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
820 {
821 struct myri10ge_cmd cmd;
822 int status;
823
824 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
825 | (addr[2] << 8) | addr[3]);
826
827 cmd.data1 = ((addr[4] << 8) | (addr[5]));
828
829 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
830 return status;
831 }
832
833 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
834 {
835 struct myri10ge_cmd cmd;
836 int status, ctl;
837
838 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
839 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
840
841 if (status) {
842 netdev_err(mgp->dev, "Failed to set flow control mode\n");
843 return status;
844 }
845 mgp->pause = pause;
846 return 0;
847 }
848
849 static void
850 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
851 {
852 struct myri10ge_cmd cmd;
853 int status, ctl;
854
855 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
856 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
857 if (status)
858 netdev_err(mgp->dev, "Failed to set promisc mode\n");
859 }
860
861 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
862 {
863 struct myri10ge_cmd cmd;
864 int status;
865 u32 len;
866 struct page *dmatest_page;
867 dma_addr_t dmatest_bus;
868 char *test = " ";
869
870 dmatest_page = alloc_page(GFP_KERNEL);
871 if (!dmatest_page)
872 return -ENOMEM;
873 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
874 DMA_BIDIRECTIONAL);
875
876 /* Run a small DMA test.
877 * The magic multipliers to the length tell the firmware
878 * to do DMA read, write, or read+write tests. The
879 * results are returned in cmd.data0. The upper 16
880 * bits or the return is the number of transfers completed.
881 * The lower 16 bits is the time in 0.5us ticks that the
882 * transfers took to complete.
883 */
884
885 len = mgp->tx_boundary;
886
887 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
888 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
889 cmd.data2 = len * 0x10000;
890 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
891 if (status != 0) {
892 test = "read";
893 goto abort;
894 }
895 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
896 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
897 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
898 cmd.data2 = len * 0x1;
899 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
900 if (status != 0) {
901 test = "write";
902 goto abort;
903 }
904 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
905
906 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
907 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
908 cmd.data2 = len * 0x10001;
909 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
910 if (status != 0) {
911 test = "read/write";
912 goto abort;
913 }
914 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
915 (cmd.data0 & 0xffff);
916
917 abort:
918 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
919 put_page(dmatest_page);
920
921 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
922 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
923 test, status);
924
925 return status;
926 }
927
928 #ifdef CONFIG_NET_RX_BUSY_POLL
929 static inline void myri10ge_ss_init_lock(struct myri10ge_slice_state *ss)
930 {
931 spin_lock_init(&ss->lock);
932 ss->state = SLICE_STATE_IDLE;
933 }
934
935 static inline bool myri10ge_ss_lock_napi(struct myri10ge_slice_state *ss)
936 {
937 bool rc = true;
938 spin_lock(&ss->lock);
939 if ((ss->state & SLICE_LOCKED)) {
940 WARN_ON((ss->state & SLICE_STATE_NAPI));
941 ss->state |= SLICE_STATE_NAPI_YIELD;
942 rc = false;
943 ss->lock_napi_yield++;
944 } else
945 ss->state = SLICE_STATE_NAPI;
946 spin_unlock(&ss->lock);
947 return rc;
948 }
949
950 static inline void myri10ge_ss_unlock_napi(struct myri10ge_slice_state *ss)
951 {
952 spin_lock(&ss->lock);
953 WARN_ON((ss->state & (SLICE_STATE_POLL | SLICE_STATE_NAPI_YIELD)));
954 ss->state = SLICE_STATE_IDLE;
955 spin_unlock(&ss->lock);
956 }
957
958 static inline bool myri10ge_ss_lock_poll(struct myri10ge_slice_state *ss)
959 {
960 bool rc = true;
961 spin_lock_bh(&ss->lock);
962 if ((ss->state & SLICE_LOCKED)) {
963 ss->state |= SLICE_STATE_POLL_YIELD;
964 rc = false;
965 ss->lock_poll_yield++;
966 } else
967 ss->state |= SLICE_STATE_POLL;
968 spin_unlock_bh(&ss->lock);
969 return rc;
970 }
971
972 static inline void myri10ge_ss_unlock_poll(struct myri10ge_slice_state *ss)
973 {
974 spin_lock_bh(&ss->lock);
975 WARN_ON((ss->state & SLICE_STATE_NAPI));
976 ss->state = SLICE_STATE_IDLE;
977 spin_unlock_bh(&ss->lock);
978 }
979
980 static inline bool myri10ge_ss_busy_polling(struct myri10ge_slice_state *ss)
981 {
982 WARN_ON(!(ss->state & SLICE_LOCKED));
983 return (ss->state & SLICE_USER_PEND);
984 }
985 #else /* CONFIG_NET_RX_BUSY_POLL */
986 static inline void myri10ge_ss_init_lock(struct myri10ge_slice_state *ss)
987 {
988 }
989
990 static inline bool myri10ge_ss_lock_napi(struct myri10ge_slice_state *ss)
991 {
992 return false;
993 }
994
995 static inline void myri10ge_ss_unlock_napi(struct myri10ge_slice_state *ss)
996 {
997 }
998
999 static inline bool myri10ge_ss_lock_poll(struct myri10ge_slice_state *ss)
1000 {
1001 return false;
1002 }
1003
1004 static inline void myri10ge_ss_unlock_poll(struct myri10ge_slice_state *ss)
1005 {
1006 }
1007
1008 static inline bool myri10ge_ss_busy_polling(struct myri10ge_slice_state *ss)
1009 {
1010 return false;
1011 }
1012 #endif
1013
1014 static int myri10ge_reset(struct myri10ge_priv *mgp)
1015 {
1016 struct myri10ge_cmd cmd;
1017 struct myri10ge_slice_state *ss;
1018 int i, status;
1019 size_t bytes;
1020 #ifdef CONFIG_MYRI10GE_DCA
1021 unsigned long dca_tag_off;
1022 #endif
1023
1024 /* try to send a reset command to the card to see if it
1025 * is alive */
1026 memset(&cmd, 0, sizeof(cmd));
1027 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
1028 if (status != 0) {
1029 dev_err(&mgp->pdev->dev, "failed reset\n");
1030 return -ENXIO;
1031 }
1032
1033 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
1034 /*
1035 * Use non-ndis mcp_slot (eg, 4 bytes total,
1036 * no toeplitz hash value returned. Older firmware will
1037 * not understand this command, but will use the correct
1038 * sized mcp_slot, so we ignore error returns
1039 */
1040 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
1041 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
1042
1043 /* Now exchange information about interrupts */
1044
1045 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
1046 cmd.data0 = (u32) bytes;
1047 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
1048
1049 /*
1050 * Even though we already know how many slices are supported
1051 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
1052 * has magic side effects, and must be called after a reset.
1053 * It must be called prior to calling any RSS related cmds,
1054 * including assigning an interrupt queue for anything but
1055 * slice 0. It must also be called *after*
1056 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
1057 * the firmware to compute offsets.
1058 */
1059
1060 if (mgp->num_slices > 1) {
1061
1062 /* ask the maximum number of slices it supports */
1063 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
1064 &cmd, 0);
1065 if (status != 0) {
1066 dev_err(&mgp->pdev->dev,
1067 "failed to get number of slices\n");
1068 }
1069
1070 /*
1071 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
1072 * to setting up the interrupt queue DMA
1073 */
1074
1075 cmd.data0 = mgp->num_slices;
1076 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1077 if (mgp->dev->real_num_tx_queues > 1)
1078 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
1079 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
1080 &cmd, 0);
1081
1082 /* Firmware older than 1.4.32 only supports multiple
1083 * RX queues, so if we get an error, first retry using a
1084 * single TX queue before giving up */
1085 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
1086 netif_set_real_num_tx_queues(mgp->dev, 1);
1087 cmd.data0 = mgp->num_slices;
1088 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1089 status = myri10ge_send_cmd(mgp,
1090 MXGEFW_CMD_ENABLE_RSS_QUEUES,
1091 &cmd, 0);
1092 }
1093
1094 if (status != 0) {
1095 dev_err(&mgp->pdev->dev,
1096 "failed to set number of slices\n");
1097
1098 return status;
1099 }
1100 }
1101 for (i = 0; i < mgp->num_slices; i++) {
1102 ss = &mgp->ss[i];
1103 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1104 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1105 cmd.data2 = i;
1106 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1107 &cmd, 0);
1108 }
1109
1110 status |=
1111 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1112 for (i = 0; i < mgp->num_slices; i++) {
1113 ss = &mgp->ss[i];
1114 ss->irq_claim =
1115 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1116 }
1117 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1118 &cmd, 0);
1119 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1120
1121 status |= myri10ge_send_cmd
1122 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1123 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1124 if (status != 0) {
1125 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1126 return status;
1127 }
1128 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1129
1130 #ifdef CONFIG_MYRI10GE_DCA
1131 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1132 dca_tag_off = cmd.data0;
1133 for (i = 0; i < mgp->num_slices; i++) {
1134 ss = &mgp->ss[i];
1135 if (status == 0) {
1136 ss->dca_tag = (__iomem __be32 *)
1137 (mgp->sram + dca_tag_off + 4 * i);
1138 } else {
1139 ss->dca_tag = NULL;
1140 }
1141 }
1142 #endif /* CONFIG_MYRI10GE_DCA */
1143
1144 /* reset mcp/driver shared state back to 0 */
1145
1146 mgp->link_changes = 0;
1147 for (i = 0; i < mgp->num_slices; i++) {
1148 ss = &mgp->ss[i];
1149
1150 memset(ss->rx_done.entry, 0, bytes);
1151 ss->tx.req = 0;
1152 ss->tx.done = 0;
1153 ss->tx.pkt_start = 0;
1154 ss->tx.pkt_done = 0;
1155 ss->rx_big.cnt = 0;
1156 ss->rx_small.cnt = 0;
1157 ss->rx_done.idx = 0;
1158 ss->rx_done.cnt = 0;
1159 ss->tx.wake_queue = 0;
1160 ss->tx.stop_queue = 0;
1161 }
1162
1163 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1164 myri10ge_change_pause(mgp, mgp->pause);
1165 myri10ge_set_multicast_list(mgp->dev);
1166 return status;
1167 }
1168
1169 #ifdef CONFIG_MYRI10GE_DCA
1170 static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1171 {
1172 int ret;
1173 u16 ctl;
1174
1175 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &ctl);
1176
1177 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1178 if (ret != on) {
1179 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1180 ctl |= (on << 4);
1181 pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, ctl);
1182 }
1183 return ret;
1184 }
1185
1186 static void
1187 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1188 {
1189 ss->cached_dca_tag = tag;
1190 put_be32(htonl(tag), ss->dca_tag);
1191 }
1192
1193 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1194 {
1195 int cpu = get_cpu();
1196 int tag;
1197
1198 if (cpu != ss->cpu) {
1199 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
1200 if (ss->cached_dca_tag != tag)
1201 myri10ge_write_dca(ss, cpu, tag);
1202 ss->cpu = cpu;
1203 }
1204 put_cpu();
1205 }
1206
1207 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1208 {
1209 int err, i;
1210 struct pci_dev *pdev = mgp->pdev;
1211
1212 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1213 return;
1214 if (!myri10ge_dca) {
1215 dev_err(&pdev->dev, "dca disabled by administrator\n");
1216 return;
1217 }
1218 err = dca_add_requester(&pdev->dev);
1219 if (err) {
1220 if (err != -ENODEV)
1221 dev_err(&pdev->dev,
1222 "dca_add_requester() failed, err=%d\n", err);
1223 return;
1224 }
1225 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
1226 mgp->dca_enabled = 1;
1227 for (i = 0; i < mgp->num_slices; i++) {
1228 mgp->ss[i].cpu = -1;
1229 mgp->ss[i].cached_dca_tag = -1;
1230 myri10ge_update_dca(&mgp->ss[i]);
1231 }
1232 }
1233
1234 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1235 {
1236 struct pci_dev *pdev = mgp->pdev;
1237
1238 if (!mgp->dca_enabled)
1239 return;
1240 mgp->dca_enabled = 0;
1241 if (mgp->relaxed_order)
1242 myri10ge_toggle_relaxed(pdev, 1);
1243 dca_remove_requester(&pdev->dev);
1244 }
1245
1246 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1247 {
1248 struct myri10ge_priv *mgp;
1249 unsigned long event;
1250
1251 mgp = dev_get_drvdata(dev);
1252 event = *(unsigned long *)data;
1253
1254 if (event == DCA_PROVIDER_ADD)
1255 myri10ge_setup_dca(mgp);
1256 else if (event == DCA_PROVIDER_REMOVE)
1257 myri10ge_teardown_dca(mgp);
1258 return 0;
1259 }
1260 #endif /* CONFIG_MYRI10GE_DCA */
1261
1262 static inline void
1263 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1264 struct mcp_kreq_ether_recv *src)
1265 {
1266 __be32 low;
1267
1268 low = src->addr_low;
1269 src->addr_low = htonl(DMA_BIT_MASK(32));
1270 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1271 mb();
1272 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1273 mb();
1274 src->addr_low = low;
1275 put_be32(low, &dst->addr_low);
1276 mb();
1277 }
1278
1279 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1280 {
1281 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1282
1283 if ((skb->protocol == htons(ETH_P_8021Q)) &&
1284 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1285 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1286 skb->csum = hw_csum;
1287 skb->ip_summed = CHECKSUM_COMPLETE;
1288 }
1289 }
1290
1291 static void
1292 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1293 int bytes, int watchdog)
1294 {
1295 struct page *page;
1296 int idx;
1297 #if MYRI10GE_ALLOC_SIZE > 4096
1298 int end_offset;
1299 #endif
1300
1301 if (unlikely(rx->watchdog_needed && !watchdog))
1302 return;
1303
1304 /* try to refill entire ring */
1305 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1306 idx = rx->fill_cnt & rx->mask;
1307 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1308 /* we can use part of previous page */
1309 get_page(rx->page);
1310 } else {
1311 /* we need a new page */
1312 page =
1313 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1314 MYRI10GE_ALLOC_ORDER);
1315 if (unlikely(page == NULL)) {
1316 if (rx->fill_cnt - rx->cnt < 16)
1317 rx->watchdog_needed = 1;
1318 return;
1319 }
1320 rx->page = page;
1321 rx->page_offset = 0;
1322 rx->bus = pci_map_page(mgp->pdev, page, 0,
1323 MYRI10GE_ALLOC_SIZE,
1324 PCI_DMA_FROMDEVICE);
1325 }
1326 rx->info[idx].page = rx->page;
1327 rx->info[idx].page_offset = rx->page_offset;
1328 /* note that this is the address of the start of the
1329 * page */
1330 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1331 rx->shadow[idx].addr_low =
1332 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1333 rx->shadow[idx].addr_high =
1334 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1335
1336 /* start next packet on a cacheline boundary */
1337 rx->page_offset += SKB_DATA_ALIGN(bytes);
1338
1339 #if MYRI10GE_ALLOC_SIZE > 4096
1340 /* don't cross a 4KB boundary */
1341 end_offset = rx->page_offset + bytes - 1;
1342 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1343 rx->page_offset = end_offset & ~4095;
1344 #endif
1345 rx->fill_cnt++;
1346
1347 /* copy 8 descriptors to the firmware at a time */
1348 if ((idx & 7) == 7) {
1349 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1350 &rx->shadow[idx - 7]);
1351 }
1352 }
1353 }
1354
1355 static inline void
1356 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1357 struct myri10ge_rx_buffer_state *info, int bytes)
1358 {
1359 /* unmap the recvd page if we're the only or last user of it */
1360 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1361 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1362 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
1363 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1364 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1365 }
1366 }
1367
1368 /*
1369 * GRO does not support acceleration of tagged vlan frames, and
1370 * this NIC does not support vlan tag offload, so we must pop
1371 * the tag ourselves to be able to achieve GRO performance that
1372 * is comparable to LRO.
1373 */
1374
1375 static inline void
1376 myri10ge_vlan_rx(struct net_device *dev, void *addr, struct sk_buff *skb)
1377 {
1378 u8 *va;
1379 struct vlan_ethhdr *veh;
1380 struct skb_frag_struct *frag;
1381 __wsum vsum;
1382
1383 va = addr;
1384 va += MXGEFW_PAD;
1385 veh = (struct vlan_ethhdr *)va;
1386 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
1387 NETIF_F_HW_VLAN_CTAG_RX &&
1388 veh->h_vlan_proto == htons(ETH_P_8021Q)) {
1389 /* fixup csum if needed */
1390 if (skb->ip_summed == CHECKSUM_COMPLETE) {
1391 vsum = csum_partial(va + ETH_HLEN, VLAN_HLEN, 0);
1392 skb->csum = csum_sub(skb->csum, vsum);
1393 }
1394 /* pop tag */
1395 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(veh->h_vlan_TCI));
1396 memmove(va + VLAN_HLEN, va, 2 * ETH_ALEN);
1397 skb->len -= VLAN_HLEN;
1398 skb->data_len -= VLAN_HLEN;
1399 frag = skb_shinfo(skb)->frags;
1400 frag->page_offset += VLAN_HLEN;
1401 skb_frag_size_set(frag, skb_frag_size(frag) - VLAN_HLEN);
1402 }
1403 }
1404
1405 #define MYRI10GE_HLEN 64 /* Bytes to copy from page to skb linear memory */
1406
1407 static inline int
1408 myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum)
1409 {
1410 struct myri10ge_priv *mgp = ss->mgp;
1411 struct sk_buff *skb;
1412 struct skb_frag_struct *rx_frags;
1413 struct myri10ge_rx_buf *rx;
1414 int i, idx, remainder, bytes;
1415 struct pci_dev *pdev = mgp->pdev;
1416 struct net_device *dev = mgp->dev;
1417 u8 *va;
1418 bool polling;
1419
1420 if (len <= mgp->small_bytes) {
1421 rx = &ss->rx_small;
1422 bytes = mgp->small_bytes;
1423 } else {
1424 rx = &ss->rx_big;
1425 bytes = mgp->big_bytes;
1426 }
1427
1428 len += MXGEFW_PAD;
1429 idx = rx->cnt & rx->mask;
1430 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1431 prefetch(va);
1432
1433 /* When busy polling in user context, allocate skb and copy headers to
1434 * skb's linear memory ourselves. When not busy polling, use the napi
1435 * gro api.
1436 */
1437 polling = myri10ge_ss_busy_polling(ss);
1438 if (polling)
1439 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1440 else
1441 skb = napi_get_frags(&ss->napi);
1442 if (unlikely(skb == NULL)) {
1443 ss->stats.rx_dropped++;
1444 for (i = 0, remainder = len; remainder > 0; i++) {
1445 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1446 put_page(rx->info[idx].page);
1447 rx->cnt++;
1448 idx = rx->cnt & rx->mask;
1449 remainder -= MYRI10GE_ALLOC_SIZE;
1450 }
1451 return 0;
1452 }
1453 rx_frags = skb_shinfo(skb)->frags;
1454 /* Fill skb_frag_struct(s) with data from our receive */
1455 for (i = 0, remainder = len; remainder > 0; i++) {
1456 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1457 skb_fill_page_desc(skb, i, rx->info[idx].page,
1458 rx->info[idx].page_offset,
1459 remainder < MYRI10GE_ALLOC_SIZE ?
1460 remainder : MYRI10GE_ALLOC_SIZE);
1461 rx->cnt++;
1462 idx = rx->cnt & rx->mask;
1463 remainder -= MYRI10GE_ALLOC_SIZE;
1464 }
1465
1466 /* remove padding */
1467 rx_frags[0].page_offset += MXGEFW_PAD;
1468 rx_frags[0].size -= MXGEFW_PAD;
1469 len -= MXGEFW_PAD;
1470
1471 skb->len = len;
1472 skb->data_len = len;
1473 skb->truesize += len;
1474 if (dev->features & NETIF_F_RXCSUM) {
1475 skb->ip_summed = CHECKSUM_COMPLETE;
1476 skb->csum = csum;
1477 }
1478 myri10ge_vlan_rx(mgp->dev, va, skb);
1479 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1480 skb_mark_napi_id(skb, &ss->napi);
1481
1482 if (polling) {
1483 int hlen;
1484
1485 /* myri10ge_vlan_rx might have moved the header, so compute
1486 * length and address again.
1487 */
1488 hlen = MYRI10GE_HLEN > skb->len ? skb->len : MYRI10GE_HLEN;
1489 va = page_address(skb_frag_page(&rx_frags[0])) +
1490 rx_frags[0].page_offset;
1491 /* Copy header into the skb linear memory */
1492 skb_copy_to_linear_data(skb, va, hlen);
1493 rx_frags[0].page_offset += hlen;
1494 rx_frags[0].size -= hlen;
1495 skb->data_len -= hlen;
1496 skb->tail += hlen;
1497 skb->protocol = eth_type_trans(skb, dev);
1498 netif_receive_skb(skb);
1499 }
1500 else
1501 napi_gro_frags(&ss->napi);
1502
1503 return 1;
1504 }
1505
1506 static inline void
1507 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1508 {
1509 struct pci_dev *pdev = ss->mgp->pdev;
1510 struct myri10ge_tx_buf *tx = &ss->tx;
1511 struct netdev_queue *dev_queue;
1512 struct sk_buff *skb;
1513 int idx, len;
1514
1515 while (tx->pkt_done != mcp_index) {
1516 idx = tx->done & tx->mask;
1517 skb = tx->info[idx].skb;
1518
1519 /* Mark as free */
1520 tx->info[idx].skb = NULL;
1521 if (tx->info[idx].last) {
1522 tx->pkt_done++;
1523 tx->info[idx].last = 0;
1524 }
1525 tx->done++;
1526 len = dma_unmap_len(&tx->info[idx], len);
1527 dma_unmap_len_set(&tx->info[idx], len, 0);
1528 if (skb) {
1529 ss->stats.tx_bytes += skb->len;
1530 ss->stats.tx_packets++;
1531 dev_kfree_skb_irq(skb);
1532 if (len)
1533 pci_unmap_single(pdev,
1534 dma_unmap_addr(&tx->info[idx],
1535 bus), len,
1536 PCI_DMA_TODEVICE);
1537 } else {
1538 if (len)
1539 pci_unmap_page(pdev,
1540 dma_unmap_addr(&tx->info[idx],
1541 bus), len,
1542 PCI_DMA_TODEVICE);
1543 }
1544 }
1545
1546 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1547 /*
1548 * Make a minimal effort to prevent the NIC from polling an
1549 * idle tx queue. If we can't get the lock we leave the queue
1550 * active. In this case, either a thread was about to start
1551 * using the queue anyway, or we lost a race and the NIC will
1552 * waste some of its resources polling an inactive queue for a
1553 * while.
1554 */
1555
1556 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1557 __netif_tx_trylock(dev_queue)) {
1558 if (tx->req == tx->done) {
1559 tx->queue_active = 0;
1560 put_be32(htonl(1), tx->send_stop);
1561 mb();
1562 mmiowb();
1563 }
1564 __netif_tx_unlock(dev_queue);
1565 }
1566
1567 /* start the queue if we've stopped it */
1568 if (netif_tx_queue_stopped(dev_queue) &&
1569 tx->req - tx->done < (tx->mask >> 1) &&
1570 ss->mgp->running == MYRI10GE_ETH_RUNNING) {
1571 tx->wake_queue++;
1572 netif_tx_wake_queue(dev_queue);
1573 }
1574 }
1575
1576 static inline int
1577 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1578 {
1579 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1580 struct myri10ge_priv *mgp = ss->mgp;
1581 unsigned long rx_bytes = 0;
1582 unsigned long rx_packets = 0;
1583 unsigned long rx_ok;
1584 int idx = rx_done->idx;
1585 int cnt = rx_done->cnt;
1586 int work_done = 0;
1587 u16 length;
1588 __wsum checksum;
1589
1590 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1591 length = ntohs(rx_done->entry[idx].length);
1592 rx_done->entry[idx].length = 0;
1593 checksum = csum_unfold(rx_done->entry[idx].checksum);
1594 rx_ok = myri10ge_rx_done(ss, length, checksum);
1595 rx_packets += rx_ok;
1596 rx_bytes += rx_ok * (unsigned long)length;
1597 cnt++;
1598 idx = cnt & (mgp->max_intr_slots - 1);
1599 work_done++;
1600 }
1601 rx_done->idx = idx;
1602 rx_done->cnt = cnt;
1603 ss->stats.rx_packets += rx_packets;
1604 ss->stats.rx_bytes += rx_bytes;
1605
1606 /* restock receive rings if needed */
1607 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1608 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1609 mgp->small_bytes + MXGEFW_PAD, 0);
1610 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1611 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1612
1613 return work_done;
1614 }
1615
1616 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1617 {
1618 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1619
1620 if (unlikely(stats->stats_updated)) {
1621 unsigned link_up = ntohl(stats->link_up);
1622 if (mgp->link_state != link_up) {
1623 mgp->link_state = link_up;
1624
1625 if (mgp->link_state == MXGEFW_LINK_UP) {
1626 netif_info(mgp, link, mgp->dev, "link up\n");
1627 netif_carrier_on(mgp->dev);
1628 mgp->link_changes++;
1629 } else {
1630 netif_info(mgp, link, mgp->dev, "link %s\n",
1631 (link_up == MXGEFW_LINK_MYRINET ?
1632 "mismatch (Myrinet detected)" :
1633 "down"));
1634 netif_carrier_off(mgp->dev);
1635 mgp->link_changes++;
1636 }
1637 }
1638 if (mgp->rdma_tags_available !=
1639 ntohl(stats->rdma_tags_available)) {
1640 mgp->rdma_tags_available =
1641 ntohl(stats->rdma_tags_available);
1642 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1643 mgp->rdma_tags_available);
1644 }
1645 mgp->down_cnt += stats->link_down;
1646 if (stats->link_down)
1647 wake_up(&mgp->down_wq);
1648 }
1649 }
1650
1651 static int myri10ge_poll(struct napi_struct *napi, int budget)
1652 {
1653 struct myri10ge_slice_state *ss =
1654 container_of(napi, struct myri10ge_slice_state, napi);
1655 int work_done;
1656
1657 #ifdef CONFIG_MYRI10GE_DCA
1658 if (ss->mgp->dca_enabled)
1659 myri10ge_update_dca(ss);
1660 #endif
1661 /* Try later if the busy_poll handler is running. */
1662 if (!myri10ge_ss_lock_napi(ss))
1663 return budget;
1664
1665 /* process as many rx events as NAPI will allow */
1666 work_done = myri10ge_clean_rx_done(ss, budget);
1667
1668 myri10ge_ss_unlock_napi(ss);
1669 if (work_done < budget) {
1670 napi_complete(napi);
1671 put_be32(htonl(3), ss->irq_claim);
1672 }
1673 return work_done;
1674 }
1675
1676 #ifdef CONFIG_NET_RX_BUSY_POLL
1677 static int myri10ge_busy_poll(struct napi_struct *napi)
1678 {
1679 struct myri10ge_slice_state *ss =
1680 container_of(napi, struct myri10ge_slice_state, napi);
1681 struct myri10ge_priv *mgp = ss->mgp;
1682 int work_done;
1683
1684 /* Poll only when the link is up */
1685 if (mgp->link_state != MXGEFW_LINK_UP)
1686 return LL_FLUSH_FAILED;
1687
1688 if (!myri10ge_ss_lock_poll(ss))
1689 return LL_FLUSH_BUSY;
1690
1691 /* Process a small number of packets */
1692 work_done = myri10ge_clean_rx_done(ss, 4);
1693 if (work_done)
1694 ss->busy_poll_cnt += work_done;
1695 else
1696 ss->busy_poll_miss++;
1697
1698 myri10ge_ss_unlock_poll(ss);
1699
1700 return work_done;
1701 }
1702 #endif /* CONFIG_NET_RX_BUSY_POLL */
1703
1704 static irqreturn_t myri10ge_intr(int irq, void *arg)
1705 {
1706 struct myri10ge_slice_state *ss = arg;
1707 struct myri10ge_priv *mgp = ss->mgp;
1708 struct mcp_irq_data *stats = ss->fw_stats;
1709 struct myri10ge_tx_buf *tx = &ss->tx;
1710 u32 send_done_count;
1711 int i;
1712
1713 /* an interrupt on a non-zero receive-only slice is implicitly
1714 * valid since MSI-X irqs are not shared */
1715 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1716 napi_schedule(&ss->napi);
1717 return IRQ_HANDLED;
1718 }
1719
1720 /* make sure it is our IRQ, and that the DMA has finished */
1721 if (unlikely(!stats->valid))
1722 return IRQ_NONE;
1723
1724 /* low bit indicates receives are present, so schedule
1725 * napi poll handler */
1726 if (stats->valid & 1)
1727 napi_schedule(&ss->napi);
1728
1729 if (!mgp->msi_enabled && !mgp->msix_enabled) {
1730 put_be32(0, mgp->irq_deassert);
1731 if (!myri10ge_deassert_wait)
1732 stats->valid = 0;
1733 mb();
1734 } else
1735 stats->valid = 0;
1736
1737 /* Wait for IRQ line to go low, if using INTx */
1738 i = 0;
1739 while (1) {
1740 i++;
1741 /* check for transmit completes and receives */
1742 send_done_count = ntohl(stats->send_done_count);
1743 if (send_done_count != tx->pkt_done)
1744 myri10ge_tx_done(ss, (int)send_done_count);
1745 if (unlikely(i > myri10ge_max_irq_loops)) {
1746 netdev_warn(mgp->dev, "irq stuck?\n");
1747 stats->valid = 0;
1748 schedule_work(&mgp->watchdog_work);
1749 }
1750 if (likely(stats->valid == 0))
1751 break;
1752 cpu_relax();
1753 barrier();
1754 }
1755
1756 /* Only slice 0 updates stats */
1757 if (ss == mgp->ss)
1758 myri10ge_check_statblock(mgp);
1759
1760 put_be32(htonl(3), ss->irq_claim + 1);
1761 return IRQ_HANDLED;
1762 }
1763
1764 static int
1765 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1766 {
1767 struct myri10ge_priv *mgp = netdev_priv(netdev);
1768 char *ptr;
1769 int i;
1770
1771 cmd->autoneg = AUTONEG_DISABLE;
1772 ethtool_cmd_speed_set(cmd, SPEED_10000);
1773 cmd->duplex = DUPLEX_FULL;
1774
1775 /*
1776 * parse the product code to deterimine the interface type
1777 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1778 * after the 3rd dash in the driver's cached copy of the
1779 * EEPROM's product code string.
1780 */
1781 ptr = mgp->product_code_string;
1782 if (ptr == NULL) {
1783 netdev_err(netdev, "Missing product code\n");
1784 return 0;
1785 }
1786 for (i = 0; i < 3; i++, ptr++) {
1787 ptr = strchr(ptr, '-');
1788 if (ptr == NULL) {
1789 netdev_err(netdev, "Invalid product code %s\n",
1790 mgp->product_code_string);
1791 return 0;
1792 }
1793 }
1794 if (*ptr == '2')
1795 ptr++;
1796 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1797 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
1798 cmd->port = PORT_FIBRE;
1799 cmd->supported |= SUPPORTED_FIBRE;
1800 cmd->advertising |= ADVERTISED_FIBRE;
1801 } else {
1802 cmd->port = PORT_OTHER;
1803 }
1804 if (*ptr == 'R' || *ptr == 'S')
1805 cmd->transceiver = XCVR_EXTERNAL;
1806 else
1807 cmd->transceiver = XCVR_INTERNAL;
1808
1809 return 0;
1810 }
1811
1812 static void
1813 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1814 {
1815 struct myri10ge_priv *mgp = netdev_priv(netdev);
1816
1817 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1818 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1819 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1820 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1821 }
1822
1823 static int
1824 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1825 {
1826 struct myri10ge_priv *mgp = netdev_priv(netdev);
1827
1828 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1829 return 0;
1830 }
1831
1832 static int
1833 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1834 {
1835 struct myri10ge_priv *mgp = netdev_priv(netdev);
1836
1837 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1838 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1839 return 0;
1840 }
1841
1842 static void
1843 myri10ge_get_pauseparam(struct net_device *netdev,
1844 struct ethtool_pauseparam *pause)
1845 {
1846 struct myri10ge_priv *mgp = netdev_priv(netdev);
1847
1848 pause->autoneg = 0;
1849 pause->rx_pause = mgp->pause;
1850 pause->tx_pause = mgp->pause;
1851 }
1852
1853 static int
1854 myri10ge_set_pauseparam(struct net_device *netdev,
1855 struct ethtool_pauseparam *pause)
1856 {
1857 struct myri10ge_priv *mgp = netdev_priv(netdev);
1858
1859 if (pause->tx_pause != mgp->pause)
1860 return myri10ge_change_pause(mgp, pause->tx_pause);
1861 if (pause->rx_pause != mgp->pause)
1862 return myri10ge_change_pause(mgp, pause->rx_pause);
1863 if (pause->autoneg != 0)
1864 return -EINVAL;
1865 return 0;
1866 }
1867
1868 static void
1869 myri10ge_get_ringparam(struct net_device *netdev,
1870 struct ethtool_ringparam *ring)
1871 {
1872 struct myri10ge_priv *mgp = netdev_priv(netdev);
1873
1874 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1875 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1876 ring->rx_jumbo_max_pending = 0;
1877 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1878 ring->rx_mini_pending = ring->rx_mini_max_pending;
1879 ring->rx_pending = ring->rx_max_pending;
1880 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1881 ring->tx_pending = ring->tx_max_pending;
1882 }
1883
1884 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1885 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1886 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1887 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1888 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1889 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1890 "tx_heartbeat_errors", "tx_window_errors",
1891 /* device-specific stats */
1892 "tx_boundary", "WC", "irq", "MSI", "MSIX",
1893 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1894 "serial_number", "watchdog_resets",
1895 #ifdef CONFIG_MYRI10GE_DCA
1896 "dca_capable_firmware", "dca_device_present",
1897 #endif
1898 "link_changes", "link_up", "dropped_link_overflow",
1899 "dropped_link_error_or_filtered",
1900 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1901 "dropped_unicast_filtered", "dropped_multicast_filtered",
1902 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1903 "dropped_no_big_buffer"
1904 };
1905
1906 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1907 "----------- slice ---------",
1908 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1909 "rx_small_cnt", "rx_big_cnt",
1910 "wake_queue", "stop_queue", "tx_linearized",
1911 #ifdef CONFIG_NET_RX_BUSY_POLL
1912 "rx_lock_napi_yield", "rx_lock_poll_yield", "rx_busy_poll_miss",
1913 "rx_busy_poll_cnt",
1914 #endif
1915 };
1916
1917 #define MYRI10GE_NET_STATS_LEN 21
1918 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1919 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1920
1921 static void
1922 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1923 {
1924 struct myri10ge_priv *mgp = netdev_priv(netdev);
1925 int i;
1926
1927 switch (stringset) {
1928 case ETH_SS_STATS:
1929 memcpy(data, *myri10ge_gstrings_main_stats,
1930 sizeof(myri10ge_gstrings_main_stats));
1931 data += sizeof(myri10ge_gstrings_main_stats);
1932 for (i = 0; i < mgp->num_slices; i++) {
1933 memcpy(data, *myri10ge_gstrings_slice_stats,
1934 sizeof(myri10ge_gstrings_slice_stats));
1935 data += sizeof(myri10ge_gstrings_slice_stats);
1936 }
1937 break;
1938 }
1939 }
1940
1941 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1942 {
1943 struct myri10ge_priv *mgp = netdev_priv(netdev);
1944
1945 switch (sset) {
1946 case ETH_SS_STATS:
1947 return MYRI10GE_MAIN_STATS_LEN +
1948 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1949 default:
1950 return -EOPNOTSUPP;
1951 }
1952 }
1953
1954 static void
1955 myri10ge_get_ethtool_stats(struct net_device *netdev,
1956 struct ethtool_stats *stats, u64 * data)
1957 {
1958 struct myri10ge_priv *mgp = netdev_priv(netdev);
1959 struct myri10ge_slice_state *ss;
1960 struct rtnl_link_stats64 link_stats;
1961 int slice;
1962 int i;
1963
1964 /* force stats update */
1965 memset(&link_stats, 0, sizeof(link_stats));
1966 (void)myri10ge_get_stats(netdev, &link_stats);
1967 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1968 data[i] = ((u64 *)&link_stats)[i];
1969
1970 data[i++] = (unsigned int)mgp->tx_boundary;
1971 data[i++] = (unsigned int)mgp->wc_enabled;
1972 data[i++] = (unsigned int)mgp->pdev->irq;
1973 data[i++] = (unsigned int)mgp->msi_enabled;
1974 data[i++] = (unsigned int)mgp->msix_enabled;
1975 data[i++] = (unsigned int)mgp->read_dma;
1976 data[i++] = (unsigned int)mgp->write_dma;
1977 data[i++] = (unsigned int)mgp->read_write_dma;
1978 data[i++] = (unsigned int)mgp->serial_number;
1979 data[i++] = (unsigned int)mgp->watchdog_resets;
1980 #ifdef CONFIG_MYRI10GE_DCA
1981 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1982 data[i++] = (unsigned int)(mgp->dca_enabled);
1983 #endif
1984 data[i++] = (unsigned int)mgp->link_changes;
1985
1986 /* firmware stats are useful only in the first slice */
1987 ss = &mgp->ss[0];
1988 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1989 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1990 data[i++] =
1991 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1992 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1993 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1994 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1995 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1996 data[i++] =
1997 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1998 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1999 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
2000 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
2001 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
2002
2003 for (slice = 0; slice < mgp->num_slices; slice++) {
2004 ss = &mgp->ss[slice];
2005 data[i++] = slice;
2006 data[i++] = (unsigned int)ss->tx.pkt_start;
2007 data[i++] = (unsigned int)ss->tx.pkt_done;
2008 data[i++] = (unsigned int)ss->tx.req;
2009 data[i++] = (unsigned int)ss->tx.done;
2010 data[i++] = (unsigned int)ss->rx_small.cnt;
2011 data[i++] = (unsigned int)ss->rx_big.cnt;
2012 data[i++] = (unsigned int)ss->tx.wake_queue;
2013 data[i++] = (unsigned int)ss->tx.stop_queue;
2014 data[i++] = (unsigned int)ss->tx.linearized;
2015 #ifdef CONFIG_NET_RX_BUSY_POLL
2016 data[i++] = ss->lock_napi_yield;
2017 data[i++] = ss->lock_poll_yield;
2018 data[i++] = ss->busy_poll_miss;
2019 data[i++] = ss->busy_poll_cnt;
2020 #endif
2021 }
2022 }
2023
2024 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
2025 {
2026 struct myri10ge_priv *mgp = netdev_priv(netdev);
2027 mgp->msg_enable = value;
2028 }
2029
2030 static u32 myri10ge_get_msglevel(struct net_device *netdev)
2031 {
2032 struct myri10ge_priv *mgp = netdev_priv(netdev);
2033 return mgp->msg_enable;
2034 }
2035
2036 /*
2037 * Use a low-level command to change the LED behavior. Rather than
2038 * blinking (which is the normal case), when identify is used, the
2039 * yellow LED turns solid.
2040 */
2041 static int myri10ge_led(struct myri10ge_priv *mgp, int on)
2042 {
2043 struct mcp_gen_header *hdr;
2044 struct device *dev = &mgp->pdev->dev;
2045 size_t hdr_off, pattern_off, hdr_len;
2046 u32 pattern = 0xfffffffe;
2047
2048 /* find running firmware header */
2049 hdr_off = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
2050 if ((hdr_off & 3) || hdr_off + sizeof(*hdr) > mgp->sram_size) {
2051 dev_err(dev, "Running firmware has bad header offset (%d)\n",
2052 (int)hdr_off);
2053 return -EIO;
2054 }
2055 hdr_len = swab32(readl(mgp->sram + hdr_off +
2056 offsetof(struct mcp_gen_header, header_length)));
2057 pattern_off = hdr_off + offsetof(struct mcp_gen_header, led_pattern);
2058 if (pattern_off >= (hdr_len + hdr_off)) {
2059 dev_info(dev, "Firmware does not support LED identification\n");
2060 return -EINVAL;
2061 }
2062 if (!on)
2063 pattern = swab32(readl(mgp->sram + pattern_off + 4));
2064 writel(swab32(pattern), mgp->sram + pattern_off);
2065 return 0;
2066 }
2067
2068 static int
2069 myri10ge_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
2070 {
2071 struct myri10ge_priv *mgp = netdev_priv(netdev);
2072 int rc;
2073
2074 switch (state) {
2075 case ETHTOOL_ID_ACTIVE:
2076 rc = myri10ge_led(mgp, 1);
2077 break;
2078
2079 case ETHTOOL_ID_INACTIVE:
2080 rc = myri10ge_led(mgp, 0);
2081 break;
2082
2083 default:
2084 rc = -EINVAL;
2085 }
2086
2087 return rc;
2088 }
2089
2090 static const struct ethtool_ops myri10ge_ethtool_ops = {
2091 .get_settings = myri10ge_get_settings,
2092 .get_drvinfo = myri10ge_get_drvinfo,
2093 .get_coalesce = myri10ge_get_coalesce,
2094 .set_coalesce = myri10ge_set_coalesce,
2095 .get_pauseparam = myri10ge_get_pauseparam,
2096 .set_pauseparam = myri10ge_set_pauseparam,
2097 .get_ringparam = myri10ge_get_ringparam,
2098 .get_link = ethtool_op_get_link,
2099 .get_strings = myri10ge_get_strings,
2100 .get_sset_count = myri10ge_get_sset_count,
2101 .get_ethtool_stats = myri10ge_get_ethtool_stats,
2102 .set_msglevel = myri10ge_set_msglevel,
2103 .get_msglevel = myri10ge_get_msglevel,
2104 .set_phys_id = myri10ge_phys_id,
2105 };
2106
2107 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
2108 {
2109 struct myri10ge_priv *mgp = ss->mgp;
2110 struct myri10ge_cmd cmd;
2111 struct net_device *dev = mgp->dev;
2112 int tx_ring_size, rx_ring_size;
2113 int tx_ring_entries, rx_ring_entries;
2114 int i, slice, status;
2115 size_t bytes;
2116
2117 /* get ring sizes */
2118 slice = ss - mgp->ss;
2119 cmd.data0 = slice;
2120 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
2121 tx_ring_size = cmd.data0;
2122 cmd.data0 = slice;
2123 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
2124 if (status != 0)
2125 return status;
2126 rx_ring_size = cmd.data0;
2127
2128 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
2129 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
2130 ss->tx.mask = tx_ring_entries - 1;
2131 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
2132
2133 status = -ENOMEM;
2134
2135 /* allocate the host shadow rings */
2136
2137 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
2138 * sizeof(*ss->tx.req_list);
2139 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
2140 if (ss->tx.req_bytes == NULL)
2141 goto abort_with_nothing;
2142
2143 /* ensure req_list entries are aligned to 8 bytes */
2144 ss->tx.req_list = (struct mcp_kreq_ether_send *)
2145 ALIGN((unsigned long)ss->tx.req_bytes, 8);
2146 ss->tx.queue_active = 0;
2147
2148 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
2149 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
2150 if (ss->rx_small.shadow == NULL)
2151 goto abort_with_tx_req_bytes;
2152
2153 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
2154 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
2155 if (ss->rx_big.shadow == NULL)
2156 goto abort_with_rx_small_shadow;
2157
2158 /* allocate the host info rings */
2159
2160 bytes = tx_ring_entries * sizeof(*ss->tx.info);
2161 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
2162 if (ss->tx.info == NULL)
2163 goto abort_with_rx_big_shadow;
2164
2165 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
2166 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
2167 if (ss->rx_small.info == NULL)
2168 goto abort_with_tx_info;
2169
2170 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
2171 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
2172 if (ss->rx_big.info == NULL)
2173 goto abort_with_rx_small_info;
2174
2175 /* Fill the receive rings */
2176 ss->rx_big.cnt = 0;
2177 ss->rx_small.cnt = 0;
2178 ss->rx_big.fill_cnt = 0;
2179 ss->rx_small.fill_cnt = 0;
2180 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2181 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2182 ss->rx_small.watchdog_needed = 0;
2183 ss->rx_big.watchdog_needed = 0;
2184 if (mgp->small_bytes == 0) {
2185 ss->rx_small.fill_cnt = ss->rx_small.mask + 1;
2186 } else {
2187 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2188 mgp->small_bytes + MXGEFW_PAD, 0);
2189 }
2190
2191 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
2192 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2193 slice, ss->rx_small.fill_cnt);
2194 goto abort_with_rx_small_ring;
2195 }
2196
2197 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2198 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
2199 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2200 slice, ss->rx_big.fill_cnt);
2201 goto abort_with_rx_big_ring;
2202 }
2203
2204 return 0;
2205
2206 abort_with_rx_big_ring:
2207 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2208 int idx = i & ss->rx_big.mask;
2209 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2210 mgp->big_bytes);
2211 put_page(ss->rx_big.info[idx].page);
2212 }
2213
2214 abort_with_rx_small_ring:
2215 if (mgp->small_bytes == 0)
2216 ss->rx_small.fill_cnt = ss->rx_small.cnt;
2217 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2218 int idx = i & ss->rx_small.mask;
2219 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2220 mgp->small_bytes + MXGEFW_PAD);
2221 put_page(ss->rx_small.info[idx].page);
2222 }
2223
2224 kfree(ss->rx_big.info);
2225
2226 abort_with_rx_small_info:
2227 kfree(ss->rx_small.info);
2228
2229 abort_with_tx_info:
2230 kfree(ss->tx.info);
2231
2232 abort_with_rx_big_shadow:
2233 kfree(ss->rx_big.shadow);
2234
2235 abort_with_rx_small_shadow:
2236 kfree(ss->rx_small.shadow);
2237
2238 abort_with_tx_req_bytes:
2239 kfree(ss->tx.req_bytes);
2240 ss->tx.req_bytes = NULL;
2241 ss->tx.req_list = NULL;
2242
2243 abort_with_nothing:
2244 return status;
2245 }
2246
2247 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2248 {
2249 struct myri10ge_priv *mgp = ss->mgp;
2250 struct sk_buff *skb;
2251 struct myri10ge_tx_buf *tx;
2252 int i, len, idx;
2253
2254 /* If not allocated, skip it */
2255 if (ss->tx.req_list == NULL)
2256 return;
2257
2258 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2259 idx = i & ss->rx_big.mask;
2260 if (i == ss->rx_big.fill_cnt - 1)
2261 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2262 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2263 mgp->big_bytes);
2264 put_page(ss->rx_big.info[idx].page);
2265 }
2266
2267 if (mgp->small_bytes == 0)
2268 ss->rx_small.fill_cnt = ss->rx_small.cnt;
2269 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2270 idx = i & ss->rx_small.mask;
2271 if (i == ss->rx_small.fill_cnt - 1)
2272 ss->rx_small.info[idx].page_offset =
2273 MYRI10GE_ALLOC_SIZE;
2274 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2275 mgp->small_bytes + MXGEFW_PAD);
2276 put_page(ss->rx_small.info[idx].page);
2277 }
2278 tx = &ss->tx;
2279 while (tx->done != tx->req) {
2280 idx = tx->done & tx->mask;
2281 skb = tx->info[idx].skb;
2282
2283 /* Mark as free */
2284 tx->info[idx].skb = NULL;
2285 tx->done++;
2286 len = dma_unmap_len(&tx->info[idx], len);
2287 dma_unmap_len_set(&tx->info[idx], len, 0);
2288 if (skb) {
2289 ss->stats.tx_dropped++;
2290 dev_kfree_skb_any(skb);
2291 if (len)
2292 pci_unmap_single(mgp->pdev,
2293 dma_unmap_addr(&tx->info[idx],
2294 bus), len,
2295 PCI_DMA_TODEVICE);
2296 } else {
2297 if (len)
2298 pci_unmap_page(mgp->pdev,
2299 dma_unmap_addr(&tx->info[idx],
2300 bus), len,
2301 PCI_DMA_TODEVICE);
2302 }
2303 }
2304 kfree(ss->rx_big.info);
2305
2306 kfree(ss->rx_small.info);
2307
2308 kfree(ss->tx.info);
2309
2310 kfree(ss->rx_big.shadow);
2311
2312 kfree(ss->rx_small.shadow);
2313
2314 kfree(ss->tx.req_bytes);
2315 ss->tx.req_bytes = NULL;
2316 ss->tx.req_list = NULL;
2317 }
2318
2319 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2320 {
2321 struct pci_dev *pdev = mgp->pdev;
2322 struct myri10ge_slice_state *ss;
2323 struct net_device *netdev = mgp->dev;
2324 int i;
2325 int status;
2326
2327 mgp->msi_enabled = 0;
2328 mgp->msix_enabled = 0;
2329 status = 0;
2330 if (myri10ge_msi) {
2331 if (mgp->num_slices > 1) {
2332 status =
2333 pci_enable_msix(pdev, mgp->msix_vectors,
2334 mgp->num_slices);
2335 if (status == 0) {
2336 mgp->msix_enabled = 1;
2337 } else {
2338 dev_err(&pdev->dev,
2339 "Error %d setting up MSI-X\n", status);
2340 return status;
2341 }
2342 }
2343 if (mgp->msix_enabled == 0) {
2344 status = pci_enable_msi(pdev);
2345 if (status != 0) {
2346 dev_err(&pdev->dev,
2347 "Error %d setting up MSI; falling back to xPIC\n",
2348 status);
2349 } else {
2350 mgp->msi_enabled = 1;
2351 }
2352 }
2353 }
2354 if (mgp->msix_enabled) {
2355 for (i = 0; i < mgp->num_slices; i++) {
2356 ss = &mgp->ss[i];
2357 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2358 "%s:slice-%d", netdev->name, i);
2359 status = request_irq(mgp->msix_vectors[i].vector,
2360 myri10ge_intr, 0, ss->irq_desc,
2361 ss);
2362 if (status != 0) {
2363 dev_err(&pdev->dev,
2364 "slice %d failed to allocate IRQ\n", i);
2365 i--;
2366 while (i >= 0) {
2367 free_irq(mgp->msix_vectors[i].vector,
2368 &mgp->ss[i]);
2369 i--;
2370 }
2371 pci_disable_msix(pdev);
2372 return status;
2373 }
2374 }
2375 } else {
2376 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2377 mgp->dev->name, &mgp->ss[0]);
2378 if (status != 0) {
2379 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2380 if (mgp->msi_enabled)
2381 pci_disable_msi(pdev);
2382 }
2383 }
2384 return status;
2385 }
2386
2387 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2388 {
2389 struct pci_dev *pdev = mgp->pdev;
2390 int i;
2391
2392 if (mgp->msix_enabled) {
2393 for (i = 0; i < mgp->num_slices; i++)
2394 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2395 } else {
2396 free_irq(pdev->irq, &mgp->ss[0]);
2397 }
2398 if (mgp->msi_enabled)
2399 pci_disable_msi(pdev);
2400 if (mgp->msix_enabled)
2401 pci_disable_msix(pdev);
2402 }
2403
2404 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2405 {
2406 struct myri10ge_cmd cmd;
2407 struct myri10ge_slice_state *ss;
2408 int status;
2409
2410 ss = &mgp->ss[slice];
2411 status = 0;
2412 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2413 cmd.data0 = slice;
2414 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2415 &cmd, 0);
2416 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2417 (mgp->sram + cmd.data0);
2418 }
2419 cmd.data0 = slice;
2420 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2421 &cmd, 0);
2422 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2423 (mgp->sram + cmd.data0);
2424
2425 cmd.data0 = slice;
2426 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2427 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2428 (mgp->sram + cmd.data0);
2429
2430 ss->tx.send_go = (__iomem __be32 *)
2431 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2432 ss->tx.send_stop = (__iomem __be32 *)
2433 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2434 return status;
2435
2436 }
2437
2438 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2439 {
2440 struct myri10ge_cmd cmd;
2441 struct myri10ge_slice_state *ss;
2442 int status;
2443
2444 ss = &mgp->ss[slice];
2445 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2446 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2447 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2448 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2449 if (status == -ENOSYS) {
2450 dma_addr_t bus = ss->fw_stats_bus;
2451 if (slice != 0)
2452 return -EINVAL;
2453 bus += offsetof(struct mcp_irq_data, send_done_count);
2454 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2455 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2456 status = myri10ge_send_cmd(mgp,
2457 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2458 &cmd, 0);
2459 /* Firmware cannot support multicast without STATS_DMA_V2 */
2460 mgp->fw_multicast_support = 0;
2461 } else {
2462 mgp->fw_multicast_support = 1;
2463 }
2464 return 0;
2465 }
2466
2467 static int myri10ge_open(struct net_device *dev)
2468 {
2469 struct myri10ge_slice_state *ss;
2470 struct myri10ge_priv *mgp = netdev_priv(dev);
2471 struct myri10ge_cmd cmd;
2472 int i, status, big_pow2, slice;
2473 u8 __iomem *itable;
2474
2475 if (mgp->running != MYRI10GE_ETH_STOPPED)
2476 return -EBUSY;
2477
2478 mgp->running = MYRI10GE_ETH_STARTING;
2479 status = myri10ge_reset(mgp);
2480 if (status != 0) {
2481 netdev_err(dev, "failed reset\n");
2482 goto abort_with_nothing;
2483 }
2484
2485 if (mgp->num_slices > 1) {
2486 cmd.data0 = mgp->num_slices;
2487 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2488 if (mgp->dev->real_num_tx_queues > 1)
2489 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2490 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2491 &cmd, 0);
2492 if (status != 0) {
2493 netdev_err(dev, "failed to set number of slices\n");
2494 goto abort_with_nothing;
2495 }
2496 /* setup the indirection table */
2497 cmd.data0 = mgp->num_slices;
2498 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2499 &cmd, 0);
2500
2501 status |= myri10ge_send_cmd(mgp,
2502 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2503 &cmd, 0);
2504 if (status != 0) {
2505 netdev_err(dev, "failed to setup rss tables\n");
2506 goto abort_with_nothing;
2507 }
2508
2509 /* just enable an identity mapping */
2510 itable = mgp->sram + cmd.data0;
2511 for (i = 0; i < mgp->num_slices; i++)
2512 __raw_writeb(i, &itable[i]);
2513
2514 cmd.data0 = 1;
2515 cmd.data1 = myri10ge_rss_hash;
2516 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2517 &cmd, 0);
2518 if (status != 0) {
2519 netdev_err(dev, "failed to enable slices\n");
2520 goto abort_with_nothing;
2521 }
2522 }
2523
2524 status = myri10ge_request_irq(mgp);
2525 if (status != 0)
2526 goto abort_with_nothing;
2527
2528 /* decide what small buffer size to use. For good TCP rx
2529 * performance, it is important to not receive 1514 byte
2530 * frames into jumbo buffers, as it confuses the socket buffer
2531 * accounting code, leading to drops and erratic performance.
2532 */
2533
2534 if (dev->mtu <= ETH_DATA_LEN)
2535 /* enough for a TCP header */
2536 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2537 ? (128 - MXGEFW_PAD)
2538 : (SMP_CACHE_BYTES - MXGEFW_PAD);
2539 else
2540 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2541 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2542
2543 /* Override the small buffer size? */
2544 if (myri10ge_small_bytes >= 0)
2545 mgp->small_bytes = myri10ge_small_bytes;
2546
2547 /* Firmware needs the big buff size as a power of 2. Lie and
2548 * tell him the buffer is larger, because we only use 1
2549 * buffer/pkt, and the mtu will prevent overruns.
2550 */
2551 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2552 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2553 while (!is_power_of_2(big_pow2))
2554 big_pow2++;
2555 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2556 } else {
2557 big_pow2 = MYRI10GE_ALLOC_SIZE;
2558 mgp->big_bytes = big_pow2;
2559 }
2560
2561 /* setup the per-slice data structures */
2562 for (slice = 0; slice < mgp->num_slices; slice++) {
2563 ss = &mgp->ss[slice];
2564
2565 status = myri10ge_get_txrx(mgp, slice);
2566 if (status != 0) {
2567 netdev_err(dev, "failed to get ring sizes or locations\n");
2568 goto abort_with_rings;
2569 }
2570 status = myri10ge_allocate_rings(ss);
2571 if (status != 0)
2572 goto abort_with_rings;
2573
2574 /* only firmware which supports multiple TX queues
2575 * supports setting up the tx stats on non-zero
2576 * slices */
2577 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2578 status = myri10ge_set_stats(mgp, slice);
2579 if (status) {
2580 netdev_err(dev, "Couldn't set stats DMA\n");
2581 goto abort_with_rings;
2582 }
2583
2584 /* Initialize the slice spinlock and state used for polling */
2585 myri10ge_ss_init_lock(ss);
2586
2587 /* must happen prior to any irq */
2588 napi_enable(&(ss)->napi);
2589 }
2590
2591 /* now give firmware buffers sizes, and MTU */
2592 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2593 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2594 cmd.data0 = mgp->small_bytes;
2595 status |=
2596 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2597 cmd.data0 = big_pow2;
2598 status |=
2599 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2600 if (status) {
2601 netdev_err(dev, "Couldn't set buffer sizes\n");
2602 goto abort_with_rings;
2603 }
2604
2605 /*
2606 * Set Linux style TSO mode; this is needed only on newer
2607 * firmware versions. Older versions default to Linux
2608 * style TSO
2609 */
2610 cmd.data0 = 0;
2611 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2612 if (status && status != -ENOSYS) {
2613 netdev_err(dev, "Couldn't set TSO mode\n");
2614 goto abort_with_rings;
2615 }
2616
2617 mgp->link_state = ~0U;
2618 mgp->rdma_tags_available = 15;
2619
2620 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2621 if (status) {
2622 netdev_err(dev, "Couldn't bring up link\n");
2623 goto abort_with_rings;
2624 }
2625
2626 mgp->running = MYRI10GE_ETH_RUNNING;
2627 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2628 add_timer(&mgp->watchdog_timer);
2629 netif_tx_wake_all_queues(dev);
2630
2631 return 0;
2632
2633 abort_with_rings:
2634 while (slice) {
2635 slice--;
2636 napi_disable(&mgp->ss[slice].napi);
2637 }
2638 for (i = 0; i < mgp->num_slices; i++)
2639 myri10ge_free_rings(&mgp->ss[i]);
2640
2641 myri10ge_free_irq(mgp);
2642
2643 abort_with_nothing:
2644 mgp->running = MYRI10GE_ETH_STOPPED;
2645 return -ENOMEM;
2646 }
2647
2648 static int myri10ge_close(struct net_device *dev)
2649 {
2650 struct myri10ge_priv *mgp = netdev_priv(dev);
2651 struct myri10ge_cmd cmd;
2652 int status, old_down_cnt;
2653 int i;
2654
2655 if (mgp->running != MYRI10GE_ETH_RUNNING)
2656 return 0;
2657
2658 if (mgp->ss[0].tx.req_bytes == NULL)
2659 return 0;
2660
2661 del_timer_sync(&mgp->watchdog_timer);
2662 mgp->running = MYRI10GE_ETH_STOPPING;
2663 local_bh_disable(); /* myri10ge_ss_lock_napi needs bh disabled */
2664 for (i = 0; i < mgp->num_slices; i++) {
2665 napi_disable(&mgp->ss[i].napi);
2666 /* Lock the slice to prevent the busy_poll handler from
2667 * accessing it. Later when we bring the NIC up, myri10ge_open
2668 * resets the slice including this lock.
2669 */
2670 while (!myri10ge_ss_lock_napi(&mgp->ss[i])) {
2671 pr_info("Slice %d locked\n", i);
2672 mdelay(1);
2673 }
2674 }
2675 local_bh_enable();
2676 netif_carrier_off(dev);
2677
2678 netif_tx_stop_all_queues(dev);
2679 if (mgp->rebooted == 0) {
2680 old_down_cnt = mgp->down_cnt;
2681 mb();
2682 status =
2683 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2684 if (status)
2685 netdev_err(dev, "Couldn't bring down link\n");
2686
2687 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2688 HZ);
2689 if (old_down_cnt == mgp->down_cnt)
2690 netdev_err(dev, "never got down irq\n");
2691 }
2692 netif_tx_disable(dev);
2693 myri10ge_free_irq(mgp);
2694 for (i = 0; i < mgp->num_slices; i++)
2695 myri10ge_free_rings(&mgp->ss[i]);
2696
2697 mgp->running = MYRI10GE_ETH_STOPPED;
2698 return 0;
2699 }
2700
2701 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2702 * backwards one at a time and handle ring wraps */
2703
2704 static inline void
2705 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2706 struct mcp_kreq_ether_send *src, int cnt)
2707 {
2708 int idx, starting_slot;
2709 starting_slot = tx->req;
2710 while (cnt > 1) {
2711 cnt--;
2712 idx = (starting_slot + cnt) & tx->mask;
2713 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2714 mb();
2715 }
2716 }
2717
2718 /*
2719 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2720 * at most 32 bytes at a time, so as to avoid involving the software
2721 * pio handler in the nic. We re-write the first segment's flags
2722 * to mark them valid only after writing the entire chain.
2723 */
2724
2725 static inline void
2726 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2727 int cnt)
2728 {
2729 int idx, i;
2730 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2731 struct mcp_kreq_ether_send *srcp;
2732 u8 last_flags;
2733
2734 idx = tx->req & tx->mask;
2735
2736 last_flags = src->flags;
2737 src->flags = 0;
2738 mb();
2739 dst = dstp = &tx->lanai[idx];
2740 srcp = src;
2741
2742 if ((idx + cnt) < tx->mask) {
2743 for (i = 0; i < (cnt - 1); i += 2) {
2744 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2745 mb(); /* force write every 32 bytes */
2746 srcp += 2;
2747 dstp += 2;
2748 }
2749 } else {
2750 /* submit all but the first request, and ensure
2751 * that it is submitted below */
2752 myri10ge_submit_req_backwards(tx, src, cnt);
2753 i = 0;
2754 }
2755 if (i < cnt) {
2756 /* submit the first request */
2757 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2758 mb(); /* barrier before setting valid flag */
2759 }
2760
2761 /* re-write the last 32-bits with the valid flags */
2762 src->flags = last_flags;
2763 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2764 tx->req += cnt;
2765 mb();
2766 }
2767
2768 /*
2769 * Transmit a packet. We need to split the packet so that a single
2770 * segment does not cross myri10ge->tx_boundary, so this makes segment
2771 * counting tricky. So rather than try to count segments up front, we
2772 * just give up if there are too few segments to hold a reasonably
2773 * fragmented packet currently available. If we run
2774 * out of segments while preparing a packet for DMA, we just linearize
2775 * it and try again.
2776 */
2777
2778 static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2779 struct net_device *dev)
2780 {
2781 struct myri10ge_priv *mgp = netdev_priv(dev);
2782 struct myri10ge_slice_state *ss;
2783 struct mcp_kreq_ether_send *req;
2784 struct myri10ge_tx_buf *tx;
2785 struct skb_frag_struct *frag;
2786 struct netdev_queue *netdev_queue;
2787 dma_addr_t bus;
2788 u32 low;
2789 __be32 high_swapped;
2790 unsigned int len;
2791 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2792 u16 pseudo_hdr_offset, cksum_offset, queue;
2793 int cum_len, seglen, boundary, rdma_count;
2794 u8 flags, odd_flag;
2795
2796 queue = skb_get_queue_mapping(skb);
2797 ss = &mgp->ss[queue];
2798 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2799 tx = &ss->tx;
2800
2801 again:
2802 req = tx->req_list;
2803 avail = tx->mask - 1 - (tx->req - tx->done);
2804
2805 mss = 0;
2806 max_segments = MXGEFW_MAX_SEND_DESC;
2807
2808 if (skb_is_gso(skb)) {
2809 mss = skb_shinfo(skb)->gso_size;
2810 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2811 }
2812
2813 if ((unlikely(avail < max_segments))) {
2814 /* we are out of transmit resources */
2815 tx->stop_queue++;
2816 netif_tx_stop_queue(netdev_queue);
2817 return NETDEV_TX_BUSY;
2818 }
2819
2820 /* Setup checksum offloading, if needed */
2821 cksum_offset = 0;
2822 pseudo_hdr_offset = 0;
2823 odd_flag = 0;
2824 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2825 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2826 cksum_offset = skb_checksum_start_offset(skb);
2827 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2828 /* If the headers are excessively large, then we must
2829 * fall back to a software checksum */
2830 if (unlikely(!mss && (cksum_offset > 255 ||
2831 pseudo_hdr_offset > 127))) {
2832 if (skb_checksum_help(skb))
2833 goto drop;
2834 cksum_offset = 0;
2835 pseudo_hdr_offset = 0;
2836 } else {
2837 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2838 flags |= MXGEFW_FLAGS_CKSUM;
2839 }
2840 }
2841
2842 cum_len = 0;
2843
2844 if (mss) { /* TSO */
2845 /* this removes any CKSUM flag from before */
2846 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2847
2848 /* negative cum_len signifies to the
2849 * send loop that we are still in the
2850 * header portion of the TSO packet.
2851 * TSO header can be at most 1KB long */
2852 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2853
2854 /* for IPv6 TSO, the checksum offset stores the
2855 * TCP header length, to save the firmware from
2856 * the need to parse the headers */
2857 if (skb_is_gso_v6(skb)) {
2858 cksum_offset = tcp_hdrlen(skb);
2859 /* Can only handle headers <= max_tso6 long */
2860 if (unlikely(-cum_len > mgp->max_tso6))
2861 return myri10ge_sw_tso(skb, dev);
2862 }
2863 /* for TSO, pseudo_hdr_offset holds mss.
2864 * The firmware figures out where to put
2865 * the checksum by parsing the header. */
2866 pseudo_hdr_offset = mss;
2867 } else
2868 /* Mark small packets, and pad out tiny packets */
2869 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2870 flags |= MXGEFW_FLAGS_SMALL;
2871
2872 /* pad frames to at least ETH_ZLEN bytes */
2873 if (unlikely(skb->len < ETH_ZLEN)) {
2874 if (skb_padto(skb, ETH_ZLEN)) {
2875 /* The packet is gone, so we must
2876 * return 0 */
2877 ss->stats.tx_dropped += 1;
2878 return NETDEV_TX_OK;
2879 }
2880 /* adjust the len to account for the zero pad
2881 * so that the nic can know how long it is */
2882 skb->len = ETH_ZLEN;
2883 }
2884 }
2885
2886 /* map the skb for DMA */
2887 len = skb_headlen(skb);
2888 idx = tx->req & tx->mask;
2889 tx->info[idx].skb = skb;
2890 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2891 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2892 dma_unmap_len_set(&tx->info[idx], len, len);
2893
2894 frag_cnt = skb_shinfo(skb)->nr_frags;
2895 frag_idx = 0;
2896 count = 0;
2897 rdma_count = 0;
2898
2899 /* "rdma_count" is the number of RDMAs belonging to the
2900 * current packet BEFORE the current send request. For
2901 * non-TSO packets, this is equal to "count".
2902 * For TSO packets, rdma_count needs to be reset
2903 * to 0 after a segment cut.
2904 *
2905 * The rdma_count field of the send request is
2906 * the number of RDMAs of the packet starting at
2907 * that request. For TSO send requests with one ore more cuts
2908 * in the middle, this is the number of RDMAs starting
2909 * after the last cut in the request. All previous
2910 * segments before the last cut implicitly have 1 RDMA.
2911 *
2912 * Since the number of RDMAs is not known beforehand,
2913 * it must be filled-in retroactively - after each
2914 * segmentation cut or at the end of the entire packet.
2915 */
2916
2917 while (1) {
2918 /* Break the SKB or Fragment up into pieces which
2919 * do not cross mgp->tx_boundary */
2920 low = MYRI10GE_LOWPART_TO_U32(bus);
2921 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2922 while (len) {
2923 u8 flags_next;
2924 int cum_len_next;
2925
2926 if (unlikely(count == max_segments))
2927 goto abort_linearize;
2928
2929 boundary =
2930 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2931 seglen = boundary - low;
2932 if (seglen > len)
2933 seglen = len;
2934 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2935 cum_len_next = cum_len + seglen;
2936 if (mss) { /* TSO */
2937 (req - rdma_count)->rdma_count = rdma_count + 1;
2938
2939 if (likely(cum_len >= 0)) { /* payload */
2940 int next_is_first, chop;
2941
2942 chop = (cum_len_next > mss);
2943 cum_len_next = cum_len_next % mss;
2944 next_is_first = (cum_len_next == 0);
2945 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2946 flags_next |= next_is_first *
2947 MXGEFW_FLAGS_FIRST;
2948 rdma_count |= -(chop | next_is_first);
2949 rdma_count += chop & ~next_is_first;
2950 } else if (likely(cum_len_next >= 0)) { /* header ends */
2951 int small;
2952
2953 rdma_count = -1;
2954 cum_len_next = 0;
2955 seglen = -cum_len;
2956 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2957 flags_next = MXGEFW_FLAGS_TSO_PLD |
2958 MXGEFW_FLAGS_FIRST |
2959 (small * MXGEFW_FLAGS_SMALL);
2960 }
2961 }
2962 req->addr_high = high_swapped;
2963 req->addr_low = htonl(low);
2964 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2965 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2966 req->rdma_count = 1;
2967 req->length = htons(seglen);
2968 req->cksum_offset = cksum_offset;
2969 req->flags = flags | ((cum_len & 1) * odd_flag);
2970
2971 low += seglen;
2972 len -= seglen;
2973 cum_len = cum_len_next;
2974 flags = flags_next;
2975 req++;
2976 count++;
2977 rdma_count++;
2978 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2979 if (unlikely(cksum_offset > seglen))
2980 cksum_offset -= seglen;
2981 else
2982 cksum_offset = 0;
2983 }
2984 }
2985 if (frag_idx == frag_cnt)
2986 break;
2987
2988 /* map next fragment for DMA */
2989 idx = (count + tx->req) & tx->mask;
2990 frag = &skb_shinfo(skb)->frags[frag_idx];
2991 frag_idx++;
2992 len = skb_frag_size(frag);
2993 bus = skb_frag_dma_map(&mgp->pdev->dev, frag, 0, len,
2994 DMA_TO_DEVICE);
2995 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2996 dma_unmap_len_set(&tx->info[idx], len, len);
2997 }
2998
2999 (req - rdma_count)->rdma_count = rdma_count;
3000 if (mss)
3001 do {
3002 req--;
3003 req->flags |= MXGEFW_FLAGS_TSO_LAST;
3004 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
3005 MXGEFW_FLAGS_FIRST)));
3006 idx = ((count - 1) + tx->req) & tx->mask;
3007 tx->info[idx].last = 1;
3008 myri10ge_submit_req(tx, tx->req_list, count);
3009 /* if using multiple tx queues, make sure NIC polls the
3010 * current slice */
3011 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
3012 tx->queue_active = 1;
3013 put_be32(htonl(1), tx->send_go);
3014 mb();
3015 mmiowb();
3016 }
3017 tx->pkt_start++;
3018 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
3019 tx->stop_queue++;
3020 netif_tx_stop_queue(netdev_queue);
3021 }
3022 return NETDEV_TX_OK;
3023
3024 abort_linearize:
3025 /* Free any DMA resources we've alloced and clear out the skb
3026 * slot so as to not trip up assertions, and to avoid a
3027 * double-free if linearizing fails */
3028
3029 last_idx = (idx + 1) & tx->mask;
3030 idx = tx->req & tx->mask;
3031 tx->info[idx].skb = NULL;
3032 do {
3033 len = dma_unmap_len(&tx->info[idx], len);
3034 if (len) {
3035 if (tx->info[idx].skb != NULL)
3036 pci_unmap_single(mgp->pdev,
3037 dma_unmap_addr(&tx->info[idx],
3038 bus), len,
3039 PCI_DMA_TODEVICE);
3040 else
3041 pci_unmap_page(mgp->pdev,
3042 dma_unmap_addr(&tx->info[idx],
3043 bus), len,
3044 PCI_DMA_TODEVICE);
3045 dma_unmap_len_set(&tx->info[idx], len, 0);
3046 tx->info[idx].skb = NULL;
3047 }
3048 idx = (idx + 1) & tx->mask;
3049 } while (idx != last_idx);
3050 if (skb_is_gso(skb)) {
3051 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
3052 goto drop;
3053 }
3054
3055 if (skb_linearize(skb))
3056 goto drop;
3057
3058 tx->linearized++;
3059 goto again;
3060
3061 drop:
3062 dev_kfree_skb_any(skb);
3063 ss->stats.tx_dropped += 1;
3064 return NETDEV_TX_OK;
3065
3066 }
3067
3068 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
3069 struct net_device *dev)
3070 {
3071 struct sk_buff *segs, *curr;
3072 struct myri10ge_priv *mgp = netdev_priv(dev);
3073 struct myri10ge_slice_state *ss;
3074 netdev_tx_t status;
3075
3076 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
3077 if (IS_ERR(segs))
3078 goto drop;
3079
3080 while (segs) {
3081 curr = segs;
3082 segs = segs->next;
3083 curr->next = NULL;
3084 status = myri10ge_xmit(curr, dev);
3085 if (status != 0) {
3086 dev_kfree_skb_any(curr);
3087 if (segs != NULL) {
3088 curr = segs;
3089 segs = segs->next;
3090 curr->next = NULL;
3091 dev_kfree_skb_any(segs);
3092 }
3093 goto drop;
3094 }
3095 }
3096 dev_kfree_skb_any(skb);
3097 return NETDEV_TX_OK;
3098
3099 drop:
3100 ss = &mgp->ss[skb_get_queue_mapping(skb)];
3101 dev_kfree_skb_any(skb);
3102 ss->stats.tx_dropped += 1;
3103 return NETDEV_TX_OK;
3104 }
3105
3106 static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
3107 struct rtnl_link_stats64 *stats)
3108 {
3109 const struct myri10ge_priv *mgp = netdev_priv(dev);
3110 const struct myri10ge_slice_netstats *slice_stats;
3111 int i;
3112
3113 for (i = 0; i < mgp->num_slices; i++) {
3114 slice_stats = &mgp->ss[i].stats;
3115 stats->rx_packets += slice_stats->rx_packets;
3116 stats->tx_packets += slice_stats->tx_packets;
3117 stats->rx_bytes += slice_stats->rx_bytes;
3118 stats->tx_bytes += slice_stats->tx_bytes;
3119 stats->rx_dropped += slice_stats->rx_dropped;
3120 stats->tx_dropped += slice_stats->tx_dropped;
3121 }
3122 return stats;
3123 }
3124
3125 static void myri10ge_set_multicast_list(struct net_device *dev)
3126 {
3127 struct myri10ge_priv *mgp = netdev_priv(dev);
3128 struct myri10ge_cmd cmd;
3129 struct netdev_hw_addr *ha;
3130 __be32 data[2] = { 0, 0 };
3131 int err;
3132
3133 /* can be called from atomic contexts,
3134 * pass 1 to force atomicity in myri10ge_send_cmd() */
3135 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3136
3137 /* This firmware is known to not support multicast */
3138 if (!mgp->fw_multicast_support)
3139 return;
3140
3141 /* Disable multicast filtering */
3142
3143 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3144 if (err != 0) {
3145 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3146 err);
3147 goto abort;
3148 }
3149
3150 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3151 /* request to disable multicast filtering, so quit here */
3152 return;
3153 }
3154
3155 /* Flush the filters */
3156
3157 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3158 &cmd, 1);
3159 if (err != 0) {
3160 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3161 err);
3162 goto abort;
3163 }
3164
3165 /* Walk the multicast list, and add each address */
3166 netdev_for_each_mc_addr(ha, dev) {
3167 memcpy(data, &ha->addr, ETH_ALEN);
3168 cmd.data0 = ntohl(data[0]);
3169 cmd.data1 = ntohl(data[1]);
3170 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3171 &cmd, 1);
3172
3173 if (err != 0) {
3174 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
3175 err, ha->addr);
3176 goto abort;
3177 }
3178 }
3179 /* Enable multicast filtering */
3180 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3181 if (err != 0) {
3182 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3183 err);
3184 goto abort;
3185 }
3186
3187 return;
3188
3189 abort:
3190 return;
3191 }
3192
3193 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3194 {
3195 struct sockaddr *sa = addr;
3196 struct myri10ge_priv *mgp = netdev_priv(dev);
3197 int status;
3198
3199 if (!is_valid_ether_addr(sa->sa_data))
3200 return -EADDRNOTAVAIL;
3201
3202 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3203 if (status != 0) {
3204 netdev_err(dev, "changing mac address failed with %d\n",
3205 status);
3206 return status;
3207 }
3208
3209 /* change the dev structure */
3210 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
3211 return 0;
3212 }
3213
3214 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3215 {
3216 struct myri10ge_priv *mgp = netdev_priv(dev);
3217 int error = 0;
3218
3219 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3220 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
3221 return -EINVAL;
3222 }
3223 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
3224 if (mgp->running) {
3225 /* if we change the mtu on an active device, we must
3226 * reset the device so the firmware sees the change */
3227 myri10ge_close(dev);
3228 dev->mtu = new_mtu;
3229 myri10ge_open(dev);
3230 } else
3231 dev->mtu = new_mtu;
3232
3233 return error;
3234 }
3235
3236 /*
3237 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3238 * Only do it if the bridge is a root port since we don't want to disturb
3239 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3240 */
3241
3242 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3243 {
3244 struct pci_dev *bridge = mgp->pdev->bus->self;
3245 struct device *dev = &mgp->pdev->dev;
3246 int cap;
3247 unsigned err_cap;
3248 int ret;
3249
3250 if (!myri10ge_ecrc_enable || !bridge)
3251 return;
3252
3253 /* check that the bridge is a root port */
3254 if (pci_pcie_type(bridge) != PCI_EXP_TYPE_ROOT_PORT) {
3255 if (myri10ge_ecrc_enable > 1) {
3256 struct pci_dev *prev_bridge, *old_bridge = bridge;
3257
3258 /* Walk the hierarchy up to the root port
3259 * where ECRC has to be enabled */
3260 do {
3261 prev_bridge = bridge;
3262 bridge = bridge->bus->self;
3263 if (!bridge || prev_bridge == bridge) {
3264 dev_err(dev,
3265 "Failed to find root port"
3266 " to force ECRC\n");
3267 return;
3268 }
3269 } while (pci_pcie_type(bridge) !=
3270 PCI_EXP_TYPE_ROOT_PORT);
3271
3272 dev_info(dev,
3273 "Forcing ECRC on non-root port %s"
3274 " (enabling on root port %s)\n",
3275 pci_name(old_bridge), pci_name(bridge));
3276 } else {
3277 dev_err(dev,
3278 "Not enabling ECRC on non-root port %s\n",
3279 pci_name(bridge));
3280 return;
3281 }
3282 }
3283
3284 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3285 if (!cap)
3286 return;
3287
3288 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3289 if (ret) {
3290 dev_err(dev, "failed reading ext-conf-space of %s\n",
3291 pci_name(bridge));
3292 dev_err(dev, "\t pci=nommconf in use? "
3293 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3294 return;
3295 }
3296 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3297 return;
3298
3299 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3300 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3301 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3302 }
3303
3304 /*
3305 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3306 * when the PCI-E Completion packets are aligned on an 8-byte
3307 * boundary. Some PCI-E chip sets always align Completion packets; on
3308 * the ones that do not, the alignment can be enforced by enabling
3309 * ECRC generation (if supported).
3310 *
3311 * When PCI-E Completion packets are not aligned, it is actually more
3312 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3313 *
3314 * If the driver can neither enable ECRC nor verify that it has
3315 * already been enabled, then it must use a firmware image which works
3316 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3317 * should also ensure that it never gives the device a Read-DMA which is
3318 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
3319 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3320 * firmware image, and set tx_boundary to 4KB.
3321 */
3322
3323 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3324 {
3325 struct pci_dev *pdev = mgp->pdev;
3326 struct device *dev = &pdev->dev;
3327 int status;
3328
3329 mgp->tx_boundary = 4096;
3330 /*
3331 * Verify the max read request size was set to 4KB
3332 * before trying the test with 4KB.
3333 */
3334 status = pcie_get_readrq(pdev);
3335 if (status < 0) {
3336 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3337 goto abort;
3338 }
3339 if (status != 4096) {
3340 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3341 mgp->tx_boundary = 2048;
3342 }
3343 /*
3344 * load the optimized firmware (which assumes aligned PCIe
3345 * completions) in order to see if it works on this host.
3346 */
3347 set_fw_name(mgp, myri10ge_fw_aligned, false);
3348 status = myri10ge_load_firmware(mgp, 1);
3349 if (status != 0) {
3350 goto abort;
3351 }
3352
3353 /*
3354 * Enable ECRC if possible
3355 */
3356 myri10ge_enable_ecrc(mgp);
3357
3358 /*
3359 * Run a DMA test which watches for unaligned completions and
3360 * aborts on the first one seen.
3361 */
3362
3363 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3364 if (status == 0)
3365 return; /* keep the aligned firmware */
3366
3367 if (status != -E2BIG)
3368 dev_warn(dev, "DMA test failed: %d\n", status);
3369 if (status == -ENOSYS)
3370 dev_warn(dev, "Falling back to ethp! "
3371 "Please install up to date fw\n");
3372 abort:
3373 /* fall back to using the unaligned firmware */
3374 mgp->tx_boundary = 2048;
3375 set_fw_name(mgp, myri10ge_fw_unaligned, false);
3376 }
3377
3378 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3379 {
3380 int overridden = 0;
3381
3382 if (myri10ge_force_firmware == 0) {
3383 int link_width;
3384 u16 lnk;
3385
3386 pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
3387 link_width = (lnk >> 4) & 0x3f;
3388
3389 /* Check to see if Link is less than 8 or if the
3390 * upstream bridge is known to provide aligned
3391 * completions */
3392 if (link_width < 8) {
3393 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3394 link_width);
3395 mgp->tx_boundary = 4096;
3396 set_fw_name(mgp, myri10ge_fw_aligned, false);
3397 } else {
3398 myri10ge_firmware_probe(mgp);
3399 }
3400 } else {
3401 if (myri10ge_force_firmware == 1) {
3402 dev_info(&mgp->pdev->dev,
3403 "Assuming aligned completions (forced)\n");
3404 mgp->tx_boundary = 4096;
3405 set_fw_name(mgp, myri10ge_fw_aligned, false);
3406 } else {
3407 dev_info(&mgp->pdev->dev,
3408 "Assuming unaligned completions (forced)\n");
3409 mgp->tx_boundary = 2048;
3410 set_fw_name(mgp, myri10ge_fw_unaligned, false);
3411 }
3412 }
3413
3414 kparam_block_sysfs_write(myri10ge_fw_name);
3415 if (myri10ge_fw_name != NULL) {
3416 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3417 if (fw_name) {
3418 overridden = 1;
3419 set_fw_name(mgp, fw_name, true);
3420 }
3421 }
3422 kparam_unblock_sysfs_write(myri10ge_fw_name);
3423
3424 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3425 myri10ge_fw_names[mgp->board_number] != NULL &&
3426 strlen(myri10ge_fw_names[mgp->board_number])) {
3427 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
3428 overridden = 1;
3429 }
3430 if (overridden)
3431 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3432 mgp->fw_name);
3433 }
3434
3435 static void myri10ge_mask_surprise_down(struct pci_dev *pdev)
3436 {
3437 struct pci_dev *bridge = pdev->bus->self;
3438 int cap;
3439 u32 mask;
3440
3441 if (bridge == NULL)
3442 return;
3443
3444 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3445 if (cap) {
3446 /* a sram parity error can cause a surprise link
3447 * down; since we expect and can recover from sram
3448 * parity errors, mask surprise link down events */
3449 pci_read_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, &mask);
3450 mask |= 0x20;
3451 pci_write_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, mask);
3452 }
3453 }
3454
3455 #ifdef CONFIG_PM
3456 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3457 {
3458 struct myri10ge_priv *mgp;
3459 struct net_device *netdev;
3460
3461 mgp = pci_get_drvdata(pdev);
3462 if (mgp == NULL)
3463 return -EINVAL;
3464 netdev = mgp->dev;
3465
3466 netif_device_detach(netdev);
3467 if (netif_running(netdev)) {
3468 netdev_info(netdev, "closing\n");
3469 rtnl_lock();
3470 myri10ge_close(netdev);
3471 rtnl_unlock();
3472 }
3473 myri10ge_dummy_rdma(mgp, 0);
3474 pci_save_state(pdev);
3475 pci_disable_device(pdev);
3476
3477 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3478 }
3479
3480 static int myri10ge_resume(struct pci_dev *pdev)
3481 {
3482 struct myri10ge_priv *mgp;
3483 struct net_device *netdev;
3484 int status;
3485 u16 vendor;
3486
3487 mgp = pci_get_drvdata(pdev);
3488 if (mgp == NULL)
3489 return -EINVAL;
3490 netdev = mgp->dev;
3491 pci_set_power_state(pdev, PCI_D0); /* zeros conf space as a side effect */
3492 msleep(5); /* give card time to respond */
3493 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3494 if (vendor == 0xffff) {
3495 netdev_err(mgp->dev, "device disappeared!\n");
3496 return -EIO;
3497 }
3498
3499 pci_restore_state(pdev);
3500
3501 status = pci_enable_device(pdev);
3502 if (status) {
3503 dev_err(&pdev->dev, "failed to enable device\n");
3504 return status;
3505 }
3506
3507 pci_set_master(pdev);
3508
3509 myri10ge_reset(mgp);
3510 myri10ge_dummy_rdma(mgp, 1);
3511
3512 /* Save configuration space to be restored if the
3513 * nic resets due to a parity error */
3514 pci_save_state(pdev);
3515
3516 if (netif_running(netdev)) {
3517 rtnl_lock();
3518 status = myri10ge_open(netdev);
3519 rtnl_unlock();
3520 if (status != 0)
3521 goto abort_with_enabled;
3522
3523 }
3524 netif_device_attach(netdev);
3525
3526 return 0;
3527
3528 abort_with_enabled:
3529 pci_disable_device(pdev);
3530 return -EIO;
3531
3532 }
3533 #endif /* CONFIG_PM */
3534
3535 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3536 {
3537 struct pci_dev *pdev = mgp->pdev;
3538 int vs = mgp->vendor_specific_offset;
3539 u32 reboot;
3540
3541 /*enter read32 mode */
3542 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3543
3544 /*read REBOOT_STATUS (0xfffffff0) */
3545 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3546 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3547 return reboot;
3548 }
3549
3550 static void
3551 myri10ge_check_slice(struct myri10ge_slice_state *ss, int *reset_needed,
3552 int *busy_slice_cnt, u32 rx_pause_cnt)
3553 {
3554 struct myri10ge_priv *mgp = ss->mgp;
3555 int slice = ss - mgp->ss;
3556
3557 if (ss->tx.req != ss->tx.done &&
3558 ss->tx.done == ss->watchdog_tx_done &&
3559 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3560 /* nic seems like it might be stuck.. */
3561 if (rx_pause_cnt != mgp->watchdog_pause) {
3562 if (net_ratelimit())
3563 netdev_warn(mgp->dev, "slice %d: TX paused, "
3564 "check link partner\n", slice);
3565 } else {
3566 netdev_warn(mgp->dev,
3567 "slice %d: TX stuck %d %d %d %d %d %d\n",
3568 slice, ss->tx.queue_active, ss->tx.req,
3569 ss->tx.done, ss->tx.pkt_start,
3570 ss->tx.pkt_done,
3571 (int)ntohl(mgp->ss[slice].fw_stats->
3572 send_done_count));
3573 *reset_needed = 1;
3574 ss->stuck = 1;
3575 }
3576 }
3577 if (ss->watchdog_tx_done != ss->tx.done ||
3578 ss->watchdog_rx_done != ss->rx_done.cnt) {
3579 *busy_slice_cnt += 1;
3580 }
3581 ss->watchdog_tx_done = ss->tx.done;
3582 ss->watchdog_tx_req = ss->tx.req;
3583 ss->watchdog_rx_done = ss->rx_done.cnt;
3584 }
3585
3586 /*
3587 * This watchdog is used to check whether the board has suffered
3588 * from a parity error and needs to be recovered.
3589 */
3590 static void myri10ge_watchdog(struct work_struct *work)
3591 {
3592 struct myri10ge_priv *mgp =
3593 container_of(work, struct myri10ge_priv, watchdog_work);
3594 struct myri10ge_slice_state *ss;
3595 u32 reboot, rx_pause_cnt;
3596 int status, rebooted;
3597 int i;
3598 int reset_needed = 0;
3599 int busy_slice_cnt = 0;
3600 u16 cmd, vendor;
3601
3602 mgp->watchdog_resets++;
3603 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3604 rebooted = 0;
3605 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3606 /* Bus master DMA disabled? Check to see
3607 * if the card rebooted due to a parity error
3608 * For now, just report it */
3609 reboot = myri10ge_read_reboot(mgp);
3610 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3611 reboot, myri10ge_reset_recover ? "" : " not");
3612 if (myri10ge_reset_recover == 0)
3613 return;
3614 rtnl_lock();
3615 mgp->rebooted = 1;
3616 rebooted = 1;
3617 myri10ge_close(mgp->dev);
3618 myri10ge_reset_recover--;
3619 mgp->rebooted = 0;
3620 /*
3621 * A rebooted nic will come back with config space as
3622 * it was after power was applied to PCIe bus.
3623 * Attempt to restore config space which was saved
3624 * when the driver was loaded, or the last time the
3625 * nic was resumed from power saving mode.
3626 */
3627 pci_restore_state(mgp->pdev);
3628
3629 /* save state again for accounting reasons */
3630 pci_save_state(mgp->pdev);
3631
3632 } else {
3633 /* if we get back -1's from our slot, perhaps somebody
3634 * powered off our card. Don't try to reset it in
3635 * this case */
3636 if (cmd == 0xffff) {
3637 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3638 if (vendor == 0xffff) {
3639 netdev_err(mgp->dev, "device disappeared!\n");
3640 return;
3641 }
3642 }
3643 /* Perhaps it is a software error. See if stuck slice
3644 * has recovered, reset if not */
3645 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3646 for (i = 0; i < mgp->num_slices; i++) {
3647 ss = mgp->ss;
3648 if (ss->stuck) {
3649 myri10ge_check_slice(ss, &reset_needed,
3650 &busy_slice_cnt,
3651 rx_pause_cnt);
3652 ss->stuck = 0;
3653 }
3654 }
3655 if (!reset_needed) {
3656 netdev_dbg(mgp->dev, "not resetting\n");
3657 return;
3658 }
3659
3660 netdev_err(mgp->dev, "device timeout, resetting\n");
3661 }
3662
3663 if (!rebooted) {
3664 rtnl_lock();
3665 myri10ge_close(mgp->dev);
3666 }
3667 status = myri10ge_load_firmware(mgp, 1);
3668 if (status != 0)
3669 netdev_err(mgp->dev, "failed to load firmware\n");
3670 else
3671 myri10ge_open(mgp->dev);
3672 rtnl_unlock();
3673 }
3674
3675 /*
3676 * We use our own timer routine rather than relying upon
3677 * netdev->tx_timeout because we have a very large hardware transmit
3678 * queue. Due to the large queue, the netdev->tx_timeout function
3679 * cannot detect a NIC with a parity error in a timely fashion if the
3680 * NIC is lightly loaded.
3681 */
3682 static void myri10ge_watchdog_timer(unsigned long arg)
3683 {
3684 struct myri10ge_priv *mgp;
3685 struct myri10ge_slice_state *ss;
3686 int i, reset_needed, busy_slice_cnt;
3687 u32 rx_pause_cnt;
3688 u16 cmd;
3689
3690 mgp = (struct myri10ge_priv *)arg;
3691
3692 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3693 busy_slice_cnt = 0;
3694 for (i = 0, reset_needed = 0;
3695 i < mgp->num_slices && reset_needed == 0; ++i) {
3696
3697 ss = &mgp->ss[i];
3698 if (ss->rx_small.watchdog_needed) {
3699 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3700 mgp->small_bytes + MXGEFW_PAD,
3701 1);
3702 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3703 myri10ge_fill_thresh)
3704 ss->rx_small.watchdog_needed = 0;
3705 }
3706 if (ss->rx_big.watchdog_needed) {
3707 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3708 mgp->big_bytes, 1);
3709 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3710 myri10ge_fill_thresh)
3711 ss->rx_big.watchdog_needed = 0;
3712 }
3713 myri10ge_check_slice(ss, &reset_needed, &busy_slice_cnt,
3714 rx_pause_cnt);
3715 }
3716 /* if we've sent or received no traffic, poll the NIC to
3717 * ensure it is still there. Otherwise, we risk not noticing
3718 * an error in a timely fashion */
3719 if (busy_slice_cnt == 0) {
3720 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3721 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3722 reset_needed = 1;
3723 }
3724 }
3725 mgp->watchdog_pause = rx_pause_cnt;
3726
3727 if (reset_needed) {
3728 schedule_work(&mgp->watchdog_work);
3729 } else {
3730 /* rearm timer */
3731 mod_timer(&mgp->watchdog_timer,
3732 jiffies + myri10ge_watchdog_timeout * HZ);
3733 }
3734 }
3735
3736 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3737 {
3738 struct myri10ge_slice_state *ss;
3739 struct pci_dev *pdev = mgp->pdev;
3740 size_t bytes;
3741 int i;
3742
3743 if (mgp->ss == NULL)
3744 return;
3745
3746 for (i = 0; i < mgp->num_slices; i++) {
3747 ss = &mgp->ss[i];
3748 if (ss->rx_done.entry != NULL) {
3749 bytes = mgp->max_intr_slots *
3750 sizeof(*ss->rx_done.entry);
3751 dma_free_coherent(&pdev->dev, bytes,
3752 ss->rx_done.entry, ss->rx_done.bus);
3753 ss->rx_done.entry = NULL;
3754 }
3755 if (ss->fw_stats != NULL) {
3756 bytes = sizeof(*ss->fw_stats);
3757 dma_free_coherent(&pdev->dev, bytes,
3758 ss->fw_stats, ss->fw_stats_bus);
3759 ss->fw_stats = NULL;
3760 }
3761 napi_hash_del(&ss->napi);
3762 netif_napi_del(&ss->napi);
3763 }
3764 /* Wait till napi structs are no longer used, and then free ss. */
3765 synchronize_rcu();
3766 kfree(mgp->ss);
3767 mgp->ss = NULL;
3768 }
3769
3770 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3771 {
3772 struct myri10ge_slice_state *ss;
3773 struct pci_dev *pdev = mgp->pdev;
3774 size_t bytes;
3775 int i;
3776
3777 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3778 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3779 if (mgp->ss == NULL) {
3780 return -ENOMEM;
3781 }
3782
3783 for (i = 0; i < mgp->num_slices; i++) {
3784 ss = &mgp->ss[i];
3785 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3786 ss->rx_done.entry = dma_zalloc_coherent(&pdev->dev, bytes,
3787 &ss->rx_done.bus,
3788 GFP_KERNEL);
3789 if (ss->rx_done.entry == NULL)
3790 goto abort;
3791 bytes = sizeof(*ss->fw_stats);
3792 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3793 &ss->fw_stats_bus,
3794 GFP_KERNEL);
3795 if (ss->fw_stats == NULL)
3796 goto abort;
3797 ss->mgp = mgp;
3798 ss->dev = mgp->dev;
3799 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3800 myri10ge_napi_weight);
3801 napi_hash_add(&ss->napi);
3802 }
3803 return 0;
3804 abort:
3805 myri10ge_free_slices(mgp);
3806 return -ENOMEM;
3807 }
3808
3809 /*
3810 * This function determines the number of slices supported.
3811 * The number slices is the minimum of the number of CPUS,
3812 * the number of MSI-X irqs supported, the number of slices
3813 * supported by the firmware
3814 */
3815 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3816 {
3817 struct myri10ge_cmd cmd;
3818 struct pci_dev *pdev = mgp->pdev;
3819 char *old_fw;
3820 bool old_allocated;
3821 int i, status, ncpus;
3822
3823 mgp->num_slices = 1;
3824 ncpus = netif_get_num_default_rss_queues();
3825
3826 if (myri10ge_max_slices == 1 || !pdev->msix_cap ||
3827 (myri10ge_max_slices == -1 && ncpus < 2))
3828 return;
3829
3830 /* try to load the slice aware rss firmware */
3831 old_fw = mgp->fw_name;
3832 old_allocated = mgp->fw_name_allocated;
3833 /* don't free old_fw if we override it. */
3834 mgp->fw_name_allocated = false;
3835
3836 if (myri10ge_fw_name != NULL) {
3837 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3838 myri10ge_fw_name);
3839 set_fw_name(mgp, myri10ge_fw_name, false);
3840 } else if (old_fw == myri10ge_fw_aligned)
3841 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
3842 else
3843 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
3844 status = myri10ge_load_firmware(mgp, 0);
3845 if (status != 0) {
3846 dev_info(&pdev->dev, "Rss firmware not found\n");
3847 if (old_allocated)
3848 kfree(old_fw);
3849 return;
3850 }
3851
3852 /* hit the board with a reset to ensure it is alive */
3853 memset(&cmd, 0, sizeof(cmd));
3854 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3855 if (status != 0) {
3856 dev_err(&mgp->pdev->dev, "failed reset\n");
3857 goto abort_with_fw;
3858 }
3859
3860 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3861
3862 /* tell it the size of the interrupt queues */
3863 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3864 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3865 if (status != 0) {
3866 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3867 goto abort_with_fw;
3868 }
3869
3870 /* ask the maximum number of slices it supports */
3871 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3872 if (status != 0)
3873 goto abort_with_fw;
3874 else
3875 mgp->num_slices = cmd.data0;
3876
3877 /* Only allow multiple slices if MSI-X is usable */
3878 if (!myri10ge_msi) {
3879 goto abort_with_fw;
3880 }
3881
3882 /* if the admin did not specify a limit to how many
3883 * slices we should use, cap it automatically to the
3884 * number of CPUs currently online */
3885 if (myri10ge_max_slices == -1)
3886 myri10ge_max_slices = ncpus;
3887
3888 if (mgp->num_slices > myri10ge_max_slices)
3889 mgp->num_slices = myri10ge_max_slices;
3890
3891 /* Now try to allocate as many MSI-X vectors as we have
3892 * slices. We give up on MSI-X if we can only get a single
3893 * vector. */
3894
3895 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3896 GFP_KERNEL);
3897 if (mgp->msix_vectors == NULL)
3898 goto disable_msix;
3899 for (i = 0; i < mgp->num_slices; i++) {
3900 mgp->msix_vectors[i].entry = i;
3901 }
3902
3903 while (mgp->num_slices > 1) {
3904 /* make sure it is a power of two */
3905 while (!is_power_of_2(mgp->num_slices))
3906 mgp->num_slices--;
3907 if (mgp->num_slices == 1)
3908 goto disable_msix;
3909 status = pci_enable_msix(pdev, mgp->msix_vectors,
3910 mgp->num_slices);
3911 if (status == 0) {
3912 pci_disable_msix(pdev);
3913 if (old_allocated)
3914 kfree(old_fw);
3915 return;
3916 }
3917 if (status > 0)
3918 mgp->num_slices = status;
3919 else
3920 goto disable_msix;
3921 }
3922
3923 disable_msix:
3924 if (mgp->msix_vectors != NULL) {
3925 kfree(mgp->msix_vectors);
3926 mgp->msix_vectors = NULL;
3927 }
3928
3929 abort_with_fw:
3930 mgp->num_slices = 1;
3931 set_fw_name(mgp, old_fw, old_allocated);
3932 myri10ge_load_firmware(mgp, 0);
3933 }
3934
3935 static const struct net_device_ops myri10ge_netdev_ops = {
3936 .ndo_open = myri10ge_open,
3937 .ndo_stop = myri10ge_close,
3938 .ndo_start_xmit = myri10ge_xmit,
3939 .ndo_get_stats64 = myri10ge_get_stats,
3940 .ndo_validate_addr = eth_validate_addr,
3941 .ndo_change_mtu = myri10ge_change_mtu,
3942 .ndo_set_rx_mode = myri10ge_set_multicast_list,
3943 .ndo_set_mac_address = myri10ge_set_mac_address,
3944 #ifdef CONFIG_NET_RX_BUSY_POLL
3945 .ndo_busy_poll = myri10ge_busy_poll,
3946 #endif
3947 };
3948
3949 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3950 {
3951 struct net_device *netdev;
3952 struct myri10ge_priv *mgp;
3953 struct device *dev = &pdev->dev;
3954 int i;
3955 int status = -ENXIO;
3956 int dac_enabled;
3957 unsigned hdr_offset, ss_offset;
3958 static int board_number;
3959
3960 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3961 if (netdev == NULL)
3962 return -ENOMEM;
3963
3964 SET_NETDEV_DEV(netdev, &pdev->dev);
3965
3966 mgp = netdev_priv(netdev);
3967 mgp->dev = netdev;
3968 mgp->pdev = pdev;
3969 mgp->pause = myri10ge_flow_control;
3970 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3971 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3972 mgp->board_number = board_number;
3973 init_waitqueue_head(&mgp->down_wq);
3974
3975 if (pci_enable_device(pdev)) {
3976 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3977 status = -ENODEV;
3978 goto abort_with_netdev;
3979 }
3980
3981 /* Find the vendor-specific cap so we can check
3982 * the reboot register later on */
3983 mgp->vendor_specific_offset
3984 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3985
3986 /* Set our max read request to 4KB */
3987 status = pcie_set_readrq(pdev, 4096);
3988 if (status != 0) {
3989 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3990 status);
3991 goto abort_with_enabled;
3992 }
3993
3994 myri10ge_mask_surprise_down(pdev);
3995 pci_set_master(pdev);
3996 dac_enabled = 1;
3997 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3998 if (status != 0) {
3999 dac_enabled = 0;
4000 dev_err(&pdev->dev,
4001 "64-bit pci address mask was refused, "
4002 "trying 32-bit\n");
4003 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4004 }
4005 if (status != 0) {
4006 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
4007 goto abort_with_enabled;
4008 }
4009 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4010 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
4011 &mgp->cmd_bus, GFP_KERNEL);
4012 if (mgp->cmd == NULL)
4013 goto abort_with_enabled;
4014
4015 mgp->board_span = pci_resource_len(pdev, 0);
4016 mgp->iomem_base = pci_resource_start(pdev, 0);
4017 mgp->mtrr = -1;
4018 mgp->wc_enabled = 0;
4019 #ifdef CONFIG_MTRR
4020 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
4021 MTRR_TYPE_WRCOMB, 1);
4022 if (mgp->mtrr >= 0)
4023 mgp->wc_enabled = 1;
4024 #endif
4025 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
4026 if (mgp->sram == NULL) {
4027 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
4028 mgp->board_span, mgp->iomem_base);
4029 status = -ENXIO;
4030 goto abort_with_mtrr;
4031 }
4032 hdr_offset =
4033 swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
4034 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
4035 mgp->sram_size = swab32(readl(mgp->sram + ss_offset));
4036 if (mgp->sram_size > mgp->board_span ||
4037 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
4038 dev_err(&pdev->dev,
4039 "invalid sram_size %dB or board span %ldB\n",
4040 mgp->sram_size, mgp->board_span);
4041 goto abort_with_ioremap;
4042 }
4043 memcpy_fromio(mgp->eeprom_strings,
4044 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
4045 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
4046 status = myri10ge_read_mac_addr(mgp);
4047 if (status)
4048 goto abort_with_ioremap;
4049
4050 for (i = 0; i < ETH_ALEN; i++)
4051 netdev->dev_addr[i] = mgp->mac_addr[i];
4052
4053 myri10ge_select_firmware(mgp);
4054
4055 status = myri10ge_load_firmware(mgp, 1);
4056 if (status != 0) {
4057 dev_err(&pdev->dev, "failed to load firmware\n");
4058 goto abort_with_ioremap;
4059 }
4060 myri10ge_probe_slices(mgp);
4061 status = myri10ge_alloc_slices(mgp);
4062 if (status != 0) {
4063 dev_err(&pdev->dev, "failed to alloc slice state\n");
4064 goto abort_with_firmware;
4065 }
4066 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
4067 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
4068 status = myri10ge_reset(mgp);
4069 if (status != 0) {
4070 dev_err(&pdev->dev, "failed reset\n");
4071 goto abort_with_slices;
4072 }
4073 #ifdef CONFIG_MYRI10GE_DCA
4074 myri10ge_setup_dca(mgp);
4075 #endif
4076 pci_set_drvdata(pdev, mgp);
4077 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
4078 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
4079 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
4080 myri10ge_initial_mtu = 68;
4081
4082 netdev->netdev_ops = &myri10ge_netdev_ops;
4083 netdev->mtu = myri10ge_initial_mtu;
4084 netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
4085
4086 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
4087 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4088
4089 netdev->features = netdev->hw_features;
4090
4091 if (dac_enabled)
4092 netdev->features |= NETIF_F_HIGHDMA;
4093
4094 netdev->vlan_features |= mgp->features;
4095 if (mgp->fw_ver_tiny < 37)
4096 netdev->vlan_features &= ~NETIF_F_TSO6;
4097 if (mgp->fw_ver_tiny < 32)
4098 netdev->vlan_features &= ~NETIF_F_TSO;
4099
4100 /* make sure we can get an irq, and that MSI can be
4101 * setup (if available). */
4102 status = myri10ge_request_irq(mgp);
4103 if (status != 0)
4104 goto abort_with_firmware;
4105 myri10ge_free_irq(mgp);
4106
4107 /* Save configuration space to be restored if the
4108 * nic resets due to a parity error */
4109 pci_save_state(pdev);
4110
4111 /* Setup the watchdog timer */
4112 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
4113 (unsigned long)mgp);
4114
4115 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
4116 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
4117 status = register_netdev(netdev);
4118 if (status != 0) {
4119 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
4120 goto abort_with_state;
4121 }
4122 if (mgp->msix_enabled)
4123 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
4124 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
4125 (mgp->wc_enabled ? "Enabled" : "Disabled"));
4126 else
4127 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
4128 mgp->msi_enabled ? "MSI" : "xPIC",
4129 pdev->irq, mgp->tx_boundary, mgp->fw_name,
4130 (mgp->wc_enabled ? "Enabled" : "Disabled"));
4131
4132 board_number++;
4133 return 0;
4134
4135 abort_with_state:
4136 pci_restore_state(pdev);
4137
4138 abort_with_slices:
4139 myri10ge_free_slices(mgp);
4140
4141 abort_with_firmware:
4142 myri10ge_dummy_rdma(mgp, 0);
4143
4144 abort_with_ioremap:
4145 if (mgp->mac_addr_string != NULL)
4146 dev_err(&pdev->dev,
4147 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4148 mgp->mac_addr_string, mgp->serial_number);
4149 iounmap(mgp->sram);
4150
4151 abort_with_mtrr:
4152 #ifdef CONFIG_MTRR
4153 if (mgp->mtrr >= 0)
4154 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4155 #endif
4156 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4157 mgp->cmd, mgp->cmd_bus);
4158
4159 abort_with_enabled:
4160 pci_disable_device(pdev);
4161
4162 abort_with_netdev:
4163 set_fw_name(mgp, NULL, false);
4164 free_netdev(netdev);
4165 return status;
4166 }
4167
4168 /*
4169 * myri10ge_remove
4170 *
4171 * Does what is necessary to shutdown one Myrinet device. Called
4172 * once for each Myrinet card by the kernel when a module is
4173 * unloaded.
4174 */
4175 static void myri10ge_remove(struct pci_dev *pdev)
4176 {
4177 struct myri10ge_priv *mgp;
4178 struct net_device *netdev;
4179
4180 mgp = pci_get_drvdata(pdev);
4181 if (mgp == NULL)
4182 return;
4183
4184 cancel_work_sync(&mgp->watchdog_work);
4185 netdev = mgp->dev;
4186 unregister_netdev(netdev);
4187
4188 #ifdef CONFIG_MYRI10GE_DCA
4189 myri10ge_teardown_dca(mgp);
4190 #endif
4191 myri10ge_dummy_rdma(mgp, 0);
4192
4193 /* avoid a memory leak */
4194 pci_restore_state(pdev);
4195
4196 iounmap(mgp->sram);
4197
4198 #ifdef CONFIG_MTRR
4199 if (mgp->mtrr >= 0)
4200 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4201 #endif
4202 myri10ge_free_slices(mgp);
4203 if (mgp->msix_vectors != NULL)
4204 kfree(mgp->msix_vectors);
4205 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4206 mgp->cmd, mgp->cmd_bus);
4207
4208 set_fw_name(mgp, NULL, false);
4209 free_netdev(netdev);
4210 pci_disable_device(pdev);
4211 }
4212
4213 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
4214 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
4215
4216 static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
4217 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4218 {PCI_DEVICE
4219 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4220 {0},
4221 };
4222
4223 MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4224
4225 static struct pci_driver myri10ge_driver = {
4226 .name = "myri10ge",
4227 .probe = myri10ge_probe,
4228 .remove = myri10ge_remove,
4229 .id_table = myri10ge_pci_tbl,
4230 #ifdef CONFIG_PM
4231 .suspend = myri10ge_suspend,
4232 .resume = myri10ge_resume,
4233 #endif
4234 };
4235
4236 #ifdef CONFIG_MYRI10GE_DCA
4237 static int
4238 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4239 {
4240 int err = driver_for_each_device(&myri10ge_driver.driver,
4241 NULL, &event,
4242 myri10ge_notify_dca_device);
4243
4244 if (err)
4245 return NOTIFY_BAD;
4246 return NOTIFY_DONE;
4247 }
4248
4249 static struct notifier_block myri10ge_dca_notifier = {
4250 .notifier_call = myri10ge_notify_dca,
4251 .next = NULL,
4252 .priority = 0,
4253 };
4254 #endif /* CONFIG_MYRI10GE_DCA */
4255
4256 static __init int myri10ge_init_module(void)
4257 {
4258 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
4259
4260 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4261 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4262 myri10ge_rss_hash);
4263 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4264 }
4265 #ifdef CONFIG_MYRI10GE_DCA
4266 dca_register_notify(&myri10ge_dca_notifier);
4267 #endif
4268 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4269 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4270
4271 return pci_register_driver(&myri10ge_driver);
4272 }
4273
4274 module_init(myri10ge_init_module);
4275
4276 static __exit void myri10ge_cleanup_module(void)
4277 {
4278 #ifdef CONFIG_MYRI10GE_DCA
4279 dca_unregister_notify(&myri10ge_dca_notifier);
4280 #endif
4281 pci_unregister_driver(&myri10ge_driver);
4282 }
4283
4284 module_exit(myri10ge_cleanup_module);
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