drivers/i2c/busses/i2c-ocores.c

   1 /*
   2  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
   3  * (http://www.opencores.org/projects.cgi/web/i2c/overview).
   4  *
   5  * Peter Korsgaard <jacmet@sunsite.dk>
   6  *
   7  * Support for the GRLIB port of the controller by
   8  * Andreas Larsson <andreas@gaisler.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public License
  11  * version 2.  This program is licensed "as is" without any warranty of any
  12  * kind, whether express or implied.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/i2c.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/wait.h>
  24 #include <linux/i2c-ocores.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/log2.h>
  28
  29 struct ocores_i2c {
  30         void __iomem *base;
  31         u32 reg_shift;
  32         u32 reg_io_width;
  33         wait_queue_head_t wait;
  34         struct i2c_adapter adap;
  35         struct i2c_msg *msg;
  36         int pos;
  37         int nmsgs;
  38         int state; /* see STATE_ */
  39         int clock_khz;
  40         void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
  41         u8 (*getreg)(struct ocores_i2c *i2c, int reg);
  42 };
  43
  44 /* registers */
  45 #define OCI2C_PRELOW            0
  46 #define OCI2C_PREHIGH           1
  47 #define OCI2C_CONTROL           2
  48 #define OCI2C_DATA              3
  49 #define OCI2C_CMD               4 /* write only */
  50 #define OCI2C_STATUS            4 /* read only, same address as OCI2C_CMD */
  51
  52 #define OCI2C_CTRL_IEN          0x40
  53 #define OCI2C_CTRL_EN           0x80
  54
  55 #define OCI2C_CMD_START         0x91
  56 #define OCI2C_CMD_STOP          0x41
  57 #define OCI2C_CMD_READ          0x21
  58 #define OCI2C_CMD_WRITE         0x11
  59 #define OCI2C_CMD_READ_ACK      0x21
  60 #define OCI2C_CMD_READ_NACK     0x29
  61 #define OCI2C_CMD_IACK          0x01
  62
  63 #define OCI2C_STAT_IF           0x01
  64 #define OCI2C_STAT_TIP          0x02
  65 #define OCI2C_STAT_ARBLOST      0x20
  66 #define OCI2C_STAT_BUSY         0x40
  67 #define OCI2C_STAT_NACK         0x80
  68
  69 #define STATE_DONE              0
  70 #define STATE_START             1
  71 #define STATE_WRITE             2
  72 #define STATE_READ              3
  73 #define STATE_ERROR             4
  74
  75 #define TYPE_OCORES             0
  76 #define TYPE_GRLIB              1
  77
  78 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
  79 {
  80         iowrite8(value, i2c->base + (reg << i2c->reg_shift));
  81 }
  82
  83 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
  84 {
  85         iowrite16(value, i2c->base + (reg << i2c->reg_shift));
  86 }
  87
  88 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
  89 {
  90         iowrite32(value, i2c->base + (reg << i2c->reg_shift));
  91 }
  92
  93 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
  94 {
  95         return ioread8(i2c->base + (reg << i2c->reg_shift));
  96 }
  97
  98 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
  99 {
 100         return ioread16(i2c->base + (reg << i2c->reg_shift));
 101 }
 102
 103 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
 104 {
 105         return ioread32(i2c->base + (reg << i2c->reg_shift));
 106 }
 107
 108 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
 109 {
 110         i2c->setreg(i2c, reg, value);
 111 }
 112
 113 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
 114 {
 115         return i2c->getreg(i2c, reg);
 116 }
 117
 118 static void ocores_process(struct ocores_i2c *i2c)
 119 {
 120         struct i2c_msg *msg = i2c->msg;
 121         u8 stat = oc_getreg(i2c, OCI2C_STATUS);
 122
 123         if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
 124                 /* stop has been sent */
 125                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 126                 wake_up(&i2c->wait);
 127                 return;
 128         }
 129
 130         /* error? */
 131         if (stat & OCI2C_STAT_ARBLOST) {
 132                 i2c->state = STATE_ERROR;
 133                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 134                 return;
 135         }
 136
 137         if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
 138                 i2c->state =
 139                         (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 140
 141                 if (stat & OCI2C_STAT_NACK) {
 142                         i2c->state = STATE_ERROR;
 143                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 144                         return;
 145                 }
 146         } else
 147                 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
 148
 149         /* end of msg? */
 150         if (i2c->pos == msg->len) {
 151                 i2c->nmsgs--;
 152                 i2c->msg++;
 153                 i2c->pos = 0;
 154                 msg = i2c->msg;
 155
 156                 if (i2c->nmsgs) {       /* end? */
 157                         /* send start? */
 158                         if (!(msg->flags & I2C_M_NOSTART)) {
 159                                 u8 addr = (msg->addr << 1);
 160
 161                                 if (msg->flags & I2C_M_RD)
 162                                         addr |= 1;
 163
 164                                 i2c->state = STATE_START;
 165
 166                                 oc_setreg(i2c, OCI2C_DATA, addr);
 167                                 oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
 168                                 return;
 169                         } else
 170                                 i2c->state = (msg->flags & I2C_M_RD)
 171                                         ? STATE_READ : STATE_WRITE;
 172                 } else {
 173                         i2c->state = STATE_DONE;
 174                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 175                         return;
 176                 }
 177         }
 178
 179         if (i2c->state == STATE_READ) {
 180                 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
 181                           OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
 182         } else {
 183                 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
 184                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
 185         }
 186 }
 187
 188 static irqreturn_t ocores_isr(int irq, void *dev_id)
 189 {
 190         struct ocores_i2c *i2c = dev_id;
 191
 192         ocores_process(i2c);
 193
 194         return IRQ_HANDLED;
 195 }
 196
 197 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 198 {
 199         struct ocores_i2c *i2c = i2c_get_adapdata(adap);
 200
 201         i2c->msg = msgs;
 202         i2c->pos = 0;
 203         i2c->nmsgs = num;
 204         i2c->state = STATE_START;
 205
 206         oc_setreg(i2c, OCI2C_DATA,
 207                         (i2c->msg->addr << 1) |
 208                         ((i2c->msg->flags & I2C_M_RD) ? 1:0));
 209
 210         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 211
 212         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
 213                                (i2c->state == STATE_DONE), HZ))
 214                 return (i2c->state == STATE_DONE) ? num : -EIO;
 215         else
 216                 return -ETIMEDOUT;
 217 }
 218
 219 static void ocores_init(struct ocores_i2c *i2c)
 220 {
 221         int prescale;
 222         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 223
 224         /* make sure the device is disabled */
 225         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 226
 227         prescale = (i2c->clock_khz / (5*100)) - 1;
 228         oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
 229         oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
 230
 231         /* Init the device */
 232         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 233         oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
 234 }
 235
 236
 237 static u32 ocores_func(struct i2c_adapter *adap)
 238 {
 239         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 240 }
 241
 242 static const struct i2c_algorithm ocores_algorithm = {
 243         .master_xfer    = ocores_xfer,
 244         .functionality  = ocores_func,
 245 };
 246
 247 static struct i2c_adapter ocores_adapter = {
 248         .owner          = THIS_MODULE,
 249         .name           = "i2c-ocores",
 250         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 251         .algo           = &ocores_algorithm,
 252 };
 253
 254 static struct of_device_id ocores_i2c_match[] = {
 255         {
 256                 .compatible = "opencores,i2c-ocores",
 257                 .data = (void *)TYPE_OCORES,
 258         },
 259         {
 260                 .compatible = "aeroflexgaisler,i2cmst",
 261                 .data = (void *)TYPE_GRLIB,
 262         },
 263         {},
 264 };
 265 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
 266
 267 #ifdef CONFIG_OF
 268 /* Read and write functions for the GRLIB port of the controller. Registers are
 269  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 270  * register. The subsequent registers has their offset decreased accordingly. */
 271 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
 272 {
 273         u32 rd;
 274         int rreg = reg;
 275         if (reg != OCI2C_PRELOW)
 276                 rreg--;
 277         rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 278         if (reg == OCI2C_PREHIGH)
 279                 return (u8)(rd >> 8);
 280         else
 281                 return (u8)rd;
 282 }
 283
 284 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
 285 {
 286         u32 curr, wr;
 287         int rreg = reg;
 288         if (reg != OCI2C_PRELOW)
 289                 rreg--;
 290         if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
 291                 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 292                 if (reg == OCI2C_PRELOW)
 293                         wr = (curr & 0xff00) | value;
 294                 else
 295                         wr = (((u32)value) << 8) | (curr & 0xff);
 296         } else {
 297                 wr = value;
 298         }
 299         iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
 300 }
 301
 302 static int ocores_i2c_of_probe(struct platform_device *pdev,
 303                                 struct ocores_i2c *i2c)
 304 {
 305         struct device_node *np = pdev->dev.of_node;
 306         const struct of_device_id *match;
 307         u32 val;
 308
 309         if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
 310                 /* no 'reg-shift', check for deprecated 'regstep' */
 311                 if (!of_property_read_u32(np, "regstep", &val)) {
 312                         if (!is_power_of_2(val)) {
 313                                 dev_err(&pdev->dev, "invalid regstep %d\n",
 314                                         val);
 315                                 return -EINVAL;
 316                         }
 317                         i2c->reg_shift = ilog2(val);
 318                         dev_warn(&pdev->dev,
 319                                 "regstep property deprecated, use reg-shift\n");
 320                 }
 321         }
 322
 323         if (of_property_read_u32(np, "clock-frequency", &val)) {
 324                 dev_err(&pdev->dev,
 325                         "Missing required parameter 'clock-frequency'\n");
 326                 return -ENODEV;
 327         }
 328         i2c->clock_khz = val / 1000;
 329
 330         of_property_read_u32(pdev->dev.of_node, "reg-io-width",
 331                                 &i2c->reg_io_width);
 332
 333         match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
 334         if (match && (long)match->data == TYPE_GRLIB) {
 335                 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
 336                 i2c->setreg = oc_setreg_grlib;
 337                 i2c->getreg = oc_getreg_grlib;
 338         }
 339
 340         return 0;
 341 }
 342 #else
 343 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV
 344 #endif
 345
 346 static int ocores_i2c_probe(struct platform_device *pdev)
 347 {
 348         struct ocores_i2c *i2c;
 349         struct ocores_i2c_platform_data *pdata;
 350         struct resource *res;
 351         int irq;
 352         int ret;
 353         int i;
 354
 355         irq = platform_get_irq(pdev, 0);
 356         if (irq < 0)
 357                 return irq;
 358
 359         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 360         if (!i2c)
 361                 return -ENOMEM;
 362
 363         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 364         i2c->base = devm_ioremap_resource(&pdev->dev, res);
 365         if (IS_ERR(i2c->base))
 366                 return PTR_ERR(i2c->base);
 367
 368         pdata = dev_get_platdata(&pdev->dev);
 369         if (pdata) {
 370                 i2c->reg_shift = pdata->reg_shift;
 371                 i2c->reg_io_width = pdata->reg_io_width;
 372                 i2c->clock_khz = pdata->clock_khz;
 373         } else {
 374                 ret = ocores_i2c_of_probe(pdev, i2c);
 375                 if (ret)
 376                         return ret;
 377         }
 378
 379         if (i2c->reg_io_width == 0)
 380                 i2c->reg_io_width = 1; /* Set to default value */
 381
 382         if (!i2c->setreg || !i2c->getreg) {
 383                 switch (i2c->reg_io_width) {
 384                 case 1:
 385                         i2c->setreg = oc_setreg_8;
 386                         i2c->getreg = oc_getreg_8;
 387                         break;
 388
 389                 case 2:
 390                         i2c->setreg = oc_setreg_16;
 391                         i2c->getreg = oc_getreg_16;
 392                         break;
 393
 394                 case 4:
 395                         i2c->setreg = oc_setreg_32;
 396                         i2c->getreg = oc_getreg_32;
 397                         break;
 398
 399                 default:
 400                         dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
 401                                 i2c->reg_io_width);
 402                         return -EINVAL;
 403                 }
 404         }
 405
 406         ocores_init(i2c);
 407
 408         init_waitqueue_head(&i2c->wait);
 409         ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
 410                                pdev->name, i2c);
 411         if (ret) {
 412                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 413                 return ret;
 414         }
 415
 416         /* hook up driver to tree */
 417         platform_set_drvdata(pdev, i2c);
 418         i2c->adap = ocores_adapter;
 419         i2c_set_adapdata(&i2c->adap, i2c);
 420         i2c->adap.dev.parent = &pdev->dev;
 421         i2c->adap.dev.of_node = pdev->dev.of_node;
 422
 423         /* add i2c adapter to i2c tree */
 424         ret = i2c_add_adapter(&i2c->adap);
 425         if (ret) {
 426                 dev_err(&pdev->dev, "Failed to add adapter\n");
 427                 return ret;
 428         }
 429
 430         /* add in known devices to the bus */
 431         if (pdata) {
 432                 for (i = 0; i < pdata->num_devices; i++)
 433                         i2c_new_device(&i2c->adap, pdata->devices + i);
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int ocores_i2c_remove(struct platform_device *pdev)
 440 {
 441         struct ocores_i2c *i2c = platform_get_drvdata(pdev);
 442
 443         /* disable i2c logic */
 444         oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
 445                   & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 446
 447         /* remove adapter & data */
 448         i2c_del_adapter(&i2c->adap);
 449
 450         return 0;
 451 }
 452
 453 #ifdef CONFIG_PM_SLEEP
 454 static int ocores_i2c_suspend(struct device *dev)
 455 {
 456         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 457         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 458
 459         /* make sure the device is disabled */
 460         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 461
 462         return 0;
 463 }
 464
 465 static int ocores_i2c_resume(struct device *dev)
 466 {
 467         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 468
 469         ocores_init(i2c);
 470
 471         return 0;
 472 }
 473
 474 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
 475 #define OCORES_I2C_PM   (&ocores_i2c_pm)
 476 #else
 477 #define OCORES_I2C_PM   NULL
 478 #endif
 479
 480 static struct platform_driver ocores_i2c_driver = {
 481         .probe   = ocores_i2c_probe,
 482         .remove  = ocores_i2c_remove,
 483         .driver  = {
 484                 .owner = THIS_MODULE,
 485                 .name = "ocores-i2c",
 486                 .of_match_table = ocores_i2c_match,
 487                 .pm = OCORES_I2C_PM,
 488         },
 489 };
 490
 491 module_platform_driver(ocores_i2c_driver);
 492
 493 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
 494 MODULE_DESCRIPTION("OpenCores I2C bus driver");
 495 MODULE_LICENSE("GPL");
 496 MODULE_ALIAS("platform:ocores-i2c");