2 * Copyright (c) 2006-2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX CPU Frequency scaling
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/cpufreq.h>
18 #include <linux/cpu.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/device.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
30 #include <plat/clock.h>
31 #include <plat/cpu-freq-core.h>
33 #include <mach/regs-clock.h>
35 /* note, cpufreq support deals in kHz, no Hz */
37 static struct cpufreq_driver s3c24xx_driver
;
38 static struct s3c_cpufreq_config cpu_cur
;
39 static struct s3c_iotimings s3c24xx_iotiming
;
40 static struct cpufreq_frequency_table
*pll_reg
;
41 static unsigned int last_target
= ~0;
42 static unsigned int ftab_size
;
43 static struct cpufreq_frequency_table
*ftab
;
45 static struct clk
*_clk_mpll
;
46 static struct clk
*_clk_xtal
;
47 static struct clk
*clk_fclk
;
48 static struct clk
*clk_hclk
;
49 static struct clk
*clk_pclk
;
50 static struct clk
*clk_arm
;
52 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
53 struct s3c_cpufreq_config
*s3c_cpufreq_getconfig(void)
58 struct s3c_iotimings
*s3c_cpufreq_getiotimings(void)
60 return &s3c24xx_iotiming
;
62 #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */
64 static void s3c_cpufreq_getcur(struct s3c_cpufreq_config
*cfg
)
66 unsigned long fclk
, pclk
, hclk
, armclk
;
68 cfg
->freq
.fclk
= fclk
= clk_get_rate(clk_fclk
);
69 cfg
->freq
.hclk
= hclk
= clk_get_rate(clk_hclk
);
70 cfg
->freq
.pclk
= pclk
= clk_get_rate(clk_pclk
);
71 cfg
->freq
.armclk
= armclk
= clk_get_rate(clk_arm
);
73 cfg
->pll
.driver_data
= __raw_readl(S3C2410_MPLLCON
);
74 cfg
->pll
.frequency
= fclk
;
76 cfg
->freq
.hclk_tns
= 1000000000 / (cfg
->freq
.hclk
/ 10);
78 cfg
->divs
.h_divisor
= fclk
/ hclk
;
79 cfg
->divs
.p_divisor
= fclk
/ pclk
;
82 static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config
*cfg
)
84 unsigned long pll
= cfg
->pll
.frequency
;
87 cfg
->freq
.hclk
= pll
/ cfg
->divs
.h_divisor
;
88 cfg
->freq
.pclk
= pll
/ cfg
->divs
.p_divisor
;
90 /* convert hclk into 10ths of nanoseconds for io calcs */
91 cfg
->freq
.hclk_tns
= 1000000000 / (cfg
->freq
.hclk
/ 10);
94 static inline int closer(unsigned int target
, unsigned int n
, unsigned int c
)
96 int diff_cur
= abs(target
- c
);
97 int diff_new
= abs(target
- n
);
99 return (diff_new
< diff_cur
);
102 static void s3c_cpufreq_show(const char *pfx
,
103 struct s3c_cpufreq_config
*cfg
)
105 s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
106 pfx
, cfg
->pll
.frequency
, cfg
->freq
.fclk
, cfg
->freq
.armclk
,
107 cfg
->freq
.hclk
, cfg
->divs
.h_divisor
,
108 cfg
->freq
.pclk
, cfg
->divs
.p_divisor
);
111 /* functions to wrapper the driver info calls to do the cpu specific work */
113 static void s3c_cpufreq_setio(struct s3c_cpufreq_config
*cfg
)
115 if (cfg
->info
->set_iotiming
)
116 (cfg
->info
->set_iotiming
)(cfg
, &s3c24xx_iotiming
);
119 static int s3c_cpufreq_calcio(struct s3c_cpufreq_config
*cfg
)
121 if (cfg
->info
->calc_iotiming
)
122 return (cfg
->info
->calc_iotiming
)(cfg
, &s3c24xx_iotiming
);
127 static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config
*cfg
)
129 (cfg
->info
->set_refresh
)(cfg
);
132 static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config
*cfg
)
134 (cfg
->info
->set_divs
)(cfg
);
137 static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config
*cfg
)
139 return (cfg
->info
->calc_divs
)(cfg
);
142 static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config
*cfg
)
144 (cfg
->info
->set_fvco
)(cfg
);
147 static inline void s3c_cpufreq_resume_clocks(void)
149 cpu_cur
.info
->resume_clocks();
152 static inline void s3c_cpufreq_updateclk(struct clk
*clk
,
155 clk_set_rate(clk
, freq
);
158 static int s3c_cpufreq_settarget(struct cpufreq_policy
*policy
,
159 unsigned int target_freq
,
160 struct cpufreq_frequency_table
*pll
)
162 struct s3c_cpufreq_freqs freqs
;
163 struct s3c_cpufreq_config cpu_new
;
166 cpu_new
= cpu_cur
; /* copy new from current */
168 s3c_cpufreq_show("cur", &cpu_cur
);
170 /* TODO - check for DMA currently outstanding */
172 cpu_new
.pll
= pll
? *pll
: cpu_cur
.pll
;
175 freqs
.pll_changing
= 1;
177 /* update our frequencies */
179 cpu_new
.freq
.armclk
= target_freq
;
180 cpu_new
.freq
.fclk
= cpu_new
.pll
.frequency
;
182 if (s3c_cpufreq_calcdivs(&cpu_new
) < 0) {
183 printk(KERN_ERR
"no divisors for %d\n", target_freq
);
184 goto err_notpossible
;
187 s3c_freq_dbg("%s: got divs\n", __func__
);
189 s3c_cpufreq_calc(&cpu_new
);
191 s3c_freq_dbg("%s: calculated frequencies for new\n", __func__
);
193 if (cpu_new
.freq
.hclk
!= cpu_cur
.freq
.hclk
) {
194 if (s3c_cpufreq_calcio(&cpu_new
) < 0) {
195 printk(KERN_ERR
"%s: no IO timings\n", __func__
);
196 goto err_notpossible
;
200 s3c_cpufreq_show("new", &cpu_new
);
202 /* setup our cpufreq parameters */
204 freqs
.old
= cpu_cur
.freq
;
205 freqs
.new = cpu_new
.freq
;
207 freqs
.freqs
.old
= cpu_cur
.freq
.armclk
/ 1000;
208 freqs
.freqs
.new = cpu_new
.freq
.armclk
/ 1000;
210 /* update f/h/p clock settings before we issue the change
211 * notification, so that drivers do not need to do anything
212 * special if they want to recalculate on CPUFREQ_PRECHANGE. */
214 s3c_cpufreq_updateclk(_clk_mpll
, cpu_new
.pll
.frequency
);
215 s3c_cpufreq_updateclk(clk_fclk
, cpu_new
.freq
.fclk
);
216 s3c_cpufreq_updateclk(clk_hclk
, cpu_new
.freq
.hclk
);
217 s3c_cpufreq_updateclk(clk_pclk
, cpu_new
.freq
.pclk
);
219 /* start the frequency change */
220 cpufreq_notify_transition(policy
, &freqs
.freqs
, CPUFREQ_PRECHANGE
);
222 /* If hclk is staying the same, then we do not need to
223 * re-write the IO or the refresh timings whilst we are changing
226 local_irq_save(flags
);
228 /* is our memory clock slowing down? */
229 if (cpu_new
.freq
.hclk
< cpu_cur
.freq
.hclk
) {
230 s3c_cpufreq_setrefresh(&cpu_new
);
231 s3c_cpufreq_setio(&cpu_new
);
234 if (cpu_new
.freq
.fclk
== cpu_cur
.freq
.fclk
) {
235 /* not changing PLL, just set the divisors */
237 s3c_cpufreq_setdivs(&cpu_new
);
239 if (cpu_new
.freq
.fclk
< cpu_cur
.freq
.fclk
) {
240 /* slow the cpu down, then set divisors */
242 s3c_cpufreq_setfvco(&cpu_new
);
243 s3c_cpufreq_setdivs(&cpu_new
);
245 /* set the divisors, then speed up */
247 s3c_cpufreq_setdivs(&cpu_new
);
248 s3c_cpufreq_setfvco(&cpu_new
);
252 /* did our memory clock speed up */
253 if (cpu_new
.freq
.hclk
> cpu_cur
.freq
.hclk
) {
254 s3c_cpufreq_setrefresh(&cpu_new
);
255 s3c_cpufreq_setio(&cpu_new
);
258 /* update our current settings */
261 local_irq_restore(flags
);
263 /* notify everyone we've done this */
264 cpufreq_notify_transition(policy
, &freqs
.freqs
, CPUFREQ_POSTCHANGE
);
266 s3c_freq_dbg("%s: finished\n", __func__
);
270 printk(KERN_ERR
"no compatible settings for %d\n", target_freq
);
274 /* s3c_cpufreq_target
276 * called by the cpufreq core to adjust the frequency that the CPU
277 * is currently running at.
280 static int s3c_cpufreq_target(struct cpufreq_policy
*policy
,
281 unsigned int target_freq
,
282 unsigned int relation
)
284 struct cpufreq_frequency_table
*pll
;
287 /* avoid repeated calls which cause a needless amout of duplicated
288 * logging output (and CPU time as the calculation process is
290 if (target_freq
== last_target
)
293 last_target
= target_freq
;
295 s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
296 __func__
, policy
, target_freq
, relation
);
299 if (cpufreq_frequency_table_target(policy
, ftab
,
300 target_freq
, relation
,
302 s3c_freq_dbg("%s: table failed\n", __func__
);
306 s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__
,
307 target_freq
, index
, ftab
[index
].frequency
);
308 target_freq
= ftab
[index
].frequency
;
311 target_freq
*= 1000; /* convert target to Hz */
313 /* find the settings for our new frequency */
315 if (!pll_reg
|| cpu_cur
.lock_pll
) {
316 /* either we've not got any PLL values, or we've locked
317 * to the current one. */
320 struct cpufreq_policy tmp_policy
;
323 /* we keep the cpu pll table in Hz, to ensure we get an
324 * accurate value for the PLL output. */
326 tmp_policy
.min
= policy
->min
* 1000;
327 tmp_policy
.max
= policy
->max
* 1000;
328 tmp_policy
.cpu
= policy
->cpu
;
330 /* cpufreq_frequency_table_target uses a pointer to 'index'
331 * which is the number of the table entry, not the value of
332 * the table entry's index field. */
334 ret
= cpufreq_frequency_table_target(&tmp_policy
, pll_reg
,
335 target_freq
, relation
,
339 printk(KERN_ERR
"%s: no PLL available\n", __func__
);
340 goto err_notpossible
;
343 pll
= pll_reg
+ index
;
345 s3c_freq_dbg("%s: target %u => %u\n",
346 __func__
, target_freq
, pll
->frequency
);
348 target_freq
= pll
->frequency
;
351 return s3c_cpufreq_settarget(policy
, target_freq
, pll
);
354 printk(KERN_ERR
"no compatible settings for %d\n", target_freq
);
358 static unsigned int s3c_cpufreq_get(unsigned int cpu
)
360 return clk_get_rate(clk_arm
) / 1000;
363 struct clk
*s3c_cpufreq_clk_get(struct device
*dev
, const char *name
)
367 clk
= clk_get(dev
, name
);
369 printk(KERN_ERR
"cpufreq: failed to get clock '%s'\n", name
);
374 static int s3c_cpufreq_init(struct cpufreq_policy
*policy
)
376 return cpufreq_generic_init(policy
, ftab
, cpu_cur
.info
->latency
);
379 static int __init
s3c_cpufreq_initclks(void)
381 _clk_mpll
= s3c_cpufreq_clk_get(NULL
, "mpll");
382 _clk_xtal
= s3c_cpufreq_clk_get(NULL
, "xtal");
383 clk_fclk
= s3c_cpufreq_clk_get(NULL
, "fclk");
384 clk_hclk
= s3c_cpufreq_clk_get(NULL
, "hclk");
385 clk_pclk
= s3c_cpufreq_clk_get(NULL
, "pclk");
386 clk_arm
= s3c_cpufreq_clk_get(NULL
, "armclk");
388 if (IS_ERR(clk_fclk
) || IS_ERR(clk_hclk
) || IS_ERR(clk_pclk
) ||
389 IS_ERR(_clk_mpll
) || IS_ERR(clk_arm
) || IS_ERR(_clk_xtal
)) {
390 printk(KERN_ERR
"%s: could not get clock(s)\n", __func__
);
394 printk(KERN_INFO
"%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__
,
395 clk_get_rate(clk_fclk
) / 1000,
396 clk_get_rate(clk_hclk
) / 1000,
397 clk_get_rate(clk_pclk
) / 1000,
398 clk_get_rate(clk_arm
) / 1000);
404 static struct cpufreq_frequency_table suspend_pll
;
405 static unsigned int suspend_freq
;
407 static int s3c_cpufreq_suspend(struct cpufreq_policy
*policy
)
409 suspend_pll
.frequency
= clk_get_rate(_clk_mpll
);
410 suspend_pll
.driver_data
= __raw_readl(S3C2410_MPLLCON
);
411 suspend_freq
= s3c_cpufreq_get(0) * 1000;
416 static int s3c_cpufreq_resume(struct cpufreq_policy
*policy
)
420 s3c_freq_dbg("%s: resuming with policy %p\n", __func__
, policy
);
422 last_target
= ~0; /* invalidate last_target setting */
424 /* first, find out what speed we resumed at. */
425 s3c_cpufreq_resume_clocks();
427 /* whilst we will be called later on, we try and re-set the
428 * cpu frequencies as soon as possible so that we do not end
429 * up resuming devices and then immediately having to re-set
430 * a number of settings once these devices have restarted.
432 * as a note, it is expected devices are not used until they
433 * have been un-suspended and at that time they should have
434 * used the updated clock settings.
437 ret
= s3c_cpufreq_settarget(NULL
, suspend_freq
, &suspend_pll
);
439 printk(KERN_ERR
"%s: failed to reset pll/freq\n", __func__
);
446 #define s3c_cpufreq_resume NULL
447 #define s3c_cpufreq_suspend NULL
450 static struct cpufreq_driver s3c24xx_driver
= {
451 .flags
= CPUFREQ_STICKY
,
452 .target
= s3c_cpufreq_target
,
453 .get
= s3c_cpufreq_get
,
454 .init
= s3c_cpufreq_init
,
455 .suspend
= s3c_cpufreq_suspend
,
456 .resume
= s3c_cpufreq_resume
,
461 int __init
s3c_cpufreq_register(struct s3c_cpufreq_info
*info
)
463 if (!info
|| !info
->name
) {
464 printk(KERN_ERR
"%s: failed to pass valid information\n",
469 printk(KERN_INFO
"S3C24XX CPU Frequency driver, %s cpu support\n",
472 /* check our driver info has valid data */
474 BUG_ON(info
->set_refresh
== NULL
);
475 BUG_ON(info
->set_divs
== NULL
);
476 BUG_ON(info
->calc_divs
== NULL
);
478 /* info->set_fvco is optional, depending on whether there
479 * is a need to set the clock code. */
483 /* Note, driver registering should probably update locktime */
488 int __init
s3c_cpufreq_setboard(struct s3c_cpufreq_board
*board
)
490 struct s3c_cpufreq_board
*ours
;
493 printk(KERN_INFO
"%s: no board data\n", __func__
);
497 /* Copy the board information so that each board can make this
500 ours
= kzalloc(sizeof(*ours
), GFP_KERNEL
);
502 printk(KERN_ERR
"%s: no memory\n", __func__
);
507 cpu_cur
.board
= ours
;
512 int __init
s3c_cpufreq_auto_io(void)
516 if (!cpu_cur
.info
->get_iotiming
) {
517 printk(KERN_ERR
"%s: get_iotiming undefined\n", __func__
);
521 printk(KERN_INFO
"%s: working out IO settings\n", __func__
);
523 ret
= (cpu_cur
.info
->get_iotiming
)(&cpu_cur
, &s3c24xx_iotiming
);
525 printk(KERN_ERR
"%s: failed to get timings\n", __func__
);
530 /* if one or is zero, then return the other, otherwise return the min */
531 #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
534 * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
535 * @dst: The destination structure
537 * @b: The other argument.
539 * Create a minimum of each frequency entry in the 'struct s3c_freq',
540 * unless the entry is zero when it is ignored and the non-zero argument
543 static void s3c_cpufreq_freq_min(struct s3c_freq
*dst
,
544 struct s3c_freq
*a
, struct s3c_freq
*b
)
546 dst
->fclk
= do_min(a
->fclk
, b
->fclk
);
547 dst
->hclk
= do_min(a
->hclk
, b
->hclk
);
548 dst
->pclk
= do_min(a
->pclk
, b
->pclk
);
549 dst
->armclk
= do_min(a
->armclk
, b
->armclk
);
552 static inline u32
calc_locktime(u32 freq
, u32 time_us
)
556 result
= freq
* time_us
;
557 result
= DIV_ROUND_UP(result
, 1000 * 1000);
562 static void s3c_cpufreq_update_loctkime(void)
564 unsigned int bits
= cpu_cur
.info
->locktime_bits
;
565 u32 rate
= (u32
)clk_get_rate(_clk_xtal
);
573 val
= calc_locktime(rate
, cpu_cur
.info
->locktime_u
) << bits
;
574 val
|= calc_locktime(rate
, cpu_cur
.info
->locktime_m
);
576 printk(KERN_INFO
"%s: new locktime is 0x%08x\n", __func__
, val
);
577 __raw_writel(val
, S3C2410_LOCKTIME
);
580 static int s3c_cpufreq_build_freq(void)
584 if (!cpu_cur
.info
->calc_freqtable
)
590 size
= cpu_cur
.info
->calc_freqtable(&cpu_cur
, NULL
, 0);
593 ftab
= kmalloc(sizeof(*ftab
) * size
, GFP_KERNEL
);
595 printk(KERN_ERR
"%s: no memory for tables\n", __func__
);
601 ret
= cpu_cur
.info
->calc_freqtable(&cpu_cur
, ftab
, size
);
602 s3c_cpufreq_addfreq(ftab
, ret
, size
, CPUFREQ_TABLE_END
);
607 static int __init
s3c_cpufreq_initcall(void)
611 if (cpu_cur
.info
&& cpu_cur
.board
) {
612 ret
= s3c_cpufreq_initclks();
616 /* get current settings */
617 s3c_cpufreq_getcur(&cpu_cur
);
618 s3c_cpufreq_show("cur", &cpu_cur
);
620 if (cpu_cur
.board
->auto_io
) {
621 ret
= s3c_cpufreq_auto_io();
623 printk(KERN_ERR
"%s: failed to get io timing\n",
629 if (cpu_cur
.board
->need_io
&& !cpu_cur
.info
->set_iotiming
) {
630 printk(KERN_ERR
"%s: no IO support registered\n",
636 if (!cpu_cur
.info
->need_pll
)
637 cpu_cur
.lock_pll
= 1;
639 s3c_cpufreq_update_loctkime();
641 s3c_cpufreq_freq_min(&cpu_cur
.max
, &cpu_cur
.board
->max
,
644 if (cpu_cur
.info
->calc_freqtable
)
645 s3c_cpufreq_build_freq();
647 ret
= cpufreq_register_driver(&s3c24xx_driver
);
654 late_initcall(s3c_cpufreq_initcall
);
657 * s3c_plltab_register - register CPU PLL table.
658 * @plls: The list of PLL entries.
659 * @plls_no: The size of the PLL entries @plls.
661 * Register the given set of PLLs with the system.
663 int __init
s3c_plltab_register(struct cpufreq_frequency_table
*plls
,
664 unsigned int plls_no
)
666 struct cpufreq_frequency_table
*vals
;
669 size
= sizeof(*vals
) * (plls_no
+ 1);
671 vals
= kmalloc(size
, GFP_KERNEL
);
673 memcpy(vals
, plls
, size
);
676 /* write a terminating entry, we don't store it in the
677 * table that is stored in the kernel */
679 vals
->frequency
= CPUFREQ_TABLE_END
;
681 printk(KERN_INFO
"cpufreq: %d PLL entries\n", plls_no
);
683 printk(KERN_ERR
"cpufreq: no memory for PLL tables\n");
685 return vals
? 0 : -ENOMEM
;