drivers/cpufreq/pmac64-cpufreq.c

   1 /*
   2  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
   3  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
  10  * that is iMac G5 and latest single CPU desktop.
  11  */
  12
  13 #undef DEBUG
  14
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/sched.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/init.h>
  23 #include <linux/completion.h>
  24 #include <linux/mutex.h>
  25 #include <linux/of_device.h>
  26 #include <asm/prom.h>
  27 #include <asm/machdep.h>
  28 #include <asm/irq.h>
  29 #include <asm/sections.h>
  30 #include <asm/cputable.h>
  31 #include <asm/time.h>
  32 #include <asm/smu.h>
  33 #include <asm/pmac_pfunc.h>
  34
  35 #define DBG(fmt...) pr_debug(fmt)
  36
  37 /* see 970FX user manual */
  38
  39 #define SCOM_PCR 0x0aa001                       /* PCR scom addr */
  40
  41 #define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
  42 #define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
  43 #define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
  44 #define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
  45 #define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
  46 #define PCR_SPEED_SHIFT         17
  47 #define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
  48 #define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
  49 #define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
  50 #define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
  51 #define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
  52 #define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
  53
  54 #define SCOM_PSR 0x408001                       /* PSR scom addr */
  55 /* warning: PSR is a 64 bits register */
  56 #define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
  57 #define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
  58 #define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
  59 #define PSR_CUR_SPEED_SHIFT     (56)
  60
  61 /*
  62  * The G5 only supports two frequencies (Quarter speed is not supported)
  63  */
  64 #define CPUFREQ_HIGH                  0
  65 #define CPUFREQ_LOW                   1
  66
  67 static struct cpufreq_frequency_table g5_cpu_freqs[] = {
  68         {CPUFREQ_HIGH,          0},
  69         {CPUFREQ_LOW,           0},
  70         {0,                     CPUFREQ_TABLE_END},
  71 };
  72
  73 /* Power mode data is an array of the 32 bits PCR values to use for
  74  * the various frequencies, retrieved from the device-tree
  75  */
  76 static int g5_pmode_cur;
  77
  78 static void (*g5_switch_volt)(int speed_mode);
  79 static int (*g5_switch_freq)(int speed_mode);
  80 static int (*g5_query_freq)(void);
  81
  82 static unsigned long transition_latency;
  83
  84 #ifdef CONFIG_PMAC_SMU
  85
  86 static const u32 *g5_pmode_data;
  87 static int g5_pmode_max;
  88
  89 static struct smu_sdbp_fvt *g5_fvt_table;       /* table of op. points */
  90 static int g5_fvt_count;                        /* number of op. points */
  91 static int g5_fvt_cur;                          /* current op. point */
  92
  93 /*
  94  * SMU based voltage switching for Neo2 platforms
  95  */
  96
  97 static void g5_smu_switch_volt(int speed_mode)
  98 {
  99         struct smu_simple_cmd   cmd;
 100
 101         DECLARE_COMPLETION_ONSTACK(comp);
 102         smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
 103                          &comp, 'V', 'S', 'L', 'E', 'W',
 104                          0xff, g5_fvt_cur+1, speed_mode);
 105         wait_for_completion(&comp);
 106 }
 107
 108 /*
 109  * Platform function based voltage/vdnap switching for Neo2
 110  */
 111
 112 static struct pmf_function *pfunc_set_vdnap0;
 113 static struct pmf_function *pfunc_vdnap0_complete;
 114
 115 static void g5_vdnap_switch_volt(int speed_mode)
 116 {
 117         struct pmf_args args;
 118         u32 slew, done = 0;
 119         unsigned long timeout;
 120
 121         slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
 122         args.count = 1;
 123         args.u[0].p = &slew;
 124
 125         pmf_call_one(pfunc_set_vdnap0, &args);
 126
 127         /* It's an irq GPIO so we should be able to just block here,
 128          * I'll do that later after I've properly tested the IRQ code for
 129          * platform functions
 130          */
 131         timeout = jiffies + HZ/10;
 132         while(!time_after(jiffies, timeout)) {
 133                 args.count = 1;
 134                 args.u[0].p = &done;
 135                 pmf_call_one(pfunc_vdnap0_complete, &args);
 136                 if (done)
 137                         break;
 138                 usleep_range(1000, 1000);
 139         }
 140         if (done == 0)
 141                 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
 142 }
 143
 144
 145 /*
 146  * SCOM based frequency switching for 970FX rev3
 147  */
 148 static int g5_scom_switch_freq(int speed_mode)
 149 {
 150         unsigned long flags;
 151         int to;
 152
 153         /* If frequency is going up, first ramp up the voltage */
 154         if (speed_mode < g5_pmode_cur)
 155                 g5_switch_volt(speed_mode);
 156
 157         local_irq_save(flags);
 158
 159         /* Clear PCR high */
 160         scom970_write(SCOM_PCR, 0);
 161         /* Clear PCR low */
 162         scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
 163         /* Set PCR low */
 164         scom970_write(SCOM_PCR, PCR_HILO_SELECT |
 165                       g5_pmode_data[speed_mode]);
 166
 167         /* Wait for completion */
 168         for (to = 0; to < 10; to++) {
 169                 unsigned long psr = scom970_read(SCOM_PSR);
 170
 171                 if ((psr & PSR_CMD_RECEIVED) == 0 &&
 172                     (((psr >> PSR_CUR_SPEED_SHIFT) ^
 173                       (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
 174                     == 0)
 175                         break;
 176                 if (psr & PSR_CMD_COMPLETED)
 177                         break;
 178                 udelay(100);
 179         }
 180
 181         local_irq_restore(flags);
 182
 183         /* If frequency is going down, last ramp the voltage */
 184         if (speed_mode > g5_pmode_cur)
 185                 g5_switch_volt(speed_mode);
 186
 187         g5_pmode_cur = speed_mode;
 188         ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 189
 190         return 0;
 191 }
 192
 193 static int g5_scom_query_freq(void)
 194 {
 195         unsigned long psr = scom970_read(SCOM_PSR);
 196         int i;
 197
 198         for (i = 0; i <= g5_pmode_max; i++)
 199                 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
 200                       (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
 201                         break;
 202         return i;
 203 }
 204
 205 /*
 206  * Fake voltage switching for platforms with missing support
 207  */
 208
 209 static void g5_dummy_switch_volt(int speed_mode)
 210 {
 211 }
 212
 213 #endif /* CONFIG_PMAC_SMU */
 214
 215 /*
 216  * Platform function based voltage switching for PowerMac7,2 & 7,3
 217  */
 218
 219 static struct pmf_function *pfunc_cpu0_volt_high;
 220 static struct pmf_function *pfunc_cpu0_volt_low;
 221 static struct pmf_function *pfunc_cpu1_volt_high;
 222 static struct pmf_function *pfunc_cpu1_volt_low;
 223
 224 static void g5_pfunc_switch_volt(int speed_mode)
 225 {
 226         if (speed_mode == CPUFREQ_HIGH) {
 227                 if (pfunc_cpu0_volt_high)
 228                         pmf_call_one(pfunc_cpu0_volt_high, NULL);
 229                 if (pfunc_cpu1_volt_high)
 230                         pmf_call_one(pfunc_cpu1_volt_high, NULL);
 231         } else {
 232                 if (pfunc_cpu0_volt_low)
 233                         pmf_call_one(pfunc_cpu0_volt_low, NULL);
 234                 if (pfunc_cpu1_volt_low)
 235                         pmf_call_one(pfunc_cpu1_volt_low, NULL);
 236         }
 237         usleep_range(10000, 10000); /* should be faster , to fix */
 238 }
 239
 240 /*
 241  * Platform function based frequency switching for PowerMac7,2 & 7,3
 242  */
 243
 244 static struct pmf_function *pfunc_cpu_setfreq_high;
 245 static struct pmf_function *pfunc_cpu_setfreq_low;
 246 static struct pmf_function *pfunc_cpu_getfreq;
 247 static struct pmf_function *pfunc_slewing_done;
 248
 249 static int g5_pfunc_switch_freq(int speed_mode)
 250 {
 251         struct pmf_args args;
 252         u32 done = 0;
 253         unsigned long timeout;
 254         int rc;
 255
 256         DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
 257
 258         /* If frequency is going up, first ramp up the voltage */
 259         if (speed_mode < g5_pmode_cur)
 260                 g5_switch_volt(speed_mode);
 261
 262         /* Do it */
 263         if (speed_mode == CPUFREQ_HIGH)
 264                 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
 265         else
 266                 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
 267
 268         if (rc)
 269                 printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc);
 270
 271         /* It's an irq GPIO so we should be able to just block here,
 272          * I'll do that later after I've properly tested the IRQ code for
 273          * platform functions
 274          */
 275         timeout = jiffies + HZ/10;
 276         while(!time_after(jiffies, timeout)) {
 277                 args.count = 1;
 278                 args.u[0].p = &done;
 279                 pmf_call_one(pfunc_slewing_done, &args);
 280                 if (done)
 281                         break;
 282                 usleep_range(500, 500);
 283         }
 284         if (done == 0)
 285                 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
 286
 287         /* If frequency is going down, last ramp the voltage */
 288         if (speed_mode > g5_pmode_cur)
 289                 g5_switch_volt(speed_mode);
 290
 291         g5_pmode_cur = speed_mode;
 292         ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 293
 294         return 0;
 295 }
 296
 297 static int g5_pfunc_query_freq(void)
 298 {
 299         struct pmf_args args;
 300         u32 val = 0;
 301
 302         args.count = 1;
 303         args.u[0].p = &val;
 304         pmf_call_one(pfunc_cpu_getfreq, &args);
 305         return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
 306 }
 307
 308
 309 /*
 310  * Common interface to the cpufreq core
 311  */
 312
 313 static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
 314 {
 315         return g5_switch_freq(index);
 316 }
 317
 318 static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
 319 {
 320         return g5_cpu_freqs[g5_pmode_cur].frequency;
 321 }
 322
 323 static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
 324 {
 325         return cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
 326 }
 327
 328 static struct cpufreq_driver g5_cpufreq_driver = {
 329         .name           = "powermac",
 330         .flags          = CPUFREQ_CONST_LOOPS,
 331         .init           = g5_cpufreq_cpu_init,
 332         .verify         = cpufreq_generic_frequency_table_verify,
 333         .target_index   = g5_cpufreq_target,
 334         .get            = g5_cpufreq_get_speed,
 335         .attr           = cpufreq_generic_attr,
 336 };
 337
 338
 339 #ifdef CONFIG_PMAC_SMU
 340
 341 static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
 342 {
 343         unsigned int psize, ssize;
 344         unsigned long max_freq;
 345         char *freq_method, *volt_method;
 346         const u32 *valp;
 347         u32 pvr_hi;
 348         int use_volts_vdnap = 0;
 349         int use_volts_smu = 0;
 350         int rc = -ENODEV;
 351
 352         /* Check supported platforms */
 353         if (of_machine_is_compatible("PowerMac8,1") ||
 354             of_machine_is_compatible("PowerMac8,2") ||
 355             of_machine_is_compatible("PowerMac9,1") ||
 356             of_machine_is_compatible("PowerMac12,1"))
 357                 use_volts_smu = 1;
 358         else if (of_machine_is_compatible("PowerMac11,2"))
 359                 use_volts_vdnap = 1;
 360         else
 361                 return -ENODEV;
 362
 363         /* Check 970FX for now */
 364         valp = of_get_property(cpunode, "cpu-version", NULL);
 365         if (!valp) {
 366                 DBG("No cpu-version property !\n");
 367                 goto bail_noprops;
 368         }
 369         pvr_hi = (*valp) >> 16;
 370         if (pvr_hi != 0x3c && pvr_hi != 0x44) {
 371                 printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
 372                 goto bail_noprops;
 373         }
 374
 375         /* Look for the powertune data in the device-tree */
 376         g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
 377         if (!g5_pmode_data) {
 378                 DBG("No power-mode-data !\n");
 379                 goto bail_noprops;
 380         }
 381         g5_pmode_max = psize / sizeof(u32) - 1;
 382
 383         if (use_volts_smu) {
 384                 const struct smu_sdbp_header *shdr;
 385
 386                 /* Look for the FVT table */
 387                 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
 388                 if (!shdr)
 389                         goto bail_noprops;
 390                 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
 391                 ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
 392                 g5_fvt_count = ssize / sizeof(*g5_fvt_table);
 393                 g5_fvt_cur = 0;
 394
 395                 /* Sanity checking */
 396                 if (g5_fvt_count < 1 || g5_pmode_max < 1)
 397                         goto bail_noprops;
 398
 399                 g5_switch_volt = g5_smu_switch_volt;
 400                 volt_method = "SMU";
 401         } else if (use_volts_vdnap) {
 402                 struct device_node *root;
 403
 404                 root = of_find_node_by_path("/");
 405                 if (root == NULL) {
 406                         printk(KERN_ERR "cpufreq: Can't find root of "
 407                                "device tree\n");
 408                         goto bail_noprops;
 409                 }
 410                 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
 411                 pfunc_vdnap0_complete =
 412                         pmf_find_function(root, "slewing-done");
 413                 if (pfunc_set_vdnap0 == NULL ||
 414                     pfunc_vdnap0_complete == NULL) {
 415                         printk(KERN_ERR "cpufreq: Can't find required "
 416                                "platform function\n");
 417                         goto bail_noprops;
 418                 }
 419
 420                 g5_switch_volt = g5_vdnap_switch_volt;
 421                 volt_method = "GPIO";
 422         } else {
 423                 g5_switch_volt = g5_dummy_switch_volt;
 424                 volt_method = "none";
 425         }
 426
 427         /*
 428          * From what I see, clock-frequency is always the maximal frequency.
 429          * The current driver can not slew sysclk yet, so we really only deal
 430          * with powertune steps for now. We also only implement full freq and
 431          * half freq in this version. So far, I haven't yet seen a machine
 432          * supporting anything else.
 433          */
 434         valp = of_get_property(cpunode, "clock-frequency", NULL);
 435         if (!valp)
 436                 return -ENODEV;
 437         max_freq = (*valp)/1000;
 438         g5_cpu_freqs[0].frequency = max_freq;
 439         g5_cpu_freqs[1].frequency = max_freq/2;
 440
 441         /* Set callbacks */
 442         transition_latency = 12000;
 443         g5_switch_freq = g5_scom_switch_freq;
 444         g5_query_freq = g5_scom_query_freq;
 445         freq_method = "SCOM";
 446
 447         /* Force apply current frequency to make sure everything is in
 448          * sync (voltage is right for example). Firmware may leave us with
 449          * a strange setting ...
 450          */
 451         g5_switch_volt(CPUFREQ_HIGH);
 452         msleep(10);
 453         g5_pmode_cur = -1;
 454         g5_switch_freq(g5_query_freq());
 455
 456         printk(KERN_INFO "Registering G5 CPU frequency driver\n");
 457         printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
 458                freq_method, volt_method);
 459         printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 460                 g5_cpu_freqs[1].frequency/1000,
 461                 g5_cpu_freqs[0].frequency/1000,
 462                 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 463
 464         rc = cpufreq_register_driver(&g5_cpufreq_driver);
 465
 466         /* We keep the CPU node on hold... hopefully, Apple G5 don't have
 467          * hotplug CPU with a dynamic device-tree ...
 468          */
 469         return rc;
 470
 471  bail_noprops:
 472         of_node_put(cpunode);
 473
 474         return rc;
 475 }
 476
 477 #endif /* CONFIG_PMAC_SMU */
 478
 479
 480 static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
 481 {
 482         struct device_node *cpuid = NULL, *hwclock = NULL;
 483         const u8 *eeprom = NULL;
 484         const u32 *valp;
 485         u64 max_freq, min_freq, ih, il;
 486         int has_volt = 1, rc = 0;
 487
 488         DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
 489             " RackMac3,1...\n");
 490
 491         /* Lookup the cpuid eeprom node */
 492         cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
 493         if (cpuid != NULL)
 494                 eeprom = of_get_property(cpuid, "cpuid", NULL);
 495         if (eeprom == NULL) {
 496                 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
 497                 rc = -ENODEV;
 498                 goto bail;
 499         }
 500
 501         /* Lookup the i2c hwclock */
 502         for (hwclock = NULL;
 503              (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
 504                 const char *loc = of_get_property(hwclock,
 505                                 "hwctrl-location", NULL);
 506                 if (loc == NULL)
 507                         continue;
 508                 if (strcmp(loc, "CPU CLOCK"))
 509                         continue;
 510                 if (!of_get_property(hwclock, "platform-get-frequency", NULL))
 511                         continue;
 512                 break;
 513         }
 514         if (hwclock == NULL) {
 515                 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
 516                 rc = -ENODEV;
 517                 goto bail;
 518         }
 519
 520         DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
 521
 522         /* Now get all the platform functions */
 523         pfunc_cpu_getfreq =
 524                 pmf_find_function(hwclock, "get-frequency");
 525         pfunc_cpu_setfreq_high =
 526                 pmf_find_function(hwclock, "set-frequency-high");
 527         pfunc_cpu_setfreq_low =
 528                 pmf_find_function(hwclock, "set-frequency-low");
 529         pfunc_slewing_done =
 530                 pmf_find_function(hwclock, "slewing-done");
 531         pfunc_cpu0_volt_high =
 532                 pmf_find_function(hwclock, "set-voltage-high-0");
 533         pfunc_cpu0_volt_low =
 534                 pmf_find_function(hwclock, "set-voltage-low-0");
 535         pfunc_cpu1_volt_high =
 536                 pmf_find_function(hwclock, "set-voltage-high-1");
 537         pfunc_cpu1_volt_low =
 538                 pmf_find_function(hwclock, "set-voltage-low-1");
 539
 540         /* Check we have minimum requirements */
 541         if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
 542             pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
 543                 printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
 544                 rc = -ENODEV;
 545                 goto bail;
 546         }
 547
 548         /* Check that we have complete sets */
 549         if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
 550                 pmf_put_function(pfunc_cpu0_volt_high);
 551                 pmf_put_function(pfunc_cpu0_volt_low);
 552                 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
 553                 has_volt = 0;
 554         }
 555         if (!has_volt ||
 556             pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
 557                 pmf_put_function(pfunc_cpu1_volt_high);
 558                 pmf_put_function(pfunc_cpu1_volt_low);
 559                 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
 560         }
 561
 562         /* Note: The device tree also contains a "platform-set-values"
 563          * function for which I haven't quite figured out the usage. It
 564          * might have to be called on init and/or wakeup, I'm not too sure
 565          * but things seem to work fine without it so far ...
 566          */
 567
 568         /* Get max frequency from device-tree */
 569         valp = of_get_property(cpunode, "clock-frequency", NULL);
 570         if (!valp) {
 571                 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
 572                 rc = -ENODEV;
 573                 goto bail;
 574         }
 575
 576         max_freq = (*valp)/1000;
 577
 578         /* Now calculate reduced frequency by using the cpuid input freq
 579          * ratio. This requires 64 bits math unless we are willing to lose
 580          * some precision
 581          */
 582         ih = *((u32 *)(eeprom + 0x10));
 583         il = *((u32 *)(eeprom + 0x20));
 584
 585         /* Check for machines with no useful settings */
 586         if (il == ih) {
 587                 printk(KERN_WARNING "cpufreq: No low frequency mode available"
 588                        " on this model !\n");
 589                 rc = -ENODEV;
 590                 goto bail;
 591         }
 592
 593         min_freq = 0;
 594         if (ih != 0 && il != 0)
 595                 min_freq = (max_freq * il) / ih;
 596
 597         /* Sanity check */
 598         if (min_freq >= max_freq || min_freq < 1000) {
 599                 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
 600                 rc = -ENXIO;
 601                 goto bail;
 602         }
 603         g5_cpu_freqs[0].frequency = max_freq;
 604         g5_cpu_freqs[1].frequency = min_freq;
 605
 606         /* Based on a measurement on Xserve G5, rounded up. */
 607         transition_latency = 10 * NSEC_PER_MSEC;
 608
 609         /* Set callbacks */
 610         g5_switch_volt = g5_pfunc_switch_volt;
 611         g5_switch_freq = g5_pfunc_switch_freq;
 612         g5_query_freq = g5_pfunc_query_freq;
 613
 614         /* Force apply current frequency to make sure everything is in
 615          * sync (voltage is right for example). Firmware may leave us with
 616          * a strange setting ...
 617          */
 618         g5_switch_volt(CPUFREQ_HIGH);
 619         msleep(10);
 620         g5_pmode_cur = -1;
 621         g5_switch_freq(g5_query_freq());
 622
 623         printk(KERN_INFO "Registering G5 CPU frequency driver\n");
 624         printk(KERN_INFO "Frequency method: i2c/pfunc, "
 625                "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
 626         printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 627                 g5_cpu_freqs[1].frequency/1000,
 628                 g5_cpu_freqs[0].frequency/1000,
 629                 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 630
 631         rc = cpufreq_register_driver(&g5_cpufreq_driver);
 632  bail:
 633         if (rc != 0) {
 634                 pmf_put_function(pfunc_cpu_getfreq);
 635                 pmf_put_function(pfunc_cpu_setfreq_high);
 636                 pmf_put_function(pfunc_cpu_setfreq_low);
 637                 pmf_put_function(pfunc_slewing_done);
 638                 pmf_put_function(pfunc_cpu0_volt_high);
 639                 pmf_put_function(pfunc_cpu0_volt_low);
 640                 pmf_put_function(pfunc_cpu1_volt_high);
 641                 pmf_put_function(pfunc_cpu1_volt_low);
 642         }
 643         of_node_put(hwclock);
 644         of_node_put(cpuid);
 645         of_node_put(cpunode);
 646
 647         return rc;
 648 }
 649
 650 static int __init g5_cpufreq_init(void)
 651 {
 652         struct device_node *cpunode;
 653         int rc = 0;
 654
 655         /* Get first CPU node */
 656         cpunode = of_cpu_device_node_get(0);
 657         if (cpunode == NULL) {
 658                 pr_err("cpufreq: Can't find any CPU node\n");
 659                 return -ENODEV;
 660         }
 661
 662         if (of_machine_is_compatible("PowerMac7,2") ||
 663             of_machine_is_compatible("PowerMac7,3") ||
 664             of_machine_is_compatible("RackMac3,1"))
 665                 rc = g5_pm72_cpufreq_init(cpunode);
 666 #ifdef CONFIG_PMAC_SMU
 667         else
 668                 rc = g5_neo2_cpufreq_init(cpunode);
 669 #endif /* CONFIG_PMAC_SMU */
 670
 671         return rc;
 672 }
 673
 674 module_init(g5_cpufreq_init);
 675
 676
 677 MODULE_LICENSE("GPL");