2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4210 - CPU frequency scaling support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
17 #include <linux/slab.h>
18 #include <linux/cpufreq.h>
20 #include <mach/regs-clock.h>
22 #include "exynos-cpufreq.h"
24 static struct clk
*cpu_clk
;
25 static struct clk
*moutcore
;
26 static struct clk
*mout_mpll
;
27 static struct clk
*mout_apll
;
29 static unsigned int exynos4210_volt_table
[] = {
30 1250000, 1150000, 1050000, 975000, 950000,
33 static struct cpufreq_frequency_table exynos4210_freq_table
[] = {
39 {0, CPUFREQ_TABLE_END
},
42 static struct apll_freq apll_freq_4210
[] = {
46 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
47 * clock divider for COPY, HPM, RESERVED
50 APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
51 APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
52 APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
53 APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
54 APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
57 static void exynos4210_set_clkdiv(unsigned int div_index
)
61 /* Change Divider - CPU0 */
63 tmp
= apll_freq_4210
[div_index
].clk_div_cpu0
;
65 __raw_writel(tmp
, EXYNOS4_CLKDIV_CPU
);
68 tmp
= __raw_readl(EXYNOS4_CLKDIV_STATCPU
);
69 } while (tmp
& 0x1111111);
71 /* Change Divider - CPU1 */
73 tmp
= apll_freq_4210
[div_index
].clk_div_cpu1
;
75 __raw_writel(tmp
, EXYNOS4_CLKDIV_CPU1
);
78 tmp
= __raw_readl(EXYNOS4_CLKDIV_STATCPU1
);
82 static void exynos4210_set_apll(unsigned int index
)
84 unsigned int tmp
, freq
= apll_freq_4210
[index
].freq
;
86 /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
87 clk_set_parent(moutcore
, mout_mpll
);
90 tmp
= (__raw_readl(EXYNOS4_CLKMUX_STATCPU
)
91 >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT
);
95 clk_set_rate(mout_apll
, freq
* 1000);
97 /* MUX_CORE_SEL = APLL */
98 clk_set_parent(moutcore
, mout_apll
);
101 tmp
= __raw_readl(EXYNOS4_CLKMUX_STATCPU
);
102 tmp
&= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK
;
103 } while (tmp
!= (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT
));
106 static void exynos4210_set_frequency(unsigned int old_index
,
107 unsigned int new_index
)
109 if (old_index
> new_index
) {
110 exynos4210_set_clkdiv(new_index
);
111 exynos4210_set_apll(new_index
);
112 } else if (old_index
< new_index
) {
113 exynos4210_set_apll(new_index
);
114 exynos4210_set_clkdiv(new_index
);
118 int exynos4210_cpufreq_init(struct exynos_dvfs_info
*info
)
122 cpu_clk
= clk_get(NULL
, "armclk");
124 return PTR_ERR(cpu_clk
);
126 moutcore
= clk_get(NULL
, "moutcore");
127 if (IS_ERR(moutcore
))
130 mout_mpll
= clk_get(NULL
, "mout_mpll");
131 if (IS_ERR(mout_mpll
))
134 rate
= clk_get_rate(mout_mpll
) / 1000;
136 mout_apll
= clk_get(NULL
, "mout_apll");
137 if (IS_ERR(mout_apll
))
140 info
->mpll_freq_khz
= rate
;
142 info
->pll_safe_idx
= L2
;
143 info
->cpu_clk
= cpu_clk
;
144 info
->volt_table
= exynos4210_volt_table
;
145 info
->freq_table
= exynos4210_freq_table
;
146 info
->set_freq
= exynos4210_set_frequency
;
157 pr_debug("%s: failed initialization\n", __func__
);