drivers/clk/samsung/clk-exynos5440.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Author: Thomas Abraham <thomas.ab@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Exynos5440 SoC.
  10 */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17
  18 #include "clk.h"
  19 #include "clk-pll.h"
  20
  21 #define CLKEN_OV_VAL            0xf8
  22 #define CPU_CLK_STATUS          0xfc
  23 #define MISC_DOUT1              0x558
  24
  25 /*
  26  * Let each supported clock get a unique id. This id is used to lookup the clock
  27  * for device tree based platforms.
  28  */
  29 enum exynos5440_clks {
  30         none, xtal, arm_clk,
  31
  32         spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
  33         usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
  34         b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
  35
  36         nr_clks,
  37 };
  38
  39 /* parent clock name list */
  40 PNAME(mout_armclk_p)    = { "cplla", "cpllb" };
  41 PNAME(mout_spi_p)       = { "div125", "div200" };
  42
  43 /* fixed rate clocks generated outside the soc */
  44 static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
  45         FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
  46 };
  47
  48 /* fixed rate clocks */
  49 static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
  50         FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
  51         FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
  52         FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
  53         FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
  54         FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
  55 };
  56
  57 /* fixed factor clocks */
  58 static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
  59         FFACTOR(none, "div250", "ppll", 1, 4, 0),
  60         FFACTOR(none, "div200", "ppll", 1, 5, 0),
  61         FFACTOR(none, "div125", "div250", 1, 2, 0),
  62 };
  63
  64 /* mux clocks */
  65 static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
  66         MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
  67         MUX_A(arm_clk, "arm_clk", mout_armclk_p,
  68                         CPU_CLK_STATUS, 0, 1, "armclk"),
  69 };
  70
  71 /* divider clocks */
  72 static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
  73         DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
  74 };
  75
  76 /* gate clocks */
  77 static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
  78         GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
  79         GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
  80         GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
  81         GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
  82         GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
  83         GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
  84         GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
  85         GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
  86         GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
  87         GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
  88         GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
  89         GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
  90         GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
  91         GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
  92         GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
  93         GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
  94         GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
  95         GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
  96         GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
  97         GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
  98 };
  99
 100 static struct of_device_id ext_clk_match[] __initdata = {
 101         { .compatible = "samsung,clock-xtal", .data = (void *)0, },
 102         {},
 103 };
 104
 105 /* register exynos5440 clocks */
 106 static void __init exynos5440_clk_init(struct device_node *np)
 107 {
 108         void __iomem *reg_base;
 109
 110         reg_base = of_iomap(np, 0);
 111         if (!reg_base) {
 112                 pr_err("%s: failed to map clock controller registers,"
 113                         " aborting clock initialization\n", __func__);
 114                 return;
 115         }
 116
 117         samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
 118         samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
 119                 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
 120
 121         samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
 122         samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
 123
 124         samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
 125                         ARRAY_SIZE(exynos5440_fixed_rate_clks));
 126         samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
 127                         ARRAY_SIZE(exynos5440_fixed_factor_clks));
 128         samsung_clk_register_mux(exynos5440_mux_clks,
 129                         ARRAY_SIZE(exynos5440_mux_clks));
 130         samsung_clk_register_div(exynos5440_div_clks,
 131                         ARRAY_SIZE(exynos5440_div_clks));
 132         samsung_clk_register_gate(exynos5440_gate_clks,
 133                         ARRAY_SIZE(exynos5440_gate_clks));
 134
 135         pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
 136         pr_info("exynos5440 clock initialization complete\n");
 137 }
 138 CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);