2 * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
4 * Copyright 2007-2009 Analog Devices Inc.
5 * Philippe Gerum <rpm@xenomai.org>
7 * Licensed under the GPL-2.
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16 #include <linux/cache.h>
17 #include <linux/clockchips.h>
18 #include <linux/profile.h>
19 #include <linux/errno.h>
21 #include <linux/cpu.h>
22 #include <linux/smp.h>
23 #include <linux/cpumask.h>
24 #include <linux/seq_file.h>
25 #include <linux/irq.h>
26 #include <linux/slab.h>
27 #include <linux/atomic.h>
28 #include <asm/cacheflush.h>
29 #include <asm/irq_handler.h>
30 #include <asm/mmu_context.h>
31 #include <asm/pgtable.h>
32 #include <asm/pgalloc.h>
33 #include <asm/processor.h>
34 #include <asm/ptrace.h>
37 #include <linux/err.h>
41 * 05000120 - we always define corelock as 32-bit integer in L2
43 struct corelock_slot corelock
__attribute__ ((__section__(".l2.bss")));
45 #ifdef CONFIG_ICACHE_FLUSH_L1
46 unsigned long blackfin_iflush_l1_entry
[NR_CPUS
];
49 struct blackfin_initial_pda initial_pda_coreb
;
51 enum ipi_message_type
{
56 BFIN_IPI_CALL_FUNC_SINGLE
,
60 struct blackfin_flush_data
{
65 void *secondary_stack
;
67 static struct blackfin_flush_data smp_flush_data
;
69 static DEFINE_SPINLOCK(stop_lock
);
71 /* A magic number - stress test shows this is safe for common cases */
72 #define BFIN_IPI_MSGQ_LEN 5
74 /* Simple FIFO buffer, overflow leads to panic */
80 static DEFINE_PER_CPU(struct ipi_data
, bfin_ipi
);
82 static void ipi_cpu_stop(unsigned int cpu
)
84 spin_lock(&stop_lock
);
85 printk(KERN_CRIT
"CPU%u: stopping\n", cpu
);
87 spin_unlock(&stop_lock
);
89 set_cpu_online(cpu
, false);
97 static void ipi_flush_icache(void *info
)
99 struct blackfin_flush_data
*fdata
= info
;
101 /* Invalidate the memory holding the bounds of the flushed region. */
102 blackfin_dcache_invalidate_range((unsigned long)fdata
,
103 (unsigned long)fdata
+ sizeof(*fdata
));
105 /* Make sure all write buffers in the data side of the core
106 * are flushed before trying to invalidate the icache. This
107 * needs to be after the data flush and before the icache
108 * flush so that the SSYNC does the right thing in preventing
109 * the instruction prefetcher from hitting things in cached
110 * memory at the wrong time -- it runs much further ahead than
115 /* ipi_flaush_icache is invoked by generic flush_icache_range,
116 * so call blackfin arch icache flush directly here.
118 blackfin_icache_flush_range(fdata
->start
, fdata
->end
);
121 /* Use IRQ_SUPPLE_0 to request reschedule.
122 * When returning from interrupt to user space,
123 * there is chance to reschedule */
124 static irqreturn_t
ipi_handler_int0(int irq
, void *dev_instance
)
126 unsigned int cpu
= smp_processor_id();
128 platform_clear_ipi(cpu
, IRQ_SUPPLE_0
);
132 DECLARE_PER_CPU(struct clock_event_device
, coretmr_events
);
135 int cpu
= smp_processor_id();
136 struct clock_event_device
*evt
= &per_cpu(coretmr_events
, cpu
);
137 evt
->event_handler(evt
);
140 static irqreturn_t
ipi_handler_int1(int irq
, void *dev_instance
)
142 struct ipi_data
*bfin_ipi_data
;
143 unsigned int cpu
= smp_processor_id();
144 unsigned long pending
;
147 platform_clear_ipi(cpu
, IRQ_SUPPLE_1
);
150 bfin_ipi_data
= &__get_cpu_var(bfin_ipi
);
151 while ((pending
= atomic_xchg(&bfin_ipi_data
->bits
, 0)) != 0) {
154 msg
= find_next_bit(&pending
, BITS_PER_LONG
, msg
+ 1);
159 case BFIN_IPI_RESCHEDULE
:
162 case BFIN_IPI_CALL_FUNC
:
163 generic_smp_call_function_interrupt();
165 case BFIN_IPI_CALL_FUNC_SINGLE
:
166 generic_smp_call_function_single_interrupt();
168 case BFIN_IPI_CPU_STOP
:
174 atomic_dec(&bfin_ipi_data
->count
);
175 } while (msg
< BITS_PER_LONG
);
182 static void bfin_ipi_init(void)
185 struct ipi_data
*bfin_ipi_data
;
186 for_each_possible_cpu(cpu
) {
187 bfin_ipi_data
= &per_cpu(bfin_ipi
, cpu
);
188 atomic_set(&bfin_ipi_data
->bits
, 0);
189 atomic_set(&bfin_ipi_data
->count
, 0);
193 void send_ipi(const struct cpumask
*cpumask
, enum ipi_message_type msg
)
196 struct ipi_data
*bfin_ipi_data
;
199 local_irq_save(flags
);
200 for_each_cpu(cpu
, cpumask
) {
201 bfin_ipi_data
= &per_cpu(bfin_ipi
, cpu
);
202 atomic_set_mask((1 << msg
), &bfin_ipi_data
->bits
);
203 atomic_inc(&bfin_ipi_data
->count
);
205 local_irq_restore(flags
);
207 for_each_cpu(cpu
, cpumask
)
208 platform_send_ipi_cpu(cpu
, IRQ_SUPPLE_1
);
211 void arch_send_call_function_single_ipi(int cpu
)
213 send_ipi(cpumask_of(cpu
), BFIN_IPI_CALL_FUNC_SINGLE
);
216 void arch_send_call_function_ipi_mask(const struct cpumask
*mask
)
218 send_ipi(mask
, BFIN_IPI_CALL_FUNC
);
221 void smp_send_reschedule(int cpu
)
223 send_ipi(cpumask_of(cpu
), BFIN_IPI_RESCHEDULE
);
228 void smp_send_msg(const struct cpumask
*mask
, unsigned long type
)
230 send_ipi(mask
, type
);
233 void smp_timer_broadcast(const struct cpumask
*mask
)
235 smp_send_msg(mask
, BFIN_IPI_TIMER
);
238 void smp_send_stop(void)
243 cpumask_copy(&callmap
, cpu_online_mask
);
244 cpumask_clear_cpu(smp_processor_id(), &callmap
);
245 if (!cpumask_empty(&callmap
))
246 send_ipi(&callmap
, BFIN_IPI_CPU_STOP
);
253 int __cpu_up(unsigned int cpu
, struct task_struct
*idle
)
257 secondary_stack
= task_stack_page(idle
) + THREAD_SIZE
;
259 ret
= platform_boot_secondary(cpu
, idle
);
261 secondary_stack
= NULL
;
266 static void setup_secondary(unsigned int cpu
)
272 ilat
= bfin_read_ILAT();
274 bfin_write_ILAT(ilat
);
277 /* Enable interrupt levels IVG7-15. IARs have been already
278 * programmed by the boot CPU. */
279 bfin_irq_flags
|= IMASK_IVG15
|
280 IMASK_IVG14
| IMASK_IVG13
| IMASK_IVG12
| IMASK_IVG11
|
281 IMASK_IVG10
| IMASK_IVG9
| IMASK_IVG8
| IMASK_IVG7
| IMASK_IVGHW
;
284 void secondary_start_kernel(void)
286 unsigned int cpu
= smp_processor_id();
287 struct mm_struct
*mm
= &init_mm
;
289 if (_bfin_swrst
& SWRST_DBL_FAULT_B
) {
290 printk(KERN_EMERG
"CoreB Recovering from DOUBLE FAULT event\n");
291 #ifdef CONFIG_DEBUG_DOUBLEFAULT
292 printk(KERN_EMERG
" While handling exception (EXCAUSE = %#x) at %pF\n",
293 initial_pda_coreb
.seqstat_doublefault
& SEQSTAT_EXCAUSE
,
294 initial_pda_coreb
.retx_doublefault
);
295 printk(KERN_NOTICE
" DCPLB_FAULT_ADDR: %pF\n",
296 initial_pda_coreb
.dcplb_doublefault_addr
);
297 printk(KERN_NOTICE
" ICPLB_FAULT_ADDR: %pF\n",
298 initial_pda_coreb
.icplb_doublefault_addr
);
300 printk(KERN_NOTICE
" The instruction at %pF caused a double exception\n",
301 initial_pda_coreb
.retx
);
305 * We want the D-cache to be enabled early, in case the atomic
306 * support code emulates cache coherence (see
307 * __ARCH_SYNC_CORE_DCACHE).
309 init_exception_vectors();
313 /* Attach the new idle task to the global mm. */
314 atomic_inc(&mm
->mm_users
);
315 atomic_inc(&mm
->mm_count
);
316 current
->active_mm
= mm
;
320 setup_secondary(cpu
);
322 platform_secondary_init(cpu
);
323 /* setup local core timer */
324 bfin_local_timer_setup();
328 bfin_setup_caches(cpu
);
330 notify_cpu_starting(cpu
);
332 * Calibrate loops per jiffy value.
333 * IRQs need to be enabled here - D-cache can be invalidated
334 * in timer irq handler, so core B can read correct jiffies.
338 /* We are done with local CPU inits, unblock the boot CPU. */
339 set_cpu_online(cpu
, true);
340 cpu_startup_entry(CPUHP_ONLINE
);
343 void __init
smp_prepare_boot_cpu(void)
347 void __init
smp_prepare_cpus(unsigned int max_cpus
)
349 platform_prepare_cpus(max_cpus
);
351 platform_request_ipi(IRQ_SUPPLE_0
, ipi_handler_int0
);
352 platform_request_ipi(IRQ_SUPPLE_1
, ipi_handler_int1
);
355 void __init
smp_cpus_done(unsigned int max_cpus
)
357 unsigned long bogosum
= 0;
360 for_each_online_cpu(cpu
)
361 bogosum
+= loops_per_jiffy
;
363 printk(KERN_INFO
"SMP: Total of %d processors activated "
364 "(%lu.%02lu BogoMIPS).\n",
366 bogosum
/ (500000/HZ
),
367 (bogosum
/ (5000/HZ
)) % 100);
370 void smp_icache_flush_range_others(unsigned long start
, unsigned long end
)
372 smp_flush_data
.start
= start
;
373 smp_flush_data
.end
= end
;
376 if (smp_call_function(&ipi_flush_icache
, &smp_flush_data
, 1))
377 printk(KERN_WARNING
"SMP: failed to run I-cache flush request on other CPUs\n");
380 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others
);
382 #ifdef __ARCH_SYNC_CORE_ICACHE
383 unsigned long icache_invld_count
[NR_CPUS
];
384 void resync_core_icache(void)
386 unsigned int cpu
= get_cpu();
387 blackfin_invalidate_entire_icache();
388 icache_invld_count
[cpu
]++;
391 EXPORT_SYMBOL(resync_core_icache
);
394 #ifdef __ARCH_SYNC_CORE_DCACHE
395 unsigned long dcache_invld_count
[NR_CPUS
];
396 unsigned long barrier_mask
__attribute__ ((__section__(".l2.bss")));
398 void resync_core_dcache(void)
400 unsigned int cpu
= get_cpu();
401 blackfin_invalidate_entire_dcache();
402 dcache_invld_count
[cpu
]++;
405 EXPORT_SYMBOL(resync_core_dcache
);
408 #ifdef CONFIG_HOTPLUG_CPU
409 int __cpu_disable(void)
411 unsigned int cpu
= smp_processor_id();
416 set_cpu_online(cpu
, false);
420 static DECLARE_COMPLETION(cpu_killed
);
422 int __cpu_die(unsigned int cpu
)
424 return wait_for_completion_timeout(&cpu_killed
, 5000);
429 complete(&cpu_killed
);
431 atomic_dec(&init_mm
.mm_users
);
432 atomic_dec(&init_mm
.mm_count
);