1 /* linux/arch/arm/plat-s3c64xx/pm.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX CPU PM support.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/suspend.h>
17 #include <linux/serial_core.h>
19 #include <linux/gpio.h>
20 #include <linux/pm_domain.h>
23 #include <mach/irqs.h>
25 #include <plat/devs.h>
27 #include <plat/wakeup-mask.h>
29 #include <mach/regs-gpio.h>
30 #include <mach/regs-clock.h>
32 #include "regs-gpio-memport.h"
33 #include "regs-modem.h"
35 #include "regs-syscon-power.h"
37 struct s3c64xx_pm_domain
{
41 struct generic_pm_domain pd
;
44 static int s3c64xx_pd_off(struct generic_pm_domain
*domain
)
46 struct s3c64xx_pm_domain
*pd
;
49 pd
= container_of(domain
, struct s3c64xx_pm_domain
, pd
);
51 val
= __raw_readl(S3C64XX_NORMAL_CFG
);
53 __raw_writel(val
, S3C64XX_NORMAL_CFG
);
58 static int s3c64xx_pd_on(struct generic_pm_domain
*domain
)
60 struct s3c64xx_pm_domain
*pd
;
62 long retry
= 1000000L;
64 pd
= container_of(domain
, struct s3c64xx_pm_domain
, pd
);
66 val
= __raw_readl(S3C64XX_NORMAL_CFG
);
68 __raw_writel(val
, S3C64XX_NORMAL_CFG
);
70 /* Not all domains provide power status readback */
74 if (__raw_readl(S3C64XX_BLK_PWR_STAT
) & pd
->pwr_stat
)
79 pr_err("Failed to start domain %s\n", pd
->name
);
87 static struct s3c64xx_pm_domain s3c64xx_pm_irom
= {
89 .ena
= S3C64XX_NORMALCFG_IROM_ON
,
91 .power_off
= s3c64xx_pd_off
,
92 .power_on
= s3c64xx_pd_on
,
96 static struct s3c64xx_pm_domain s3c64xx_pm_etm
= {
98 .ena
= S3C64XX_NORMALCFG_DOMAIN_ETM_ON
,
99 .pwr_stat
= S3C64XX_BLKPWRSTAT_ETM
,
101 .power_off
= s3c64xx_pd_off
,
102 .power_on
= s3c64xx_pd_on
,
106 static struct s3c64xx_pm_domain s3c64xx_pm_s
= {
108 .ena
= S3C64XX_NORMALCFG_DOMAIN_S_ON
,
109 .pwr_stat
= S3C64XX_BLKPWRSTAT_S
,
111 .power_off
= s3c64xx_pd_off
,
112 .power_on
= s3c64xx_pd_on
,
116 static struct s3c64xx_pm_domain s3c64xx_pm_f
= {
118 .ena
= S3C64XX_NORMALCFG_DOMAIN_F_ON
,
119 .pwr_stat
= S3C64XX_BLKPWRSTAT_F
,
121 .power_off
= s3c64xx_pd_off
,
122 .power_on
= s3c64xx_pd_on
,
126 static struct s3c64xx_pm_domain s3c64xx_pm_p
= {
128 .ena
= S3C64XX_NORMALCFG_DOMAIN_P_ON
,
129 .pwr_stat
= S3C64XX_BLKPWRSTAT_P
,
131 .power_off
= s3c64xx_pd_off
,
132 .power_on
= s3c64xx_pd_on
,
136 static struct s3c64xx_pm_domain s3c64xx_pm_i
= {
138 .ena
= S3C64XX_NORMALCFG_DOMAIN_I_ON
,
139 .pwr_stat
= S3C64XX_BLKPWRSTAT_I
,
141 .power_off
= s3c64xx_pd_off
,
142 .power_on
= s3c64xx_pd_on
,
146 static struct s3c64xx_pm_domain s3c64xx_pm_g
= {
148 .ena
= S3C64XX_NORMALCFG_DOMAIN_G_ON
,
150 .power_off
= s3c64xx_pd_off
,
151 .power_on
= s3c64xx_pd_on
,
155 static struct s3c64xx_pm_domain s3c64xx_pm_v
= {
157 .ena
= S3C64XX_NORMALCFG_DOMAIN_V_ON
,
158 .pwr_stat
= S3C64XX_BLKPWRSTAT_V
,
160 .power_off
= s3c64xx_pd_off
,
161 .power_on
= s3c64xx_pd_on
,
165 static struct s3c64xx_pm_domain
*s3c64xx_always_on_pm_domains
[] = {
169 static struct s3c64xx_pm_domain
*s3c64xx_pm_domains
[] = {
179 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
180 void s3c_pm_debug_smdkled(u32 set
, u32 clear
)
185 local_irq_save(flags
);
186 for (i
= 0; i
< 4; i
++) {
187 if (clear
& (1 << i
))
188 gpio_set_value(S3C64XX_GPN(12 + i
), 0);
190 gpio_set_value(S3C64XX_GPN(12 + i
), 1);
192 local_irq_restore(flags
);
196 static struct sleep_save core_save
[] = {
197 SAVE_ITEM(S3C64XX_MEM0DRVCON
),
198 SAVE_ITEM(S3C64XX_MEM1DRVCON
),
201 static struct sleep_save misc_save
[] = {
202 SAVE_ITEM(S3C64XX_AHB_CON0
),
203 SAVE_ITEM(S3C64XX_AHB_CON1
),
204 SAVE_ITEM(S3C64XX_AHB_CON2
),
206 SAVE_ITEM(S3C64XX_SPCON
),
208 SAVE_ITEM(S3C64XX_MEM0CONSTOP
),
209 SAVE_ITEM(S3C64XX_MEM1CONSTOP
),
210 SAVE_ITEM(S3C64XX_MEM0CONSLP0
),
211 SAVE_ITEM(S3C64XX_MEM0CONSLP1
),
212 SAVE_ITEM(S3C64XX_MEM1CONSLP
),
214 SAVE_ITEM(S3C64XX_SDMA_SEL
),
215 SAVE_ITEM(S3C64XX_MODEM_MIFPCON
),
217 SAVE_ITEM(S3C64XX_NORMAL_CFG
),
220 void s3c_pm_configure_extint(void)
222 __raw_writel(s3c_irqwake_eintmask
, S3C64XX_EINT_MASK
);
225 void s3c_pm_restore_core(void)
227 __raw_writel(0, S3C64XX_EINT_MASK
);
229 s3c_pm_debug_smdkled(1 << 2, 0);
231 s3c_pm_do_restore_core(core_save
, ARRAY_SIZE(core_save
));
232 s3c_pm_do_restore(misc_save
, ARRAY_SIZE(misc_save
));
235 void s3c_pm_save_core(void)
237 s3c_pm_do_save(misc_save
, ARRAY_SIZE(misc_save
));
238 s3c_pm_do_save(core_save
, ARRAY_SIZE(core_save
));
241 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
242 * put the per-cpu code in here until any new cpu comes along and changes
246 static int s3c64xx_cpu_suspend(unsigned long arg
)
250 /* set our standby method to sleep */
252 tmp
= __raw_readl(S3C64XX_PWR_CFG
);
253 tmp
&= ~S3C64XX_PWRCFG_CFG_WFI_MASK
;
254 tmp
|= S3C64XX_PWRCFG_CFG_WFI_SLEEP
;
255 __raw_writel(tmp
, S3C64XX_PWR_CFG
);
257 /* clear any old wakeup */
259 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT
),
260 S3C64XX_WAKEUP_STAT
);
262 /* set the LED state to 0110 over sleep */
263 s3c_pm_debug_smdkled(3 << 1, 0xf);
265 /* issue the standby signal into the pm unit. Note, we
266 * issue a write-buffer drain just in case */
273 "mcr p15, 0, %0, c7, c10, 5\n\t"
274 "mcr p15, 0, %0, c7, c10, 4\n\t"
275 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp
));
277 /* we should never get past here */
279 pr_info("Failed to suspend the system\n");
280 return 1; /* Aborting suspend */
283 /* mapping of interrupts to parts of the wakeup mask */
284 static struct samsung_wakeup_mask wake_irqs
[] = {
285 { .irq
= IRQ_RTC_ALARM
, .bit
= S3C64XX_PWRCFG_RTC_ALARM_DISABLE
, },
286 { .irq
= IRQ_RTC_TIC
, .bit
= S3C64XX_PWRCFG_RTC_TICK_DISABLE
, },
287 { .irq
= IRQ_PENDN
, .bit
= S3C64XX_PWRCFG_TS_DISABLE
, },
288 { .irq
= IRQ_HSMMC0
, .bit
= S3C64XX_PWRCFG_MMC0_DISABLE
, },
289 { .irq
= IRQ_HSMMC1
, .bit
= S3C64XX_PWRCFG_MMC1_DISABLE
, },
290 { .irq
= IRQ_HSMMC2
, .bit
= S3C64XX_PWRCFG_MMC2_DISABLE
, },
291 { .irq
= NO_WAKEUP_IRQ
, .bit
= S3C64XX_PWRCFG_BATF_DISABLE
},
292 { .irq
= NO_WAKEUP_IRQ
, .bit
= S3C64XX_PWRCFG_MSM_DISABLE
},
293 { .irq
= NO_WAKEUP_IRQ
, .bit
= S3C64XX_PWRCFG_HSI_DISABLE
},
294 { .irq
= NO_WAKEUP_IRQ
, .bit
= S3C64XX_PWRCFG_MSM_DISABLE
},
297 static void s3c64xx_pm_prepare(void)
299 samsung_sync_wakemask(S3C64XX_PWR_CFG
,
300 wake_irqs
, ARRAY_SIZE(wake_irqs
));
302 /* store address of resume. */
303 __raw_writel(virt_to_phys(s3c_cpu_resume
), S3C64XX_INFORM0
);
305 /* ensure previous wakeup state is cleared before sleeping */
306 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT
), S3C64XX_WAKEUP_STAT
);
309 int __init
s3c64xx_pm_init(void)
315 for (i
= 0; i
< ARRAY_SIZE(s3c64xx_always_on_pm_domains
); i
++)
316 pm_genpd_init(&s3c64xx_always_on_pm_domains
[i
]->pd
,
317 &pm_domain_always_on_gov
, false);
319 for (i
= 0; i
< ARRAY_SIZE(s3c64xx_pm_domains
); i
++)
320 pm_genpd_init(&s3c64xx_pm_domains
[i
]->pd
, NULL
, false);
322 #ifdef CONFIG_S3C_DEV_FB
323 if (dev_get_platdata(&s3c_device_fb
.dev
))
324 pm_genpd_add_device(&s3c64xx_pm_f
.pd
, &s3c_device_fb
.dev
);
330 static __init
int s3c64xx_pm_initcall(void)
332 pm_cpu_prep
= s3c64xx_pm_prepare
;
333 pm_cpu_sleep
= s3c64xx_cpu_suspend
;
334 pm_uart_udivslot
= 1;
336 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
337 gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
338 gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
339 gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
340 gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
341 gpio_direction_output(S3C64XX_GPN(12), 0);
342 gpio_direction_output(S3C64XX_GPN(13), 0);
343 gpio_direction_output(S3C64XX_GPN(14), 0);
344 gpio_direction_output(S3C64XX_GPN(15), 0);
349 arch_initcall(s3c64xx_pm_initcall
);
351 int __init
s3c64xx_pm_late_initcall(void)
353 pm_genpd_poweroff_unused();